drivers/gpu/drm/nouveau/nv04_instmem.c

   1 #include "drmP.h"
   2 #include "drm.h"
   3 #include "nouveau_drv.h"
   4
   5 /* returns the size of fifo context */
   6 static int
   7 nouveau_fifo_ctx_size(struct drm_device *dev)
   8 {
   9         struct drm_nouveau_private *dev_priv = dev->dev_private;
  10
  11         if (dev_priv->chipset >= 0x40)
  12                 return 128;
  13         else
  14         if (dev_priv->chipset >= 0x17)
  15                 return 64;
  16
  17         return 32;
  18 }
  19
  20 static void
  21 nv04_instmem_determine_amount(struct drm_device *dev)
  22 {
  23         struct drm_nouveau_private *dev_priv = dev->dev_private;
  24         int i;
  25
  26         /* Figure out how much instance memory we need */
  27         if (dev_priv->card_type >= NV_40) {
  28                 /* We'll want more instance memory than this on some NV4x cards.
  29                  * There's a 16MB aperture to play with that maps onto the end
  30                  * of vram.  For now, only reserve a small piece until we know
  31                  * more about what each chipset requires.
  32                  */
  33                 switch (dev_priv->chipset) {
  34                 case 0x40:
  35                 case 0x47:
  36                 case 0x49:
  37                 case 0x4b:
  38                         dev_priv->ramin_rsvd_vram = (2 * 1024 * 1024);
  39                         break;
  40                 default:
  41                         dev_priv->ramin_rsvd_vram = (1 * 1024 * 1024);
  42                         break;
  43                 }
  44         } else {
  45                 /*XXX: what *are* the limits on <NV40 cards?
  46                  */
  47                 dev_priv->ramin_rsvd_vram = (512 * 1024);
  48         }
  49         NV_DEBUG(dev, "RAMIN size: %dKiB\n", dev_priv->ramin_rsvd_vram >> 10);
  50
  51         /* Clear all of it, except the BIOS image that's in the first 64KiB */
  52         for (i = 64 * 1024; i < dev_priv->ramin_rsvd_vram; i += 4)
  53                 nv_wi32(dev, i, 0x00000000);
  54 }
  55
  56 static void
  57 nv04_instmem_configure_fixed_tables(struct drm_device *dev)
  58 {
  59         struct drm_nouveau_private *dev_priv = dev->dev_private;
  60         struct nouveau_engine *engine = &dev_priv->engine;
  61
  62         /* FIFO hash table (RAMHT)
  63          *   use 4k hash table at RAMIN+0x10000
  64          *   TODO: extend the hash table
  65          */
  66         dev_priv->ramht_offset = 0x10000;
  67         dev_priv->ramht_bits   = 9;
  68         dev_priv->ramht_size   = (1 << dev_priv->ramht_bits); /* nr entries */
  69         dev_priv->ramht_size  *= 8; /* 2 32-bit values per entry in RAMHT */
  70         NV_DEBUG(dev, "RAMHT offset=0x%x, size=%d\n", dev_priv->ramht_offset,
  71                                                       dev_priv->ramht_size);
  72
  73         /* FIFO runout table (RAMRO) - 512k at 0x11200 */
  74         dev_priv->ramro_offset = 0x11200;
  75         dev_priv->ramro_size   = 512;
  76         NV_DEBUG(dev, "RAMRO offset=0x%x, size=%d\n", dev_priv->ramro_offset,
  77                                                       dev_priv->ramro_size);
  78
  79         /* FIFO context table (RAMFC)
  80          *   NV40  : Not sure exactly how to position RAMFC on some cards,
  81          *           0x30002 seems to position it at RAMIN+0x20000 on these
  82          *           cards.  RAMFC is 4kb (32 fifos, 128byte entries).
  83          *   Others: Position RAMFC at RAMIN+0x11400
  84          */
  85         dev_priv->ramfc_size = engine->fifo.channels *
  86                                                 nouveau_fifo_ctx_size(dev);
  87         switch (dev_priv->card_type) {
  88         case NV_40:
  89                 dev_priv->ramfc_offset = 0x20000;
  90                 break;
  91         case NV_30:
  92         case NV_20:
  93         case NV_10:
  94         case NV_04:
  95         default:
  96                 dev_priv->ramfc_offset = 0x11400;
  97                 break;
  98         }
  99         NV_DEBUG(dev, "RAMFC offset=0x%x, size=%d\n", dev_priv->ramfc_offset,
 100                                                       dev_priv->ramfc_size);
 101 }
 102
 103 int nv04_instmem_init(struct drm_device *dev)
 104 {
 105         struct drm_nouveau_private *dev_priv = dev->dev_private;
 106         uint32_t offset;
 107         int ret;
 108
 109         nv04_instmem_determine_amount(dev);
 110         nv04_instmem_configure_fixed_tables(dev);
 111
 112         /* Create a heap to manage RAMIN allocations, we don't allocate
 113          * the space that was reserved for RAMHT/FC/RO.
 114          */
 115         offset = dev_priv->ramfc_offset + dev_priv->ramfc_size;
 116
 117         /* It appears RAMRO (or something?) is controlled by 0x2220/0x2230
 118          * on certain NV4x chipsets as well as RAMFC.  When 0x2230 == 0
 119          * ("new style" control) the upper 16-bits of 0x2220 points at this
 120          * other mysterious table that's clobbering important things.
 121          *
 122          * We're now pointing this at RAMIN+0x30000 to avoid RAMFC getting
 123          * smashed to pieces on us, so reserve 0x30000-0x40000 too..
 124          */
 125         if (dev_priv->card_type >= NV_40) {
 126                 if (offset < 0x40000)
 127                         offset = 0x40000;
 128         }
 129
 130         ret = drm_mm_init(&dev_priv->ramin_heap, offset,
 131                           dev_priv->ramin_rsvd_vram - offset);
 132         if (ret) {
 133                 NV_ERROR(dev, "Failed to init RAMIN heap: %d\n", ret);
 134                 return ret;
 135         }
 136
 137         return 0;
 138 }
 139
 140 void
 141 nv04_instmem_takedown(struct drm_device *dev)
 142 {
 143 }
 144
 145 int
 146 nv04_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj, uint32_t *sz)
 147 {
 148         if (gpuobj->im_backing)
 149                 return -EINVAL;
 150
 151         return 0;
 152 }
 153
 154 void
 155 nv04_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
 156 {
 157         struct drm_nouveau_private *dev_priv = dev->dev_private;
 158
 159         if (gpuobj && gpuobj->im_backing) {
 160                 if (gpuobj->im_bound)
 161                         dev_priv->engine.instmem.unbind(dev, gpuobj);
 162                 gpuobj->im_backing = NULL;
 163         }
 164 }
 165
 166 int
 167 nv04_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
 168 {
 169         if (!gpuobj->im_pramin || gpuobj->im_bound)
 170                 return -EINVAL;
 171
 172         gpuobj->im_bound = 1;
 173         return 0;
 174 }
 175
 176 int
 177 nv04_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
 178 {
 179         if (gpuobj->im_bound == 0)
 180                 return -EINVAL;
 181
 182         gpuobj->im_bound = 0;
 183         return 0;
 184 }
 185
 186 void
 187 nv04_instmem_flush(struct drm_device *dev)
 188 {
 189 }
 190
 191 int
 192 nv04_instmem_suspend(struct drm_device *dev)
 193 {
 194         return 0;
 195 }
 196
 197 void
 198 nv04_instmem_resume(struct drm_device *dev)
 199 {
 200 }
 201