drivers/gpu/drm/nouveau/nv17_fifo.c

   1 /*
   2  * Copyright (C) 2012 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "nouveau_drv.h"
  30 #include "nouveau_fifo.h"
  31 #include "nouveau_util.h"
  32 #include "nouveau_ramht.h"
  33
  34 static struct ramfc_desc {
  35         unsigned bits:6;
  36         unsigned ctxs:5;
  37         unsigned ctxp:8;
  38         unsigned regs:5;
  39         unsigned regp;
  40 } nv17_ramfc[] = {
  41         { 32,  0, 0x00,  0, NV04_PFIFO_CACHE1_DMA_PUT },
  42         { 32,  0, 0x04,  0, NV04_PFIFO_CACHE1_DMA_GET },
  43         { 32,  0, 0x08,  0, NV10_PFIFO_CACHE1_REF_CNT },
  44         { 16,  0, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
  45         { 16, 16, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
  46         { 32,  0, 0x10,  0, NV04_PFIFO_CACHE1_DMA_STATE },
  47         { 32,  0, 0x14,  0, NV04_PFIFO_CACHE1_DMA_FETCH },
  48         { 32,  0, 0x18,  0, NV04_PFIFO_CACHE1_ENGINE },
  49         { 32,  0, 0x1c,  0, NV04_PFIFO_CACHE1_PULL1 },
  50         { 32,  0, 0x20,  0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE },
  51         { 32,  0, 0x24,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP },
  52         { 32,  0, 0x28,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT },
  53         { 32,  0, 0x2c,  0, NV10_PFIFO_CACHE1_SEMAPHORE },
  54         { 32,  0, 0x30,  0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE },
  55         {}
  56 };
  57
  58 struct nv17_fifo_priv {
  59         struct nouveau_fifo_priv base;
  60         struct ramfc_desc *ramfc_desc;
  61 };
  62
  63 struct nv17_fifo_chan {
  64         struct nouveau_fifo_chan base;
  65         struct nouveau_gpuobj *ramfc;
  66 };
  67
  68 static int
  69 nv17_fifo_context_new(struct nouveau_channel *chan, int engine)
  70 {
  71         struct drm_device *dev = chan->dev;
  72         struct drm_nouveau_private *dev_priv = dev->dev_private;
  73         struct nv17_fifo_priv *priv = nv_engine(dev, engine);
  74         struct nv17_fifo_chan *fctx;
  75         unsigned long flags;
  76         int ret;
  77
  78         fctx = chan->engctx[engine] = kzalloc(sizeof(*fctx), GFP_KERNEL);
  79         if (!fctx)
  80                 return -ENOMEM;
  81
  82         /* map channel control registers */
  83         chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
  84                              NV03_USER(chan->id), PAGE_SIZE);
  85         if (!chan->user) {
  86                 ret = -ENOMEM;
  87                 goto error;
  88         }
  89
  90         /* initialise default fifo context */
  91         ret = nouveau_gpuobj_new_fake(dev, dev_priv->ramfc->pinst +
  92                                       chan->id * 64, ~0, 64,
  93                                       NVOBJ_FLAG_ZERO_ALLOC |
  94                                       NVOBJ_FLAG_ZERO_FREE, &fctx->ramfc);
  95         if (ret)
  96                 goto error;
  97
  98         nv_wo32(fctx->ramfc, 0x00, chan->pushbuf_base);
  99         nv_wo32(fctx->ramfc, 0x04, chan->pushbuf_base);
 100         nv_wo32(fctx->ramfc, 0x0c, chan->pushbuf->pinst >> 4);
 101         nv_wo32(fctx->ramfc, 0x14, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
 102                                    NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
 103 #ifdef __BIG_ENDIAN
 104                                    NV_PFIFO_CACHE1_BIG_ENDIAN |
 105 #endif
 106                                    NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
 107
 108         /* enable dma mode on the channel */
 109         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 110         nv_mask(dev, NV04_PFIFO_MODE, (1 << chan->id), (1 << chan->id));
 111         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 112
 113 error:
 114         if (ret)
 115                 priv->base.base.context_del(chan, engine);
 116         return ret;
 117 }
 118
 119 static int
 120 nv17_fifo_init(struct drm_device *dev, int engine)
 121 {
 122         struct drm_nouveau_private *dev_priv = dev->dev_private;
 123         struct nv17_fifo_priv *priv = nv_engine(dev, engine);
 124         int i;
 125
 126         nv_mask(dev, NV03_PMC_ENABLE, NV_PMC_ENABLE_PFIFO, 0);
 127         nv_mask(dev, NV03_PMC_ENABLE, NV_PMC_ENABLE_PFIFO, NV_PMC_ENABLE_PFIFO);
 128
 129         nv_wr32(dev, NV04_PFIFO_DELAY_0, 0x000000ff);
 130         nv_wr32(dev, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff);
 131
 132         nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
 133                                        ((dev_priv->ramht->bits - 9) << 16) |
 134                                        (dev_priv->ramht->gpuobj->pinst >> 8));
 135         nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro->pinst >> 8);
 136         nv_wr32(dev, NV03_PFIFO_RAMFC, 0x00010000 |
 137                                        dev_priv->ramfc->pinst >> 8);
 138
 139         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, priv->base.channels);
 140
 141         nv_wr32(dev, NV03_PFIFO_INTR_0, 0xffffffff);
 142         nv_wr32(dev, NV03_PFIFO_INTR_EN_0, 0xffffffff);
 143
 144         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 1);
 145         nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
 146         nv_wr32(dev, NV03_PFIFO_CACHES, 1);
 147
 148         for (i = 0; i < priv->base.channels; i++) {
 149                 if (dev_priv->channels.ptr[i])
 150                         nv_mask(dev, NV04_PFIFO_MODE, (1 << i), (1 << i));
 151         }
 152
 153         return 0;
 154 }
 155
 156 int
 157 nv17_fifo_create(struct drm_device *dev)
 158 {
 159         struct drm_nouveau_private *dev_priv = dev->dev_private;
 160         struct nv17_fifo_priv *priv;
 161
 162         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 163         if (!priv)
 164                 return -ENOMEM;
 165
 166         priv->base.base.destroy = nv04_fifo_destroy;
 167         priv->base.base.init = nv17_fifo_init;
 168         priv->base.base.fini = nv04_fifo_fini;
 169         priv->base.base.context_new = nv17_fifo_context_new;
 170         priv->base.base.context_del = nv04_fifo_context_del;
 171         priv->base.channels = 31;
 172         priv->ramfc_desc = nv17_ramfc;
 173         dev_priv->eng[NVOBJ_ENGINE_FIFO] = &priv->base.base;
 174
 175         nouveau_irq_register(dev, 8, nv04_fifo_isr);
 176         return 0;
 177 }