drm/nouveau: Rework tile region handling.
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nv30_fb.c
1 /*
2 * Copyright (C) 2010 Francisco Jerez.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27 #include "drmP.h"
28 #include "drm.h"
29 #include "nouveau_drv.h"
30 #include "nouveau_drm.h"
31
32 void
33 nv30_fb_init_tile_region(struct drm_device *dev, int i, uint32_t addr,
34 uint32_t size, uint32_t pitch, uint32_t flags)
35 {
36 struct drm_nouveau_private *dev_priv = dev->dev_private;
37 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
38
39 tile->addr = addr | 1;
40 tile->limit = max(1u, addr + size) - 1;
41 tile->pitch = pitch;
42 }
43
44 void
45 nv30_fb_free_tile_region(struct drm_device *dev, int i)
46 {
47 struct drm_nouveau_private *dev_priv = dev->dev_private;
48 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
49
50 tile->addr = tile->limit = tile->pitch = 0;
51 }
52
53 static int
54 calc_bias(struct drm_device *dev, int k, int i, int j)
55 {
56 struct drm_nouveau_private *dev_priv = dev->dev_private;
57 int b = (dev_priv->chipset > 0x30 ?
58 nv_rd32(dev, 0x122c + 0x10 * k + 0x4 * j) >> (4 * (i ^ 1)) :
59 0) & 0xf;
60
61 return 2 * (b & 0x8 ? b - 0x10 : b);
62 }
63
64 static int
65 calc_ref(struct drm_device *dev, int l, int k, int i)
66 {
67 int j, x = 0;
68
69 for (j = 0; j < 4; j++) {
70 int m = (l >> (8 * i) & 0xff) + calc_bias(dev, k, i, j);
71
72 x |= (0x80 | clamp(m, 0, 0x1f)) << (8 * j);
73 }
74
75 return x;
76 }
77
78 int
79 nv30_fb_init(struct drm_device *dev)
80 {
81 struct drm_nouveau_private *dev_priv = dev->dev_private;
82 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
83 int i, j;
84
85 pfb->num_tiles = NV10_PFB_TILE__SIZE;
86
87 /* Turn all the tiling regions off. */
88 for (i = 0; i < pfb->num_tiles; i++)
89 pfb->set_tile_region(dev, i);
90
91 /* Init the memory timing regs at 0x10037c/0x1003ac */
92 if (dev_priv->chipset == 0x30 ||
93 dev_priv->chipset == 0x31 ||
94 dev_priv->chipset == 0x35) {
95 /* Related to ROP count */
96 int n = (dev_priv->chipset == 0x31 ? 2 : 4);
97 int l = nv_rd32(dev, 0x1003d0);
98
99 for (i = 0; i < n; i++) {
100 for (j = 0; j < 3; j++)
101 nv_wr32(dev, 0x10037c + 0xc * i + 0x4 * j,
102 calc_ref(dev, l, 0, j));
103
104 for (j = 0; j < 2; j++)
105 nv_wr32(dev, 0x1003ac + 0x8 * i + 0x4 * j,
106 calc_ref(dev, l, 1, j));
107 }
108 }
109
110 return 0;
111 }
112
113 void
114 nv30_fb_takedown(struct drm_device *dev)
115 {
116 }
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