drivers/gpu/drm/nouveau/nv50_crtc.c

   1 /*
   2  * Copyright (C) 2008 Maarten Maathuis.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm_mode.h"
  29 #include "drm_crtc_helper.h"
  30
  31 #define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
  32 #include "nouveau_reg.h"
  33 #include "nouveau_drv.h"
  34 #include "nouveau_hw.h"
  35 #include "nouveau_encoder.h"
  36 #include "nouveau_crtc.h"
  37 #include "nouveau_fb.h"
  38 #include "nouveau_connector.h"
  39 #include "nv50_display.h"
  40
  41 static void
  42 nv50_crtc_lut_load(struct drm_crtc *crtc)
  43 {
  44         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
  45         void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
  46         int i;
  47
  48         NV_DEBUG_KMS(crtc->dev, "\n");
  49
  50         for (i = 0; i < 256; i++) {
  51                 writew(nv_crtc->lut.r[i] >> 2, lut + 8*i + 0);
  52                 writew(nv_crtc->lut.g[i] >> 2, lut + 8*i + 2);
  53                 writew(nv_crtc->lut.b[i] >> 2, lut + 8*i + 4);
  54         }
  55
  56         if (nv_crtc->lut.depth == 30) {
  57                 writew(nv_crtc->lut.r[i - 1] >> 2, lut + 8*i + 0);
  58                 writew(nv_crtc->lut.g[i - 1] >> 2, lut + 8*i + 2);
  59                 writew(nv_crtc->lut.b[i - 1] >> 2, lut + 8*i + 4);
  60         }
  61 }
  62
  63 int
  64 nv50_crtc_blank(struct nouveau_crtc *nv_crtc, bool blanked)
  65 {
  66         struct drm_device *dev = nv_crtc->base.dev;
  67         struct drm_nouveau_private *dev_priv = dev->dev_private;
  68         struct nouveau_channel *evo = dev_priv->evo;
  69         int index = nv_crtc->index, ret;
  70
  71         NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
  72         NV_DEBUG_KMS(dev, "%s\n", blanked ? "blanked" : "unblanked");
  73
  74         if (blanked) {
  75                 nv_crtc->cursor.hide(nv_crtc, false);
  76
  77                 ret = RING_SPACE(evo, dev_priv->chipset != 0x50 ? 7 : 5);
  78                 if (ret) {
  79                         NV_ERROR(dev, "no space while blanking crtc\n");
  80                         return ret;
  81                 }
  82                 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2);
  83                 OUT_RING(evo, NV50_EVO_CRTC_CLUT_MODE_BLANK);
  84                 OUT_RING(evo, 0);
  85                 if (dev_priv->chipset != 0x50) {
  86                         BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1);
  87                         OUT_RING(evo, NV84_EVO_CRTC_CLUT_DMA_HANDLE_NONE);
  88                 }
  89
  90                 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1);
  91                 OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
  92         } else {
  93                 if (nv_crtc->cursor.visible)
  94                         nv_crtc->cursor.show(nv_crtc, false);
  95                 else
  96                         nv_crtc->cursor.hide(nv_crtc, false);
  97
  98                 ret = RING_SPACE(evo, dev_priv->chipset != 0x50 ? 10 : 8);
  99                 if (ret) {
 100                         NV_ERROR(dev, "no space while unblanking crtc\n");
 101                         return ret;
 102                 }
 103                 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2);
 104                 OUT_RING(evo, nv_crtc->lut.depth == 8 ?
 105                                 NV50_EVO_CRTC_CLUT_MODE_OFF :
 106                                 NV50_EVO_CRTC_CLUT_MODE_ON);
 107                 OUT_RING(evo, (nv_crtc->lut.nvbo->bo.mem.mm_node->start <<
 108                                  PAGE_SHIFT) >> 8);
 109                 if (dev_priv->chipset != 0x50) {
 110                         BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1);
 111                         OUT_RING(evo, NvEvoVRAM);
 112                 }
 113
 114                 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_OFFSET), 2);
 115                 OUT_RING(evo, nv_crtc->fb.offset >> 8);
 116                 OUT_RING(evo, 0);
 117                 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1);
 118                 if (dev_priv->chipset != 0x50)
 119                         if (nv_crtc->fb.tile_flags == 0x7a00)
 120                                 OUT_RING(evo, NvEvoFB32);
 121                         else
 122                         if (nv_crtc->fb.tile_flags == 0x7000)
 123                                 OUT_RING(evo, NvEvoFB16);
 124                         else
 125                                 OUT_RING(evo, NvEvoVRAM);
 126                 else
 127                         OUT_RING(evo, NvEvoVRAM);
 128         }
 129
 130         nv_crtc->fb.blanked = blanked;
 131         return 0;
 132 }
 133
 134 static int
 135 nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool on, bool update)
 136 {
 137         struct drm_device *dev = nv_crtc->base.dev;
 138         struct drm_nouveau_private *dev_priv = dev->dev_private;
 139         struct nouveau_channel *evo = dev_priv->evo;
 140         int ret;
 141
 142         NV_DEBUG_KMS(dev, "\n");
 143
 144         ret = RING_SPACE(evo, 2 + (update ? 2 : 0));
 145         if (ret) {
 146                 NV_ERROR(dev, "no space while setting dither\n");
 147                 return ret;
 148         }
 149
 150         BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, DITHER_CTRL), 1);
 151         if (on)
 152                 OUT_RING(evo, NV50_EVO_CRTC_DITHER_CTRL_ON);
 153         else
 154                 OUT_RING(evo, NV50_EVO_CRTC_DITHER_CTRL_OFF);
 155
 156         if (update) {
 157                 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
 158                 OUT_RING(evo, 0);
 159                 FIRE_RING(evo);
 160         }
 161
 162         return 0;
 163 }
 164
 165 struct nouveau_connector *
 166 nouveau_crtc_connector_get(struct nouveau_crtc *nv_crtc)
 167 {
 168         struct drm_device *dev = nv_crtc->base.dev;
 169         struct drm_connector *connector;
 170         struct drm_crtc *crtc = to_drm_crtc(nv_crtc);
 171
 172         /* The safest approach is to find an encoder with the right crtc, that
 173          * is also linked to a connector. */
 174         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 175                 if (connector->encoder)
 176                         if (connector->encoder->crtc == crtc)
 177                                 return nouveau_connector(connector);
 178         }
 179
 180         return NULL;
 181 }
 182
 183 static int
 184 nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, int scaling_mode, bool update)
 185 {
 186         struct nouveau_connector *nv_connector =
 187                 nouveau_crtc_connector_get(nv_crtc);
 188         struct drm_device *dev = nv_crtc->base.dev;
 189         struct drm_nouveau_private *dev_priv = dev->dev_private;
 190         struct nouveau_channel *evo = dev_priv->evo;
 191         struct drm_display_mode *native_mode = NULL;
 192         struct drm_display_mode *mode = &nv_crtc->base.mode;
 193         uint32_t outX, outY, horiz, vert;
 194         int ret;
 195
 196         NV_DEBUG_KMS(dev, "\n");
 197
 198         switch (scaling_mode) {
 199         case DRM_MODE_SCALE_NONE:
 200                 break;
 201         default:
 202                 if (!nv_connector || !nv_connector->native_mode) {
 203                         NV_ERROR(dev, "No native mode, forcing panel scaling\n");
 204                         scaling_mode = DRM_MODE_SCALE_NONE;
 205                 } else {
 206                         native_mode = nv_connector->native_mode;
 207                 }
 208                 break;
 209         }
 210
 211         switch (scaling_mode) {
 212         case DRM_MODE_SCALE_ASPECT:
 213                 horiz = (native_mode->hdisplay << 19) / mode->hdisplay;
 214                 vert = (native_mode->vdisplay << 19) / mode->vdisplay;
 215
 216                 if (vert > horiz) {
 217                         outX = (mode->hdisplay * horiz) >> 19;
 218                         outY = (mode->vdisplay * horiz) >> 19;
 219                 } else {
 220                         outX = (mode->hdisplay * vert) >> 19;
 221                         outY = (mode->vdisplay * vert) >> 19;
 222                 }
 223                 break;
 224         case DRM_MODE_SCALE_FULLSCREEN:
 225                 outX = native_mode->hdisplay;
 226                 outY = native_mode->vdisplay;
 227                 break;
 228         case DRM_MODE_SCALE_CENTER:
 229         case DRM_MODE_SCALE_NONE:
 230         default:
 231                 outX = mode->hdisplay;
 232                 outY = mode->vdisplay;
 233                 break;
 234         }
 235
 236         ret = RING_SPACE(evo, update ? 7 : 5);
 237         if (ret)
 238                 return ret;
 239
 240         /* Got a better name for SCALER_ACTIVE? */
 241         /* One day i've got to really figure out why this is needed. */
 242         BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CTRL), 1);
 243         if ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ||
 244             (mode->flags & DRM_MODE_FLAG_INTERLACE) ||
 245             mode->hdisplay != outX || mode->vdisplay != outY) {
 246                 OUT_RING(evo, NV50_EVO_CRTC_SCALE_CTRL_ACTIVE);
 247         } else {
 248                 OUT_RING(evo, NV50_EVO_CRTC_SCALE_CTRL_INACTIVE);
 249         }
 250
 251         BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_RES1), 2);
 252         OUT_RING(evo, outY << 16 | outX);
 253         OUT_RING(evo, outY << 16 | outX);
 254
 255         if (update) {
 256                 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
 257                 OUT_RING(evo, 0);
 258                 FIRE_RING(evo);
 259         }
 260
 261         return 0;
 262 }
 263
 264 int
 265 nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
 266 {
 267         struct drm_nouveau_private *dev_priv = dev->dev_private;
 268         struct pll_lims pll;
 269         uint32_t reg, reg1, reg2;
 270         int ret, N1, M1, N2, M2, P;
 271
 272         if (dev_priv->chipset < NV_C0)
 273                 reg = NV50_PDISPLAY_CRTC_CLK_CTRL1(head);
 274         else
 275                 reg = 0x614140 + (head * 0x800);
 276
 277         ret = get_pll_limits(dev, reg, &pll);
 278         if (ret)
 279                 return ret;
 280
 281         if (pll.vco2.maxfreq) {
 282                 ret = nv50_calc_pll(dev, &pll, pclk, &N1, &M1, &N2, &M2, &P);
 283                 if (ret <= 0)
 284                         return 0;
 285
 286                 NV_DEBUG(dev, "pclk %d out %d NM1 %d %d NM2 %d %d P %d\n",
 287                          pclk, ret, N1, M1, N2, M2, P);
 288
 289                 reg1 = nv_rd32(dev, reg + 4) & 0xff00ff00;
 290                 reg2 = nv_rd32(dev, reg + 8) & 0x8000ff00;
 291                 nv_wr32(dev, reg, 0x10000611);
 292                 nv_wr32(dev, reg + 4, reg1 | (M1 << 16) | N1);
 293                 nv_wr32(dev, reg + 8, reg2 | (P << 28) | (M2 << 16) | N2);
 294         } else
 295         if (dev_priv->chipset < NV_C0) {
 296                 ret = nv50_calc_pll2(dev, &pll, pclk, &N1, &N2, &M1, &P);
 297                 if (ret <= 0)
 298                         return 0;
 299
 300                 NV_DEBUG(dev, "pclk %d out %d N %d fN 0x%04x M %d P %d\n",
 301                          pclk, ret, N1, N2, M1, P);
 302
 303                 reg1 = nv_rd32(dev, reg + 4) & 0xffc00000;
 304                 nv_wr32(dev, reg, 0x50000610);
 305                 nv_wr32(dev, reg + 4, reg1 | (P << 16) | (M1 << 8) | N1);
 306                 nv_wr32(dev, reg + 8, N2);
 307         } else {
 308                 ret = nv50_calc_pll2(dev, &pll, pclk, &N1, &N2, &M1, &P);
 309                 if (ret <= 0)
 310                         return 0;
 311
 312                 NV_DEBUG(dev, "pclk %d out %d N %d fN 0x%04x M %d P %d\n",
 313                          pclk, ret, N1, N2, M1, P);
 314
 315                 nv_mask(dev, reg + 0x0c, 0x00000000, 0x00000100);
 316                 nv_wr32(dev, reg + 0x04, (P << 16) | (N1 << 8) | M1);
 317                 nv_wr32(dev, reg + 0x10, N2 << 16);
 318         }
 319
 320         return 0;
 321 }
 322
 323 static void
 324 nv50_crtc_destroy(struct drm_crtc *crtc)
 325 {
 326         struct drm_device *dev;
 327         struct nouveau_crtc *nv_crtc;
 328
 329         if (!crtc)
 330                 return;
 331
 332         dev = crtc->dev;
 333         nv_crtc = nouveau_crtc(crtc);
 334
 335         NV_DEBUG_KMS(dev, "\n");
 336
 337         drm_crtc_cleanup(&nv_crtc->base);
 338
 339         nv50_cursor_fini(nv_crtc);
 340
 341         nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
 342         nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
 343         kfree(nv_crtc->mode);
 344         kfree(nv_crtc);
 345 }
 346
 347 int
 348 nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
 349                      uint32_t buffer_handle, uint32_t width, uint32_t height)
 350 {
 351         struct drm_device *dev = crtc->dev;
 352         struct drm_nouveau_private *dev_priv = dev->dev_private;
 353         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 354         struct nouveau_bo *cursor = NULL;
 355         struct drm_gem_object *gem;
 356         int ret = 0, i;
 357
 358         if (width != 64 || height != 64)
 359                 return -EINVAL;
 360
 361         if (!buffer_handle) {
 362                 nv_crtc->cursor.hide(nv_crtc, true);
 363                 return 0;
 364         }
 365
 366         gem = drm_gem_object_lookup(dev, file_priv, buffer_handle);
 367         if (!gem)
 368                 return -ENOENT;
 369         cursor = nouveau_gem_object(gem);
 370
 371         ret = nouveau_bo_map(cursor);
 372         if (ret)
 373                 goto out;
 374
 375         /* The simple will do for now. */
 376         for (i = 0; i < 64 * 64; i++)
 377                 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, nouveau_bo_rd32(cursor, i));
 378
 379         nouveau_bo_unmap(cursor);
 380
 381         nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.nvbo->bo.offset -
 382                                             dev_priv->vm_vram_base);
 383         nv_crtc->cursor.show(nv_crtc, true);
 384
 385 out:
 386         drm_gem_object_unreference_unlocked(gem);
 387         return ret;
 388 }
 389
 390 int
 391 nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 392 {
 393         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 394
 395         nv_crtc->cursor.set_pos(nv_crtc, x, y);
 396         return 0;
 397 }
 398
 399 static void
 400 nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
 401                     uint32_t size)
 402 {
 403         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 404         int i;
 405
 406         if (size != 256)
 407                 return;
 408
 409         for (i = 0; i < 256; i++) {
 410                 nv_crtc->lut.r[i] = r[i];
 411                 nv_crtc->lut.g[i] = g[i];
 412                 nv_crtc->lut.b[i] = b[i];
 413         }
 414
 415         /* We need to know the depth before we upload, but it's possible to
 416          * get called before a framebuffer is bound.  If this is the case,
 417          * mark the lut values as dirty by setting depth==0, and it'll be
 418          * uploaded on the first mode_set_base()
 419          */
 420         if (!nv_crtc->base.fb) {
 421                 nv_crtc->lut.depth = 0;
 422                 return;
 423         }
 424
 425         nv50_crtc_lut_load(crtc);
 426 }
 427
 428 static void
 429 nv50_crtc_save(struct drm_crtc *crtc)
 430 {
 431         NV_ERROR(crtc->dev, "!!\n");
 432 }
 433
 434 static void
 435 nv50_crtc_restore(struct drm_crtc *crtc)
 436 {
 437         NV_ERROR(crtc->dev, "!!\n");
 438 }
 439
 440 static const struct drm_crtc_funcs nv50_crtc_funcs = {
 441         .save = nv50_crtc_save,
 442         .restore = nv50_crtc_restore,
 443         .cursor_set = nv50_crtc_cursor_set,
 444         .cursor_move = nv50_crtc_cursor_move,
 445         .gamma_set = nv50_crtc_gamma_set,
 446         .set_config = drm_crtc_helper_set_config,
 447         .destroy = nv50_crtc_destroy,
 448 };
 449
 450 static void
 451 nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
 452 {
 453 }
 454
 455 static void
 456 nv50_crtc_prepare(struct drm_crtc *crtc)
 457 {
 458         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 459         struct drm_device *dev = crtc->dev;
 460
 461         NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
 462
 463         nv50_crtc_blank(nv_crtc, true);
 464 }
 465
 466 static void
 467 nv50_crtc_commit(struct drm_crtc *crtc)
 468 {
 469         struct drm_device *dev = crtc->dev;
 470         struct drm_nouveau_private *dev_priv = dev->dev_private;
 471         struct nouveau_channel *evo = dev_priv->evo;
 472         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 473         int ret;
 474
 475         NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
 476
 477         nv50_crtc_blank(nv_crtc, false);
 478
 479         ret = RING_SPACE(evo, 2);
 480         if (ret) {
 481                 NV_ERROR(dev, "no space while committing crtc\n");
 482                 return;
 483         }
 484         BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
 485         OUT_RING  (evo, 0);
 486         FIRE_RING (evo);
 487 }
 488
 489 static bool
 490 nv50_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *mode,
 491                      struct drm_display_mode *adjusted_mode)
 492 {
 493         return true;
 494 }
 495
 496 static int
 497 nv50_crtc_do_mode_set_base(struct drm_crtc *crtc, int x, int y,
 498                            struct drm_framebuffer *old_fb, bool update)
 499 {
 500         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 501         struct drm_device *dev = nv_crtc->base.dev;
 502         struct drm_nouveau_private *dev_priv = dev->dev_private;
 503         struct nouveau_channel *evo = dev_priv->evo;
 504         struct drm_framebuffer *drm_fb = nv_crtc->base.fb;
 505         struct nouveau_framebuffer *fb = nouveau_framebuffer(drm_fb);
 506         int ret, format;
 507
 508         NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
 509
 510         switch (drm_fb->depth) {
 511         case  8:
 512                 format = NV50_EVO_CRTC_FB_DEPTH_8;
 513                 break;
 514         case 15:
 515                 format = NV50_EVO_CRTC_FB_DEPTH_15;
 516                 break;
 517         case 16:
 518                 format = NV50_EVO_CRTC_FB_DEPTH_16;
 519                 break;
 520         case 24:
 521         case 32:
 522                 format = NV50_EVO_CRTC_FB_DEPTH_24;
 523                 break;
 524         case 30:
 525                 format = NV50_EVO_CRTC_FB_DEPTH_30;
 526                 break;
 527         default:
 528                  NV_ERROR(dev, "unknown depth %d\n", drm_fb->depth);
 529                  return -EINVAL;
 530         }
 531
 532         ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM);
 533         if (ret)
 534                 return ret;
 535
 536         if (old_fb) {
 537                 struct nouveau_framebuffer *ofb = nouveau_framebuffer(old_fb);
 538                 nouveau_bo_unpin(ofb->nvbo);
 539         }
 540
 541         nv_crtc->fb.offset = fb->nvbo->bo.offset - dev_priv->vm_vram_base;
 542         nv_crtc->fb.tile_flags = fb->nvbo->tile_flags;
 543         nv_crtc->fb.cpp = drm_fb->bits_per_pixel / 8;
 544         if (!nv_crtc->fb.blanked && dev_priv->chipset != 0x50) {
 545                 ret = RING_SPACE(evo, 2);
 546                 if (ret)
 547                         return ret;
 548
 549                 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_DMA), 1);
 550                 if (nv_crtc->fb.tile_flags == 0x7a00)
 551                         OUT_RING(evo, NvEvoFB32);
 552                 else
 553                 if (nv_crtc->fb.tile_flags == 0x7000)
 554                         OUT_RING(evo, NvEvoFB16);
 555                 else
 556                         OUT_RING(evo, NvEvoVRAM);
 557         }
 558
 559         ret = RING_SPACE(evo, 12);
 560         if (ret)
 561                 return ret;
 562
 563         BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_OFFSET), 5);
 564         OUT_RING(evo, nv_crtc->fb.offset >> 8);
 565         OUT_RING(evo, 0);
 566         OUT_RING(evo, (drm_fb->height << 16) | drm_fb->width);
 567         if (!nv_crtc->fb.tile_flags) {
 568                 OUT_RING(evo, drm_fb->pitch | (1 << 20));
 569         } else {
 570                 OUT_RING(evo, ((drm_fb->pitch / 4) << 4) |
 571                                   fb->nvbo->tile_mode);
 572         }
 573         if (dev_priv->chipset == 0x50)
 574                 OUT_RING(evo, (fb->nvbo->tile_flags << 8) | format);
 575         else
 576                 OUT_RING(evo, format);
 577
 578         BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CLUT_MODE), 1);
 579         OUT_RING(evo, fb->base.depth == 8 ?
 580                  NV50_EVO_CRTC_CLUT_MODE_OFF : NV50_EVO_CRTC_CLUT_MODE_ON);
 581
 582         BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, COLOR_CTRL), 1);
 583         OUT_RING(evo, NV50_EVO_CRTC_COLOR_CTRL_COLOR);
 584         BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_POS), 1);
 585         OUT_RING(evo, (y << 16) | x);
 586
 587         if (nv_crtc->lut.depth != fb->base.depth) {
 588                 nv_crtc->lut.depth = fb->base.depth;
 589                 nv50_crtc_lut_load(crtc);
 590         }
 591
 592         if (update) {
 593                 ret = RING_SPACE(evo, 2);
 594                 if (ret)
 595                         return ret;
 596                 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
 597                 OUT_RING(evo, 0);
 598                 FIRE_RING(evo);
 599         }
 600
 601         return 0;
 602 }
 603
 604 static int
 605 nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
 606                    struct drm_display_mode *adjusted_mode, int x, int y,
 607                    struct drm_framebuffer *old_fb)
 608 {
 609         struct drm_device *dev = crtc->dev;
 610         struct drm_nouveau_private *dev_priv = dev->dev_private;
 611         struct nouveau_channel *evo = dev_priv->evo;
 612         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 613         struct nouveau_connector *nv_connector = NULL;
 614         uint32_t hsync_dur,  vsync_dur, hsync_start_to_end, vsync_start_to_end;
 615         uint32_t hunk1, vunk1, vunk2a, vunk2b;
 616         int ret;
 617
 618         /* Find the connector attached to this CRTC */
 619         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 620
 621         *nv_crtc->mode = *adjusted_mode;
 622
 623         NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
 624
 625         hsync_dur = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
 626         vsync_dur = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
 627         hsync_start_to_end = adjusted_mode->htotal - adjusted_mode->hsync_start;
 628         vsync_start_to_end = adjusted_mode->vtotal - adjusted_mode->vsync_start;
 629         /* I can't give this a proper name, anyone else can? */
 630         hunk1 = adjusted_mode->htotal -
 631                 adjusted_mode->hsync_start + adjusted_mode->hdisplay;
 632         vunk1 = adjusted_mode->vtotal -
 633                 adjusted_mode->vsync_start + adjusted_mode->vdisplay;
 634         /* Another strange value, this time only for interlaced adjusted_modes. */
 635         vunk2a = 2 * adjusted_mode->vtotal -
 636                  adjusted_mode->vsync_start + adjusted_mode->vdisplay;
 637         vunk2b = adjusted_mode->vtotal -
 638                  adjusted_mode->vsync_start + adjusted_mode->vtotal;
 639
 640         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
 641                 vsync_dur /= 2;
 642                 vsync_start_to_end  /= 2;
 643                 vunk1 /= 2;
 644                 vunk2a /= 2;
 645                 vunk2b /= 2;
 646                 /* magic */
 647                 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 648                         vsync_start_to_end -= 1;
 649                         vunk1 -= 1;
 650                         vunk2a -= 1;
 651                         vunk2b -= 1;
 652                 }
 653         }
 654
 655         ret = RING_SPACE(evo, 17);
 656         if (ret)
 657                 return ret;
 658
 659         BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CLOCK), 2);
 660         OUT_RING(evo, adjusted_mode->clock | 0x800000);
 661         OUT_RING(evo, (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 0);
 662
 663         BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, DISPLAY_START), 5);
 664         OUT_RING(evo, 0);
 665         OUT_RING(evo, (adjusted_mode->vtotal << 16) | adjusted_mode->htotal);
 666         OUT_RING(evo, (vsync_dur - 1) << 16 | (hsync_dur - 1));
 667         OUT_RING(evo, (vsync_start_to_end - 1) << 16 |
 668                         (hsync_start_to_end - 1));
 669         OUT_RING(evo, (vunk1 - 1) << 16 | (hunk1 - 1));
 670
 671         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
 672                 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK0824), 1);
 673                 OUT_RING(evo, (vunk2b - 1) << 16 | (vunk2a - 1));
 674         } else {
 675                 OUT_RING(evo, 0);
 676                 OUT_RING(evo, 0);
 677         }
 678
 679         BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK082C), 1);
 680         OUT_RING(evo, 0);
 681
 682         /* This is the actual resolution of the mode. */
 683         BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, REAL_RES), 1);
 684         OUT_RING(evo, (mode->vdisplay << 16) | mode->hdisplay);
 685         BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CENTER_OFFSET), 1);
 686         OUT_RING(evo, NV50_EVO_CRTC_SCALE_CENTER_OFFSET_VAL(0, 0));
 687
 688         nv_crtc->set_dither(nv_crtc, nv_connector->use_dithering, false);
 689         nv_crtc->set_scale(nv_crtc, nv_connector->scaling_mode, false);
 690
 691         return nv50_crtc_do_mode_set_base(crtc, x, y, old_fb, false);
 692 }
 693
 694 static int
 695 nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 696                         struct drm_framebuffer *old_fb)
 697 {
 698         return nv50_crtc_do_mode_set_base(crtc, x, y, old_fb, true);
 699 }
 700
 701 static const struct drm_crtc_helper_funcs nv50_crtc_helper_funcs = {
 702         .dpms = nv50_crtc_dpms,
 703         .prepare = nv50_crtc_prepare,
 704         .commit = nv50_crtc_commit,
 705         .mode_fixup = nv50_crtc_mode_fixup,
 706         .mode_set = nv50_crtc_mode_set,
 707         .mode_set_base = nv50_crtc_mode_set_base,
 708         .load_lut = nv50_crtc_lut_load,
 709 };
 710
 711 int
 712 nv50_crtc_create(struct drm_device *dev, int index)
 713 {
 714         struct nouveau_crtc *nv_crtc = NULL;
 715         int ret, i;
 716
 717         NV_DEBUG_KMS(dev, "\n");
 718
 719         nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
 720         if (!nv_crtc)
 721                 return -ENOMEM;
 722
 723         nv_crtc->mode = kzalloc(sizeof(*nv_crtc->mode), GFP_KERNEL);
 724         if (!nv_crtc->mode) {
 725                 kfree(nv_crtc);
 726                 return -ENOMEM;
 727         }
 728
 729         /* Default CLUT parameters, will be activated on the hw upon
 730          * first mode set.
 731          */
 732         for (i = 0; i < 256; i++) {
 733                 nv_crtc->lut.r[i] = i << 8;
 734                 nv_crtc->lut.g[i] = i << 8;
 735                 nv_crtc->lut.b[i] = i << 8;
 736         }
 737         nv_crtc->lut.depth = 0;
 738
 739         ret = nouveau_bo_new(dev, NULL, 4096, 0x100, TTM_PL_FLAG_VRAM,
 740                              0, 0x0000, false, true, &nv_crtc->lut.nvbo);
 741         if (!ret) {
 742                 ret = nouveau_bo_pin(nv_crtc->lut.nvbo, TTM_PL_FLAG_VRAM);
 743                 if (!ret)
 744                         ret = nouveau_bo_map(nv_crtc->lut.nvbo);
 745                 if (ret)
 746                         nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
 747         }
 748
 749         if (ret) {
 750                 kfree(nv_crtc->mode);
 751                 kfree(nv_crtc);
 752                 return ret;
 753         }
 754
 755         nv_crtc->index = index;
 756
 757         /* set function pointers */
 758         nv_crtc->set_dither = nv50_crtc_set_dither;
 759         nv_crtc->set_scale = nv50_crtc_set_scale;
 760
 761         drm_crtc_init(dev, &nv_crtc->base, &nv50_crtc_funcs);
 762         drm_crtc_helper_add(&nv_crtc->base, &nv50_crtc_helper_funcs);
 763         drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256);
 764
 765         ret = nouveau_bo_new(dev, NULL, 64*64*4, 0x100, TTM_PL_FLAG_VRAM,
 766                              0, 0x0000, false, true, &nv_crtc->cursor.nvbo);
 767         if (!ret) {
 768                 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
 769                 if (!ret)
 770                         ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
 771                 if (ret)
 772                         nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
 773         }
 774
 775         nv50_cursor_init(nv_crtc);
 776         return 0;
 777 }