2 * Copyright 2011 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/dma-mapping.h>
28 #include <drm/drm_crtc_helper.h>
30 #include "nouveau_drm.h"
31 #include "nouveau_dma.h"
32 #include "nouveau_gem.h"
33 #include "nouveau_connector.h"
34 #include "nouveau_encoder.h"
35 #include "nouveau_crtc.h"
36 #include "nouveau_fence.h"
37 #include "nv50_display.h"
39 #include <core/client.h>
40 #include <core/gpuobj.h>
41 #include <core/class.h>
43 #include <subdev/timer.h>
44 #include <subdev/bar.h>
45 #include <subdev/fb.h>
46 #include <subdev/i2c.h>
50 #define EVO_MASTER (0x00)
51 #define EVO_FLIP(c) (0x01 + (c))
52 #define EVO_OVLY(c) (0x05 + (c))
53 #define EVO_OIMM(c) (0x09 + (c))
54 #define EVO_CURS(c) (0x0d + (c))
56 /* offsets in shared sync bo of various structures */
57 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
58 #define EVO_MAST_NTFY EVO_SYNC( 0, 0x00)
59 #define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00)
60 #define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10)
62 #define EVO_CORE_HANDLE (0xd1500000)
63 #define EVO_CHAN_HANDLE(t,i) (0xd15c0000 | (((t) & 0x00ff) << 8) | (i))
64 #define EVO_CHAN_OCLASS(t,c) ((nv_hclass(c) & 0xff00) | ((t) & 0x00ff))
65 #define EVO_PUSH_HANDLE(t,i) (0xd15b0000 | (i) | \
66 (((NV50_DISP_##t##_CLASS) & 0x00ff) << 8))
68 /******************************************************************************
70 *****************************************************************************/
73 struct nouveau_object
*user
;
78 nv50_chan_create(struct nouveau_object
*core
, u32 bclass
, u8 head
,
79 void *data
, u32 size
, struct nv50_chan
*chan
)
81 struct nouveau_object
*client
= nv_pclass(core
, NV_CLIENT_CLASS
);
82 const u32 oclass
= EVO_CHAN_OCLASS(bclass
, core
);
83 const u32 handle
= EVO_CHAN_HANDLE(bclass
, head
);
86 ret
= nouveau_object_new(client
, EVO_CORE_HANDLE
, handle
,
87 oclass
, data
, size
, &chan
->user
);
91 chan
->handle
= handle
;
96 nv50_chan_destroy(struct nouveau_object
*core
, struct nv50_chan
*chan
)
98 struct nouveau_object
*client
= nv_pclass(core
, NV_CLIENT_CLASS
);
100 nouveau_object_del(client
, EVO_CORE_HANDLE
, chan
->handle
);
103 /******************************************************************************
105 *****************************************************************************/
108 struct nv50_chan base
;
112 nv50_pioc_destroy(struct nouveau_object
*core
, struct nv50_pioc
*pioc
)
114 nv50_chan_destroy(core
, &pioc
->base
);
118 nv50_pioc_create(struct nouveau_object
*core
, u32 bclass
, u8 head
,
119 void *data
, u32 size
, struct nv50_pioc
*pioc
)
121 return nv50_chan_create(core
, bclass
, head
, data
, size
, &pioc
->base
);
124 /******************************************************************************
126 *****************************************************************************/
129 struct nv50_chan base
;
133 /* Protects against concurrent pushbuf access to this channel, lock is
134 * grabbed by evo_wait (if the pushbuf reservation is successful) and
135 * dropped again by evo_kick. */
140 nv50_dmac_destroy(struct nouveau_object
*core
, struct nv50_dmac
*dmac
)
143 struct pci_dev
*pdev
= nv_device(core
)->pdev
;
144 pci_free_consistent(pdev
, PAGE_SIZE
, dmac
->ptr
, dmac
->handle
);
147 nv50_chan_destroy(core
, &dmac
->base
);
151 nv50_dmac_create_fbdma(struct nouveau_object
*core
, u32 parent
)
153 struct nouveau_fb
*pfb
= nouveau_fb(core
);
154 struct nouveau_object
*client
= nv_pclass(core
, NV_CLIENT_CLASS
);
155 struct nouveau_object
*object
;
156 int ret
= nouveau_object_new(client
, parent
, NvEvoVRAM_LP
,
157 NV_DMA_IN_MEMORY_CLASS
,
158 &(struct nv_dma_class
) {
159 .flags
= NV_DMA_TARGET_VRAM
|
162 .limit
= pfb
->ram
->size
- 1,
163 .conf0
= NV50_DMA_CONF0_ENABLE
|
164 NV50_DMA_CONF0_PART_256
,
165 }, sizeof(struct nv_dma_class
), &object
);
169 ret
= nouveau_object_new(client
, parent
, NvEvoFB16
,
170 NV_DMA_IN_MEMORY_CLASS
,
171 &(struct nv_dma_class
) {
172 .flags
= NV_DMA_TARGET_VRAM
|
175 .limit
= pfb
->ram
->size
- 1,
176 .conf0
= NV50_DMA_CONF0_ENABLE
| 0x70 |
177 NV50_DMA_CONF0_PART_256
,
178 }, sizeof(struct nv_dma_class
), &object
);
182 ret
= nouveau_object_new(client
, parent
, NvEvoFB32
,
183 NV_DMA_IN_MEMORY_CLASS
,
184 &(struct nv_dma_class
) {
185 .flags
= NV_DMA_TARGET_VRAM
|
188 .limit
= pfb
->ram
->size
- 1,
189 .conf0
= NV50_DMA_CONF0_ENABLE
| 0x7a |
190 NV50_DMA_CONF0_PART_256
,
191 }, sizeof(struct nv_dma_class
), &object
);
196 nvc0_dmac_create_fbdma(struct nouveau_object
*core
, u32 parent
)
198 struct nouveau_fb
*pfb
= nouveau_fb(core
);
199 struct nouveau_object
*client
= nv_pclass(core
, NV_CLIENT_CLASS
);
200 struct nouveau_object
*object
;
201 int ret
= nouveau_object_new(client
, parent
, NvEvoVRAM_LP
,
202 NV_DMA_IN_MEMORY_CLASS
,
203 &(struct nv_dma_class
) {
204 .flags
= NV_DMA_TARGET_VRAM
|
207 .limit
= pfb
->ram
->size
- 1,
208 .conf0
= NVC0_DMA_CONF0_ENABLE
,
209 }, sizeof(struct nv_dma_class
), &object
);
213 ret
= nouveau_object_new(client
, parent
, NvEvoFB16
,
214 NV_DMA_IN_MEMORY_CLASS
,
215 &(struct nv_dma_class
) {
216 .flags
= NV_DMA_TARGET_VRAM
|
219 .limit
= pfb
->ram
->size
- 1,
220 .conf0
= NVC0_DMA_CONF0_ENABLE
| 0xfe,
221 }, sizeof(struct nv_dma_class
), &object
);
225 ret
= nouveau_object_new(client
, parent
, NvEvoFB32
,
226 NV_DMA_IN_MEMORY_CLASS
,
227 &(struct nv_dma_class
) {
228 .flags
= NV_DMA_TARGET_VRAM
|
231 .limit
= pfb
->ram
->size
- 1,
232 .conf0
= NVC0_DMA_CONF0_ENABLE
| 0xfe,
233 }, sizeof(struct nv_dma_class
), &object
);
238 nvd0_dmac_create_fbdma(struct nouveau_object
*core
, u32 parent
)
240 struct nouveau_fb
*pfb
= nouveau_fb(core
);
241 struct nouveau_object
*client
= nv_pclass(core
, NV_CLIENT_CLASS
);
242 struct nouveau_object
*object
;
243 int ret
= nouveau_object_new(client
, parent
, NvEvoVRAM_LP
,
244 NV_DMA_IN_MEMORY_CLASS
,
245 &(struct nv_dma_class
) {
246 .flags
= NV_DMA_TARGET_VRAM
|
249 .limit
= pfb
->ram
->size
- 1,
250 .conf0
= NVD0_DMA_CONF0_ENABLE
|
251 NVD0_DMA_CONF0_PAGE_LP
,
252 }, sizeof(struct nv_dma_class
), &object
);
256 ret
= nouveau_object_new(client
, parent
, NvEvoFB32
,
257 NV_DMA_IN_MEMORY_CLASS
,
258 &(struct nv_dma_class
) {
259 .flags
= NV_DMA_TARGET_VRAM
|
262 .limit
= pfb
->ram
->size
- 1,
263 .conf0
= NVD0_DMA_CONF0_ENABLE
| 0xfe |
264 NVD0_DMA_CONF0_PAGE_LP
,
265 }, sizeof(struct nv_dma_class
), &object
);
270 nv50_dmac_create(struct nouveau_object
*core
, u32 bclass
, u8 head
,
271 void *data
, u32 size
, u64 syncbuf
,
272 struct nv50_dmac
*dmac
)
274 struct nouveau_fb
*pfb
= nouveau_fb(core
);
275 struct nouveau_object
*client
= nv_pclass(core
, NV_CLIENT_CLASS
);
276 struct nouveau_object
*object
;
277 u32 pushbuf
= *(u32
*)data
;
280 mutex_init(&dmac
->lock
);
282 dmac
->ptr
= pci_alloc_consistent(nv_device(core
)->pdev
, PAGE_SIZE
,
287 ret
= nouveau_object_new(client
, NVDRM_DEVICE
, pushbuf
,
288 NV_DMA_FROM_MEMORY_CLASS
,
289 &(struct nv_dma_class
) {
290 .flags
= NV_DMA_TARGET_PCI_US
|
292 .start
= dmac
->handle
+ 0x0000,
293 .limit
= dmac
->handle
+ 0x0fff,
294 }, sizeof(struct nv_dma_class
), &object
);
298 ret
= nv50_chan_create(core
, bclass
, head
, data
, size
, &dmac
->base
);
302 ret
= nouveau_object_new(client
, dmac
->base
.handle
, NvEvoSync
,
303 NV_DMA_IN_MEMORY_CLASS
,
304 &(struct nv_dma_class
) {
305 .flags
= NV_DMA_TARGET_VRAM
|
307 .start
= syncbuf
+ 0x0000,
308 .limit
= syncbuf
+ 0x0fff,
309 }, sizeof(struct nv_dma_class
), &object
);
313 ret
= nouveau_object_new(client
, dmac
->base
.handle
, NvEvoVRAM
,
314 NV_DMA_IN_MEMORY_CLASS
,
315 &(struct nv_dma_class
) {
316 .flags
= NV_DMA_TARGET_VRAM
|
319 .limit
= pfb
->ram
->size
- 1,
320 }, sizeof(struct nv_dma_class
), &object
);
324 if (nv_device(core
)->card_type
< NV_C0
)
325 ret
= nv50_dmac_create_fbdma(core
, dmac
->base
.handle
);
327 if (nv_device(core
)->card_type
< NV_D0
)
328 ret
= nvc0_dmac_create_fbdma(core
, dmac
->base
.handle
);
330 ret
= nvd0_dmac_create_fbdma(core
, dmac
->base
.handle
);
335 struct nv50_dmac base
;
339 struct nv50_pioc base
;
343 struct nv50_dmac base
;
349 struct nv50_dmac base
;
353 struct nv50_pioc base
;
357 struct nouveau_crtc base
;
358 struct nv50_curs curs
;
359 struct nv50_sync sync
;
360 struct nv50_ovly ovly
;
361 struct nv50_oimm oimm
;
364 #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
365 #define nv50_curs(c) (&nv50_head(c)->curs)
366 #define nv50_sync(c) (&nv50_head(c)->sync)
367 #define nv50_ovly(c) (&nv50_head(c)->ovly)
368 #define nv50_oimm(c) (&nv50_head(c)->oimm)
369 #define nv50_chan(c) (&(c)->base.base)
370 #define nv50_vers(c) nv_mclass(nv50_chan(c)->user)
373 struct nouveau_object
*core
;
374 struct nv50_mast mast
;
378 struct nouveau_bo
*sync
;
381 static struct nv50_disp
*
382 nv50_disp(struct drm_device
*dev
)
384 return nouveau_display(dev
)->priv
;
387 #define nv50_mast(d) (&nv50_disp(d)->mast)
389 static struct drm_crtc
*
390 nv50_display_crtc_get(struct drm_encoder
*encoder
)
392 return nouveau_encoder(encoder
)->crtc
;
395 /******************************************************************************
396 * EVO channel helpers
397 *****************************************************************************/
399 evo_wait(void *evoc
, int nr
)
401 struct nv50_dmac
*dmac
= evoc
;
402 u32 put
= nv_ro32(dmac
->base
.user
, 0x0000) / 4;
404 mutex_lock(&dmac
->lock
);
405 if (put
+ nr
>= (PAGE_SIZE
/ 4) - 8) {
406 dmac
->ptr
[put
] = 0x20000000;
408 nv_wo32(dmac
->base
.user
, 0x0000, 0x00000000);
409 if (!nv_wait(dmac
->base
.user
, 0x0004, ~0, 0x00000000)) {
410 mutex_unlock(&dmac
->lock
);
411 NV_ERROR(dmac
->base
.user
, "channel stalled\n");
418 return dmac
->ptr
+ put
;
422 evo_kick(u32
*push
, void *evoc
)
424 struct nv50_dmac
*dmac
= evoc
;
425 nv_wo32(dmac
->base
.user
, 0x0000, (push
- dmac
->ptr
) << 2);
426 mutex_unlock(&dmac
->lock
);
429 #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
430 #define evo_data(p,d) *((p)++) = (d)
433 evo_sync_wait(void *data
)
435 if (nouveau_bo_rd32(data
, EVO_MAST_NTFY
) != 0x00000000)
442 evo_sync(struct drm_device
*dev
)
444 struct nouveau_device
*device
= nouveau_dev(dev
);
445 struct nv50_disp
*disp
= nv50_disp(dev
);
446 struct nv50_mast
*mast
= nv50_mast(dev
);
447 u32
*push
= evo_wait(mast
, 8);
449 nouveau_bo_wr32(disp
->sync
, EVO_MAST_NTFY
, 0x00000000);
450 evo_mthd(push
, 0x0084, 1);
451 evo_data(push
, 0x80000000 | EVO_MAST_NTFY
);
452 evo_mthd(push
, 0x0080, 2);
453 evo_data(push
, 0x00000000);
454 evo_data(push
, 0x00000000);
455 evo_kick(push
, mast
);
456 if (nv_wait_cb(device
, evo_sync_wait
, disp
->sync
))
463 /******************************************************************************
464 * Page flipping channel
465 *****************************************************************************/
467 nv50_display_crtc_sema(struct drm_device
*dev
, int crtc
)
469 return nv50_disp(dev
)->sync
;
472 struct nv50_display_flip
{
473 struct nv50_disp
*disp
;
474 struct nv50_sync
*chan
;
478 nv50_display_flip_wait(void *data
)
480 struct nv50_display_flip
*flip
= data
;
481 if (nouveau_bo_rd32(flip
->disp
->sync
, flip
->chan
->addr
/ 4) ==
489 nv50_display_flip_stop(struct drm_crtc
*crtc
)
491 struct nouveau_device
*device
= nouveau_dev(crtc
->dev
);
492 struct nv50_display_flip flip
= {
493 .disp
= nv50_disp(crtc
->dev
),
494 .chan
= nv50_sync(crtc
),
498 push
= evo_wait(flip
.chan
, 8);
500 evo_mthd(push
, 0x0084, 1);
501 evo_data(push
, 0x00000000);
502 evo_mthd(push
, 0x0094, 1);
503 evo_data(push
, 0x00000000);
504 evo_mthd(push
, 0x00c0, 1);
505 evo_data(push
, 0x00000000);
506 evo_mthd(push
, 0x0080, 1);
507 evo_data(push
, 0x00000000);
508 evo_kick(push
, flip
.chan
);
511 nv_wait_cb(device
, nv50_display_flip_wait
, &flip
);
515 nv50_display_flip_next(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
516 struct nouveau_channel
*chan
, u32 swap_interval
)
518 struct nouveau_framebuffer
*nv_fb
= nouveau_framebuffer(fb
);
519 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
520 struct nv50_sync
*sync
= nv50_sync(crtc
);
521 int head
= nv_crtc
->index
, ret
;
525 if (swap_interval
== 0)
526 swap_interval
|= 0x100;
530 push
= evo_wait(sync
, 128);
531 if (unlikely(push
== NULL
))
534 if (chan
&& nv_mclass(chan
->object
) < NV84_CHANNEL_IND_CLASS
) {
535 ret
= RING_SPACE(chan
, 8);
539 BEGIN_NV04(chan
, 0, NV11_SUBCHAN_DMA_SEMAPHORE
, 2);
540 OUT_RING (chan
, NvEvoSema0
+ head
);
541 OUT_RING (chan
, sync
->addr
^ 0x10);
542 BEGIN_NV04(chan
, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE
, 1);
543 OUT_RING (chan
, sync
->data
+ 1);
544 BEGIN_NV04(chan
, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET
, 2);
545 OUT_RING (chan
, sync
->addr
);
546 OUT_RING (chan
, sync
->data
);
548 if (chan
&& nv_mclass(chan
->object
) < NVC0_CHANNEL_IND_CLASS
) {
549 u64 addr
= nv84_fence_crtc(chan
, head
) + sync
->addr
;
550 ret
= RING_SPACE(chan
, 12);
554 BEGIN_NV04(chan
, 0, NV11_SUBCHAN_DMA_SEMAPHORE
, 1);
555 OUT_RING (chan
, chan
->vram
);
556 BEGIN_NV04(chan
, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH
, 4);
557 OUT_RING (chan
, upper_32_bits(addr
^ 0x10));
558 OUT_RING (chan
, lower_32_bits(addr
^ 0x10));
559 OUT_RING (chan
, sync
->data
+ 1);
560 OUT_RING (chan
, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG
);
561 BEGIN_NV04(chan
, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH
, 4);
562 OUT_RING (chan
, upper_32_bits(addr
));
563 OUT_RING (chan
, lower_32_bits(addr
));
564 OUT_RING (chan
, sync
->data
);
565 OUT_RING (chan
, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL
);
568 u64 addr
= nv84_fence_crtc(chan
, head
) + sync
->addr
;
569 ret
= RING_SPACE(chan
, 10);
573 BEGIN_NVC0(chan
, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH
, 4);
574 OUT_RING (chan
, upper_32_bits(addr
^ 0x10));
575 OUT_RING (chan
, lower_32_bits(addr
^ 0x10));
576 OUT_RING (chan
, sync
->data
+ 1);
577 OUT_RING (chan
, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG
|
578 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD
);
579 BEGIN_NVC0(chan
, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH
, 4);
580 OUT_RING (chan
, upper_32_bits(addr
));
581 OUT_RING (chan
, lower_32_bits(addr
));
582 OUT_RING (chan
, sync
->data
);
583 OUT_RING (chan
, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL
|
584 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD
);
594 evo_mthd(push
, 0x0100, 1);
595 evo_data(push
, 0xfffe0000);
596 evo_mthd(push
, 0x0084, 1);
597 evo_data(push
, swap_interval
);
598 if (!(swap_interval
& 0x00000100)) {
599 evo_mthd(push
, 0x00e0, 1);
600 evo_data(push
, 0x40000000);
602 evo_mthd(push
, 0x0088, 4);
603 evo_data(push
, sync
->addr
);
604 evo_data(push
, sync
->data
++);
605 evo_data(push
, sync
->data
);
606 evo_data(push
, NvEvoSync
);
607 evo_mthd(push
, 0x00a0, 2);
608 evo_data(push
, 0x00000000);
609 evo_data(push
, 0x00000000);
610 evo_mthd(push
, 0x00c0, 1);
611 evo_data(push
, nv_fb
->r_dma
);
612 evo_mthd(push
, 0x0110, 2);
613 evo_data(push
, 0x00000000);
614 evo_data(push
, 0x00000000);
615 if (nv50_vers(sync
) < NVD0_DISP_SYNC_CLASS
) {
616 evo_mthd(push
, 0x0800, 5);
617 evo_data(push
, nv_fb
->nvbo
->bo
.offset
>> 8);
619 evo_data(push
, (fb
->height
<< 16) | fb
->width
);
620 evo_data(push
, nv_fb
->r_pitch
);
621 evo_data(push
, nv_fb
->r_format
);
623 evo_mthd(push
, 0x0400, 5);
624 evo_data(push
, nv_fb
->nvbo
->bo
.offset
>> 8);
626 evo_data(push
, (fb
->height
<< 16) | fb
->width
);
627 evo_data(push
, nv_fb
->r_pitch
);
628 evo_data(push
, nv_fb
->r_format
);
630 evo_mthd(push
, 0x0080, 1);
631 evo_data(push
, 0x00000000);
632 evo_kick(push
, sync
);
636 /******************************************************************************
638 *****************************************************************************/
640 nv50_crtc_set_dither(struct nouveau_crtc
*nv_crtc
, bool update
)
642 struct nv50_mast
*mast
= nv50_mast(nv_crtc
->base
.dev
);
643 struct nouveau_connector
*nv_connector
;
644 struct drm_connector
*connector
;
645 u32
*push
, mode
= 0x00;
647 nv_connector
= nouveau_crtc_connector_get(nv_crtc
);
648 connector
= &nv_connector
->base
;
649 if (nv_connector
->dithering_mode
== DITHERING_MODE_AUTO
) {
650 if (nv_crtc
->base
.fb
->depth
> connector
->display_info
.bpc
* 3)
651 mode
= DITHERING_MODE_DYNAMIC2X2
;
653 mode
= nv_connector
->dithering_mode
;
656 if (nv_connector
->dithering_depth
== DITHERING_DEPTH_AUTO
) {
657 if (connector
->display_info
.bpc
>= 8)
658 mode
|= DITHERING_DEPTH_8BPC
;
660 mode
|= nv_connector
->dithering_depth
;
663 push
= evo_wait(mast
, 4);
665 if (nv50_vers(mast
) < NVD0_DISP_MAST_CLASS
) {
666 evo_mthd(push
, 0x08a0 + (nv_crtc
->index
* 0x0400), 1);
667 evo_data(push
, mode
);
669 if (nv50_vers(mast
) < NVE0_DISP_MAST_CLASS
) {
670 evo_mthd(push
, 0x0490 + (nv_crtc
->index
* 0x0300), 1);
671 evo_data(push
, mode
);
673 evo_mthd(push
, 0x04a0 + (nv_crtc
->index
* 0x0300), 1);
674 evo_data(push
, mode
);
678 evo_mthd(push
, 0x0080, 1);
679 evo_data(push
, 0x00000000);
681 evo_kick(push
, mast
);
688 nv50_crtc_set_scale(struct nouveau_crtc
*nv_crtc
, bool update
)
690 struct nv50_mast
*mast
= nv50_mast(nv_crtc
->base
.dev
);
691 struct drm_display_mode
*omode
, *umode
= &nv_crtc
->base
.mode
;
692 struct drm_crtc
*crtc
= &nv_crtc
->base
;
693 struct nouveau_connector
*nv_connector
;
694 int mode
= DRM_MODE_SCALE_NONE
;
697 /* start off at the resolution we programmed the crtc for, this
698 * effectively handles NONE/FULL scaling
700 nv_connector
= nouveau_crtc_connector_get(nv_crtc
);
701 if (nv_connector
&& nv_connector
->native_mode
)
702 mode
= nv_connector
->scaling_mode
;
704 if (mode
!= DRM_MODE_SCALE_NONE
)
705 omode
= nv_connector
->native_mode
;
709 oX
= omode
->hdisplay
;
710 oY
= omode
->vdisplay
;
711 if (omode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
714 /* add overscan compensation if necessary, will keep the aspect
715 * ratio the same as the backend mode unless overridden by the
716 * user setting both hborder and vborder properties.
718 if (nv_connector
&& ( nv_connector
->underscan
== UNDERSCAN_ON
||
719 (nv_connector
->underscan
== UNDERSCAN_AUTO
&&
720 nv_connector
->edid
&&
721 drm_detect_hdmi_monitor(nv_connector
->edid
)))) {
722 u32 bX
= nv_connector
->underscan_hborder
;
723 u32 bY
= nv_connector
->underscan_vborder
;
724 u32 aspect
= (oY
<< 19) / oX
;
728 if (bY
) oY
-= (bY
* 2);
729 else oY
= ((oX
* aspect
) + (aspect
/ 2)) >> 19;
731 oX
-= (oX
>> 4) + 32;
732 if (bY
) oY
-= (bY
* 2);
733 else oY
= ((oX
* aspect
) + (aspect
/ 2)) >> 19;
737 /* handle CENTER/ASPECT scaling, taking into account the areas
738 * removed already for overscan compensation
741 case DRM_MODE_SCALE_CENTER
:
742 oX
= min((u32
)umode
->hdisplay
, oX
);
743 oY
= min((u32
)umode
->vdisplay
, oY
);
745 case DRM_MODE_SCALE_ASPECT
:
747 u32 aspect
= (umode
->hdisplay
<< 19) / umode
->vdisplay
;
748 oX
= ((oY
* aspect
) + (aspect
/ 2)) >> 19;
750 u32 aspect
= (umode
->vdisplay
<< 19) / umode
->hdisplay
;
751 oY
= ((oX
* aspect
) + (aspect
/ 2)) >> 19;
758 push
= evo_wait(mast
, 8);
760 if (nv50_vers(mast
) < NVD0_DISP_MAST_CLASS
) {
761 /*XXX: SCALE_CTRL_ACTIVE??? */
762 evo_mthd(push
, 0x08d8 + (nv_crtc
->index
* 0x400), 2);
763 evo_data(push
, (oY
<< 16) | oX
);
764 evo_data(push
, (oY
<< 16) | oX
);
765 evo_mthd(push
, 0x08a4 + (nv_crtc
->index
* 0x400), 1);
766 evo_data(push
, 0x00000000);
767 evo_mthd(push
, 0x08c8 + (nv_crtc
->index
* 0x400), 1);
768 evo_data(push
, umode
->vdisplay
<< 16 | umode
->hdisplay
);
770 evo_mthd(push
, 0x04c0 + (nv_crtc
->index
* 0x300), 3);
771 evo_data(push
, (oY
<< 16) | oX
);
772 evo_data(push
, (oY
<< 16) | oX
);
773 evo_data(push
, (oY
<< 16) | oX
);
774 evo_mthd(push
, 0x0494 + (nv_crtc
->index
* 0x300), 1);
775 evo_data(push
, 0x00000000);
776 evo_mthd(push
, 0x04b8 + (nv_crtc
->index
* 0x300), 1);
777 evo_data(push
, umode
->vdisplay
<< 16 | umode
->hdisplay
);
780 evo_kick(push
, mast
);
783 nv50_display_flip_stop(crtc
);
784 nv50_display_flip_next(crtc
, crtc
->fb
, NULL
, 1);
792 nv50_crtc_set_color_vibrance(struct nouveau_crtc
*nv_crtc
, bool update
)
794 struct nv50_mast
*mast
= nv50_mast(nv_crtc
->base
.dev
);
798 adj
= (nv_crtc
->color_vibrance
> 0) ? 50 : 0;
799 vib
= ((nv_crtc
->color_vibrance
* 2047 + adj
) / 100) & 0xfff;
800 hue
= ((nv_crtc
->vibrant_hue
* 2047) / 100) & 0xfff;
802 push
= evo_wait(mast
, 16);
804 if (nv50_vers(mast
) < NVD0_DISP_MAST_CLASS
) {
805 evo_mthd(push
, 0x08a8 + (nv_crtc
->index
* 0x400), 1);
806 evo_data(push
, (hue
<< 20) | (vib
<< 8));
808 evo_mthd(push
, 0x0498 + (nv_crtc
->index
* 0x300), 1);
809 evo_data(push
, (hue
<< 20) | (vib
<< 8));
813 evo_mthd(push
, 0x0080, 1);
814 evo_data(push
, 0x00000000);
816 evo_kick(push
, mast
);
823 nv50_crtc_set_image(struct nouveau_crtc
*nv_crtc
, struct drm_framebuffer
*fb
,
824 int x
, int y
, bool update
)
826 struct nouveau_framebuffer
*nvfb
= nouveau_framebuffer(fb
);
827 struct nv50_mast
*mast
= nv50_mast(nv_crtc
->base
.dev
);
830 push
= evo_wait(mast
, 16);
832 if (nv50_vers(mast
) < NVD0_DISP_MAST_CLASS
) {
833 evo_mthd(push
, 0x0860 + (nv_crtc
->index
* 0x400), 1);
834 evo_data(push
, nvfb
->nvbo
->bo
.offset
>> 8);
835 evo_mthd(push
, 0x0868 + (nv_crtc
->index
* 0x400), 3);
836 evo_data(push
, (fb
->height
<< 16) | fb
->width
);
837 evo_data(push
, nvfb
->r_pitch
);
838 evo_data(push
, nvfb
->r_format
);
839 evo_mthd(push
, 0x08c0 + (nv_crtc
->index
* 0x400), 1);
840 evo_data(push
, (y
<< 16) | x
);
841 if (nv50_vers(mast
) > NV50_DISP_MAST_CLASS
) {
842 evo_mthd(push
, 0x0874 + (nv_crtc
->index
* 0x400), 1);
843 evo_data(push
, nvfb
->r_dma
);
846 evo_mthd(push
, 0x0460 + (nv_crtc
->index
* 0x300), 1);
847 evo_data(push
, nvfb
->nvbo
->bo
.offset
>> 8);
848 evo_mthd(push
, 0x0468 + (nv_crtc
->index
* 0x300), 4);
849 evo_data(push
, (fb
->height
<< 16) | fb
->width
);
850 evo_data(push
, nvfb
->r_pitch
);
851 evo_data(push
, nvfb
->r_format
);
852 evo_data(push
, nvfb
->r_dma
);
853 evo_mthd(push
, 0x04b0 + (nv_crtc
->index
* 0x300), 1);
854 evo_data(push
, (y
<< 16) | x
);
858 evo_mthd(push
, 0x0080, 1);
859 evo_data(push
, 0x00000000);
861 evo_kick(push
, mast
);
864 nv_crtc
->fb
.tile_flags
= nvfb
->r_dma
;
869 nv50_crtc_cursor_show(struct nouveau_crtc
*nv_crtc
)
871 struct nv50_mast
*mast
= nv50_mast(nv_crtc
->base
.dev
);
872 u32
*push
= evo_wait(mast
, 16);
874 if (nv50_vers(mast
) < NV84_DISP_MAST_CLASS
) {
875 evo_mthd(push
, 0x0880 + (nv_crtc
->index
* 0x400), 2);
876 evo_data(push
, 0x85000000);
877 evo_data(push
, nv_crtc
->cursor
.nvbo
->bo
.offset
>> 8);
879 if (nv50_vers(mast
) < NVD0_DISP_MAST_CLASS
) {
880 evo_mthd(push
, 0x0880 + (nv_crtc
->index
* 0x400), 2);
881 evo_data(push
, 0x85000000);
882 evo_data(push
, nv_crtc
->cursor
.nvbo
->bo
.offset
>> 8);
883 evo_mthd(push
, 0x089c + (nv_crtc
->index
* 0x400), 1);
884 evo_data(push
, NvEvoVRAM
);
886 evo_mthd(push
, 0x0480 + (nv_crtc
->index
* 0x300), 2);
887 evo_data(push
, 0x85000000);
888 evo_data(push
, nv_crtc
->cursor
.nvbo
->bo
.offset
>> 8);
889 evo_mthd(push
, 0x048c + (nv_crtc
->index
* 0x300), 1);
890 evo_data(push
, NvEvoVRAM
);
892 evo_kick(push
, mast
);
897 nv50_crtc_cursor_hide(struct nouveau_crtc
*nv_crtc
)
899 struct nv50_mast
*mast
= nv50_mast(nv_crtc
->base
.dev
);
900 u32
*push
= evo_wait(mast
, 16);
902 if (nv50_vers(mast
) < NV84_DISP_MAST_CLASS
) {
903 evo_mthd(push
, 0x0880 + (nv_crtc
->index
* 0x400), 1);
904 evo_data(push
, 0x05000000);
906 if (nv50_vers(mast
) < NVD0_DISP_MAST_CLASS
) {
907 evo_mthd(push
, 0x0880 + (nv_crtc
->index
* 0x400), 1);
908 evo_data(push
, 0x05000000);
909 evo_mthd(push
, 0x089c + (nv_crtc
->index
* 0x400), 1);
910 evo_data(push
, 0x00000000);
912 evo_mthd(push
, 0x0480 + (nv_crtc
->index
* 0x300), 1);
913 evo_data(push
, 0x05000000);
914 evo_mthd(push
, 0x048c + (nv_crtc
->index
* 0x300), 1);
915 evo_data(push
, 0x00000000);
917 evo_kick(push
, mast
);
922 nv50_crtc_cursor_show_hide(struct nouveau_crtc
*nv_crtc
, bool show
, bool update
)
924 struct nv50_mast
*mast
= nv50_mast(nv_crtc
->base
.dev
);
927 nv50_crtc_cursor_show(nv_crtc
);
929 nv50_crtc_cursor_hide(nv_crtc
);
932 u32
*push
= evo_wait(mast
, 2);
934 evo_mthd(push
, 0x0080, 1);
935 evo_data(push
, 0x00000000);
936 evo_kick(push
, mast
);
942 nv50_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
947 nv50_crtc_prepare(struct drm_crtc
*crtc
)
949 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
950 struct nv50_mast
*mast
= nv50_mast(crtc
->dev
);
953 nv50_display_flip_stop(crtc
);
955 push
= evo_wait(mast
, 2);
957 if (nv50_vers(mast
) < NV84_DISP_MAST_CLASS
) {
958 evo_mthd(push
, 0x0874 + (nv_crtc
->index
* 0x400), 1);
959 evo_data(push
, 0x00000000);
960 evo_mthd(push
, 0x0840 + (nv_crtc
->index
* 0x400), 1);
961 evo_data(push
, 0x40000000);
963 if (nv50_vers(mast
) < NVD0_DISP_MAST_CLASS
) {
964 evo_mthd(push
, 0x0874 + (nv_crtc
->index
* 0x400), 1);
965 evo_data(push
, 0x00000000);
966 evo_mthd(push
, 0x0840 + (nv_crtc
->index
* 0x400), 1);
967 evo_data(push
, 0x40000000);
968 evo_mthd(push
, 0x085c + (nv_crtc
->index
* 0x400), 1);
969 evo_data(push
, 0x00000000);
971 evo_mthd(push
, 0x0474 + (nv_crtc
->index
* 0x300), 1);
972 evo_data(push
, 0x00000000);
973 evo_mthd(push
, 0x0440 + (nv_crtc
->index
* 0x300), 1);
974 evo_data(push
, 0x03000000);
975 evo_mthd(push
, 0x045c + (nv_crtc
->index
* 0x300), 1);
976 evo_data(push
, 0x00000000);
979 evo_kick(push
, mast
);
982 nv50_crtc_cursor_show_hide(nv_crtc
, false, false);
986 nv50_crtc_commit(struct drm_crtc
*crtc
)
988 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
989 struct nv50_mast
*mast
= nv50_mast(crtc
->dev
);
992 push
= evo_wait(mast
, 32);
994 if (nv50_vers(mast
) < NV84_DISP_MAST_CLASS
) {
995 evo_mthd(push
, 0x0874 + (nv_crtc
->index
* 0x400), 1);
996 evo_data(push
, NvEvoVRAM_LP
);
997 evo_mthd(push
, 0x0840 + (nv_crtc
->index
* 0x400), 2);
998 evo_data(push
, 0xc0000000);
999 evo_data(push
, nv_crtc
->lut
.nvbo
->bo
.offset
>> 8);
1001 if (nv50_vers(mast
) < NVD0_DISP_MAST_CLASS
) {
1002 evo_mthd(push
, 0x0874 + (nv_crtc
->index
* 0x400), 1);
1003 evo_data(push
, nv_crtc
->fb
.tile_flags
);
1004 evo_mthd(push
, 0x0840 + (nv_crtc
->index
* 0x400), 2);
1005 evo_data(push
, 0xc0000000);
1006 evo_data(push
, nv_crtc
->lut
.nvbo
->bo
.offset
>> 8);
1007 evo_mthd(push
, 0x085c + (nv_crtc
->index
* 0x400), 1);
1008 evo_data(push
, NvEvoVRAM
);
1010 evo_mthd(push
, 0x0474 + (nv_crtc
->index
* 0x300), 1);
1011 evo_data(push
, nv_crtc
->fb
.tile_flags
);
1012 evo_mthd(push
, 0x0440 + (nv_crtc
->index
* 0x300), 4);
1013 evo_data(push
, 0x83000000);
1014 evo_data(push
, nv_crtc
->lut
.nvbo
->bo
.offset
>> 8);
1015 evo_data(push
, 0x00000000);
1016 evo_data(push
, 0x00000000);
1017 evo_mthd(push
, 0x045c + (nv_crtc
->index
* 0x300), 1);
1018 evo_data(push
, NvEvoVRAM
);
1019 evo_mthd(push
, 0x0430 + (nv_crtc
->index
* 0x300), 1);
1020 evo_data(push
, 0xffffff00);
1023 evo_kick(push
, mast
);
1026 nv50_crtc_cursor_show_hide(nv_crtc
, nv_crtc
->cursor
.visible
, true);
1027 nv50_display_flip_next(crtc
, crtc
->fb
, NULL
, 1);
1031 nv50_crtc_mode_fixup(struct drm_crtc
*crtc
, const struct drm_display_mode
*mode
,
1032 struct drm_display_mode
*adjusted_mode
)
1038 nv50_crtc_swap_fbs(struct drm_crtc
*crtc
, struct drm_framebuffer
*old_fb
)
1040 struct nouveau_framebuffer
*nvfb
= nouveau_framebuffer(crtc
->fb
);
1043 ret
= nouveau_bo_pin(nvfb
->nvbo
, TTM_PL_FLAG_VRAM
);
1048 nvfb
= nouveau_framebuffer(old_fb
);
1049 nouveau_bo_unpin(nvfb
->nvbo
);
1056 nv50_crtc_mode_set(struct drm_crtc
*crtc
, struct drm_display_mode
*umode
,
1057 struct drm_display_mode
*mode
, int x
, int y
,
1058 struct drm_framebuffer
*old_fb
)
1060 struct nv50_mast
*mast
= nv50_mast(crtc
->dev
);
1061 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
1062 struct nouveau_connector
*nv_connector
;
1063 u32 ilace
= (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) ? 2 : 1;
1064 u32 vscan
= (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
) ? 2 : 1;
1065 u32 hactive
, hsynce
, hbackp
, hfrontp
, hblanke
, hblanks
;
1066 u32 vactive
, vsynce
, vbackp
, vfrontp
, vblanke
, vblanks
;
1067 u32 vblan2e
= 0, vblan2s
= 1;
1071 hactive
= mode
->htotal
;
1072 hsynce
= mode
->hsync_end
- mode
->hsync_start
- 1;
1073 hbackp
= mode
->htotal
- mode
->hsync_end
;
1074 hblanke
= hsynce
+ hbackp
;
1075 hfrontp
= mode
->hsync_start
- mode
->hdisplay
;
1076 hblanks
= mode
->htotal
- hfrontp
- 1;
1078 vactive
= mode
->vtotal
* vscan
/ ilace
;
1079 vsynce
= ((mode
->vsync_end
- mode
->vsync_start
) * vscan
/ ilace
) - 1;
1080 vbackp
= (mode
->vtotal
- mode
->vsync_end
) * vscan
/ ilace
;
1081 vblanke
= vsynce
+ vbackp
;
1082 vfrontp
= (mode
->vsync_start
- mode
->vdisplay
) * vscan
/ ilace
;
1083 vblanks
= vactive
- vfrontp
- 1;
1084 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
1085 vblan2e
= vactive
+ vsynce
+ vbackp
;
1086 vblan2s
= vblan2e
+ (mode
->vdisplay
* vscan
/ ilace
);
1087 vactive
= (vactive
* 2) + 1;
1090 ret
= nv50_crtc_swap_fbs(crtc
, old_fb
);
1094 push
= evo_wait(mast
, 64);
1096 if (nv50_vers(mast
) < NVD0_DISP_MAST_CLASS
) {
1097 evo_mthd(push
, 0x0804 + (nv_crtc
->index
* 0x400), 2);
1098 evo_data(push
, 0x00800000 | mode
->clock
);
1099 evo_data(push
, (ilace
== 2) ? 2 : 0);
1100 evo_mthd(push
, 0x0810 + (nv_crtc
->index
* 0x400), 6);
1101 evo_data(push
, 0x00000000);
1102 evo_data(push
, (vactive
<< 16) | hactive
);
1103 evo_data(push
, ( vsynce
<< 16) | hsynce
);
1104 evo_data(push
, (vblanke
<< 16) | hblanke
);
1105 evo_data(push
, (vblanks
<< 16) | hblanks
);
1106 evo_data(push
, (vblan2e
<< 16) | vblan2s
);
1107 evo_mthd(push
, 0x082c + (nv_crtc
->index
* 0x400), 1);
1108 evo_data(push
, 0x00000000);
1109 evo_mthd(push
, 0x0900 + (nv_crtc
->index
* 0x400), 2);
1110 evo_data(push
, 0x00000311);
1111 evo_data(push
, 0x00000100);
1113 evo_mthd(push
, 0x0410 + (nv_crtc
->index
* 0x300), 6);
1114 evo_data(push
, 0x00000000);
1115 evo_data(push
, (vactive
<< 16) | hactive
);
1116 evo_data(push
, ( vsynce
<< 16) | hsynce
);
1117 evo_data(push
, (vblanke
<< 16) | hblanke
);
1118 evo_data(push
, (vblanks
<< 16) | hblanks
);
1119 evo_data(push
, (vblan2e
<< 16) | vblan2s
);
1120 evo_mthd(push
, 0x042c + (nv_crtc
->index
* 0x300), 1);
1121 evo_data(push
, 0x00000000); /* ??? */
1122 evo_mthd(push
, 0x0450 + (nv_crtc
->index
* 0x300), 3);
1123 evo_data(push
, mode
->clock
* 1000);
1124 evo_data(push
, 0x00200000); /* ??? */
1125 evo_data(push
, mode
->clock
* 1000);
1126 evo_mthd(push
, 0x04d0 + (nv_crtc
->index
* 0x300), 2);
1127 evo_data(push
, 0x00000311);
1128 evo_data(push
, 0x00000100);
1131 evo_kick(push
, mast
);
1134 nv_connector
= nouveau_crtc_connector_get(nv_crtc
);
1135 nv50_crtc_set_dither(nv_crtc
, false);
1136 nv50_crtc_set_scale(nv_crtc
, false);
1137 nv50_crtc_set_color_vibrance(nv_crtc
, false);
1138 nv50_crtc_set_image(nv_crtc
, crtc
->fb
, x
, y
, false);
1143 nv50_crtc_mode_set_base(struct drm_crtc
*crtc
, int x
, int y
,
1144 struct drm_framebuffer
*old_fb
)
1146 struct nouveau_drm
*drm
= nouveau_drm(crtc
->dev
);
1147 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
1151 NV_DEBUG(drm
, "No FB bound\n");
1155 ret
= nv50_crtc_swap_fbs(crtc
, old_fb
);
1159 nv50_display_flip_stop(crtc
);
1160 nv50_crtc_set_image(nv_crtc
, crtc
->fb
, x
, y
, true);
1161 nv50_display_flip_next(crtc
, crtc
->fb
, NULL
, 1);
1166 nv50_crtc_mode_set_base_atomic(struct drm_crtc
*crtc
,
1167 struct drm_framebuffer
*fb
, int x
, int y
,
1168 enum mode_set_atomic state
)
1170 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
1171 nv50_display_flip_stop(crtc
);
1172 nv50_crtc_set_image(nv_crtc
, fb
, x
, y
, true);
1177 nv50_crtc_lut_load(struct drm_crtc
*crtc
)
1179 struct nv50_disp
*disp
= nv50_disp(crtc
->dev
);
1180 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
1181 void __iomem
*lut
= nvbo_kmap_obj_iovirtual(nv_crtc
->lut
.nvbo
);
1184 for (i
= 0; i
< 256; i
++) {
1185 u16 r
= nv_crtc
->lut
.r
[i
] >> 2;
1186 u16 g
= nv_crtc
->lut
.g
[i
] >> 2;
1187 u16 b
= nv_crtc
->lut
.b
[i
] >> 2;
1189 if (nv_mclass(disp
->core
) < NVD0_DISP_CLASS
) {
1190 writew(r
+ 0x0000, lut
+ (i
* 0x08) + 0);
1191 writew(g
+ 0x0000, lut
+ (i
* 0x08) + 2);
1192 writew(b
+ 0x0000, lut
+ (i
* 0x08) + 4);
1194 writew(r
+ 0x6000, lut
+ (i
* 0x20) + 0);
1195 writew(g
+ 0x6000, lut
+ (i
* 0x20) + 2);
1196 writew(b
+ 0x6000, lut
+ (i
* 0x20) + 4);
1202 nv50_crtc_cursor_set(struct drm_crtc
*crtc
, struct drm_file
*file_priv
,
1203 uint32_t handle
, uint32_t width
, uint32_t height
)
1205 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
1206 struct drm_device
*dev
= crtc
->dev
;
1207 struct drm_gem_object
*gem
;
1208 struct nouveau_bo
*nvbo
;
1209 bool visible
= (handle
!= 0);
1213 if (width
!= 64 || height
!= 64)
1216 gem
= drm_gem_object_lookup(dev
, file_priv
, handle
);
1219 nvbo
= nouveau_gem_object(gem
);
1221 ret
= nouveau_bo_map(nvbo
);
1223 for (i
= 0; i
< 64 * 64; i
++) {
1224 u32 v
= nouveau_bo_rd32(nvbo
, i
);
1225 nouveau_bo_wr32(nv_crtc
->cursor
.nvbo
, i
, v
);
1227 nouveau_bo_unmap(nvbo
);
1230 drm_gem_object_unreference_unlocked(gem
);
1233 if (visible
!= nv_crtc
->cursor
.visible
) {
1234 nv50_crtc_cursor_show_hide(nv_crtc
, visible
, true);
1235 nv_crtc
->cursor
.visible
= visible
;
1242 nv50_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
1244 struct nv50_curs
*curs
= nv50_curs(crtc
);
1245 struct nv50_chan
*chan
= nv50_chan(curs
);
1246 nv_wo32(chan
->user
, 0x0084, (y
<< 16) | (x
& 0xffff));
1247 nv_wo32(chan
->user
, 0x0080, 0x00000000);
1252 nv50_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*r
, u16
*g
, u16
*b
,
1253 uint32_t start
, uint32_t size
)
1255 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
1256 u32 end
= max(start
+ size
, (u32
)256);
1259 for (i
= start
; i
< end
; i
++) {
1260 nv_crtc
->lut
.r
[i
] = r
[i
];
1261 nv_crtc
->lut
.g
[i
] = g
[i
];
1262 nv_crtc
->lut
.b
[i
] = b
[i
];
1265 nv50_crtc_lut_load(crtc
);
1269 nv50_crtc_destroy(struct drm_crtc
*crtc
)
1271 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
1272 struct nv50_disp
*disp
= nv50_disp(crtc
->dev
);
1273 struct nv50_head
*head
= nv50_head(crtc
);
1274 nv50_dmac_destroy(disp
->core
, &head
->ovly
.base
);
1275 nv50_pioc_destroy(disp
->core
, &head
->oimm
.base
);
1276 nv50_dmac_destroy(disp
->core
, &head
->sync
.base
);
1277 nv50_pioc_destroy(disp
->core
, &head
->curs
.base
);
1278 nouveau_bo_unmap(nv_crtc
->cursor
.nvbo
);
1279 if (nv_crtc
->cursor
.nvbo
)
1280 nouveau_bo_unpin(nv_crtc
->cursor
.nvbo
);
1281 nouveau_bo_ref(NULL
, &nv_crtc
->cursor
.nvbo
);
1282 nouveau_bo_unmap(nv_crtc
->lut
.nvbo
);
1283 if (nv_crtc
->lut
.nvbo
)
1284 nouveau_bo_unpin(nv_crtc
->lut
.nvbo
);
1285 nouveau_bo_ref(NULL
, &nv_crtc
->lut
.nvbo
);
1286 drm_crtc_cleanup(crtc
);
1290 static const struct drm_crtc_helper_funcs nv50_crtc_hfunc
= {
1291 .dpms
= nv50_crtc_dpms
,
1292 .prepare
= nv50_crtc_prepare
,
1293 .commit
= nv50_crtc_commit
,
1294 .mode_fixup
= nv50_crtc_mode_fixup
,
1295 .mode_set
= nv50_crtc_mode_set
,
1296 .mode_set_base
= nv50_crtc_mode_set_base
,
1297 .mode_set_base_atomic
= nv50_crtc_mode_set_base_atomic
,
1298 .load_lut
= nv50_crtc_lut_load
,
1301 static const struct drm_crtc_funcs nv50_crtc_func
= {
1302 .cursor_set
= nv50_crtc_cursor_set
,
1303 .cursor_move
= nv50_crtc_cursor_move
,
1304 .gamma_set
= nv50_crtc_gamma_set
,
1305 .set_config
= drm_crtc_helper_set_config
,
1306 .destroy
= nv50_crtc_destroy
,
1307 .page_flip
= nouveau_crtc_page_flip
,
1311 nv50_cursor_set_pos(struct nouveau_crtc
*nv_crtc
, int x
, int y
)
1316 nv50_cursor_set_offset(struct nouveau_crtc
*nv_crtc
, uint32_t offset
)
1321 nv50_crtc_create(struct drm_device
*dev
, struct nouveau_object
*core
, int index
)
1323 struct nv50_disp
*disp
= nv50_disp(dev
);
1324 struct nv50_head
*head
;
1325 struct drm_crtc
*crtc
;
1328 head
= kzalloc(sizeof(*head
), GFP_KERNEL
);
1332 head
->base
.index
= index
;
1333 head
->base
.set_dither
= nv50_crtc_set_dither
;
1334 head
->base
.set_scale
= nv50_crtc_set_scale
;
1335 head
->base
.set_color_vibrance
= nv50_crtc_set_color_vibrance
;
1336 head
->base
.color_vibrance
= 50;
1337 head
->base
.vibrant_hue
= 0;
1338 head
->base
.cursor
.set_offset
= nv50_cursor_set_offset
;
1339 head
->base
.cursor
.set_pos
= nv50_cursor_set_pos
;
1340 for (i
= 0; i
< 256; i
++) {
1341 head
->base
.lut
.r
[i
] = i
<< 8;
1342 head
->base
.lut
.g
[i
] = i
<< 8;
1343 head
->base
.lut
.b
[i
] = i
<< 8;
1346 crtc
= &head
->base
.base
;
1347 drm_crtc_init(dev
, crtc
, &nv50_crtc_func
);
1348 drm_crtc_helper_add(crtc
, &nv50_crtc_hfunc
);
1349 drm_mode_crtc_set_gamma_size(crtc
, 256);
1351 ret
= nouveau_bo_new(dev
, 8192, 0x100, TTM_PL_FLAG_VRAM
,
1352 0, 0x0000, NULL
, &head
->base
.lut
.nvbo
);
1354 ret
= nouveau_bo_pin(head
->base
.lut
.nvbo
, TTM_PL_FLAG_VRAM
);
1356 ret
= nouveau_bo_map(head
->base
.lut
.nvbo
);
1358 nouveau_bo_unpin(head
->base
.lut
.nvbo
);
1361 nouveau_bo_ref(NULL
, &head
->base
.lut
.nvbo
);
1367 nv50_crtc_lut_load(crtc
);
1369 /* allocate cursor resources */
1370 ret
= nv50_pioc_create(disp
->core
, NV50_DISP_CURS_CLASS
, index
,
1371 &(struct nv50_display_curs_class
) {
1373 }, sizeof(struct nv50_display_curs_class
),
1378 ret
= nouveau_bo_new(dev
, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM
,
1379 0, 0x0000, NULL
, &head
->base
.cursor
.nvbo
);
1381 ret
= nouveau_bo_pin(head
->base
.cursor
.nvbo
, TTM_PL_FLAG_VRAM
);
1383 ret
= nouveau_bo_map(head
->base
.cursor
.nvbo
);
1385 nouveau_bo_unpin(head
->base
.lut
.nvbo
);
1388 nouveau_bo_ref(NULL
, &head
->base
.cursor
.nvbo
);
1394 /* allocate page flip / sync resources */
1395 ret
= nv50_dmac_create(disp
->core
, NV50_DISP_SYNC_CLASS
, index
,
1396 &(struct nv50_display_sync_class
) {
1397 .pushbuf
= EVO_PUSH_HANDLE(SYNC
, index
),
1399 }, sizeof(struct nv50_display_sync_class
),
1400 disp
->sync
->bo
.offset
, &head
->sync
.base
);
1404 head
->sync
.addr
= EVO_FLIP_SEM0(index
);
1405 head
->sync
.data
= 0x00000000;
1407 /* allocate overlay resources */
1408 ret
= nv50_pioc_create(disp
->core
, NV50_DISP_OIMM_CLASS
, index
,
1409 &(struct nv50_display_oimm_class
) {
1411 }, sizeof(struct nv50_display_oimm_class
),
1416 ret
= nv50_dmac_create(disp
->core
, NV50_DISP_OVLY_CLASS
, index
,
1417 &(struct nv50_display_ovly_class
) {
1418 .pushbuf
= EVO_PUSH_HANDLE(OVLY
, index
),
1420 }, sizeof(struct nv50_display_ovly_class
),
1421 disp
->sync
->bo
.offset
, &head
->ovly
.base
);
1427 nv50_crtc_destroy(crtc
);
1431 /******************************************************************************
1433 *****************************************************************************/
1435 nv50_dac_dpms(struct drm_encoder
*encoder
, int mode
)
1437 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
1438 struct nv50_disp
*disp
= nv50_disp(encoder
->dev
);
1439 int or = nv_encoder
->or;
1442 dpms_ctrl
= 0x00000000;
1443 if (mode
== DRM_MODE_DPMS_STANDBY
|| mode
== DRM_MODE_DPMS_OFF
)
1444 dpms_ctrl
|= 0x00000001;
1445 if (mode
== DRM_MODE_DPMS_SUSPEND
|| mode
== DRM_MODE_DPMS_OFF
)
1446 dpms_ctrl
|= 0x00000004;
1448 nv_call(disp
->core
, NV50_DISP_DAC_PWR
+ or, dpms_ctrl
);
1452 nv50_dac_mode_fixup(struct drm_encoder
*encoder
,
1453 const struct drm_display_mode
*mode
,
1454 struct drm_display_mode
*adjusted_mode
)
1456 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
1457 struct nouveau_connector
*nv_connector
;
1459 nv_connector
= nouveau_encoder_connector_get(nv_encoder
);
1460 if (nv_connector
&& nv_connector
->native_mode
) {
1461 if (nv_connector
->scaling_mode
!= DRM_MODE_SCALE_NONE
) {
1462 int id
= adjusted_mode
->base
.id
;
1463 *adjusted_mode
= *nv_connector
->native_mode
;
1464 adjusted_mode
->base
.id
= id
;
1472 nv50_dac_commit(struct drm_encoder
*encoder
)
1477 nv50_dac_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
1478 struct drm_display_mode
*adjusted_mode
)
1480 struct nv50_mast
*mast
= nv50_mast(encoder
->dev
);
1481 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
1482 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(encoder
->crtc
);
1485 nv50_dac_dpms(encoder
, DRM_MODE_DPMS_ON
);
1487 push
= evo_wait(mast
, 8);
1489 if (nv50_vers(mast
) < NVD0_DISP_MAST_CLASS
) {
1490 u32 syncs
= 0x00000000;
1492 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
1493 syncs
|= 0x00000001;
1494 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
1495 syncs
|= 0x00000002;
1497 evo_mthd(push
, 0x0400 + (nv_encoder
->or * 0x080), 2);
1498 evo_data(push
, 1 << nv_crtc
->index
);
1499 evo_data(push
, syncs
);
1501 u32 magic
= 0x31ec6000 | (nv_crtc
->index
<< 25);
1502 u32 syncs
= 0x00000001;
1504 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
1505 syncs
|= 0x00000008;
1506 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
1507 syncs
|= 0x00000010;
1509 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1510 magic
|= 0x00000001;
1512 evo_mthd(push
, 0x0404 + (nv_crtc
->index
* 0x300), 2);
1513 evo_data(push
, syncs
);
1514 evo_data(push
, magic
);
1515 evo_mthd(push
, 0x0180 + (nv_encoder
->or * 0x020), 1);
1516 evo_data(push
, 1 << nv_crtc
->index
);
1519 evo_kick(push
, mast
);
1522 nv_encoder
->crtc
= encoder
->crtc
;
1526 nv50_dac_disconnect(struct drm_encoder
*encoder
)
1528 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
1529 struct nv50_mast
*mast
= nv50_mast(encoder
->dev
);
1530 const int or = nv_encoder
->or;
1533 if (nv_encoder
->crtc
) {
1534 nv50_crtc_prepare(nv_encoder
->crtc
);
1536 push
= evo_wait(mast
, 4);
1538 if (nv50_vers(mast
) < NVD0_DISP_MAST_CLASS
) {
1539 evo_mthd(push
, 0x0400 + (or * 0x080), 1);
1540 evo_data(push
, 0x00000000);
1542 evo_mthd(push
, 0x0180 + (or * 0x020), 1);
1543 evo_data(push
, 0x00000000);
1545 evo_kick(push
, mast
);
1549 nv_encoder
->crtc
= NULL
;
1552 static enum drm_connector_status
1553 nv50_dac_detect(struct drm_encoder
*encoder
, struct drm_connector
*connector
)
1555 struct nv50_disp
*disp
= nv50_disp(encoder
->dev
);
1556 int ret
, or = nouveau_encoder(encoder
)->or;
1557 u32 load
= nouveau_drm(encoder
->dev
)->vbios
.dactestval
;
1561 ret
= nv_exec(disp
->core
, NV50_DISP_DAC_LOAD
+ or, &load
, sizeof(load
));
1562 if (ret
|| load
!= 7)
1563 return connector_status_disconnected
;
1565 return connector_status_connected
;
1569 nv50_dac_destroy(struct drm_encoder
*encoder
)
1571 drm_encoder_cleanup(encoder
);
1575 static const struct drm_encoder_helper_funcs nv50_dac_hfunc
= {
1576 .dpms
= nv50_dac_dpms
,
1577 .mode_fixup
= nv50_dac_mode_fixup
,
1578 .prepare
= nv50_dac_disconnect
,
1579 .commit
= nv50_dac_commit
,
1580 .mode_set
= nv50_dac_mode_set
,
1581 .disable
= nv50_dac_disconnect
,
1582 .get_crtc
= nv50_display_crtc_get
,
1583 .detect
= nv50_dac_detect
1586 static const struct drm_encoder_funcs nv50_dac_func
= {
1587 .destroy
= nv50_dac_destroy
,
1591 nv50_dac_create(struct drm_connector
*connector
, struct dcb_output
*dcbe
)
1593 struct nouveau_drm
*drm
= nouveau_drm(connector
->dev
);
1594 struct nouveau_i2c
*i2c
= nouveau_i2c(drm
->device
);
1595 struct nouveau_encoder
*nv_encoder
;
1596 struct drm_encoder
*encoder
;
1597 int type
= DRM_MODE_ENCODER_DAC
;
1599 nv_encoder
= kzalloc(sizeof(*nv_encoder
), GFP_KERNEL
);
1602 nv_encoder
->dcb
= dcbe
;
1603 nv_encoder
->or = ffs(dcbe
->or) - 1;
1604 nv_encoder
->i2c
= i2c
->find(i2c
, dcbe
->i2c_index
);
1606 encoder
= to_drm_encoder(nv_encoder
);
1607 encoder
->possible_crtcs
= dcbe
->heads
;
1608 encoder
->possible_clones
= 0;
1609 drm_encoder_init(connector
->dev
, encoder
, &nv50_dac_func
, type
);
1610 drm_encoder_helper_add(encoder
, &nv50_dac_hfunc
);
1612 drm_mode_connector_attach_encoder(connector
, encoder
);
1616 /******************************************************************************
1618 *****************************************************************************/
1620 nv50_audio_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
)
1622 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
1623 struct nouveau_connector
*nv_connector
;
1624 struct nv50_disp
*disp
= nv50_disp(encoder
->dev
);
1626 nv_connector
= nouveau_encoder_connector_get(nv_encoder
);
1627 if (!drm_detect_monitor_audio(nv_connector
->edid
))
1630 drm_edid_to_eld(&nv_connector
->base
, nv_connector
->edid
);
1632 nv_exec(disp
->core
, NVA3_DISP_SOR_HDA_ELD
+ nv_encoder
->or,
1633 nv_connector
->base
.eld
,
1634 nv_connector
->base
.eld
[2] * 4);
1638 nv50_audio_disconnect(struct drm_encoder
*encoder
)
1640 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
1641 struct nv50_disp
*disp
= nv50_disp(encoder
->dev
);
1643 nv_exec(disp
->core
, NVA3_DISP_SOR_HDA_ELD
+ nv_encoder
->or, NULL
, 0);
1646 /******************************************************************************
1648 *****************************************************************************/
1650 nv50_hdmi_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
)
1652 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
1653 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(encoder
->crtc
);
1654 struct nouveau_connector
*nv_connector
;
1655 struct nv50_disp
*disp
= nv50_disp(encoder
->dev
);
1656 const u32 moff
= (nv_crtc
->index
<< 3) | nv_encoder
->or;
1657 u32 rekey
= 56; /* binary driver, and tegra constant */
1660 nv_connector
= nouveau_encoder_connector_get(nv_encoder
);
1661 if (!drm_detect_hdmi_monitor(nv_connector
->edid
))
1664 max_ac_packet
= mode
->htotal
- mode
->hdisplay
;
1665 max_ac_packet
-= rekey
;
1666 max_ac_packet
-= 18; /* constant from tegra */
1667 max_ac_packet
/= 32;
1669 nv_call(disp
->core
, NV84_DISP_SOR_HDMI_PWR
+ moff
,
1670 NV84_DISP_SOR_HDMI_PWR_STATE_ON
|
1671 (max_ac_packet
<< 16) | rekey
);
1673 nv50_audio_mode_set(encoder
, mode
);
1677 nv50_hdmi_disconnect(struct drm_encoder
*encoder
)
1679 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
1680 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(nv_encoder
->crtc
);
1681 struct nv50_disp
*disp
= nv50_disp(encoder
->dev
);
1682 const u32 moff
= (nv_crtc
->index
<< 3) | nv_encoder
->or;
1684 nv50_audio_disconnect(encoder
);
1686 nv_call(disp
->core
, NV84_DISP_SOR_HDMI_PWR
+ moff
, 0x00000000);
1689 /******************************************************************************
1691 *****************************************************************************/
1693 nv50_sor_dpms(struct drm_encoder
*encoder
, int mode
)
1695 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
1696 struct drm_device
*dev
= encoder
->dev
;
1697 struct nv50_disp
*disp
= nv50_disp(dev
);
1698 struct drm_encoder
*partner
;
1699 int or = nv_encoder
->or;
1701 nv_encoder
->last_dpms
= mode
;
1703 list_for_each_entry(partner
, &dev
->mode_config
.encoder_list
, head
) {
1704 struct nouveau_encoder
*nv_partner
= nouveau_encoder(partner
);
1706 if (partner
->encoder_type
!= DRM_MODE_ENCODER_TMDS
)
1709 if (nv_partner
!= nv_encoder
&&
1710 nv_partner
->dcb
->or == nv_encoder
->dcb
->or) {
1711 if (nv_partner
->last_dpms
== DRM_MODE_DPMS_ON
)
1717 nv_call(disp
->core
, NV50_DISP_SOR_PWR
+ or, (mode
== DRM_MODE_DPMS_ON
));
1721 nv50_sor_mode_fixup(struct drm_encoder
*encoder
,
1722 const struct drm_display_mode
*mode
,
1723 struct drm_display_mode
*adjusted_mode
)
1725 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
1726 struct nouveau_connector
*nv_connector
;
1728 nv_connector
= nouveau_encoder_connector_get(nv_encoder
);
1729 if (nv_connector
&& nv_connector
->native_mode
) {
1730 if (nv_connector
->scaling_mode
!= DRM_MODE_SCALE_NONE
) {
1731 int id
= adjusted_mode
->base
.id
;
1732 *adjusted_mode
= *nv_connector
->native_mode
;
1733 adjusted_mode
->base
.id
= id
;
1741 nv50_sor_disconnect(struct drm_encoder
*encoder
)
1743 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
1744 struct nv50_mast
*mast
= nv50_mast(encoder
->dev
);
1745 const int or = nv_encoder
->or;
1748 if (nv_encoder
->crtc
) {
1749 nv50_crtc_prepare(nv_encoder
->crtc
);
1751 push
= evo_wait(mast
, 4);
1753 if (nv50_vers(mast
) < NVD0_DISP_MAST_CLASS
) {
1754 evo_mthd(push
, 0x0600 + (or * 0x40), 1);
1755 evo_data(push
, 0x00000000);
1757 evo_mthd(push
, 0x0200 + (or * 0x20), 1);
1758 evo_data(push
, 0x00000000);
1760 evo_kick(push
, mast
);
1763 nv50_hdmi_disconnect(encoder
);
1766 nv_encoder
->last_dpms
= DRM_MODE_DPMS_OFF
;
1767 nv_encoder
->crtc
= NULL
;
1771 nv50_sor_commit(struct drm_encoder
*encoder
)
1776 nv50_sor_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*umode
,
1777 struct drm_display_mode
*mode
)
1779 struct nv50_disp
*disp
= nv50_disp(encoder
->dev
);
1780 struct nv50_mast
*mast
= nv50_mast(encoder
->dev
);
1781 struct drm_device
*dev
= encoder
->dev
;
1782 struct nouveau_drm
*drm
= nouveau_drm(dev
);
1783 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
1784 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(encoder
->crtc
);
1785 struct nouveau_connector
*nv_connector
;
1786 struct nvbios
*bios
= &drm
->vbios
;
1787 u32
*push
, lvds
= 0;
1788 u8 owner
= 1 << nv_crtc
->index
;
1792 nv_connector
= nouveau_encoder_connector_get(nv_encoder
);
1793 switch (nv_encoder
->dcb
->type
) {
1794 case DCB_OUTPUT_TMDS
:
1795 if (nv_encoder
->dcb
->sorconf
.link
& 1) {
1796 if (mode
->clock
< 165000)
1804 nv50_hdmi_mode_set(encoder
, mode
);
1806 case DCB_OUTPUT_LVDS
:
1809 if (bios
->fp_no_ddc
) {
1810 if (bios
->fp
.dual_link
)
1812 if (bios
->fp
.if_is_24bit
)
1815 if (nv_connector
->type
== DCB_CONNECTOR_LVDS_SPWG
) {
1816 if (((u8
*)nv_connector
->edid
)[121] == 2)
1819 if (mode
->clock
>= bios
->fp
.duallink_transition_clk
) {
1823 if (lvds
& 0x0100) {
1824 if (bios
->fp
.strapless_is_24bit
& 2)
1827 if (bios
->fp
.strapless_is_24bit
& 1)
1831 if (nv_connector
->base
.display_info
.bpc
== 8)
1835 nv_call(disp
->core
, NV50_DISP_SOR_LVDS_SCRIPT
+ nv_encoder
->or, lvds
);
1838 if (nv_connector
->base
.display_info
.bpc
== 6) {
1839 nv_encoder
->dp
.datarate
= mode
->clock
* 18 / 8;
1842 if (nv_connector
->base
.display_info
.bpc
== 8) {
1843 nv_encoder
->dp
.datarate
= mode
->clock
* 24 / 8;
1846 nv_encoder
->dp
.datarate
= mode
->clock
* 30 / 8;
1850 if (nv_encoder
->dcb
->sorconf
.link
& 1)
1860 nv50_sor_dpms(encoder
, DRM_MODE_DPMS_ON
);
1862 push
= evo_wait(nv50_mast(dev
), 8);
1864 if (nv50_vers(mast
) < NVD0_DISP_CLASS
) {
1865 u32 ctrl
= (depth
<< 16) | (proto
<< 8) | owner
;
1866 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
1868 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
1870 evo_mthd(push
, 0x0600 + (nv_encoder
->or * 0x040), 1);
1871 evo_data(push
, ctrl
);
1873 u32 magic
= 0x31ec6000 | (nv_crtc
->index
<< 25);
1874 u32 syncs
= 0x00000001;
1876 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
1877 syncs
|= 0x00000008;
1878 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
1879 syncs
|= 0x00000010;
1881 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1882 magic
|= 0x00000001;
1884 evo_mthd(push
, 0x0404 + (nv_crtc
->index
* 0x300), 2);
1885 evo_data(push
, syncs
| (depth
<< 6));
1886 evo_data(push
, magic
);
1887 evo_mthd(push
, 0x0200 + (nv_encoder
->or * 0x020), 1);
1888 evo_data(push
, owner
| (proto
<< 8));
1891 evo_kick(push
, mast
);
1894 nv_encoder
->crtc
= encoder
->crtc
;
1898 nv50_sor_destroy(struct drm_encoder
*encoder
)
1900 drm_encoder_cleanup(encoder
);
1904 static const struct drm_encoder_helper_funcs nv50_sor_hfunc
= {
1905 .dpms
= nv50_sor_dpms
,
1906 .mode_fixup
= nv50_sor_mode_fixup
,
1907 .prepare
= nv50_sor_disconnect
,
1908 .commit
= nv50_sor_commit
,
1909 .mode_set
= nv50_sor_mode_set
,
1910 .disable
= nv50_sor_disconnect
,
1911 .get_crtc
= nv50_display_crtc_get
,
1914 static const struct drm_encoder_funcs nv50_sor_func
= {
1915 .destroy
= nv50_sor_destroy
,
1919 nv50_sor_create(struct drm_connector
*connector
, struct dcb_output
*dcbe
)
1921 struct nouveau_drm
*drm
= nouveau_drm(connector
->dev
);
1922 struct nouveau_i2c
*i2c
= nouveau_i2c(drm
->device
);
1923 struct nouveau_encoder
*nv_encoder
;
1924 struct drm_encoder
*encoder
;
1927 switch (dcbe
->type
) {
1928 case DCB_OUTPUT_LVDS
: type
= DRM_MODE_ENCODER_LVDS
; break;
1929 case DCB_OUTPUT_TMDS
:
1932 type
= DRM_MODE_ENCODER_TMDS
;
1936 nv_encoder
= kzalloc(sizeof(*nv_encoder
), GFP_KERNEL
);
1939 nv_encoder
->dcb
= dcbe
;
1940 nv_encoder
->or = ffs(dcbe
->or) - 1;
1941 nv_encoder
->i2c
= i2c
->find(i2c
, dcbe
->i2c_index
);
1942 nv_encoder
->last_dpms
= DRM_MODE_DPMS_OFF
;
1944 encoder
= to_drm_encoder(nv_encoder
);
1945 encoder
->possible_crtcs
= dcbe
->heads
;
1946 encoder
->possible_clones
= 0;
1947 drm_encoder_init(connector
->dev
, encoder
, &nv50_sor_func
, type
);
1948 drm_encoder_helper_add(encoder
, &nv50_sor_hfunc
);
1950 drm_mode_connector_attach_encoder(connector
, encoder
);
1954 /******************************************************************************
1956 *****************************************************************************/
1959 nv50_pior_dpms(struct drm_encoder
*encoder
, int mode
)
1961 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
1962 struct nv50_disp
*disp
= nv50_disp(encoder
->dev
);
1963 u32 mthd
= (nv_encoder
->dcb
->type
<< 12) | nv_encoder
->or;
1964 u32 ctrl
= (mode
== DRM_MODE_DPMS_ON
);
1965 nv_call(disp
->core
, NV50_DISP_PIOR_PWR
+ mthd
, ctrl
);
1969 nv50_pior_mode_fixup(struct drm_encoder
*encoder
,
1970 const struct drm_display_mode
*mode
,
1971 struct drm_display_mode
*adjusted_mode
)
1973 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
1974 struct nouveau_connector
*nv_connector
;
1976 nv_connector
= nouveau_encoder_connector_get(nv_encoder
);
1977 if (nv_connector
&& nv_connector
->native_mode
) {
1978 if (nv_connector
->scaling_mode
!= DRM_MODE_SCALE_NONE
) {
1979 int id
= adjusted_mode
->base
.id
;
1980 *adjusted_mode
= *nv_connector
->native_mode
;
1981 adjusted_mode
->base
.id
= id
;
1985 adjusted_mode
->clock
*= 2;
1990 nv50_pior_commit(struct drm_encoder
*encoder
)
1995 nv50_pior_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
1996 struct drm_display_mode
*adjusted_mode
)
1998 struct nv50_mast
*mast
= nv50_mast(encoder
->dev
);
1999 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
2000 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(encoder
->crtc
);
2001 struct nouveau_connector
*nv_connector
;
2002 u8 owner
= 1 << nv_crtc
->index
;
2006 nv_connector
= nouveau_encoder_connector_get(nv_encoder
);
2007 switch (nv_connector
->base
.display_info
.bpc
) {
2008 case 10: depth
= 0x6; break;
2009 case 8: depth
= 0x5; break;
2010 case 6: depth
= 0x2; break;
2011 default: depth
= 0x0; break;
2014 switch (nv_encoder
->dcb
->type
) {
2015 case DCB_OUTPUT_TMDS
:
2024 nv50_pior_dpms(encoder
, DRM_MODE_DPMS_ON
);
2026 push
= evo_wait(mast
, 8);
2028 if (nv50_vers(mast
) < NVD0_DISP_MAST_CLASS
) {
2029 u32 ctrl
= (depth
<< 16) | (proto
<< 8) | owner
;
2030 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
2032 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
2034 evo_mthd(push
, 0x0700 + (nv_encoder
->or * 0x040), 1);
2035 evo_data(push
, ctrl
);
2038 evo_kick(push
, mast
);
2041 nv_encoder
->crtc
= encoder
->crtc
;
2045 nv50_pior_disconnect(struct drm_encoder
*encoder
)
2047 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
2048 struct nv50_mast
*mast
= nv50_mast(encoder
->dev
);
2049 const int or = nv_encoder
->or;
2052 if (nv_encoder
->crtc
) {
2053 nv50_crtc_prepare(nv_encoder
->crtc
);
2055 push
= evo_wait(mast
, 4);
2057 if (nv50_vers(mast
) < NVD0_DISP_MAST_CLASS
) {
2058 evo_mthd(push
, 0x0700 + (or * 0x040), 1);
2059 evo_data(push
, 0x00000000);
2061 evo_kick(push
, mast
);
2065 nv_encoder
->crtc
= NULL
;
2069 nv50_pior_destroy(struct drm_encoder
*encoder
)
2071 drm_encoder_cleanup(encoder
);
2075 static const struct drm_encoder_helper_funcs nv50_pior_hfunc
= {
2076 .dpms
= nv50_pior_dpms
,
2077 .mode_fixup
= nv50_pior_mode_fixup
,
2078 .prepare
= nv50_pior_disconnect
,
2079 .commit
= nv50_pior_commit
,
2080 .mode_set
= nv50_pior_mode_set
,
2081 .disable
= nv50_pior_disconnect
,
2082 .get_crtc
= nv50_display_crtc_get
,
2085 static const struct drm_encoder_funcs nv50_pior_func
= {
2086 .destroy
= nv50_pior_destroy
,
2090 nv50_pior_create(struct drm_connector
*connector
, struct dcb_output
*dcbe
)
2092 struct nouveau_drm
*drm
= nouveau_drm(connector
->dev
);
2093 struct nouveau_i2c
*i2c
= nouveau_i2c(drm
->device
);
2094 struct nouveau_i2c_port
*ddc
= NULL
;
2095 struct nouveau_encoder
*nv_encoder
;
2096 struct drm_encoder
*encoder
;
2099 switch (dcbe
->type
) {
2100 case DCB_OUTPUT_TMDS
:
2101 ddc
= i2c
->find_type(i2c
, NV_I2C_TYPE_EXTDDC(dcbe
->extdev
));
2102 type
= DRM_MODE_ENCODER_TMDS
;
2105 ddc
= i2c
->find_type(i2c
, NV_I2C_TYPE_EXTAUX(dcbe
->extdev
));
2106 type
= DRM_MODE_ENCODER_TMDS
;
2112 nv_encoder
= kzalloc(sizeof(*nv_encoder
), GFP_KERNEL
);
2115 nv_encoder
->dcb
= dcbe
;
2116 nv_encoder
->or = ffs(dcbe
->or) - 1;
2117 nv_encoder
->i2c
= ddc
;
2119 encoder
= to_drm_encoder(nv_encoder
);
2120 encoder
->possible_crtcs
= dcbe
->heads
;
2121 encoder
->possible_clones
= 0;
2122 drm_encoder_init(connector
->dev
, encoder
, &nv50_pior_func
, type
);
2123 drm_encoder_helper_add(encoder
, &nv50_pior_hfunc
);
2125 drm_mode_connector_attach_encoder(connector
, encoder
);
2129 /******************************************************************************
2131 *****************************************************************************/
2133 nv50_display_fini(struct drm_device
*dev
)
2138 nv50_display_init(struct drm_device
*dev
)
2140 struct nv50_disp
*disp
= nv50_disp(dev
);
2141 struct drm_crtc
*crtc
;
2144 push
= evo_wait(nv50_mast(dev
), 32);
2148 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2149 struct nv50_sync
*sync
= nv50_sync(crtc
);
2150 nouveau_bo_wr32(disp
->sync
, sync
->addr
/ 4, sync
->data
);
2153 evo_mthd(push
, 0x0088, 1);
2154 evo_data(push
, NvEvoSync
);
2155 evo_kick(push
, nv50_mast(dev
));
2160 nv50_display_destroy(struct drm_device
*dev
)
2162 struct nv50_disp
*disp
= nv50_disp(dev
);
2164 nv50_dmac_destroy(disp
->core
, &disp
->mast
.base
);
2166 nouveau_bo_unmap(disp
->sync
);
2168 nouveau_bo_unpin(disp
->sync
);
2169 nouveau_bo_ref(NULL
, &disp
->sync
);
2171 nouveau_display(dev
)->priv
= NULL
;
2176 nv50_display_create(struct drm_device
*dev
)
2178 static const u16 oclass
[] = {
2188 struct nouveau_device
*device
= nouveau_dev(dev
);
2189 struct nouveau_drm
*drm
= nouveau_drm(dev
);
2190 struct dcb_table
*dcb
= &drm
->vbios
.dcb
;
2191 struct drm_connector
*connector
, *tmp
;
2192 struct nv50_disp
*disp
;
2193 struct dcb_output
*dcbe
;
2196 disp
= kzalloc(sizeof(*disp
), GFP_KERNEL
);
2200 nouveau_display(dev
)->priv
= disp
;
2201 nouveau_display(dev
)->dtor
= nv50_display_destroy
;
2202 nouveau_display(dev
)->init
= nv50_display_init
;
2203 nouveau_display(dev
)->fini
= nv50_display_fini
;
2205 /* small shared memory area we use for notifiers and semaphores */
2206 ret
= nouveau_bo_new(dev
, 4096, 0x1000, TTM_PL_FLAG_VRAM
,
2207 0, 0x0000, NULL
, &disp
->sync
);
2209 ret
= nouveau_bo_pin(disp
->sync
, TTM_PL_FLAG_VRAM
);
2211 ret
= nouveau_bo_map(disp
->sync
);
2213 nouveau_bo_unpin(disp
->sync
);
2216 nouveau_bo_ref(NULL
, &disp
->sync
);
2222 /* attempt to allocate a supported evo display class */
2224 for (i
= 0; ret
&& i
< ARRAY_SIZE(oclass
); i
++) {
2225 ret
= nouveau_object_new(nv_object(drm
), NVDRM_DEVICE
,
2226 0xd1500000, oclass
[i
], NULL
, 0,
2233 /* allocate master evo channel */
2234 ret
= nv50_dmac_create(disp
->core
, NV50_DISP_MAST_CLASS
, 0,
2235 &(struct nv50_display_mast_class
) {
2236 .pushbuf
= EVO_PUSH_HANDLE(MAST
, 0),
2237 }, sizeof(struct nv50_display_mast_class
),
2238 disp
->sync
->bo
.offset
, &disp
->mast
.base
);
2242 /* create crtc objects to represent the hw heads */
2243 if (nv_mclass(disp
->core
) >= NVD0_DISP_CLASS
)
2244 crtcs
= nv_rd32(device
, 0x022448);
2248 for (i
= 0; i
< crtcs
; i
++) {
2249 ret
= nv50_crtc_create(dev
, disp
->core
, i
);
2254 /* create encoder/connector objects based on VBIOS DCB table */
2255 for (i
= 0, dcbe
= &dcb
->entry
[0]; i
< dcb
->entries
; i
++, dcbe
++) {
2256 connector
= nouveau_connector_create(dev
, dcbe
->connector
);
2257 if (IS_ERR(connector
))
2260 if (dcbe
->location
== DCB_LOC_ON_CHIP
) {
2261 switch (dcbe
->type
) {
2262 case DCB_OUTPUT_TMDS
:
2263 case DCB_OUTPUT_LVDS
:
2265 ret
= nv50_sor_create(connector
, dcbe
);
2267 case DCB_OUTPUT_ANALOG
:
2268 ret
= nv50_dac_create(connector
, dcbe
);
2275 ret
= nv50_pior_create(connector
, dcbe
);
2279 NV_WARN(drm
, "failed to create encoder %d/%d/%d: %d\n",
2280 dcbe
->location
, dcbe
->type
,
2281 ffs(dcbe
->or) - 1, ret
);
2286 /* cull any connectors we created that don't have an encoder */
2287 list_for_each_entry_safe(connector
, tmp
, &dev
->mode_config
.connector_list
, head
) {
2288 if (connector
->encoder_ids
[0])
2291 NV_WARN(drm
, "%s has no encoders, removing\n",
2292 drm_get_connector_name(connector
));
2293 connector
->funcs
->destroy(connector
);
2298 nv50_display_destroy(dev
);