2 * Copyright 2011 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/dma-mapping.h>
28 #include <drm/drm_crtc_helper.h>
29 #include <drm/drm_plane_helper.h>
30 #include <drm/drm_dp_helper.h>
31 #include <drm/drm_fb_helper.h>
33 #include <nvif/class.h>
34 #include <nvif/cl0002.h>
35 #include <nvif/cl5070.h>
36 #include <nvif/cl507a.h>
37 #include <nvif/cl507b.h>
38 #include <nvif/cl507c.h>
39 #include <nvif/cl507d.h>
40 #include <nvif/cl507e.h>
42 #include "nouveau_drv.h"
43 #include "nouveau_dma.h"
44 #include "nouveau_gem.h"
45 #include "nouveau_connector.h"
46 #include "nouveau_encoder.h"
47 #include "nouveau_crtc.h"
48 #include "nouveau_fence.h"
49 #include "nv50_display.h"
53 #define EVO_MASTER (0x00)
54 #define EVO_FLIP(c) (0x01 + (c))
55 #define EVO_OVLY(c) (0x05 + (c))
56 #define EVO_OIMM(c) (0x09 + (c))
57 #define EVO_CURS(c) (0x0d + (c))
59 /* offsets in shared sync bo of various structures */
60 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
61 #define EVO_MAST_NTFY EVO_SYNC( 0, 0x00)
62 #define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00)
63 #define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10)
65 /******************************************************************************
67 *****************************************************************************/
70 struct nvif_object user
;
71 struct nvif_device
*device
;
75 nv50_chan_create(struct nvif_device
*device
, struct nvif_object
*disp
,
76 const s32
*oclass
, u8 head
, void *data
, u32 size
,
77 struct nv50_chan
*chan
)
79 struct nvif_sclass
*sclass
;
82 chan
->device
= device
;
84 ret
= n
= nvif_object_sclass_get(disp
, &sclass
);
89 for (i
= 0; i
< n
; i
++) {
90 if (sclass
[i
].oclass
== oclass
[0]) {
91 ret
= nvif_object_init(disp
, 0, oclass
[0],
92 data
, size
, &chan
->user
);
94 nvif_object_map(&chan
->user
);
95 nvif_object_sclass_put(&sclass
);
102 nvif_object_sclass_put(&sclass
);
107 nv50_chan_destroy(struct nv50_chan
*chan
)
109 nvif_object_fini(&chan
->user
);
112 /******************************************************************************
114 *****************************************************************************/
117 struct nv50_chan base
;
121 nv50_pioc_destroy(struct nv50_pioc
*pioc
)
123 nv50_chan_destroy(&pioc
->base
);
127 nv50_pioc_create(struct nvif_device
*device
, struct nvif_object
*disp
,
128 const s32
*oclass
, u8 head
, void *data
, u32 size
,
129 struct nv50_pioc
*pioc
)
131 return nv50_chan_create(device
, disp
, oclass
, head
, data
, size
,
135 /******************************************************************************
137 *****************************************************************************/
140 struct nv50_pioc base
;
144 nv50_curs_create(struct nvif_device
*device
, struct nvif_object
*disp
,
145 int head
, struct nv50_curs
*curs
)
147 struct nv50_disp_cursor_v0 args
= {
150 static const s32 oclass
[] = {
159 return nv50_pioc_create(device
, disp
, oclass
, head
, &args
, sizeof(args
),
163 /******************************************************************************
165 *****************************************************************************/
168 struct nv50_pioc base
;
172 nv50_oimm_create(struct nvif_device
*device
, struct nvif_object
*disp
,
173 int head
, struct nv50_oimm
*oimm
)
175 struct nv50_disp_cursor_v0 args
= {
178 static const s32 oclass
[] = {
187 return nv50_pioc_create(device
, disp
, oclass
, head
, &args
, sizeof(args
),
191 /******************************************************************************
193 *****************************************************************************/
196 struct nv50_chan base
;
200 struct nvif_object sync
;
201 struct nvif_object vram
;
203 /* Protects against concurrent pushbuf access to this channel, lock is
204 * grabbed by evo_wait (if the pushbuf reservation is successful) and
205 * dropped again by evo_kick. */
210 nv50_dmac_destroy(struct nv50_dmac
*dmac
, struct nvif_object
*disp
)
212 struct nvif_device
*device
= dmac
->base
.device
;
214 nvif_object_fini(&dmac
->vram
);
215 nvif_object_fini(&dmac
->sync
);
217 nv50_chan_destroy(&dmac
->base
);
220 struct device
*dev
= nvxx_device(device
)->dev
;
221 dma_free_coherent(dev
, PAGE_SIZE
, dmac
->ptr
, dmac
->handle
);
226 nv50_dmac_create(struct nvif_device
*device
, struct nvif_object
*disp
,
227 const s32
*oclass
, u8 head
, void *data
, u32 size
, u64 syncbuf
,
228 struct nv50_dmac
*dmac
)
230 struct nv50_disp_core_channel_dma_v0
*args
= data
;
231 struct nvif_object pushbuf
;
234 mutex_init(&dmac
->lock
);
236 dmac
->ptr
= dma_alloc_coherent(nvxx_device(device
)->dev
, PAGE_SIZE
,
237 &dmac
->handle
, GFP_KERNEL
);
241 ret
= nvif_object_init(&device
->object
, 0, NV_DMA_FROM_MEMORY
,
242 &(struct nv_dma_v0
) {
243 .target
= NV_DMA_V0_TARGET_PCI_US
,
244 .access
= NV_DMA_V0_ACCESS_RD
,
245 .start
= dmac
->handle
+ 0x0000,
246 .limit
= dmac
->handle
+ 0x0fff,
247 }, sizeof(struct nv_dma_v0
), &pushbuf
);
251 args
->pushbuf
= nvif_handle(&pushbuf
);
253 ret
= nv50_chan_create(device
, disp
, oclass
, head
, data
, size
,
255 nvif_object_fini(&pushbuf
);
259 ret
= nvif_object_init(&dmac
->base
.user
, 0xf0000000, NV_DMA_IN_MEMORY
,
260 &(struct nv_dma_v0
) {
261 .target
= NV_DMA_V0_TARGET_VRAM
,
262 .access
= NV_DMA_V0_ACCESS_RDWR
,
263 .start
= syncbuf
+ 0x0000,
264 .limit
= syncbuf
+ 0x0fff,
265 }, sizeof(struct nv_dma_v0
),
270 ret
= nvif_object_init(&dmac
->base
.user
, 0xf0000001, NV_DMA_IN_MEMORY
,
271 &(struct nv_dma_v0
) {
272 .target
= NV_DMA_V0_TARGET_VRAM
,
273 .access
= NV_DMA_V0_ACCESS_RDWR
,
275 .limit
= device
->info
.ram_user
- 1,
276 }, sizeof(struct nv_dma_v0
),
284 /******************************************************************************
286 *****************************************************************************/
289 struct nv50_dmac base
;
293 nv50_core_create(struct nvif_device
*device
, struct nvif_object
*disp
,
294 u64 syncbuf
, struct nv50_mast
*core
)
296 struct nv50_disp_core_channel_dma_v0 args
= {
297 .pushbuf
= 0xb0007d00,
299 static const s32 oclass
[] = {
300 GP104_DISP_CORE_CHANNEL_DMA
,
301 GP100_DISP_CORE_CHANNEL_DMA
,
302 GM200_DISP_CORE_CHANNEL_DMA
,
303 GM107_DISP_CORE_CHANNEL_DMA
,
304 GK110_DISP_CORE_CHANNEL_DMA
,
305 GK104_DISP_CORE_CHANNEL_DMA
,
306 GF110_DISP_CORE_CHANNEL_DMA
,
307 GT214_DISP_CORE_CHANNEL_DMA
,
308 GT206_DISP_CORE_CHANNEL_DMA
,
309 GT200_DISP_CORE_CHANNEL_DMA
,
310 G82_DISP_CORE_CHANNEL_DMA
,
311 NV50_DISP_CORE_CHANNEL_DMA
,
315 return nv50_dmac_create(device
, disp
, oclass
, 0, &args
, sizeof(args
),
316 syncbuf
, &core
->base
);
319 /******************************************************************************
321 *****************************************************************************/
324 struct nv50_dmac base
;
330 nv50_base_create(struct nvif_device
*device
, struct nvif_object
*disp
,
331 int head
, u64 syncbuf
, struct nv50_sync
*base
)
333 struct nv50_disp_base_channel_dma_v0 args
= {
334 .pushbuf
= 0xb0007c00 | head
,
337 static const s32 oclass
[] = {
338 GK110_DISP_BASE_CHANNEL_DMA
,
339 GK104_DISP_BASE_CHANNEL_DMA
,
340 GF110_DISP_BASE_CHANNEL_DMA
,
341 GT214_DISP_BASE_CHANNEL_DMA
,
342 GT200_DISP_BASE_CHANNEL_DMA
,
343 G82_DISP_BASE_CHANNEL_DMA
,
344 NV50_DISP_BASE_CHANNEL_DMA
,
348 return nv50_dmac_create(device
, disp
, oclass
, head
, &args
, sizeof(args
),
349 syncbuf
, &base
->base
);
352 /******************************************************************************
354 *****************************************************************************/
357 struct nv50_dmac base
;
361 nv50_ovly_create(struct nvif_device
*device
, struct nvif_object
*disp
,
362 int head
, u64 syncbuf
, struct nv50_ovly
*ovly
)
364 struct nv50_disp_overlay_channel_dma_v0 args
= {
365 .pushbuf
= 0xb0007e00 | head
,
368 static const s32 oclass
[] = {
369 GK104_DISP_OVERLAY_CONTROL_DMA
,
370 GF110_DISP_OVERLAY_CONTROL_DMA
,
371 GT214_DISP_OVERLAY_CHANNEL_DMA
,
372 GT200_DISP_OVERLAY_CHANNEL_DMA
,
373 G82_DISP_OVERLAY_CHANNEL_DMA
,
374 NV50_DISP_OVERLAY_CHANNEL_DMA
,
378 return nv50_dmac_create(device
, disp
, oclass
, head
, &args
, sizeof(args
),
379 syncbuf
, &ovly
->base
);
383 struct nouveau_crtc base
;
384 struct nouveau_bo
*image
;
385 struct nv50_curs curs
;
386 struct nv50_sync sync
;
387 struct nv50_ovly ovly
;
388 struct nv50_oimm oimm
;
391 #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
392 #define nv50_curs(c) (&nv50_head(c)->curs)
393 #define nv50_sync(c) (&nv50_head(c)->sync)
394 #define nv50_ovly(c) (&nv50_head(c)->ovly)
395 #define nv50_oimm(c) (&nv50_head(c)->oimm)
396 #define nv50_chan(c) (&(c)->base.base)
397 #define nv50_vers(c) nv50_chan(c)->user.oclass
400 struct list_head head
;
401 struct nvif_object core
;
402 struct nvif_object base
[4];
406 struct nvif_object
*disp
;
407 struct nv50_mast mast
;
409 struct list_head fbdma
;
411 struct nouveau_bo
*sync
;
414 static struct nv50_disp
*
415 nv50_disp(struct drm_device
*dev
)
417 return nouveau_display(dev
)->priv
;
420 #define nv50_mast(d) (&nv50_disp(d)->mast)
422 static struct drm_crtc
*
423 nv50_display_crtc_get(struct drm_encoder
*encoder
)
425 return nouveau_encoder(encoder
)->crtc
;
428 /******************************************************************************
429 * EVO channel helpers
430 *****************************************************************************/
432 evo_wait(void *evoc
, int nr
)
434 struct nv50_dmac
*dmac
= evoc
;
435 struct nvif_device
*device
= dmac
->base
.device
;
436 u32 put
= nvif_rd32(&dmac
->base
.user
, 0x0000) / 4;
438 mutex_lock(&dmac
->lock
);
439 if (put
+ nr
>= (PAGE_SIZE
/ 4) - 8) {
440 dmac
->ptr
[put
] = 0x20000000;
442 nvif_wr32(&dmac
->base
.user
, 0x0000, 0x00000000);
443 if (nvif_msec(device
, 2000,
444 if (!nvif_rd32(&dmac
->base
.user
, 0x0004))
447 mutex_unlock(&dmac
->lock
);
448 printk(KERN_ERR
"nouveau: evo channel stalled\n");
455 return dmac
->ptr
+ put
;
459 evo_kick(u32
*push
, void *evoc
)
461 struct nv50_dmac
*dmac
= evoc
;
462 nvif_wr32(&dmac
->base
.user
, 0x0000, (push
- dmac
->ptr
) << 2);
463 mutex_unlock(&dmac
->lock
);
467 #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
468 #define evo_data(p,d) *((p)++) = (d)
470 #define evo_mthd(p,m,s) do { \
471 const u32 _m = (m), _s = (s); \
472 printk(KERN_ERR "%04x %d %s\n", _m, _s, __func__); \
473 *((p)++) = ((_s << 18) | _m); \
475 #define evo_data(p,d) do { \
476 const u32 _d = (d); \
477 printk(KERN_ERR "\t%08x\n", _d); \
483 evo_sync_wait(void *data
)
485 if (nouveau_bo_rd32(data
, EVO_MAST_NTFY
) != 0x00000000)
492 evo_sync(struct drm_device
*dev
)
494 struct nvif_device
*device
= &nouveau_drm(dev
)->device
;
495 struct nv50_disp
*disp
= nv50_disp(dev
);
496 struct nv50_mast
*mast
= nv50_mast(dev
);
497 u32
*push
= evo_wait(mast
, 8);
499 nouveau_bo_wr32(disp
->sync
, EVO_MAST_NTFY
, 0x00000000);
500 evo_mthd(push
, 0x0084, 1);
501 evo_data(push
, 0x80000000 | EVO_MAST_NTFY
);
502 evo_mthd(push
, 0x0080, 2);
503 evo_data(push
, 0x00000000);
504 evo_data(push
, 0x00000000);
505 evo_kick(push
, mast
);
506 if (nvif_msec(device
, 2000,
507 if (evo_sync_wait(disp
->sync
))
516 /******************************************************************************
517 * Page flipping channel
518 *****************************************************************************/
520 nv50_display_crtc_sema(struct drm_device
*dev
, int crtc
)
522 return nv50_disp(dev
)->sync
;
525 struct nv50_display_flip
{
526 struct nv50_disp
*disp
;
527 struct nv50_sync
*chan
;
531 nv50_display_flip_wait(void *data
)
533 struct nv50_display_flip
*flip
= data
;
534 if (nouveau_bo_rd32(flip
->disp
->sync
, flip
->chan
->addr
/ 4) ==
542 nv50_display_flip_stop(struct drm_crtc
*crtc
)
544 struct nvif_device
*device
= &nouveau_drm(crtc
->dev
)->device
;
545 struct nv50_display_flip flip
= {
546 .disp
= nv50_disp(crtc
->dev
),
547 .chan
= nv50_sync(crtc
),
551 push
= evo_wait(flip
.chan
, 8);
553 evo_mthd(push
, 0x0084, 1);
554 evo_data(push
, 0x00000000);
555 evo_mthd(push
, 0x0094, 1);
556 evo_data(push
, 0x00000000);
557 evo_mthd(push
, 0x00c0, 1);
558 evo_data(push
, 0x00000000);
559 evo_mthd(push
, 0x0080, 1);
560 evo_data(push
, 0x00000000);
561 evo_kick(push
, flip
.chan
);
564 nvif_msec(device
, 2000,
565 if (nv50_display_flip_wait(&flip
))
571 nv50_display_flip_next(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
572 struct nouveau_channel
*chan
, u32 swap_interval
)
574 struct nouveau_framebuffer
*nv_fb
= nouveau_framebuffer(fb
);
575 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
576 struct nv50_head
*head
= nv50_head(crtc
);
577 struct nv50_sync
*sync
= nv50_sync(crtc
);
581 if (crtc
->primary
->fb
->width
!= fb
->width
||
582 crtc
->primary
->fb
->height
!= fb
->height
)
586 if (swap_interval
== 0)
587 swap_interval
|= 0x100;
591 push
= evo_wait(sync
, 128);
592 if (unlikely(push
== NULL
))
595 if (chan
&& chan
->user
.oclass
< G82_CHANNEL_GPFIFO
) {
596 ret
= RING_SPACE(chan
, 8);
600 BEGIN_NV04(chan
, 0, NV11_SUBCHAN_DMA_SEMAPHORE
, 2);
601 OUT_RING (chan
, NvEvoSema0
+ nv_crtc
->index
);
602 OUT_RING (chan
, sync
->addr
^ 0x10);
603 BEGIN_NV04(chan
, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE
, 1);
604 OUT_RING (chan
, sync
->data
+ 1);
605 BEGIN_NV04(chan
, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET
, 2);
606 OUT_RING (chan
, sync
->addr
);
607 OUT_RING (chan
, sync
->data
);
609 if (chan
&& chan
->user
.oclass
< FERMI_CHANNEL_GPFIFO
) {
610 u64 addr
= nv84_fence_crtc(chan
, nv_crtc
->index
) + sync
->addr
;
611 ret
= RING_SPACE(chan
, 12);
615 BEGIN_NV04(chan
, 0, NV11_SUBCHAN_DMA_SEMAPHORE
, 1);
616 OUT_RING (chan
, chan
->vram
.handle
);
617 BEGIN_NV04(chan
, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH
, 4);
618 OUT_RING (chan
, upper_32_bits(addr
^ 0x10));
619 OUT_RING (chan
, lower_32_bits(addr
^ 0x10));
620 OUT_RING (chan
, sync
->data
+ 1);
621 OUT_RING (chan
, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG
);
622 BEGIN_NV04(chan
, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH
, 4);
623 OUT_RING (chan
, upper_32_bits(addr
));
624 OUT_RING (chan
, lower_32_bits(addr
));
625 OUT_RING (chan
, sync
->data
);
626 OUT_RING (chan
, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL
);
629 u64 addr
= nv84_fence_crtc(chan
, nv_crtc
->index
) + sync
->addr
;
630 ret
= RING_SPACE(chan
, 10);
634 BEGIN_NVC0(chan
, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH
, 4);
635 OUT_RING (chan
, upper_32_bits(addr
^ 0x10));
636 OUT_RING (chan
, lower_32_bits(addr
^ 0x10));
637 OUT_RING (chan
, sync
->data
+ 1);
638 OUT_RING (chan
, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG
|
639 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD
);
640 BEGIN_NVC0(chan
, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH
, 4);
641 OUT_RING (chan
, upper_32_bits(addr
));
642 OUT_RING (chan
, lower_32_bits(addr
));
643 OUT_RING (chan
, sync
->data
);
644 OUT_RING (chan
, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL
|
645 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD
);
655 evo_mthd(push
, 0x0100, 1);
656 evo_data(push
, 0xfffe0000);
657 evo_mthd(push
, 0x0084, 1);
658 evo_data(push
, swap_interval
);
659 if (!(swap_interval
& 0x00000100)) {
660 evo_mthd(push
, 0x00e0, 1);
661 evo_data(push
, 0x40000000);
663 evo_mthd(push
, 0x0088, 4);
664 evo_data(push
, sync
->addr
);
665 evo_data(push
, sync
->data
++);
666 evo_data(push
, sync
->data
);
667 evo_data(push
, sync
->base
.sync
.handle
);
668 evo_mthd(push
, 0x00a0, 2);
669 evo_data(push
, 0x00000000);
670 evo_data(push
, 0x00000000);
671 evo_mthd(push
, 0x00c0, 1);
672 evo_data(push
, nv_fb
->r_handle
);
673 evo_mthd(push
, 0x0110, 2);
674 evo_data(push
, 0x00000000);
675 evo_data(push
, 0x00000000);
676 if (nv50_vers(sync
) < GF110_DISP_BASE_CHANNEL_DMA
) {
677 evo_mthd(push
, 0x0800, 5);
678 evo_data(push
, nv_fb
->nvbo
->bo
.offset
>> 8);
680 evo_data(push
, (fb
->height
<< 16) | fb
->width
);
681 evo_data(push
, nv_fb
->r_pitch
);
682 evo_data(push
, nv_fb
->r_format
);
684 evo_mthd(push
, 0x0400, 5);
685 evo_data(push
, nv_fb
->nvbo
->bo
.offset
>> 8);
687 evo_data(push
, (fb
->height
<< 16) | fb
->width
);
688 evo_data(push
, nv_fb
->r_pitch
);
689 evo_data(push
, nv_fb
->r_format
);
691 evo_mthd(push
, 0x0080, 1);
692 evo_data(push
, 0x00000000);
693 evo_kick(push
, sync
);
695 nouveau_bo_ref(nv_fb
->nvbo
, &head
->image
);
699 /******************************************************************************
701 *****************************************************************************/
703 nv50_crtc_set_dither(struct nouveau_crtc
*nv_crtc
, bool update
)
705 struct nv50_mast
*mast
= nv50_mast(nv_crtc
->base
.dev
);
706 struct nouveau_connector
*nv_connector
;
707 struct drm_connector
*connector
;
708 u32
*push
, mode
= 0x00;
710 nv_connector
= nouveau_crtc_connector_get(nv_crtc
);
711 connector
= &nv_connector
->base
;
712 if (nv_connector
->dithering_mode
== DITHERING_MODE_AUTO
) {
713 if (nv_crtc
->base
.primary
->fb
->depth
> connector
->display_info
.bpc
* 3)
714 mode
= DITHERING_MODE_DYNAMIC2X2
;
716 mode
= nv_connector
->dithering_mode
;
719 if (nv_connector
->dithering_depth
== DITHERING_DEPTH_AUTO
) {
720 if (connector
->display_info
.bpc
>= 8)
721 mode
|= DITHERING_DEPTH_8BPC
;
723 mode
|= nv_connector
->dithering_depth
;
726 push
= evo_wait(mast
, 4);
728 if (nv50_vers(mast
) < GF110_DISP_CORE_CHANNEL_DMA
) {
729 evo_mthd(push
, 0x08a0 + (nv_crtc
->index
* 0x0400), 1);
730 evo_data(push
, mode
);
732 if (nv50_vers(mast
) < GK104_DISP_CORE_CHANNEL_DMA
) {
733 evo_mthd(push
, 0x0490 + (nv_crtc
->index
* 0x0300), 1);
734 evo_data(push
, mode
);
736 evo_mthd(push
, 0x04a0 + (nv_crtc
->index
* 0x0300), 1);
737 evo_data(push
, mode
);
741 evo_mthd(push
, 0x0080, 1);
742 evo_data(push
, 0x00000000);
744 evo_kick(push
, mast
);
751 nv50_crtc_set_scale(struct nouveau_crtc
*nv_crtc
, bool update
)
753 struct nv50_mast
*mast
= nv50_mast(nv_crtc
->base
.dev
);
754 struct drm_display_mode
*omode
, *umode
= &nv_crtc
->base
.mode
;
755 struct drm_crtc
*crtc
= &nv_crtc
->base
;
756 struct nouveau_connector
*nv_connector
;
757 int mode
= DRM_MODE_SCALE_NONE
;
760 /* start off at the resolution we programmed the crtc for, this
761 * effectively handles NONE/FULL scaling
763 nv_connector
= nouveau_crtc_connector_get(nv_crtc
);
764 if (nv_connector
&& nv_connector
->native_mode
) {
765 mode
= nv_connector
->scaling_mode
;
766 if (nv_connector
->scaling_full
) /* non-EDID LVDS/eDP mode */
767 mode
= DRM_MODE_SCALE_FULLSCREEN
;
770 if (mode
!= DRM_MODE_SCALE_NONE
)
771 omode
= nv_connector
->native_mode
;
775 oX
= omode
->hdisplay
;
776 oY
= omode
->vdisplay
;
777 if (omode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
780 /* add overscan compensation if necessary, will keep the aspect
781 * ratio the same as the backend mode unless overridden by the
782 * user setting both hborder and vborder properties.
784 if (nv_connector
&& ( nv_connector
->underscan
== UNDERSCAN_ON
||
785 (nv_connector
->underscan
== UNDERSCAN_AUTO
&&
786 drm_detect_hdmi_monitor(nv_connector
->edid
)))) {
787 u32 bX
= nv_connector
->underscan_hborder
;
788 u32 bY
= nv_connector
->underscan_vborder
;
789 u32 aspect
= (oY
<< 19) / oX
;
793 if (bY
) oY
-= (bY
* 2);
794 else oY
= ((oX
* aspect
) + (aspect
/ 2)) >> 19;
796 oX
-= (oX
>> 4) + 32;
797 if (bY
) oY
-= (bY
* 2);
798 else oY
= ((oX
* aspect
) + (aspect
/ 2)) >> 19;
802 /* handle CENTER/ASPECT scaling, taking into account the areas
803 * removed already for overscan compensation
806 case DRM_MODE_SCALE_CENTER
:
807 oX
= min((u32
)umode
->hdisplay
, oX
);
808 oY
= min((u32
)umode
->vdisplay
, oY
);
810 case DRM_MODE_SCALE_ASPECT
:
812 u32 aspect
= (umode
->hdisplay
<< 19) / umode
->vdisplay
;
813 oX
= ((oY
* aspect
) + (aspect
/ 2)) >> 19;
815 u32 aspect
= (umode
->vdisplay
<< 19) / umode
->hdisplay
;
816 oY
= ((oX
* aspect
) + (aspect
/ 2)) >> 19;
823 push
= evo_wait(mast
, 8);
825 if (nv50_vers(mast
) < GF110_DISP_CORE_CHANNEL_DMA
) {
826 /*XXX: SCALE_CTRL_ACTIVE??? */
827 evo_mthd(push
, 0x08d8 + (nv_crtc
->index
* 0x400), 2);
828 evo_data(push
, (oY
<< 16) | oX
);
829 evo_data(push
, (oY
<< 16) | oX
);
830 evo_mthd(push
, 0x08a4 + (nv_crtc
->index
* 0x400), 1);
831 evo_data(push
, 0x00000000);
832 evo_mthd(push
, 0x08c8 + (nv_crtc
->index
* 0x400), 1);
833 evo_data(push
, umode
->vdisplay
<< 16 | umode
->hdisplay
);
835 evo_mthd(push
, 0x04c0 + (nv_crtc
->index
* 0x300), 3);
836 evo_data(push
, (oY
<< 16) | oX
);
837 evo_data(push
, (oY
<< 16) | oX
);
838 evo_data(push
, (oY
<< 16) | oX
);
839 evo_mthd(push
, 0x0494 + (nv_crtc
->index
* 0x300), 1);
840 evo_data(push
, 0x00000000);
841 evo_mthd(push
, 0x04b8 + (nv_crtc
->index
* 0x300), 1);
842 evo_data(push
, umode
->vdisplay
<< 16 | umode
->hdisplay
);
845 evo_kick(push
, mast
);
848 nv50_display_flip_stop(crtc
);
849 nv50_display_flip_next(crtc
, crtc
->primary
->fb
,
858 nv50_crtc_set_raster_vblank_dmi(struct nouveau_crtc
*nv_crtc
, u32 usec
)
860 struct nv50_mast
*mast
= nv50_mast(nv_crtc
->base
.dev
);
863 push
= evo_wait(mast
, 8);
867 evo_mthd(push
, 0x0828 + (nv_crtc
->index
* 0x400), 1);
868 evo_data(push
, usec
);
869 evo_kick(push
, mast
);
874 nv50_crtc_set_color_vibrance(struct nouveau_crtc
*nv_crtc
, bool update
)
876 struct nv50_mast
*mast
= nv50_mast(nv_crtc
->base
.dev
);
880 adj
= (nv_crtc
->color_vibrance
> 0) ? 50 : 0;
881 vib
= ((nv_crtc
->color_vibrance
* 2047 + adj
) / 100) & 0xfff;
882 hue
= ((nv_crtc
->vibrant_hue
* 2047) / 100) & 0xfff;
884 push
= evo_wait(mast
, 16);
886 if (nv50_vers(mast
) < GF110_DISP_CORE_CHANNEL_DMA
) {
887 evo_mthd(push
, 0x08a8 + (nv_crtc
->index
* 0x400), 1);
888 evo_data(push
, (hue
<< 20) | (vib
<< 8));
890 evo_mthd(push
, 0x0498 + (nv_crtc
->index
* 0x300), 1);
891 evo_data(push
, (hue
<< 20) | (vib
<< 8));
895 evo_mthd(push
, 0x0080, 1);
896 evo_data(push
, 0x00000000);
898 evo_kick(push
, mast
);
905 nv50_crtc_set_image(struct nouveau_crtc
*nv_crtc
, struct drm_framebuffer
*fb
,
906 int x
, int y
, bool update
)
908 struct nouveau_framebuffer
*nvfb
= nouveau_framebuffer(fb
);
909 struct nv50_mast
*mast
= nv50_mast(nv_crtc
->base
.dev
);
912 push
= evo_wait(mast
, 16);
914 if (nv50_vers(mast
) < GF110_DISP_CORE_CHANNEL_DMA
) {
915 evo_mthd(push
, 0x0860 + (nv_crtc
->index
* 0x400), 1);
916 evo_data(push
, nvfb
->nvbo
->bo
.offset
>> 8);
917 evo_mthd(push
, 0x0868 + (nv_crtc
->index
* 0x400), 3);
918 evo_data(push
, (fb
->height
<< 16) | fb
->width
);
919 evo_data(push
, nvfb
->r_pitch
);
920 evo_data(push
, nvfb
->r_format
);
921 evo_mthd(push
, 0x08c0 + (nv_crtc
->index
* 0x400), 1);
922 evo_data(push
, (y
<< 16) | x
);
923 if (nv50_vers(mast
) > NV50_DISP_CORE_CHANNEL_DMA
) {
924 evo_mthd(push
, 0x0874 + (nv_crtc
->index
* 0x400), 1);
925 evo_data(push
, nvfb
->r_handle
);
928 evo_mthd(push
, 0x0460 + (nv_crtc
->index
* 0x300), 1);
929 evo_data(push
, nvfb
->nvbo
->bo
.offset
>> 8);
930 evo_mthd(push
, 0x0468 + (nv_crtc
->index
* 0x300), 4);
931 evo_data(push
, (fb
->height
<< 16) | fb
->width
);
932 evo_data(push
, nvfb
->r_pitch
);
933 evo_data(push
, nvfb
->r_format
);
934 evo_data(push
, nvfb
->r_handle
);
935 evo_mthd(push
, 0x04b0 + (nv_crtc
->index
* 0x300), 1);
936 evo_data(push
, (y
<< 16) | x
);
940 evo_mthd(push
, 0x0080, 1);
941 evo_data(push
, 0x00000000);
943 evo_kick(push
, mast
);
946 nv_crtc
->fb
.handle
= nvfb
->r_handle
;
951 nv50_crtc_cursor_show(struct nouveau_crtc
*nv_crtc
)
953 struct nv50_mast
*mast
= nv50_mast(nv_crtc
->base
.dev
);
954 u32
*push
= evo_wait(mast
, 16);
956 if (nv50_vers(mast
) < G82_DISP_CORE_CHANNEL_DMA
) {
957 evo_mthd(push
, 0x0880 + (nv_crtc
->index
* 0x400), 2);
958 evo_data(push
, 0x85000000);
959 evo_data(push
, nv_crtc
->cursor
.nvbo
->bo
.offset
>> 8);
961 if (nv50_vers(mast
) < GF110_DISP_CORE_CHANNEL_DMA
) {
962 evo_mthd(push
, 0x0880 + (nv_crtc
->index
* 0x400), 2);
963 evo_data(push
, 0x85000000);
964 evo_data(push
, nv_crtc
->cursor
.nvbo
->bo
.offset
>> 8);
965 evo_mthd(push
, 0x089c + (nv_crtc
->index
* 0x400), 1);
966 evo_data(push
, mast
->base
.vram
.handle
);
968 evo_mthd(push
, 0x0480 + (nv_crtc
->index
* 0x300), 2);
969 evo_data(push
, 0x85000000);
970 evo_data(push
, nv_crtc
->cursor
.nvbo
->bo
.offset
>> 8);
971 evo_mthd(push
, 0x048c + (nv_crtc
->index
* 0x300), 1);
972 evo_data(push
, mast
->base
.vram
.handle
);
974 evo_kick(push
, mast
);
976 nv_crtc
->cursor
.visible
= true;
980 nv50_crtc_cursor_hide(struct nouveau_crtc
*nv_crtc
)
982 struct nv50_mast
*mast
= nv50_mast(nv_crtc
->base
.dev
);
983 u32
*push
= evo_wait(mast
, 16);
985 if (nv50_vers(mast
) < G82_DISP_CORE_CHANNEL_DMA
) {
986 evo_mthd(push
, 0x0880 + (nv_crtc
->index
* 0x400), 1);
987 evo_data(push
, 0x05000000);
989 if (nv50_vers(mast
) < GF110_DISP_CORE_CHANNEL_DMA
) {
990 evo_mthd(push
, 0x0880 + (nv_crtc
->index
* 0x400), 1);
991 evo_data(push
, 0x05000000);
992 evo_mthd(push
, 0x089c + (nv_crtc
->index
* 0x400), 1);
993 evo_data(push
, 0x00000000);
995 evo_mthd(push
, 0x0480 + (nv_crtc
->index
* 0x300), 1);
996 evo_data(push
, 0x05000000);
997 evo_mthd(push
, 0x048c + (nv_crtc
->index
* 0x300), 1);
998 evo_data(push
, 0x00000000);
1000 evo_kick(push
, mast
);
1002 nv_crtc
->cursor
.visible
= false;
1006 nv50_crtc_cursor_show_hide(struct nouveau_crtc
*nv_crtc
, bool show
, bool update
)
1008 struct nv50_mast
*mast
= nv50_mast(nv_crtc
->base
.dev
);
1010 if (show
&& nv_crtc
->cursor
.nvbo
&& nv_crtc
->base
.enabled
)
1011 nv50_crtc_cursor_show(nv_crtc
);
1013 nv50_crtc_cursor_hide(nv_crtc
);
1016 u32
*push
= evo_wait(mast
, 2);
1018 evo_mthd(push
, 0x0080, 1);
1019 evo_data(push
, 0x00000000);
1020 evo_kick(push
, mast
);
1026 nv50_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
1031 nv50_crtc_prepare(struct drm_crtc
*crtc
)
1033 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
1034 struct nv50_mast
*mast
= nv50_mast(crtc
->dev
);
1037 nv50_display_flip_stop(crtc
);
1039 push
= evo_wait(mast
, 6);
1041 if (nv50_vers(mast
) < G82_DISP_CORE_CHANNEL_DMA
) {
1042 evo_mthd(push
, 0x0874 + (nv_crtc
->index
* 0x400), 1);
1043 evo_data(push
, 0x00000000);
1044 evo_mthd(push
, 0x0840 + (nv_crtc
->index
* 0x400), 1);
1045 evo_data(push
, 0x40000000);
1047 if (nv50_vers(mast
) < GF110_DISP_CORE_CHANNEL_DMA
) {
1048 evo_mthd(push
, 0x0874 + (nv_crtc
->index
* 0x400), 1);
1049 evo_data(push
, 0x00000000);
1050 evo_mthd(push
, 0x0840 + (nv_crtc
->index
* 0x400), 1);
1051 evo_data(push
, 0x40000000);
1052 evo_mthd(push
, 0x085c + (nv_crtc
->index
* 0x400), 1);
1053 evo_data(push
, 0x00000000);
1055 evo_mthd(push
, 0x0474 + (nv_crtc
->index
* 0x300), 1);
1056 evo_data(push
, 0x00000000);
1057 evo_mthd(push
, 0x0440 + (nv_crtc
->index
* 0x300), 1);
1058 evo_data(push
, 0x03000000);
1059 evo_mthd(push
, 0x045c + (nv_crtc
->index
* 0x300), 1);
1060 evo_data(push
, 0x00000000);
1063 evo_kick(push
, mast
);
1066 nv50_crtc_cursor_show_hide(nv_crtc
, false, false);
1070 nv50_crtc_commit(struct drm_crtc
*crtc
)
1072 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
1073 struct nv50_mast
*mast
= nv50_mast(crtc
->dev
);
1076 push
= evo_wait(mast
, 32);
1078 if (nv50_vers(mast
) < G82_DISP_CORE_CHANNEL_DMA
) {
1079 evo_mthd(push
, 0x0874 + (nv_crtc
->index
* 0x400), 1);
1080 evo_data(push
, nv_crtc
->fb
.handle
);
1081 evo_mthd(push
, 0x0840 + (nv_crtc
->index
* 0x400), 2);
1082 evo_data(push
, 0xc0000000);
1083 evo_data(push
, nv_crtc
->lut
.nvbo
->bo
.offset
>> 8);
1085 if (nv50_vers(mast
) < GF110_DISP_CORE_CHANNEL_DMA
) {
1086 evo_mthd(push
, 0x0874 + (nv_crtc
->index
* 0x400), 1);
1087 evo_data(push
, nv_crtc
->fb
.handle
);
1088 evo_mthd(push
, 0x0840 + (nv_crtc
->index
* 0x400), 2);
1089 evo_data(push
, 0xc0000000);
1090 evo_data(push
, nv_crtc
->lut
.nvbo
->bo
.offset
>> 8);
1091 evo_mthd(push
, 0x085c + (nv_crtc
->index
* 0x400), 1);
1092 evo_data(push
, mast
->base
.vram
.handle
);
1094 evo_mthd(push
, 0x0474 + (nv_crtc
->index
* 0x300), 1);
1095 evo_data(push
, nv_crtc
->fb
.handle
);
1096 evo_mthd(push
, 0x0440 + (nv_crtc
->index
* 0x300), 4);
1097 evo_data(push
, 0x83000000);
1098 evo_data(push
, nv_crtc
->lut
.nvbo
->bo
.offset
>> 8);
1099 evo_data(push
, 0x00000000);
1100 evo_data(push
, 0x00000000);
1101 evo_mthd(push
, 0x045c + (nv_crtc
->index
* 0x300), 1);
1102 evo_data(push
, mast
->base
.vram
.handle
);
1103 evo_mthd(push
, 0x0430 + (nv_crtc
->index
* 0x300), 1);
1104 evo_data(push
, 0xffffff00);
1107 evo_kick(push
, mast
);
1110 nv50_crtc_cursor_show_hide(nv_crtc
, true, true);
1111 nv50_display_flip_next(crtc
, crtc
->primary
->fb
, NULL
, 1);
1115 nv50_crtc_mode_fixup(struct drm_crtc
*crtc
, const struct drm_display_mode
*mode
,
1116 struct drm_display_mode
*adjusted_mode
)
1118 drm_mode_set_crtcinfo(adjusted_mode
, CRTC_INTERLACE_HALVE_V
);
1123 nv50_crtc_swap_fbs(struct drm_crtc
*crtc
, struct drm_framebuffer
*old_fb
)
1125 struct nouveau_framebuffer
*nvfb
= nouveau_framebuffer(crtc
->primary
->fb
);
1126 struct nv50_head
*head
= nv50_head(crtc
);
1129 ret
= nouveau_bo_pin(nvfb
->nvbo
, TTM_PL_FLAG_VRAM
, true);
1132 nouveau_bo_unpin(head
->image
);
1133 nouveau_bo_ref(nvfb
->nvbo
, &head
->image
);
1140 nv50_crtc_mode_set(struct drm_crtc
*crtc
, struct drm_display_mode
*umode
,
1141 struct drm_display_mode
*mode
, int x
, int y
,
1142 struct drm_framebuffer
*old_fb
)
1144 struct nv50_mast
*mast
= nv50_mast(crtc
->dev
);
1145 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
1146 struct nouveau_connector
*nv_connector
;
1147 u32 ilace
= (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) ? 2 : 1;
1148 u32 vscan
= (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
) ? 2 : 1;
1149 u32 hactive
, hsynce
, hbackp
, hfrontp
, hblanke
, hblanks
;
1150 u32 vactive
, vsynce
, vbackp
, vfrontp
, vblanke
, vblanks
;
1151 u32 vblan2e
= 0, vblan2s
= 1, vblankus
= 0;
1155 hactive
= mode
->htotal
;
1156 hsynce
= mode
->hsync_end
- mode
->hsync_start
- 1;
1157 hbackp
= mode
->htotal
- mode
->hsync_end
;
1158 hblanke
= hsynce
+ hbackp
;
1159 hfrontp
= mode
->hsync_start
- mode
->hdisplay
;
1160 hblanks
= mode
->htotal
- hfrontp
- 1;
1162 vactive
= mode
->vtotal
* vscan
/ ilace
;
1163 vsynce
= ((mode
->vsync_end
- mode
->vsync_start
) * vscan
/ ilace
) - 1;
1164 vbackp
= (mode
->vtotal
- mode
->vsync_end
) * vscan
/ ilace
;
1165 vblanke
= vsynce
+ vbackp
;
1166 vfrontp
= (mode
->vsync_start
- mode
->vdisplay
) * vscan
/ ilace
;
1167 vblanks
= vactive
- vfrontp
- 1;
1168 /* XXX: Safe underestimate, even "0" works */
1169 vblankus
= (vactive
- mode
->vdisplay
- 2) * hactive
;
1171 vblankus
/= mode
->clock
;
1173 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
1174 vblan2e
= vactive
+ vsynce
+ vbackp
;
1175 vblan2s
= vblan2e
+ (mode
->vdisplay
* vscan
/ ilace
);
1176 vactive
= (vactive
* 2) + 1;
1179 ret
= nv50_crtc_swap_fbs(crtc
, old_fb
);
1183 push
= evo_wait(mast
, 64);
1185 if (nv50_vers(mast
) < GF110_DISP_CORE_CHANNEL_DMA
) {
1186 evo_mthd(push
, 0x0804 + (nv_crtc
->index
* 0x400), 2);
1187 evo_data(push
, 0x00800000 | mode
->clock
);
1188 evo_data(push
, (ilace
== 2) ? 2 : 0);
1189 evo_mthd(push
, 0x0810 + (nv_crtc
->index
* 0x400), 6);
1190 evo_data(push
, 0x00000000);
1191 evo_data(push
, (vactive
<< 16) | hactive
);
1192 evo_data(push
, ( vsynce
<< 16) | hsynce
);
1193 evo_data(push
, (vblanke
<< 16) | hblanke
);
1194 evo_data(push
, (vblanks
<< 16) | hblanks
);
1195 evo_data(push
, (vblan2e
<< 16) | vblan2s
);
1196 evo_mthd(push
, 0x082c + (nv_crtc
->index
* 0x400), 1);
1197 evo_data(push
, 0x00000000);
1198 evo_mthd(push
, 0x0900 + (nv_crtc
->index
* 0x400), 2);
1199 evo_data(push
, 0x00000311);
1200 evo_data(push
, 0x00000100);
1202 evo_mthd(push
, 0x0410 + (nv_crtc
->index
* 0x300), 6);
1203 evo_data(push
, 0x00000000);
1204 evo_data(push
, (vactive
<< 16) | hactive
);
1205 evo_data(push
, ( vsynce
<< 16) | hsynce
);
1206 evo_data(push
, (vblanke
<< 16) | hblanke
);
1207 evo_data(push
, (vblanks
<< 16) | hblanks
);
1208 evo_data(push
, (vblan2e
<< 16) | vblan2s
);
1209 evo_mthd(push
, 0x042c + (nv_crtc
->index
* 0x300), 1);
1210 evo_data(push
, 0x00000000); /* ??? */
1211 evo_mthd(push
, 0x0450 + (nv_crtc
->index
* 0x300), 3);
1212 evo_data(push
, mode
->clock
* 1000);
1213 evo_data(push
, 0x00200000); /* ??? */
1214 evo_data(push
, mode
->clock
* 1000);
1215 evo_mthd(push
, 0x04d0 + (nv_crtc
->index
* 0x300), 2);
1216 evo_data(push
, 0x00000311);
1217 evo_data(push
, 0x00000100);
1220 evo_kick(push
, mast
);
1223 nv_connector
= nouveau_crtc_connector_get(nv_crtc
);
1224 nv50_crtc_set_dither(nv_crtc
, false);
1225 nv50_crtc_set_scale(nv_crtc
, false);
1227 /* G94 only accepts this after setting scale */
1228 if (nv50_vers(mast
) < GF110_DISP_CORE_CHANNEL_DMA
)
1229 nv50_crtc_set_raster_vblank_dmi(nv_crtc
, vblankus
);
1231 nv50_crtc_set_color_vibrance(nv_crtc
, false);
1232 nv50_crtc_set_image(nv_crtc
, crtc
->primary
->fb
, x
, y
, false);
1237 nv50_crtc_mode_set_base(struct drm_crtc
*crtc
, int x
, int y
,
1238 struct drm_framebuffer
*old_fb
)
1240 struct nouveau_drm
*drm
= nouveau_drm(crtc
->dev
);
1241 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
1244 if (!crtc
->primary
->fb
) {
1245 NV_DEBUG(drm
, "No FB bound\n");
1249 ret
= nv50_crtc_swap_fbs(crtc
, old_fb
);
1253 nv50_display_flip_stop(crtc
);
1254 nv50_crtc_set_image(nv_crtc
, crtc
->primary
->fb
, x
, y
, true);
1255 nv50_display_flip_next(crtc
, crtc
->primary
->fb
, NULL
, 1);
1260 nv50_crtc_mode_set_base_atomic(struct drm_crtc
*crtc
,
1261 struct drm_framebuffer
*fb
, int x
, int y
,
1262 enum mode_set_atomic state
)
1264 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
1265 nv50_display_flip_stop(crtc
);
1266 nv50_crtc_set_image(nv_crtc
, fb
, x
, y
, true);
1271 nv50_crtc_lut_load(struct drm_crtc
*crtc
)
1273 struct nv50_disp
*disp
= nv50_disp(crtc
->dev
);
1274 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
1275 void __iomem
*lut
= nvbo_kmap_obj_iovirtual(nv_crtc
->lut
.nvbo
);
1278 for (i
= 0; i
< 256; i
++) {
1279 u16 r
= nv_crtc
->lut
.r
[i
] >> 2;
1280 u16 g
= nv_crtc
->lut
.g
[i
] >> 2;
1281 u16 b
= nv_crtc
->lut
.b
[i
] >> 2;
1283 if (disp
->disp
->oclass
< GF110_DISP
) {
1284 writew(r
+ 0x0000, lut
+ (i
* 0x08) + 0);
1285 writew(g
+ 0x0000, lut
+ (i
* 0x08) + 2);
1286 writew(b
+ 0x0000, lut
+ (i
* 0x08) + 4);
1288 writew(r
+ 0x6000, lut
+ (i
* 0x20) + 0);
1289 writew(g
+ 0x6000, lut
+ (i
* 0x20) + 2);
1290 writew(b
+ 0x6000, lut
+ (i
* 0x20) + 4);
1296 nv50_crtc_disable(struct drm_crtc
*crtc
)
1298 struct nv50_head
*head
= nv50_head(crtc
);
1299 evo_sync(crtc
->dev
);
1301 nouveau_bo_unpin(head
->image
);
1302 nouveau_bo_ref(NULL
, &head
->image
);
1306 nv50_crtc_cursor_set(struct drm_crtc
*crtc
, struct drm_file
*file_priv
,
1307 uint32_t handle
, uint32_t width
, uint32_t height
)
1309 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
1310 struct drm_gem_object
*gem
= NULL
;
1311 struct nouveau_bo
*nvbo
= NULL
;
1315 if (width
!= 64 || height
!= 64)
1318 gem
= drm_gem_object_lookup(file_priv
, handle
);
1321 nvbo
= nouveau_gem_object(gem
);
1323 ret
= nouveau_bo_pin(nvbo
, TTM_PL_FLAG_VRAM
, true);
1327 if (nv_crtc
->cursor
.nvbo
)
1328 nouveau_bo_unpin(nv_crtc
->cursor
.nvbo
);
1329 nouveau_bo_ref(nvbo
, &nv_crtc
->cursor
.nvbo
);
1331 drm_gem_object_unreference_unlocked(gem
);
1333 nv50_crtc_cursor_show_hide(nv_crtc
, true, true);
1338 nv50_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
1340 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
1341 struct nv50_curs
*curs
= nv50_curs(crtc
);
1342 struct nv50_chan
*chan
= nv50_chan(curs
);
1343 nvif_wr32(&chan
->user
, 0x0084, (y
<< 16) | (x
& 0xffff));
1344 nvif_wr32(&chan
->user
, 0x0080, 0x00000000);
1346 nv_crtc
->cursor_saved_x
= x
;
1347 nv_crtc
->cursor_saved_y
= y
;
1352 nv50_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*r
, u16
*g
, u16
*b
,
1355 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
1358 for (i
= 0; i
< size
; i
++) {
1359 nv_crtc
->lut
.r
[i
] = r
[i
];
1360 nv_crtc
->lut
.g
[i
] = g
[i
];
1361 nv_crtc
->lut
.b
[i
] = b
[i
];
1364 nv50_crtc_lut_load(crtc
);
1370 nv50_crtc_cursor_restore(struct nouveau_crtc
*nv_crtc
, int x
, int y
)
1372 nv50_crtc_cursor_move(&nv_crtc
->base
, x
, y
);
1374 nv50_crtc_cursor_show_hide(nv_crtc
, true, true);
1378 nv50_crtc_destroy(struct drm_crtc
*crtc
)
1380 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
1381 struct nv50_disp
*disp
= nv50_disp(crtc
->dev
);
1382 struct nv50_head
*head
= nv50_head(crtc
);
1383 struct nv50_fbdma
*fbdma
;
1385 list_for_each_entry(fbdma
, &disp
->fbdma
, head
) {
1386 nvif_object_fini(&fbdma
->base
[nv_crtc
->index
]);
1389 nv50_dmac_destroy(&head
->ovly
.base
, disp
->disp
);
1390 nv50_pioc_destroy(&head
->oimm
.base
);
1391 nv50_dmac_destroy(&head
->sync
.base
, disp
->disp
);
1392 nv50_pioc_destroy(&head
->curs
.base
);
1394 /*XXX: this shouldn't be necessary, but the core doesn't call
1395 * disconnect() during the cleanup paths
1398 nouveau_bo_unpin(head
->image
);
1399 nouveau_bo_ref(NULL
, &head
->image
);
1402 if (nv_crtc
->cursor
.nvbo
)
1403 nouveau_bo_unpin(nv_crtc
->cursor
.nvbo
);
1404 nouveau_bo_ref(NULL
, &nv_crtc
->cursor
.nvbo
);
1406 nouveau_bo_unmap(nv_crtc
->lut
.nvbo
);
1407 if (nv_crtc
->lut
.nvbo
)
1408 nouveau_bo_unpin(nv_crtc
->lut
.nvbo
);
1409 nouveau_bo_ref(NULL
, &nv_crtc
->lut
.nvbo
);
1411 drm_crtc_cleanup(crtc
);
1415 static const struct drm_crtc_helper_funcs nv50_crtc_hfunc
= {
1416 .dpms
= nv50_crtc_dpms
,
1417 .prepare
= nv50_crtc_prepare
,
1418 .commit
= nv50_crtc_commit
,
1419 .mode_fixup
= nv50_crtc_mode_fixup
,
1420 .mode_set
= nv50_crtc_mode_set
,
1421 .mode_set_base
= nv50_crtc_mode_set_base
,
1422 .mode_set_base_atomic
= nv50_crtc_mode_set_base_atomic
,
1423 .load_lut
= nv50_crtc_lut_load
,
1424 .disable
= nv50_crtc_disable
,
1427 static const struct drm_crtc_funcs nv50_crtc_func
= {
1428 .cursor_set
= nv50_crtc_cursor_set
,
1429 .cursor_move
= nv50_crtc_cursor_move
,
1430 .gamma_set
= nv50_crtc_gamma_set
,
1431 .set_config
= nouveau_crtc_set_config
,
1432 .destroy
= nv50_crtc_destroy
,
1433 .page_flip
= nouveau_crtc_page_flip
,
1437 nv50_crtc_create(struct drm_device
*dev
, int index
)
1439 struct nouveau_drm
*drm
= nouveau_drm(dev
);
1440 struct nvif_device
*device
= &drm
->device
;
1441 struct nv50_disp
*disp
= nv50_disp(dev
);
1442 struct nv50_head
*head
;
1443 struct drm_crtc
*crtc
;
1446 head
= kzalloc(sizeof(*head
), GFP_KERNEL
);
1450 head
->base
.index
= index
;
1451 head
->base
.set_dither
= nv50_crtc_set_dither
;
1452 head
->base
.set_scale
= nv50_crtc_set_scale
;
1453 head
->base
.set_color_vibrance
= nv50_crtc_set_color_vibrance
;
1454 head
->base
.color_vibrance
= 50;
1455 head
->base
.vibrant_hue
= 0;
1456 head
->base
.cursor
.set_pos
= nv50_crtc_cursor_restore
;
1457 for (i
= 0; i
< 256; i
++) {
1458 head
->base
.lut
.r
[i
] = i
<< 8;
1459 head
->base
.lut
.g
[i
] = i
<< 8;
1460 head
->base
.lut
.b
[i
] = i
<< 8;
1463 crtc
= &head
->base
.base
;
1464 drm_crtc_init(dev
, crtc
, &nv50_crtc_func
);
1465 drm_crtc_helper_add(crtc
, &nv50_crtc_hfunc
);
1466 drm_mode_crtc_set_gamma_size(crtc
, 256);
1468 ret
= nouveau_bo_new(dev
, 8192, 0x100, TTM_PL_FLAG_VRAM
,
1469 0, 0x0000, NULL
, NULL
, &head
->base
.lut
.nvbo
);
1471 ret
= nouveau_bo_pin(head
->base
.lut
.nvbo
, TTM_PL_FLAG_VRAM
, true);
1473 ret
= nouveau_bo_map(head
->base
.lut
.nvbo
);
1475 nouveau_bo_unpin(head
->base
.lut
.nvbo
);
1478 nouveau_bo_ref(NULL
, &head
->base
.lut
.nvbo
);
1484 /* allocate cursor resources */
1485 ret
= nv50_curs_create(device
, disp
->disp
, index
, &head
->curs
);
1489 /* allocate page flip / sync resources */
1490 ret
= nv50_base_create(device
, disp
->disp
, index
, disp
->sync
->bo
.offset
,
1495 head
->sync
.addr
= EVO_FLIP_SEM0(index
);
1496 head
->sync
.data
= 0x00000000;
1498 /* allocate overlay resources */
1499 ret
= nv50_oimm_create(device
, disp
->disp
, index
, &head
->oimm
);
1503 ret
= nv50_ovly_create(device
, disp
->disp
, index
, disp
->sync
->bo
.offset
,
1510 nv50_crtc_destroy(crtc
);
1514 /******************************************************************************
1516 *****************************************************************************/
1518 nv50_encoder_mode_fixup(struct drm_encoder
*encoder
,
1519 const struct drm_display_mode
*mode
,
1520 struct drm_display_mode
*adjusted_mode
)
1522 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
1523 struct nouveau_connector
*nv_connector
;
1525 nv_connector
= nouveau_encoder_connector_get(nv_encoder
);
1526 if (nv_connector
&& nv_connector
->native_mode
) {
1527 nv_connector
->scaling_full
= false;
1528 if (nv_connector
->scaling_mode
== DRM_MODE_SCALE_NONE
) {
1529 switch (nv_connector
->type
) {
1530 case DCB_CONNECTOR_LVDS
:
1531 case DCB_CONNECTOR_LVDS_SPWG
:
1532 case DCB_CONNECTOR_eDP
:
1533 /* force use of scaler for non-edid modes */
1534 if (adjusted_mode
->type
& DRM_MODE_TYPE_DRIVER
)
1536 nv_connector
->scaling_full
= true;
1543 drm_mode_copy(adjusted_mode
, nv_connector
->native_mode
);
1549 /******************************************************************************
1551 *****************************************************************************/
1553 nv50_dac_dpms(struct drm_encoder
*encoder
, int mode
)
1555 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
1556 struct nv50_disp
*disp
= nv50_disp(encoder
->dev
);
1558 struct nv50_disp_mthd_v1 base
;
1559 struct nv50_disp_dac_pwr_v0 pwr
;
1562 .base
.method
= NV50_DISP_MTHD_V1_DAC_PWR
,
1563 .base
.hasht
= nv_encoder
->dcb
->hasht
,
1564 .base
.hashm
= nv_encoder
->dcb
->hashm
,
1567 .pwr
.vsync
= (mode
!= DRM_MODE_DPMS_SUSPEND
&&
1568 mode
!= DRM_MODE_DPMS_OFF
),
1569 .pwr
.hsync
= (mode
!= DRM_MODE_DPMS_STANDBY
&&
1570 mode
!= DRM_MODE_DPMS_OFF
),
1573 nvif_mthd(disp
->disp
, 0, &args
, sizeof(args
));
1577 nv50_dac_commit(struct drm_encoder
*encoder
)
1582 nv50_dac_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
1583 struct drm_display_mode
*adjusted_mode
)
1585 struct nv50_mast
*mast
= nv50_mast(encoder
->dev
);
1586 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
1587 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(encoder
->crtc
);
1590 nv50_dac_dpms(encoder
, DRM_MODE_DPMS_ON
);
1592 push
= evo_wait(mast
, 8);
1594 if (nv50_vers(mast
) < GF110_DISP_CORE_CHANNEL_DMA
) {
1595 u32 syncs
= 0x00000000;
1597 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
1598 syncs
|= 0x00000001;
1599 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
1600 syncs
|= 0x00000002;
1602 evo_mthd(push
, 0x0400 + (nv_encoder
->or * 0x080), 2);
1603 evo_data(push
, 1 << nv_crtc
->index
);
1604 evo_data(push
, syncs
);
1606 u32 magic
= 0x31ec6000 | (nv_crtc
->index
<< 25);
1607 u32 syncs
= 0x00000001;
1609 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
1610 syncs
|= 0x00000008;
1611 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
1612 syncs
|= 0x00000010;
1614 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1615 magic
|= 0x00000001;
1617 evo_mthd(push
, 0x0404 + (nv_crtc
->index
* 0x300), 2);
1618 evo_data(push
, syncs
);
1619 evo_data(push
, magic
);
1620 evo_mthd(push
, 0x0180 + (nv_encoder
->or * 0x020), 1);
1621 evo_data(push
, 1 << nv_crtc
->index
);
1624 evo_kick(push
, mast
);
1627 nv_encoder
->crtc
= encoder
->crtc
;
1631 nv50_dac_disconnect(struct drm_encoder
*encoder
)
1633 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
1634 struct nv50_mast
*mast
= nv50_mast(encoder
->dev
);
1635 const int or = nv_encoder
->or;
1638 if (nv_encoder
->crtc
) {
1639 nv50_crtc_prepare(nv_encoder
->crtc
);
1641 push
= evo_wait(mast
, 4);
1643 if (nv50_vers(mast
) < GF110_DISP_CORE_CHANNEL_DMA
) {
1644 evo_mthd(push
, 0x0400 + (or * 0x080), 1);
1645 evo_data(push
, 0x00000000);
1647 evo_mthd(push
, 0x0180 + (or * 0x020), 1);
1648 evo_data(push
, 0x00000000);
1650 evo_kick(push
, mast
);
1654 nv_encoder
->crtc
= NULL
;
1657 static enum drm_connector_status
1658 nv50_dac_detect(struct drm_encoder
*encoder
, struct drm_connector
*connector
)
1660 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
1661 struct nv50_disp
*disp
= nv50_disp(encoder
->dev
);
1663 struct nv50_disp_mthd_v1 base
;
1664 struct nv50_disp_dac_load_v0 load
;
1667 .base
.method
= NV50_DISP_MTHD_V1_DAC_LOAD
,
1668 .base
.hasht
= nv_encoder
->dcb
->hasht
,
1669 .base
.hashm
= nv_encoder
->dcb
->hashm
,
1673 args
.load
.data
= nouveau_drm(encoder
->dev
)->vbios
.dactestval
;
1674 if (args
.load
.data
== 0)
1675 args
.load
.data
= 340;
1677 ret
= nvif_mthd(disp
->disp
, 0, &args
, sizeof(args
));
1678 if (ret
|| !args
.load
.load
)
1679 return connector_status_disconnected
;
1681 return connector_status_connected
;
1685 nv50_dac_destroy(struct drm_encoder
*encoder
)
1687 drm_encoder_cleanup(encoder
);
1691 static const struct drm_encoder_helper_funcs nv50_dac_hfunc
= {
1692 .dpms
= nv50_dac_dpms
,
1693 .mode_fixup
= nv50_encoder_mode_fixup
,
1694 .prepare
= nv50_dac_disconnect
,
1695 .commit
= nv50_dac_commit
,
1696 .mode_set
= nv50_dac_mode_set
,
1697 .disable
= nv50_dac_disconnect
,
1698 .get_crtc
= nv50_display_crtc_get
,
1699 .detect
= nv50_dac_detect
1702 static const struct drm_encoder_funcs nv50_dac_func
= {
1703 .destroy
= nv50_dac_destroy
,
1707 nv50_dac_create(struct drm_connector
*connector
, struct dcb_output
*dcbe
)
1709 struct nouveau_drm
*drm
= nouveau_drm(connector
->dev
);
1710 struct nvkm_i2c
*i2c
= nvxx_i2c(&drm
->device
);
1711 struct nvkm_i2c_bus
*bus
;
1712 struct nouveau_encoder
*nv_encoder
;
1713 struct drm_encoder
*encoder
;
1714 int type
= DRM_MODE_ENCODER_DAC
;
1716 nv_encoder
= kzalloc(sizeof(*nv_encoder
), GFP_KERNEL
);
1719 nv_encoder
->dcb
= dcbe
;
1720 nv_encoder
->or = ffs(dcbe
->or) - 1;
1722 bus
= nvkm_i2c_bus_find(i2c
, dcbe
->i2c_index
);
1724 nv_encoder
->i2c
= &bus
->i2c
;
1726 encoder
= to_drm_encoder(nv_encoder
);
1727 encoder
->possible_crtcs
= dcbe
->heads
;
1728 encoder
->possible_clones
= 0;
1729 drm_encoder_init(connector
->dev
, encoder
, &nv50_dac_func
, type
, NULL
);
1730 drm_encoder_helper_add(encoder
, &nv50_dac_hfunc
);
1732 drm_mode_connector_attach_encoder(connector
, encoder
);
1736 /******************************************************************************
1738 *****************************************************************************/
1740 nv50_audio_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
)
1742 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
1743 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(encoder
->crtc
);
1744 struct nouveau_connector
*nv_connector
;
1745 struct nv50_disp
*disp
= nv50_disp(encoder
->dev
);
1748 struct nv50_disp_mthd_v1 mthd
;
1749 struct nv50_disp_sor_hda_eld_v0 eld
;
1751 u8 data
[sizeof(nv_connector
->base
.eld
)];
1753 .base
.mthd
.version
= 1,
1754 .base
.mthd
.method
= NV50_DISP_MTHD_V1_SOR_HDA_ELD
,
1755 .base
.mthd
.hasht
= nv_encoder
->dcb
->hasht
,
1756 .base
.mthd
.hashm
= (0xf0ff & nv_encoder
->dcb
->hashm
) |
1757 (0x0100 << nv_crtc
->index
),
1760 nv_connector
= nouveau_encoder_connector_get(nv_encoder
);
1761 if (!drm_detect_monitor_audio(nv_connector
->edid
))
1764 drm_edid_to_eld(&nv_connector
->base
, nv_connector
->edid
);
1765 memcpy(args
.data
, nv_connector
->base
.eld
, sizeof(args
.data
));
1767 nvif_mthd(disp
->disp
, 0, &args
,
1768 sizeof(args
.base
) + drm_eld_size(args
.data
));
1772 nv50_audio_disconnect(struct drm_encoder
*encoder
, struct nouveau_crtc
*nv_crtc
)
1774 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
1775 struct nv50_disp
*disp
= nv50_disp(encoder
->dev
);
1777 struct nv50_disp_mthd_v1 base
;
1778 struct nv50_disp_sor_hda_eld_v0 eld
;
1781 .base
.method
= NV50_DISP_MTHD_V1_SOR_HDA_ELD
,
1782 .base
.hasht
= nv_encoder
->dcb
->hasht
,
1783 .base
.hashm
= (0xf0ff & nv_encoder
->dcb
->hashm
) |
1784 (0x0100 << nv_crtc
->index
),
1787 nvif_mthd(disp
->disp
, 0, &args
, sizeof(args
));
1790 /******************************************************************************
1792 *****************************************************************************/
1794 nv50_hdmi_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
)
1796 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
1797 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(encoder
->crtc
);
1798 struct nv50_disp
*disp
= nv50_disp(encoder
->dev
);
1800 struct nv50_disp_mthd_v1 base
;
1801 struct nv50_disp_sor_hdmi_pwr_v0 pwr
;
1804 .base
.method
= NV50_DISP_MTHD_V1_SOR_HDMI_PWR
,
1805 .base
.hasht
= nv_encoder
->dcb
->hasht
,
1806 .base
.hashm
= (0xf0ff & nv_encoder
->dcb
->hashm
) |
1807 (0x0100 << nv_crtc
->index
),
1809 .pwr
.rekey
= 56, /* binary driver, and tegra, constant */
1811 struct nouveau_connector
*nv_connector
;
1814 nv_connector
= nouveau_encoder_connector_get(nv_encoder
);
1815 if (!drm_detect_hdmi_monitor(nv_connector
->edid
))
1818 max_ac_packet
= mode
->htotal
- mode
->hdisplay
;
1819 max_ac_packet
-= args
.pwr
.rekey
;
1820 max_ac_packet
-= 18; /* constant from tegra */
1821 args
.pwr
.max_ac_packet
= max_ac_packet
/ 32;
1823 nvif_mthd(disp
->disp
, 0, &args
, sizeof(args
));
1824 nv50_audio_mode_set(encoder
, mode
);
1828 nv50_hdmi_disconnect(struct drm_encoder
*encoder
, struct nouveau_crtc
*nv_crtc
)
1830 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
1831 struct nv50_disp
*disp
= nv50_disp(encoder
->dev
);
1833 struct nv50_disp_mthd_v1 base
;
1834 struct nv50_disp_sor_hdmi_pwr_v0 pwr
;
1837 .base
.method
= NV50_DISP_MTHD_V1_SOR_HDMI_PWR
,
1838 .base
.hasht
= nv_encoder
->dcb
->hasht
,
1839 .base
.hashm
= (0xf0ff & nv_encoder
->dcb
->hashm
) |
1840 (0x0100 << nv_crtc
->index
),
1843 nvif_mthd(disp
->disp
, 0, &args
, sizeof(args
));
1846 /******************************************************************************
1848 *****************************************************************************/
1850 nv50_sor_dpms(struct drm_encoder
*encoder
, int mode
)
1852 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
1853 struct nv50_disp
*disp
= nv50_disp(encoder
->dev
);
1855 struct nv50_disp_mthd_v1 base
;
1856 struct nv50_disp_sor_pwr_v0 pwr
;
1859 .base
.method
= NV50_DISP_MTHD_V1_SOR_PWR
,
1860 .base
.hasht
= nv_encoder
->dcb
->hasht
,
1861 .base
.hashm
= nv_encoder
->dcb
->hashm
,
1862 .pwr
.state
= mode
== DRM_MODE_DPMS_ON
,
1865 struct nv50_disp_mthd_v1 base
;
1866 struct nv50_disp_sor_dp_pwr_v0 pwr
;
1869 .base
.method
= NV50_DISP_MTHD_V1_SOR_DP_PWR
,
1870 .base
.hasht
= nv_encoder
->dcb
->hasht
,
1871 .base
.hashm
= nv_encoder
->dcb
->hashm
,
1872 .pwr
.state
= mode
== DRM_MODE_DPMS_ON
,
1874 struct drm_device
*dev
= encoder
->dev
;
1875 struct drm_encoder
*partner
;
1877 nv_encoder
->last_dpms
= mode
;
1879 list_for_each_entry(partner
, &dev
->mode_config
.encoder_list
, head
) {
1880 struct nouveau_encoder
*nv_partner
= nouveau_encoder(partner
);
1882 if (partner
->encoder_type
!= DRM_MODE_ENCODER_TMDS
)
1885 if (nv_partner
!= nv_encoder
&&
1886 nv_partner
->dcb
->or == nv_encoder
->dcb
->or) {
1887 if (nv_partner
->last_dpms
== DRM_MODE_DPMS_ON
)
1893 if (nv_encoder
->dcb
->type
== DCB_OUTPUT_DP
) {
1895 nvif_mthd(disp
->disp
, 0, &args
, sizeof(args
));
1896 nvif_mthd(disp
->disp
, 0, &link
, sizeof(link
));
1898 nvif_mthd(disp
->disp
, 0, &args
, sizeof(args
));
1903 nv50_sor_ctrl(struct nouveau_encoder
*nv_encoder
, u32 mask
, u32 data
)
1905 struct nv50_mast
*mast
= nv50_mast(nv_encoder
->base
.base
.dev
);
1906 u32 temp
= (nv_encoder
->ctrl
& ~mask
) | (data
& mask
), *push
;
1907 if (temp
!= nv_encoder
->ctrl
&& (push
= evo_wait(mast
, 2))) {
1908 if (nv50_vers(mast
) < GF110_DISP_CORE_CHANNEL_DMA
) {
1909 evo_mthd(push
, 0x0600 + (nv_encoder
->or * 0x40), 1);
1910 evo_data(push
, (nv_encoder
->ctrl
= temp
));
1912 evo_mthd(push
, 0x0200 + (nv_encoder
->or * 0x20), 1);
1913 evo_data(push
, (nv_encoder
->ctrl
= temp
));
1915 evo_kick(push
, mast
);
1920 nv50_sor_disconnect(struct drm_encoder
*encoder
)
1922 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
1923 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(nv_encoder
->crtc
);
1925 nv_encoder
->last_dpms
= DRM_MODE_DPMS_OFF
;
1926 nv_encoder
->crtc
= NULL
;
1929 nv50_crtc_prepare(&nv_crtc
->base
);
1930 nv50_sor_ctrl(nv_encoder
, 1 << nv_crtc
->index
, 0);
1931 nv50_audio_disconnect(encoder
, nv_crtc
);
1932 nv50_hdmi_disconnect(&nv_encoder
->base
.base
, nv_crtc
);
1937 nv50_sor_commit(struct drm_encoder
*encoder
)
1942 nv50_sor_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*umode
,
1943 struct drm_display_mode
*mode
)
1945 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
1946 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(encoder
->crtc
);
1948 struct nv50_disp_mthd_v1 base
;
1949 struct nv50_disp_sor_lvds_script_v0 lvds
;
1952 .base
.method
= NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT
,
1953 .base
.hasht
= nv_encoder
->dcb
->hasht
,
1954 .base
.hashm
= nv_encoder
->dcb
->hashm
,
1956 struct nv50_disp
*disp
= nv50_disp(encoder
->dev
);
1957 struct nv50_mast
*mast
= nv50_mast(encoder
->dev
);
1958 struct drm_device
*dev
= encoder
->dev
;
1959 struct nouveau_drm
*drm
= nouveau_drm(dev
);
1960 struct nouveau_connector
*nv_connector
;
1961 struct nvbios
*bios
= &drm
->vbios
;
1963 u8 owner
= 1 << nv_crtc
->index
;
1967 nv_connector
= nouveau_encoder_connector_get(nv_encoder
);
1968 nv_encoder
->crtc
= encoder
->crtc
;
1970 switch (nv_encoder
->dcb
->type
) {
1971 case DCB_OUTPUT_TMDS
:
1972 if (nv_encoder
->dcb
->sorconf
.link
& 1) {
1974 /* Only enable dual-link if:
1975 * - Need to (i.e. rate > 165MHz)
1977 * - Not an HDMI monitor, since there's no dual-link
1980 if (mode
->clock
>= 165000 &&
1981 nv_encoder
->dcb
->duallink_possible
&&
1982 !drm_detect_hdmi_monitor(nv_connector
->edid
))
1988 nv50_hdmi_mode_set(&nv_encoder
->base
.base
, mode
);
1990 case DCB_OUTPUT_LVDS
:
1993 if (bios
->fp_no_ddc
) {
1994 if (bios
->fp
.dual_link
)
1995 lvds
.lvds
.script
|= 0x0100;
1996 if (bios
->fp
.if_is_24bit
)
1997 lvds
.lvds
.script
|= 0x0200;
1999 if (nv_connector
->type
== DCB_CONNECTOR_LVDS_SPWG
) {
2000 if (((u8
*)nv_connector
->edid
)[121] == 2)
2001 lvds
.lvds
.script
|= 0x0100;
2003 if (mode
->clock
>= bios
->fp
.duallink_transition_clk
) {
2004 lvds
.lvds
.script
|= 0x0100;
2007 if (lvds
.lvds
.script
& 0x0100) {
2008 if (bios
->fp
.strapless_is_24bit
& 2)
2009 lvds
.lvds
.script
|= 0x0200;
2011 if (bios
->fp
.strapless_is_24bit
& 1)
2012 lvds
.lvds
.script
|= 0x0200;
2015 if (nv_connector
->base
.display_info
.bpc
== 8)
2016 lvds
.lvds
.script
|= 0x0200;
2019 nvif_mthd(disp
->disp
, 0, &lvds
, sizeof(lvds
));
2022 if (nv_connector
->base
.display_info
.bpc
== 6) {
2023 nv_encoder
->dp
.datarate
= mode
->clock
* 18 / 8;
2026 if (nv_connector
->base
.display_info
.bpc
== 8) {
2027 nv_encoder
->dp
.datarate
= mode
->clock
* 24 / 8;
2030 nv_encoder
->dp
.datarate
= mode
->clock
* 30 / 8;
2034 if (nv_encoder
->dcb
->sorconf
.link
& 1)
2038 nv50_audio_mode_set(encoder
, mode
);
2045 nv50_sor_dpms(&nv_encoder
->base
.base
, DRM_MODE_DPMS_ON
);
2047 if (nv50_vers(mast
) >= GF110_DISP
) {
2048 u32
*push
= evo_wait(mast
, 3);
2050 u32 magic
= 0x31ec6000 | (nv_crtc
->index
<< 25);
2051 u32 syncs
= 0x00000001;
2053 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
2054 syncs
|= 0x00000008;
2055 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
2056 syncs
|= 0x00000010;
2058 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
2059 magic
|= 0x00000001;
2061 evo_mthd(push
, 0x0404 + (nv_crtc
->index
* 0x300), 2);
2062 evo_data(push
, syncs
| (depth
<< 6));
2063 evo_data(push
, magic
);
2064 evo_kick(push
, mast
);
2070 ctrl
= (depth
<< 16) | (proto
<< 8);
2071 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
2073 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
2078 nv50_sor_ctrl(nv_encoder
, mask
| owner
, ctrl
| owner
);
2082 nv50_sor_destroy(struct drm_encoder
*encoder
)
2084 drm_encoder_cleanup(encoder
);
2088 static const struct drm_encoder_helper_funcs nv50_sor_hfunc
= {
2089 .dpms
= nv50_sor_dpms
,
2090 .mode_fixup
= nv50_encoder_mode_fixup
,
2091 .prepare
= nv50_sor_disconnect
,
2092 .commit
= nv50_sor_commit
,
2093 .mode_set
= nv50_sor_mode_set
,
2094 .disable
= nv50_sor_disconnect
,
2095 .get_crtc
= nv50_display_crtc_get
,
2098 static const struct drm_encoder_funcs nv50_sor_func
= {
2099 .destroy
= nv50_sor_destroy
,
2103 nv50_sor_create(struct drm_connector
*connector
, struct dcb_output
*dcbe
)
2105 struct nouveau_drm
*drm
= nouveau_drm(connector
->dev
);
2106 struct nvkm_i2c
*i2c
= nvxx_i2c(&drm
->device
);
2107 struct nouveau_encoder
*nv_encoder
;
2108 struct drm_encoder
*encoder
;
2111 switch (dcbe
->type
) {
2112 case DCB_OUTPUT_LVDS
: type
= DRM_MODE_ENCODER_LVDS
; break;
2113 case DCB_OUTPUT_TMDS
:
2116 type
= DRM_MODE_ENCODER_TMDS
;
2120 nv_encoder
= kzalloc(sizeof(*nv_encoder
), GFP_KERNEL
);
2123 nv_encoder
->dcb
= dcbe
;
2124 nv_encoder
->or = ffs(dcbe
->or) - 1;
2125 nv_encoder
->last_dpms
= DRM_MODE_DPMS_OFF
;
2127 if (dcbe
->type
== DCB_OUTPUT_DP
) {
2128 struct nvkm_i2c_aux
*aux
=
2129 nvkm_i2c_aux_find(i2c
, dcbe
->i2c_index
);
2131 nv_encoder
->i2c
= &aux
->i2c
;
2132 nv_encoder
->aux
= aux
;
2135 struct nvkm_i2c_bus
*bus
=
2136 nvkm_i2c_bus_find(i2c
, dcbe
->i2c_index
);
2138 nv_encoder
->i2c
= &bus
->i2c
;
2141 encoder
= to_drm_encoder(nv_encoder
);
2142 encoder
->possible_crtcs
= dcbe
->heads
;
2143 encoder
->possible_clones
= 0;
2144 drm_encoder_init(connector
->dev
, encoder
, &nv50_sor_func
, type
, NULL
);
2145 drm_encoder_helper_add(encoder
, &nv50_sor_hfunc
);
2147 drm_mode_connector_attach_encoder(connector
, encoder
);
2151 /******************************************************************************
2153 *****************************************************************************/
2156 nv50_pior_dpms(struct drm_encoder
*encoder
, int mode
)
2158 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
2159 struct nv50_disp
*disp
= nv50_disp(encoder
->dev
);
2161 struct nv50_disp_mthd_v1 base
;
2162 struct nv50_disp_pior_pwr_v0 pwr
;
2165 .base
.method
= NV50_DISP_MTHD_V1_PIOR_PWR
,
2166 .base
.hasht
= nv_encoder
->dcb
->hasht
,
2167 .base
.hashm
= nv_encoder
->dcb
->hashm
,
2168 .pwr
.state
= mode
== DRM_MODE_DPMS_ON
,
2169 .pwr
.type
= nv_encoder
->dcb
->type
,
2172 nvif_mthd(disp
->disp
, 0, &args
, sizeof(args
));
2176 nv50_pior_mode_fixup(struct drm_encoder
*encoder
,
2177 const struct drm_display_mode
*mode
,
2178 struct drm_display_mode
*adjusted_mode
)
2180 if (!nv50_encoder_mode_fixup(encoder
, mode
, adjusted_mode
))
2182 adjusted_mode
->clock
*= 2;
2187 nv50_pior_commit(struct drm_encoder
*encoder
)
2192 nv50_pior_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
2193 struct drm_display_mode
*adjusted_mode
)
2195 struct nv50_mast
*mast
= nv50_mast(encoder
->dev
);
2196 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
2197 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(encoder
->crtc
);
2198 struct nouveau_connector
*nv_connector
;
2199 u8 owner
= 1 << nv_crtc
->index
;
2203 nv_connector
= nouveau_encoder_connector_get(nv_encoder
);
2204 switch (nv_connector
->base
.display_info
.bpc
) {
2205 case 10: depth
= 0x6; break;
2206 case 8: depth
= 0x5; break;
2207 case 6: depth
= 0x2; break;
2208 default: depth
= 0x0; break;
2211 switch (nv_encoder
->dcb
->type
) {
2212 case DCB_OUTPUT_TMDS
:
2221 nv50_pior_dpms(encoder
, DRM_MODE_DPMS_ON
);
2223 push
= evo_wait(mast
, 8);
2225 if (nv50_vers(mast
) < GF110_DISP_CORE_CHANNEL_DMA
) {
2226 u32 ctrl
= (depth
<< 16) | (proto
<< 8) | owner
;
2227 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
2229 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
2231 evo_mthd(push
, 0x0700 + (nv_encoder
->or * 0x040), 1);
2232 evo_data(push
, ctrl
);
2235 evo_kick(push
, mast
);
2238 nv_encoder
->crtc
= encoder
->crtc
;
2242 nv50_pior_disconnect(struct drm_encoder
*encoder
)
2244 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
2245 struct nv50_mast
*mast
= nv50_mast(encoder
->dev
);
2246 const int or = nv_encoder
->or;
2249 if (nv_encoder
->crtc
) {
2250 nv50_crtc_prepare(nv_encoder
->crtc
);
2252 push
= evo_wait(mast
, 4);
2254 if (nv50_vers(mast
) < GF110_DISP_CORE_CHANNEL_DMA
) {
2255 evo_mthd(push
, 0x0700 + (or * 0x040), 1);
2256 evo_data(push
, 0x00000000);
2258 evo_kick(push
, mast
);
2262 nv_encoder
->crtc
= NULL
;
2266 nv50_pior_destroy(struct drm_encoder
*encoder
)
2268 drm_encoder_cleanup(encoder
);
2272 static const struct drm_encoder_helper_funcs nv50_pior_hfunc
= {
2273 .dpms
= nv50_pior_dpms
,
2274 .mode_fixup
= nv50_pior_mode_fixup
,
2275 .prepare
= nv50_pior_disconnect
,
2276 .commit
= nv50_pior_commit
,
2277 .mode_set
= nv50_pior_mode_set
,
2278 .disable
= nv50_pior_disconnect
,
2279 .get_crtc
= nv50_display_crtc_get
,
2282 static const struct drm_encoder_funcs nv50_pior_func
= {
2283 .destroy
= nv50_pior_destroy
,
2287 nv50_pior_create(struct drm_connector
*connector
, struct dcb_output
*dcbe
)
2289 struct nouveau_drm
*drm
= nouveau_drm(connector
->dev
);
2290 struct nvkm_i2c
*i2c
= nvxx_i2c(&drm
->device
);
2291 struct nvkm_i2c_bus
*bus
= NULL
;
2292 struct nvkm_i2c_aux
*aux
= NULL
;
2293 struct i2c_adapter
*ddc
;
2294 struct nouveau_encoder
*nv_encoder
;
2295 struct drm_encoder
*encoder
;
2298 switch (dcbe
->type
) {
2299 case DCB_OUTPUT_TMDS
:
2300 bus
= nvkm_i2c_bus_find(i2c
, NVKM_I2C_BUS_EXT(dcbe
->extdev
));
2301 ddc
= bus
? &bus
->i2c
: NULL
;
2302 type
= DRM_MODE_ENCODER_TMDS
;
2305 aux
= nvkm_i2c_aux_find(i2c
, NVKM_I2C_AUX_EXT(dcbe
->extdev
));
2306 ddc
= aux
? &aux
->i2c
: NULL
;
2307 type
= DRM_MODE_ENCODER_TMDS
;
2313 nv_encoder
= kzalloc(sizeof(*nv_encoder
), GFP_KERNEL
);
2316 nv_encoder
->dcb
= dcbe
;
2317 nv_encoder
->or = ffs(dcbe
->or) - 1;
2318 nv_encoder
->i2c
= ddc
;
2319 nv_encoder
->aux
= aux
;
2321 encoder
= to_drm_encoder(nv_encoder
);
2322 encoder
->possible_crtcs
= dcbe
->heads
;
2323 encoder
->possible_clones
= 0;
2324 drm_encoder_init(connector
->dev
, encoder
, &nv50_pior_func
, type
, NULL
);
2325 drm_encoder_helper_add(encoder
, &nv50_pior_hfunc
);
2327 drm_mode_connector_attach_encoder(connector
, encoder
);
2331 /******************************************************************************
2333 *****************************************************************************/
2336 nv50_fbdma_fini(struct nv50_fbdma
*fbdma
)
2339 for (i
= 0; i
< ARRAY_SIZE(fbdma
->base
); i
++)
2340 nvif_object_fini(&fbdma
->base
[i
]);
2341 nvif_object_fini(&fbdma
->core
);
2342 list_del(&fbdma
->head
);
2347 nv50_fbdma_init(struct drm_device
*dev
, u32 name
, u64 offset
, u64 length
, u8 kind
)
2349 struct nouveau_drm
*drm
= nouveau_drm(dev
);
2350 struct nv50_disp
*disp
= nv50_disp(dev
);
2351 struct nv50_mast
*mast
= nv50_mast(dev
);
2352 struct __attribute__ ((packed
)) {
2353 struct nv_dma_v0 base
;
2355 struct nv50_dma_v0 nv50
;
2356 struct gf100_dma_v0 gf100
;
2357 struct gf119_dma_v0 gf119
;
2360 struct nv50_fbdma
*fbdma
;
2361 struct drm_crtc
*crtc
;
2362 u32 size
= sizeof(args
.base
);
2365 list_for_each_entry(fbdma
, &disp
->fbdma
, head
) {
2366 if (fbdma
->core
.handle
== name
)
2370 fbdma
= kzalloc(sizeof(*fbdma
), GFP_KERNEL
);
2373 list_add(&fbdma
->head
, &disp
->fbdma
);
2375 args
.base
.target
= NV_DMA_V0_TARGET_VRAM
;
2376 args
.base
.access
= NV_DMA_V0_ACCESS_RDWR
;
2377 args
.base
.start
= offset
;
2378 args
.base
.limit
= offset
+ length
- 1;
2380 if (drm
->device
.info
.chipset
< 0x80) {
2381 args
.nv50
.part
= NV50_DMA_V0_PART_256
;
2382 size
+= sizeof(args
.nv50
);
2384 if (drm
->device
.info
.chipset
< 0xc0) {
2385 args
.nv50
.part
= NV50_DMA_V0_PART_256
;
2386 args
.nv50
.kind
= kind
;
2387 size
+= sizeof(args
.nv50
);
2389 if (drm
->device
.info
.chipset
< 0xd0) {
2390 args
.gf100
.kind
= kind
;
2391 size
+= sizeof(args
.gf100
);
2393 args
.gf119
.page
= GF119_DMA_V0_PAGE_LP
;
2394 args
.gf119
.kind
= kind
;
2395 size
+= sizeof(args
.gf119
);
2398 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2399 struct nv50_head
*head
= nv50_head(crtc
);
2400 int ret
= nvif_object_init(&head
->sync
.base
.base
.user
, name
,
2401 NV_DMA_IN_MEMORY
, &args
, size
,
2402 &fbdma
->base
[head
->base
.index
]);
2404 nv50_fbdma_fini(fbdma
);
2409 ret
= nvif_object_init(&mast
->base
.base
.user
, name
, NV_DMA_IN_MEMORY
,
2410 &args
, size
, &fbdma
->core
);
2412 nv50_fbdma_fini(fbdma
);
2420 nv50_fb_dtor(struct drm_framebuffer
*fb
)
2425 nv50_fb_ctor(struct drm_framebuffer
*fb
)
2427 struct nouveau_framebuffer
*nv_fb
= nouveau_framebuffer(fb
);
2428 struct nouveau_drm
*drm
= nouveau_drm(fb
->dev
);
2429 struct nouveau_bo
*nvbo
= nv_fb
->nvbo
;
2430 struct nv50_disp
*disp
= nv50_disp(fb
->dev
);
2431 u8 kind
= nouveau_bo_tile_layout(nvbo
) >> 8;
2432 u8 tile
= nvbo
->tile_mode
;
2434 if (drm
->device
.info
.chipset
>= 0xc0)
2435 tile
>>= 4; /* yep.. */
2437 switch (fb
->depth
) {
2438 case 8: nv_fb
->r_format
= 0x1e00; break;
2439 case 15: nv_fb
->r_format
= 0xe900; break;
2440 case 16: nv_fb
->r_format
= 0xe800; break;
2442 case 32: nv_fb
->r_format
= 0xcf00; break;
2443 case 30: nv_fb
->r_format
= 0xd100; break;
2445 NV_ERROR(drm
, "unknown depth %d\n", fb
->depth
);
2449 if (disp
->disp
->oclass
< G82_DISP
) {
2450 nv_fb
->r_pitch
= kind
? (((fb
->pitches
[0] / 4) << 4) | tile
) :
2451 (fb
->pitches
[0] | 0x00100000);
2452 nv_fb
->r_format
|= kind
<< 16;
2454 if (disp
->disp
->oclass
< GF110_DISP
) {
2455 nv_fb
->r_pitch
= kind
? (((fb
->pitches
[0] / 4) << 4) | tile
) :
2456 (fb
->pitches
[0] | 0x00100000);
2458 nv_fb
->r_pitch
= kind
? (((fb
->pitches
[0] / 4) << 4) | tile
) :
2459 (fb
->pitches
[0] | 0x01000000);
2461 nv_fb
->r_handle
= 0xffff0000 | kind
;
2463 return nv50_fbdma_init(fb
->dev
, nv_fb
->r_handle
, 0,
2464 drm
->device
.info
.ram_user
, kind
);
2467 /******************************************************************************
2469 *****************************************************************************/
2472 nv50_display_fini(struct drm_device
*dev
)
2477 nv50_display_init(struct drm_device
*dev
)
2479 struct nv50_disp
*disp
= nv50_disp(dev
);
2480 struct drm_crtc
*crtc
;
2483 push
= evo_wait(nv50_mast(dev
), 32);
2487 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2488 struct nv50_sync
*sync
= nv50_sync(crtc
);
2490 nv50_crtc_lut_load(crtc
);
2491 nouveau_bo_wr32(disp
->sync
, sync
->addr
/ 4, sync
->data
);
2494 evo_mthd(push
, 0x0088, 1);
2495 evo_data(push
, nv50_mast(dev
)->base
.sync
.handle
);
2496 evo_kick(push
, nv50_mast(dev
));
2501 nv50_display_destroy(struct drm_device
*dev
)
2503 struct nv50_disp
*disp
= nv50_disp(dev
);
2504 struct nv50_fbdma
*fbdma
, *fbtmp
;
2506 list_for_each_entry_safe(fbdma
, fbtmp
, &disp
->fbdma
, head
) {
2507 nv50_fbdma_fini(fbdma
);
2510 nv50_dmac_destroy(&disp
->mast
.base
, disp
->disp
);
2512 nouveau_bo_unmap(disp
->sync
);
2514 nouveau_bo_unpin(disp
->sync
);
2515 nouveau_bo_ref(NULL
, &disp
->sync
);
2517 nouveau_display(dev
)->priv
= NULL
;
2522 nv50_display_create(struct drm_device
*dev
)
2524 struct nvif_device
*device
= &nouveau_drm(dev
)->device
;
2525 struct nouveau_drm
*drm
= nouveau_drm(dev
);
2526 struct dcb_table
*dcb
= &drm
->vbios
.dcb
;
2527 struct drm_connector
*connector
, *tmp
;
2528 struct nv50_disp
*disp
;
2529 struct dcb_output
*dcbe
;
2532 disp
= kzalloc(sizeof(*disp
), GFP_KERNEL
);
2535 INIT_LIST_HEAD(&disp
->fbdma
);
2537 nouveau_display(dev
)->priv
= disp
;
2538 nouveau_display(dev
)->dtor
= nv50_display_destroy
;
2539 nouveau_display(dev
)->init
= nv50_display_init
;
2540 nouveau_display(dev
)->fini
= nv50_display_fini
;
2541 nouveau_display(dev
)->fb_ctor
= nv50_fb_ctor
;
2542 nouveau_display(dev
)->fb_dtor
= nv50_fb_dtor
;
2543 disp
->disp
= &nouveau_display(dev
)->disp
;
2545 /* small shared memory area we use for notifiers and semaphores */
2546 ret
= nouveau_bo_new(dev
, 4096, 0x1000, TTM_PL_FLAG_VRAM
,
2547 0, 0x0000, NULL
, NULL
, &disp
->sync
);
2549 ret
= nouveau_bo_pin(disp
->sync
, TTM_PL_FLAG_VRAM
, true);
2551 ret
= nouveau_bo_map(disp
->sync
);
2553 nouveau_bo_unpin(disp
->sync
);
2556 nouveau_bo_ref(NULL
, &disp
->sync
);
2562 /* allocate master evo channel */
2563 ret
= nv50_core_create(device
, disp
->disp
, disp
->sync
->bo
.offset
,
2568 /* create crtc objects to represent the hw heads */
2569 if (disp
->disp
->oclass
>= GF110_DISP
)
2570 crtcs
= nvif_rd32(&device
->object
, 0x022448);
2574 for (i
= 0; i
< crtcs
; i
++) {
2575 ret
= nv50_crtc_create(dev
, i
);
2580 /* create encoder/connector objects based on VBIOS DCB table */
2581 for (i
= 0, dcbe
= &dcb
->entry
[0]; i
< dcb
->entries
; i
++, dcbe
++) {
2582 connector
= nouveau_connector_create(dev
, dcbe
->connector
);
2583 if (IS_ERR(connector
))
2586 if (dcbe
->location
== DCB_LOC_ON_CHIP
) {
2587 switch (dcbe
->type
) {
2588 case DCB_OUTPUT_TMDS
:
2589 case DCB_OUTPUT_LVDS
:
2591 ret
= nv50_sor_create(connector
, dcbe
);
2593 case DCB_OUTPUT_ANALOG
:
2594 ret
= nv50_dac_create(connector
, dcbe
);
2601 ret
= nv50_pior_create(connector
, dcbe
);
2605 NV_WARN(drm
, "failed to create encoder %d/%d/%d: %d\n",
2606 dcbe
->location
, dcbe
->type
,
2607 ffs(dcbe
->or) - 1, ret
);
2612 /* cull any connectors we created that don't have an encoder */
2613 list_for_each_entry_safe(connector
, tmp
, &dev
->mode_config
.connector_list
, head
) {
2614 if (connector
->encoder_ids
[0])
2617 NV_WARN(drm
, "%s has no encoders, removing\n",
2619 connector
->funcs
->destroy(connector
);
2624 nv50_display_destroy(dev
);