projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'trace-v4.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt...
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nv50_display.c
1 /*
2 * Copyright 2011 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <linux/dma-mapping.h>
26
27 #include <drm/drmP.h>
28 #include <drm/drm_crtc_helper.h>
29 #include <drm/drm_plane_helper.h>
30 #include <drm/drm_dp_helper.h>
31 #include <drm/drm_fb_helper.h>
32
33 #include <nvif/class.h>
34 #include <nvif/cl0002.h>
35 #include <nvif/cl5070.h>
36 #include <nvif/cl507a.h>
37 #include <nvif/cl507b.h>
38 #include <nvif/cl507c.h>
39 #include <nvif/cl507d.h>
40 #include <nvif/cl507e.h>
41
42 #include "nouveau_drv.h"
43 #include "nouveau_dma.h"
44 #include "nouveau_gem.h"
45 #include "nouveau_connector.h"
46 #include "nouveau_encoder.h"
47 #include "nouveau_crtc.h"
48 #include "nouveau_fence.h"
49 #include "nv50_display.h"
50
51 #define EVO_DMA_NR 9
52
53 #define EVO_MASTER (0x00)
54 #define EVO_FLIP(c) (0x01 + (c))
55 #define EVO_OVLY(c) (0x05 + (c))
56 #define EVO_OIMM(c) (0x09 + (c))
57 #define EVO_CURS(c) (0x0d + (c))
58
59 /* offsets in shared sync bo of various structures */
60 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
61 #define EVO_MAST_NTFY EVO_SYNC( 0, 0x00)
62 #define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00)
63 #define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10)
64
65 /******************************************************************************
66 * EVO channel
67 *****************************************************************************/
68
69 struct nv50_chan {
70 struct nvif_object user;
71 struct nvif_device *device;
72 };
73
74 static int
75 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
76 const s32 *oclass, u8 head, void *data, u32 size,
77 struct nv50_chan *chan)
78 {
79 struct nvif_sclass *sclass;
80 int ret, i, n;
81
82 chan->device = device;
83
84 ret = n = nvif_object_sclass_get(disp, &sclass);
85 if (ret < 0)
86 return ret;
87
88 while (oclass[0]) {
89 for (i = 0; i < n; i++) {
90 if (sclass[i].oclass == oclass[0]) {
91 ret = nvif_object_init(disp, 0, oclass[0],
92 data, size, &chan->user);
93 if (ret == 0)
94 nvif_object_map(&chan->user);
95 nvif_object_sclass_put(&sclass);
96 return ret;
97 }
98 }
99 oclass++;
100 }
101
102 nvif_object_sclass_put(&sclass);
103 return -ENOSYS;
104 }
105
106 static void
107 nv50_chan_destroy(struct nv50_chan *chan)
108 {
109 nvif_object_fini(&chan->user);
110 }
111
112 /******************************************************************************
113 * PIO EVO channel
114 *****************************************************************************/
115
116 struct nv50_pioc {
117 struct nv50_chan base;
118 };
119
120 static void
121 nv50_pioc_destroy(struct nv50_pioc *pioc)
122 {
123 nv50_chan_destroy(&pioc->base);
124 }
125
126 static int
127 nv50_pioc_create(struct nvif_device *device, struct nvif_object *disp,
128 const s32 *oclass, u8 head, void *data, u32 size,
129 struct nv50_pioc *pioc)
130 {
131 return nv50_chan_create(device, disp, oclass, head, data, size,
132 &pioc->base);
133 }
134
135 /******************************************************************************
136 * Cursor Immediate
137 *****************************************************************************/
138
139 struct nv50_curs {
140 struct nv50_pioc base;
141 };
142
143 static int
144 nv50_curs_create(struct nvif_device *device, struct nvif_object *disp,
145 int head, struct nv50_curs *curs)
146 {
147 struct nv50_disp_cursor_v0 args = {
148 .head = head,
149 };
150 static const s32 oclass[] = {
151 GK104_DISP_CURSOR,
152 GF110_DISP_CURSOR,
153 GT214_DISP_CURSOR,
154 G82_DISP_CURSOR,
155 NV50_DISP_CURSOR,
156 0
157 };
158
159 return nv50_pioc_create(device, disp, oclass, head, &args, sizeof(args),
160 &curs->base);
161 }
162
163 /******************************************************************************
164 * Overlay Immediate
165 *****************************************************************************/
166
167 struct nv50_oimm {
168 struct nv50_pioc base;
169 };
170
171 static int
172 nv50_oimm_create(struct nvif_device *device, struct nvif_object *disp,
173 int head, struct nv50_oimm *oimm)
174 {
175 struct nv50_disp_cursor_v0 args = {
176 .head = head,
177 };
178 static const s32 oclass[] = {
179 GK104_DISP_OVERLAY,
180 GF110_DISP_OVERLAY,
181 GT214_DISP_OVERLAY,
182 G82_DISP_OVERLAY,
183 NV50_DISP_OVERLAY,
184 0
185 };
186
187 return nv50_pioc_create(device, disp, oclass, head, &args, sizeof(args),
188 &oimm->base);
189 }
190
191 /******************************************************************************
192 * DMA EVO channel
193 *****************************************************************************/
194
195 struct nv50_dmac {
196 struct nv50_chan base;
197 dma_addr_t handle;
198 u32 *ptr;
199
200 struct nvif_object sync;
201 struct nvif_object vram;
202
203 /* Protects against concurrent pushbuf access to this channel, lock is
204 * grabbed by evo_wait (if the pushbuf reservation is successful) and
205 * dropped again by evo_kick. */
206 struct mutex lock;
207 };
208
209 static void
210 nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp)
211 {
212 struct nvif_device *device = dmac->base.device;
213
214 nvif_object_fini(&dmac->vram);
215 nvif_object_fini(&dmac->sync);
216
217 nv50_chan_destroy(&dmac->base);
218
219 if (dmac->ptr) {
220 struct device *dev = nvxx_device(device)->dev;
221 dma_free_coherent(dev, PAGE_SIZE, dmac->ptr, dmac->handle);
222 }
223 }
224
225 static int
226 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
227 const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
228 struct nv50_dmac *dmac)
229 {
230 struct nv50_disp_core_channel_dma_v0 *args = data;
231 struct nvif_object pushbuf;
232 int ret;
233
234 mutex_init(&dmac->lock);
235
236 dmac->ptr = dma_alloc_coherent(nvxx_device(device)->dev, PAGE_SIZE,
237 &dmac->handle, GFP_KERNEL);
238 if (!dmac->ptr)
239 return -ENOMEM;
240
241 ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY,
242 &(struct nv_dma_v0) {
243 .target = NV_DMA_V0_TARGET_PCI_US,
244 .access = NV_DMA_V0_ACCESS_RD,
245 .start = dmac->handle + 0x0000,
246 .limit = dmac->handle + 0x0fff,
247 }, sizeof(struct nv_dma_v0), &pushbuf);
248 if (ret)
249 return ret;
250
251 args->pushbuf = nvif_handle(&pushbuf);
252
253 ret = nv50_chan_create(device, disp, oclass, head, data, size,
254 &dmac->base);
255 nvif_object_fini(&pushbuf);
256 if (ret)
257 return ret;
258
259 ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
260 &(struct nv_dma_v0) {
261 .target = NV_DMA_V0_TARGET_VRAM,
262 .access = NV_DMA_V0_ACCESS_RDWR,
263 .start = syncbuf + 0x0000,
264 .limit = syncbuf + 0x0fff,
265 }, sizeof(struct nv_dma_v0),
266 &dmac->sync);
267 if (ret)
268 return ret;
269
270 ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
271 &(struct nv_dma_v0) {
272 .target = NV_DMA_V0_TARGET_VRAM,
273 .access = NV_DMA_V0_ACCESS_RDWR,
274 .start = 0,
275 .limit = device->info.ram_user - 1,
276 }, sizeof(struct nv_dma_v0),
277 &dmac->vram);
278 if (ret)
279 return ret;
280
281 return ret;
282 }
283
284 /******************************************************************************
285 * Core
286 *****************************************************************************/
287
288 struct nv50_mast {
289 struct nv50_dmac base;
290 };
291
292 static int
293 nv50_core_create(struct nvif_device *device, struct nvif_object *disp,
294 u64 syncbuf, struct nv50_mast *core)
295 {
296 struct nv50_disp_core_channel_dma_v0 args = {
297 .pushbuf = 0xb0007d00,
298 };
299 static const s32 oclass[] = {
300 GP104_DISP_CORE_CHANNEL_DMA,
301 GP100_DISP_CORE_CHANNEL_DMA,
302 GM200_DISP_CORE_CHANNEL_DMA,
303 GM107_DISP_CORE_CHANNEL_DMA,
304 GK110_DISP_CORE_CHANNEL_DMA,
305 GK104_DISP_CORE_CHANNEL_DMA,
306 GF110_DISP_CORE_CHANNEL_DMA,
307 GT214_DISP_CORE_CHANNEL_DMA,
308 GT206_DISP_CORE_CHANNEL_DMA,
309 GT200_DISP_CORE_CHANNEL_DMA,
310 G82_DISP_CORE_CHANNEL_DMA,
311 NV50_DISP_CORE_CHANNEL_DMA,
312 0
313 };
314
315 return nv50_dmac_create(device, disp, oclass, 0, &args, sizeof(args),
316 syncbuf, &core->base);
317 }
318
319 /******************************************************************************
320 * Base
321 *****************************************************************************/
322
323 struct nv50_sync {
324 struct nv50_dmac base;
325 u32 addr;
326 u32 data;
327 };
328
329 static int
330 nv50_base_create(struct nvif_device *device, struct nvif_object *disp,
331 int head, u64 syncbuf, struct nv50_sync *base)
332 {
333 struct nv50_disp_base_channel_dma_v0 args = {
334 .pushbuf = 0xb0007c00 | head,
335 .head = head,
336 };
337 static const s32 oclass[] = {
338 GK110_DISP_BASE_CHANNEL_DMA,
339 GK104_DISP_BASE_CHANNEL_DMA,
340 GF110_DISP_BASE_CHANNEL_DMA,
341 GT214_DISP_BASE_CHANNEL_DMA,
342 GT200_DISP_BASE_CHANNEL_DMA,
343 G82_DISP_BASE_CHANNEL_DMA,
344 NV50_DISP_BASE_CHANNEL_DMA,
345 0
346 };
347
348 return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args),
349 syncbuf, &base->base);
350 }
351
352 /******************************************************************************
353 * Overlay
354 *****************************************************************************/
355
356 struct nv50_ovly {
357 struct nv50_dmac base;
358 };
359
360 static int
361 nv50_ovly_create(struct nvif_device *device, struct nvif_object *disp,
362 int head, u64 syncbuf, struct nv50_ovly *ovly)
363 {
364 struct nv50_disp_overlay_channel_dma_v0 args = {
365 .pushbuf = 0xb0007e00 | head,
366 .head = head,
367 };
368 static const s32 oclass[] = {
369 GK104_DISP_OVERLAY_CONTROL_DMA,
370 GF110_DISP_OVERLAY_CONTROL_DMA,
371 GT214_DISP_OVERLAY_CHANNEL_DMA,
372 GT200_DISP_OVERLAY_CHANNEL_DMA,
373 G82_DISP_OVERLAY_CHANNEL_DMA,
374 NV50_DISP_OVERLAY_CHANNEL_DMA,
375 0
376 };
377
378 return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args),
379 syncbuf, &ovly->base);
380 }
381
382 struct nv50_head {
383 struct nouveau_crtc base;
384 struct nouveau_bo *image;
385 struct nv50_curs curs;
386 struct nv50_sync sync;
387 struct nv50_ovly ovly;
388 struct nv50_oimm oimm;
389 };
390
391 #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
392 #define nv50_curs(c) (&nv50_head(c)->curs)
393 #define nv50_sync(c) (&nv50_head(c)->sync)
394 #define nv50_ovly(c) (&nv50_head(c)->ovly)
395 #define nv50_oimm(c) (&nv50_head(c)->oimm)
396 #define nv50_chan(c) (&(c)->base.base)
397 #define nv50_vers(c) nv50_chan(c)->user.oclass
398
399 struct nv50_fbdma {
400 struct list_head head;
401 struct nvif_object core;
402 struct nvif_object base[4];
403 };
404
405 struct nv50_disp {
406 struct nvif_object *disp;
407 struct nv50_mast mast;
408
409 struct list_head fbdma;
410
411 struct nouveau_bo *sync;
412 };
413
414 static struct nv50_disp *
415 nv50_disp(struct drm_device *dev)
416 {
417 return nouveau_display(dev)->priv;
418 }
419
420 #define nv50_mast(d) (&nv50_disp(d)->mast)
421
422 static struct drm_crtc *
423 nv50_display_crtc_get(struct drm_encoder *encoder)
424 {
425 return nouveau_encoder(encoder)->crtc;
426 }
427
428 /******************************************************************************
429 * EVO channel helpers
430 *****************************************************************************/
431 static u32 *
432 evo_wait(void *evoc, int nr)
433 {
434 struct nv50_dmac *dmac = evoc;
435 struct nvif_device *device = dmac->base.device;
436 u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
437
438 mutex_lock(&dmac->lock);
439 if (put + nr >= (PAGE_SIZE / 4) - 8) {
440 dmac->ptr[put] = 0x20000000;
441
442 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
443 if (nvif_msec(device, 2000,
444 if (!nvif_rd32(&dmac->base.user, 0x0004))
445 break;
446 ) < 0) {
447 mutex_unlock(&dmac->lock);
448 printk(KERN_ERR "nouveau: evo channel stalled\n");
449 return NULL;
450 }
451
452 put = 0;
453 }
454
455 return dmac->ptr + put;
456 }
457
458 static void
459 evo_kick(u32 *push, void *evoc)
460 {
461 struct nv50_dmac *dmac = evoc;
462 nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
463 mutex_unlock(&dmac->lock);
464 }
465
466 #if 1
467 #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
468 #define evo_data(p,d) *((p)++) = (d)
469 #else
470 #define evo_mthd(p,m,s) do { \
471 const u32 _m = (m), _s = (s); \
472 printk(KERN_ERR "%04x %d %s\n", _m, _s, __func__); \
473 *((p)++) = ((_s << 18) | _m); \
474 } while(0)
475 #define evo_data(p,d) do { \
476 const u32 _d = (d); \
477 printk(KERN_ERR "\t%08x\n", _d); \
478 *((p)++) = _d; \
479 } while(0)
480 #endif
481
482 static bool
483 evo_sync_wait(void *data)
484 {
485 if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000)
486 return true;
487 usleep_range(1, 2);
488 return false;
489 }
490
491 static int
492 evo_sync(struct drm_device *dev)
493 {
494 struct nvif_device *device = &nouveau_drm(dev)->device;
495 struct nv50_disp *disp = nv50_disp(dev);
496 struct nv50_mast *mast = nv50_mast(dev);
497 u32 *push = evo_wait(mast, 8);
498 if (push) {
499 nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
500 evo_mthd(push, 0x0084, 1);
501 evo_data(push, 0x80000000 | EVO_MAST_NTFY);
502 evo_mthd(push, 0x0080, 2);
503 evo_data(push, 0x00000000);
504 evo_data(push, 0x00000000);
505 evo_kick(push, mast);
506 if (nvif_msec(device, 2000,
507 if (evo_sync_wait(disp->sync))
508 break;
509 ) >= 0)
510 return 0;
511 }
512
513 return -EBUSY;
514 }
515
516 /******************************************************************************
517 * Page flipping channel
518 *****************************************************************************/
519 struct nouveau_bo *
520 nv50_display_crtc_sema(struct drm_device *dev, int crtc)
521 {
522 return nv50_disp(dev)->sync;
523 }
524
525 struct nv50_display_flip {
526 struct nv50_disp *disp;
527 struct nv50_sync *chan;
528 };
529
530 static bool
531 nv50_display_flip_wait(void *data)
532 {
533 struct nv50_display_flip *flip = data;
534 if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) ==
535 flip->chan->data)
536 return true;
537 usleep_range(1, 2);
538 return false;
539 }
540
541 void
542 nv50_display_flip_stop(struct drm_crtc *crtc)
543 {
544 struct nvif_device *device = &nouveau_drm(crtc->dev)->device;
545 struct nv50_display_flip flip = {
546 .disp = nv50_disp(crtc->dev),
547 .chan = nv50_sync(crtc),
548 };
549 u32 *push;
550
551 push = evo_wait(flip.chan, 8);
552 if (push) {
553 evo_mthd(push, 0x0084, 1);
554 evo_data(push, 0x00000000);
555 evo_mthd(push, 0x0094, 1);
556 evo_data(push, 0x00000000);
557 evo_mthd(push, 0x00c0, 1);
558 evo_data(push, 0x00000000);
559 evo_mthd(push, 0x0080, 1);
560 evo_data(push, 0x00000000);
561 evo_kick(push, flip.chan);
562 }
563
564 nvif_msec(device, 2000,
565 if (nv50_display_flip_wait(&flip))
566 break;
567 );
568 }
569
570 int
571 nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
572 struct nouveau_channel *chan, u32 swap_interval)
573 {
574 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
575 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
576 struct nv50_head *head = nv50_head(crtc);
577 struct nv50_sync *sync = nv50_sync(crtc);
578 u32 *push;
579 int ret;
580
581 if (crtc->primary->fb->width != fb->width ||
582 crtc->primary->fb->height != fb->height)
583 return -EINVAL;
584
585 swap_interval <<= 4;
586 if (swap_interval == 0)
587 swap_interval |= 0x100;
588 if (chan == NULL)
589 evo_sync(crtc->dev);
590
591 push = evo_wait(sync, 128);
592 if (unlikely(push == NULL))
593 return -EBUSY;
594
595 if (chan && chan->user.oclass < G82_CHANNEL_GPFIFO) {
596 ret = RING_SPACE(chan, 8);
597 if (ret)
598 return ret;
599
600 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
601 OUT_RING (chan, NvEvoSema0 + nv_crtc->index);
602 OUT_RING (chan, sync->addr ^ 0x10);
603 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
604 OUT_RING (chan, sync->data + 1);
605 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
606 OUT_RING (chan, sync->addr);
607 OUT_RING (chan, sync->data);
608 } else
609 if (chan && chan->user.oclass < FERMI_CHANNEL_GPFIFO) {
610 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
611 ret = RING_SPACE(chan, 12);
612 if (ret)
613 return ret;
614
615 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
616 OUT_RING (chan, chan->vram.handle);
617 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
618 OUT_RING (chan, upper_32_bits(addr ^ 0x10));
619 OUT_RING (chan, lower_32_bits(addr ^ 0x10));
620 OUT_RING (chan, sync->data + 1);
621 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
622 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
623 OUT_RING (chan, upper_32_bits(addr));
624 OUT_RING (chan, lower_32_bits(addr));
625 OUT_RING (chan, sync->data);
626 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL);
627 } else
628 if (chan) {
629 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
630 ret = RING_SPACE(chan, 10);
631 if (ret)
632 return ret;
633
634 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
635 OUT_RING (chan, upper_32_bits(addr ^ 0x10));
636 OUT_RING (chan, lower_32_bits(addr ^ 0x10));
637 OUT_RING (chan, sync->data + 1);
638 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG |
639 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
640 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
641 OUT_RING (chan, upper_32_bits(addr));
642 OUT_RING (chan, lower_32_bits(addr));
643 OUT_RING (chan, sync->data);
644 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL |
645 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
646 }
647
648 if (chan) {
649 sync->addr ^= 0x10;
650 sync->data++;
651 FIRE_RING (chan);
652 }
653
654 /* queue the flip */
655 evo_mthd(push, 0x0100, 1);
656 evo_data(push, 0xfffe0000);
657 evo_mthd(push, 0x0084, 1);
658 evo_data(push, swap_interval);
659 if (!(swap_interval & 0x00000100)) {
660 evo_mthd(push, 0x00e0, 1);
661 evo_data(push, 0x40000000);
662 }
663 evo_mthd(push, 0x0088, 4);
664 evo_data(push, sync->addr);
665 evo_data(push, sync->data++);
666 evo_data(push, sync->data);
667 evo_data(push, sync->base.sync.handle);
668 evo_mthd(push, 0x00a0, 2);
669 evo_data(push, 0x00000000);
670 evo_data(push, 0x00000000);
671 evo_mthd(push, 0x00c0, 1);
672 evo_data(push, nv_fb->r_handle);
673 evo_mthd(push, 0x0110, 2);
674 evo_data(push, 0x00000000);
675 evo_data(push, 0x00000000);
676 if (nv50_vers(sync) < GF110_DISP_BASE_CHANNEL_DMA) {
677 evo_mthd(push, 0x0800, 5);
678 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
679 evo_data(push, 0);
680 evo_data(push, (fb->height << 16) | fb->width);
681 evo_data(push, nv_fb->r_pitch);
682 evo_data(push, nv_fb->r_format);
683 } else {
684 evo_mthd(push, 0x0400, 5);
685 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
686 evo_data(push, 0);
687 evo_data(push, (fb->height << 16) | fb->width);
688 evo_data(push, nv_fb->r_pitch);
689 evo_data(push, nv_fb->r_format);
690 }
691 evo_mthd(push, 0x0080, 1);
692 evo_data(push, 0x00000000);
693 evo_kick(push, sync);
694
695 nouveau_bo_ref(nv_fb->nvbo, &head->image);
696 return 0;
697 }
698
699 /******************************************************************************
700 * CRTC
701 *****************************************************************************/
702 static int
703 nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
704 {
705 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
706 struct nouveau_connector *nv_connector;
707 struct drm_connector *connector;
708 u32 *push, mode = 0x00;
709
710 nv_connector = nouveau_crtc_connector_get(nv_crtc);
711 connector = &nv_connector->base;
712 if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
713 if (nv_crtc->base.primary->fb->depth > connector->display_info.bpc * 3)
714 mode = DITHERING_MODE_DYNAMIC2X2;
715 } else {
716 mode = nv_connector->dithering_mode;
717 }
718
719 if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
720 if (connector->display_info.bpc >= 8)
721 mode |= DITHERING_DEPTH_8BPC;
722 } else {
723 mode |= nv_connector->dithering_depth;
724 }
725
726 push = evo_wait(mast, 4);
727 if (push) {
728 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
729 evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1);
730 evo_data(push, mode);
731 } else
732 if (nv50_vers(mast) < GK104_DISP_CORE_CHANNEL_DMA) {
733 evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1);
734 evo_data(push, mode);
735 } else {
736 evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1);
737 evo_data(push, mode);
738 }
739
740 if (update) {
741 evo_mthd(push, 0x0080, 1);
742 evo_data(push, 0x00000000);
743 }
744 evo_kick(push, mast);
745 }
746
747 return 0;
748 }
749
750 static int
751 nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
752 {
753 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
754 struct drm_display_mode *omode, *umode = &nv_crtc->base.mode;
755 struct drm_crtc *crtc = &nv_crtc->base;
756 struct nouveau_connector *nv_connector;
757 int mode = DRM_MODE_SCALE_NONE;
758 u32 oX, oY, *push;
759
760 /* start off at the resolution we programmed the crtc for, this
761 * effectively handles NONE/FULL scaling
762 */
763 nv_connector = nouveau_crtc_connector_get(nv_crtc);
764 if (nv_connector && nv_connector->native_mode) {
765 mode = nv_connector->scaling_mode;
766 if (nv_connector->scaling_full) /* non-EDID LVDS/eDP mode */
767 mode = DRM_MODE_SCALE_FULLSCREEN;
768 }
769
770 if (mode != DRM_MODE_SCALE_NONE)
771 omode = nv_connector->native_mode;
772 else
773 omode = umode;
774
775 oX = omode->hdisplay;
776 oY = omode->vdisplay;
777 if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
778 oY *= 2;
779
780 /* add overscan compensation if necessary, will keep the aspect
781 * ratio the same as the backend mode unless overridden by the
782 * user setting both hborder and vborder properties.
783 */
784 if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON ||
785 (nv_connector->underscan == UNDERSCAN_AUTO &&
786 drm_detect_hdmi_monitor(nv_connector->edid)))) {
787 u32 bX = nv_connector->underscan_hborder;
788 u32 bY = nv_connector->underscan_vborder;
789 u32 aspect = (oY << 19) / oX;
790
791 if (bX) {
792 oX -= (bX * 2);
793 if (bY) oY -= (bY * 2);
794 else oY = ((oX * aspect) + (aspect / 2)) >> 19;
795 } else {
796 oX -= (oX >> 4) + 32;
797 if (bY) oY -= (bY * 2);
798 else oY = ((oX * aspect) + (aspect / 2)) >> 19;
799 }
800 }
801
802 /* handle CENTER/ASPECT scaling, taking into account the areas
803 * removed already for overscan compensation
804 */
805 switch (mode) {
806 case DRM_MODE_SCALE_CENTER:
807 oX = min((u32)umode->hdisplay, oX);
808 oY = min((u32)umode->vdisplay, oY);
809 /* fall-through */
810 case DRM_MODE_SCALE_ASPECT:
811 if (oY < oX) {
812 u32 aspect = (umode->hdisplay << 19) / umode->vdisplay;
813 oX = ((oY * aspect) + (aspect / 2)) >> 19;
814 } else {
815 u32 aspect = (umode->vdisplay << 19) / umode->hdisplay;
816 oY = ((oX * aspect) + (aspect / 2)) >> 19;
817 }
818 break;
819 default:
820 break;
821 }
822
823 push = evo_wait(mast, 8);
824 if (push) {
825 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
826 /*XXX: SCALE_CTRL_ACTIVE??? */
827 evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2);
828 evo_data(push, (oY << 16) | oX);
829 evo_data(push, (oY << 16) | oX);
830 evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1);
831 evo_data(push, 0x00000000);
832 evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1);
833 evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
834 } else {
835 evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
836 evo_data(push, (oY << 16) | oX);
837 evo_data(push, (oY << 16) | oX);
838 evo_data(push, (oY << 16) | oX);
839 evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
840 evo_data(push, 0x00000000);
841 evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
842 evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
843 }
844
845 evo_kick(push, mast);
846
847 if (update) {
848 nv50_display_flip_stop(crtc);
849 nv50_display_flip_next(crtc, crtc->primary->fb,
850 NULL, 1);
851 }
852 }
853
854 return 0;
855 }
856
857 static int
858 nv50_crtc_set_raster_vblank_dmi(struct nouveau_crtc *nv_crtc, u32 usec)
859 {
860 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
861 u32 *push;
862
863 push = evo_wait(mast, 8);
864 if (!push)
865 return -ENOMEM;
866
867 evo_mthd(push, 0x0828 + (nv_crtc->index * 0x400), 1);
868 evo_data(push, usec);
869 evo_kick(push, mast);
870 return 0;
871 }
872
873 static int
874 nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update)
875 {
876 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
877 u32 *push, hue, vib;
878 int adj;
879
880 adj = (nv_crtc->color_vibrance > 0) ? 50 : 0;
881 vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff;
882 hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff;
883
884 push = evo_wait(mast, 16);
885 if (push) {
886 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
887 evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1);
888 evo_data(push, (hue << 20) | (vib << 8));
889 } else {
890 evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1);
891 evo_data(push, (hue << 20) | (vib << 8));
892 }
893
894 if (update) {
895 evo_mthd(push, 0x0080, 1);
896 evo_data(push, 0x00000000);
897 }
898 evo_kick(push, mast);
899 }
900
901 return 0;
902 }
903
904 static int
905 nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
906 int x, int y, bool update)
907 {
908 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
909 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
910 u32 *push;
911
912 push = evo_wait(mast, 16);
913 if (push) {
914 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
915 evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1);
916 evo_data(push, nvfb->nvbo->bo.offset >> 8);
917 evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3);
918 evo_data(push, (fb->height << 16) | fb->width);
919 evo_data(push, nvfb->r_pitch);
920 evo_data(push, nvfb->r_format);
921 evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1);
922 evo_data(push, (y << 16) | x);
923 if (nv50_vers(mast) > NV50_DISP_CORE_CHANNEL_DMA) {
924 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
925 evo_data(push, nvfb->r_handle);
926 }
927 } else {
928 evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
929 evo_data(push, nvfb->nvbo->bo.offset >> 8);
930 evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
931 evo_data(push, (fb->height << 16) | fb->width);
932 evo_data(push, nvfb->r_pitch);
933 evo_data(push, nvfb->r_format);
934 evo_data(push, nvfb->r_handle);
935 evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
936 evo_data(push, (y << 16) | x);
937 }
938
939 if (update) {
940 evo_mthd(push, 0x0080, 1);
941 evo_data(push, 0x00000000);
942 }
943 evo_kick(push, mast);
944 }
945
946 nv_crtc->fb.handle = nvfb->r_handle;
947 return 0;
948 }
949
950 static void
951 nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc)
952 {
953 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
954 u32 *push = evo_wait(mast, 16);
955 if (push) {
956 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
957 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
958 evo_data(push, 0x85000000);
959 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
960 } else
961 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
962 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
963 evo_data(push, 0x85000000);
964 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
965 evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
966 evo_data(push, mast->base.vram.handle);
967 } else {
968 evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
969 evo_data(push, 0x85000000);
970 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
971 evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
972 evo_data(push, mast->base.vram.handle);
973 }
974 evo_kick(push, mast);
975 }
976 nv_crtc->cursor.visible = true;
977 }
978
979 static void
980 nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc)
981 {
982 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
983 u32 *push = evo_wait(mast, 16);
984 if (push) {
985 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
986 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
987 evo_data(push, 0x05000000);
988 } else
989 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
990 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
991 evo_data(push, 0x05000000);
992 evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
993 evo_data(push, 0x00000000);
994 } else {
995 evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
996 evo_data(push, 0x05000000);
997 evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
998 evo_data(push, 0x00000000);
999 }
1000 evo_kick(push, mast);
1001 }
1002 nv_crtc->cursor.visible = false;
1003 }
1004
1005 static void
1006 nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update)
1007 {
1008 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
1009
1010 if (show && nv_crtc->cursor.nvbo && nv_crtc->base.enabled)
1011 nv50_crtc_cursor_show(nv_crtc);
1012 else
1013 nv50_crtc_cursor_hide(nv_crtc);
1014
1015 if (update) {
1016 u32 *push = evo_wait(mast, 2);
1017 if (push) {
1018 evo_mthd(push, 0x0080, 1);
1019 evo_data(push, 0x00000000);
1020 evo_kick(push, mast);
1021 }
1022 }
1023 }
1024
1025 static void
1026 nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
1027 {
1028 }
1029
1030 static void
1031 nv50_crtc_prepare(struct drm_crtc *crtc)
1032 {
1033 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1034 struct nv50_mast *mast = nv50_mast(crtc->dev);
1035 u32 *push;
1036
1037 nv50_display_flip_stop(crtc);
1038
1039 push = evo_wait(mast, 6);
1040 if (push) {
1041 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
1042 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1043 evo_data(push, 0x00000000);
1044 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
1045 evo_data(push, 0x40000000);
1046 } else
1047 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1048 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1049 evo_data(push, 0x00000000);
1050 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
1051 evo_data(push, 0x40000000);
1052 evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
1053 evo_data(push, 0x00000000);
1054 } else {
1055 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
1056 evo_data(push, 0x00000000);
1057 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
1058 evo_data(push, 0x03000000);
1059 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
1060 evo_data(push, 0x00000000);
1061 }
1062
1063 evo_kick(push, mast);
1064 }
1065
1066 nv50_crtc_cursor_show_hide(nv_crtc, false, false);
1067 }
1068
1069 static void
1070 nv50_crtc_commit(struct drm_crtc *crtc)
1071 {
1072 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1073 struct nv50_mast *mast = nv50_mast(crtc->dev);
1074 u32 *push;
1075
1076 push = evo_wait(mast, 32);
1077 if (push) {
1078 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
1079 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1080 evo_data(push, nv_crtc->fb.handle);
1081 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1082 evo_data(push, 0xc0000000);
1083 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1084 } else
1085 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1086 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1087 evo_data(push, nv_crtc->fb.handle);
1088 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1089 evo_data(push, 0xc0000000);
1090 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1091 evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
1092 evo_data(push, mast->base.vram.handle);
1093 } else {
1094 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
1095 evo_data(push, nv_crtc->fb.handle);
1096 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
1097 evo_data(push, 0x83000000);
1098 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1099 evo_data(push, 0x00000000);
1100 evo_data(push, 0x00000000);
1101 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
1102 evo_data(push, mast->base.vram.handle);
1103 evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
1104 evo_data(push, 0xffffff00);
1105 }
1106
1107 evo_kick(push, mast);
1108 }
1109
1110 nv50_crtc_cursor_show_hide(nv_crtc, true, true);
1111 nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
1112 }
1113
1114 static bool
1115 nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1116 struct drm_display_mode *adjusted_mode)
1117 {
1118 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
1119 return true;
1120 }
1121
1122 static int
1123 nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
1124 {
1125 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb);
1126 struct nv50_head *head = nv50_head(crtc);
1127 int ret;
1128
1129 ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM, true);
1130 if (ret == 0) {
1131 if (head->image)
1132 nouveau_bo_unpin(head->image);
1133 nouveau_bo_ref(nvfb->nvbo, &head->image);
1134 }
1135
1136 return ret;
1137 }
1138
1139 static int
1140 nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
1141 struct drm_display_mode *mode, int x, int y,
1142 struct drm_framebuffer *old_fb)
1143 {
1144 struct nv50_mast *mast = nv50_mast(crtc->dev);
1145 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1146 struct nouveau_connector *nv_connector;
1147 u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
1148 u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
1149 u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
1150 u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
1151 u32 vblan2e = 0, vblan2s = 1, vblankus = 0;
1152 u32 *push;
1153 int ret;
1154
1155 hactive = mode->htotal;
1156 hsynce = mode->hsync_end - mode->hsync_start - 1;
1157 hbackp = mode->htotal - mode->hsync_end;
1158 hblanke = hsynce + hbackp;
1159 hfrontp = mode->hsync_start - mode->hdisplay;
1160 hblanks = mode->htotal - hfrontp - 1;
1161
1162 vactive = mode->vtotal * vscan / ilace;
1163 vsynce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
1164 vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace;
1165 vblanke = vsynce + vbackp;
1166 vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
1167 vblanks = vactive - vfrontp - 1;
1168 /* XXX: Safe underestimate, even "0" works */
1169 vblankus = (vactive - mode->vdisplay - 2) * hactive;
1170 vblankus *= 1000;
1171 vblankus /= mode->clock;
1172
1173 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1174 vblan2e = vactive + vsynce + vbackp;
1175 vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
1176 vactive = (vactive * 2) + 1;
1177 }
1178
1179 ret = nv50_crtc_swap_fbs(crtc, old_fb);
1180 if (ret)
1181 return ret;
1182
1183 push = evo_wait(mast, 64);
1184 if (push) {
1185 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1186 evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2);
1187 evo_data(push, 0x00800000 | mode->clock);
1188 evo_data(push, (ilace == 2) ? 2 : 0);
1189 evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 6);
1190 evo_data(push, 0x00000000);
1191 evo_data(push, (vactive << 16) | hactive);
1192 evo_data(push, ( vsynce << 16) | hsynce);
1193 evo_data(push, (vblanke << 16) | hblanke);
1194 evo_data(push, (vblanks << 16) | hblanks);
1195 evo_data(push, (vblan2e << 16) | vblan2s);
1196 evo_mthd(push, 0x082c + (nv_crtc->index * 0x400), 1);
1197 evo_data(push, 0x00000000);
1198 evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2);
1199 evo_data(push, 0x00000311);
1200 evo_data(push, 0x00000100);
1201 } else {
1202 evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6);
1203 evo_data(push, 0x00000000);
1204 evo_data(push, (vactive << 16) | hactive);
1205 evo_data(push, ( vsynce << 16) | hsynce);
1206 evo_data(push, (vblanke << 16) | hblanke);
1207 evo_data(push, (vblanks << 16) | hblanks);
1208 evo_data(push, (vblan2e << 16) | vblan2s);
1209 evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
1210 evo_data(push, 0x00000000); /* ??? */
1211 evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
1212 evo_data(push, mode->clock * 1000);
1213 evo_data(push, 0x00200000); /* ??? */
1214 evo_data(push, mode->clock * 1000);
1215 evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2);
1216 evo_data(push, 0x00000311);
1217 evo_data(push, 0x00000100);
1218 }
1219
1220 evo_kick(push, mast);
1221 }
1222
1223 nv_connector = nouveau_crtc_connector_get(nv_crtc);
1224 nv50_crtc_set_dither(nv_crtc, false);
1225 nv50_crtc_set_scale(nv_crtc, false);
1226
1227 /* G94 only accepts this after setting scale */
1228 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA)
1229 nv50_crtc_set_raster_vblank_dmi(nv_crtc, vblankus);
1230
1231 nv50_crtc_set_color_vibrance(nv_crtc, false);
1232 nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, false);
1233 return 0;
1234 }
1235
1236 static int
1237 nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
1238 struct drm_framebuffer *old_fb)
1239 {
1240 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
1241 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1242 int ret;
1243
1244 if (!crtc->primary->fb) {
1245 NV_DEBUG(drm, "No FB bound\n");
1246 return 0;
1247 }
1248
1249 ret = nv50_crtc_swap_fbs(crtc, old_fb);
1250 if (ret)
1251 return ret;
1252
1253 nv50_display_flip_stop(crtc);
1254 nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, true);
1255 nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
1256 return 0;
1257 }
1258
1259 static int
1260 nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
1261 struct drm_framebuffer *fb, int x, int y,
1262 enum mode_set_atomic state)
1263 {
1264 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1265 nv50_display_flip_stop(crtc);
1266 nv50_crtc_set_image(nv_crtc, fb, x, y, true);
1267 return 0;
1268 }
1269
1270 static void
1271 nv50_crtc_lut_load(struct drm_crtc *crtc)
1272 {
1273 struct nv50_disp *disp = nv50_disp(crtc->dev);
1274 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1275 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
1276 int i;
1277
1278 for (i = 0; i < 256; i++) {
1279 u16 r = nv_crtc->lut.r[i] >> 2;
1280 u16 g = nv_crtc->lut.g[i] >> 2;
1281 u16 b = nv_crtc->lut.b[i] >> 2;
1282
1283 if (disp->disp->oclass < GF110_DISP) {
1284 writew(r + 0x0000, lut + (i * 0x08) + 0);
1285 writew(g + 0x0000, lut + (i * 0x08) + 2);
1286 writew(b + 0x0000, lut + (i * 0x08) + 4);
1287 } else {
1288 writew(r + 0x6000, lut + (i * 0x20) + 0);
1289 writew(g + 0x6000, lut + (i * 0x20) + 2);
1290 writew(b + 0x6000, lut + (i * 0x20) + 4);
1291 }
1292 }
1293 }
1294
1295 static void
1296 nv50_crtc_disable(struct drm_crtc *crtc)
1297 {
1298 struct nv50_head *head = nv50_head(crtc);
1299 evo_sync(crtc->dev);
1300 if (head->image)
1301 nouveau_bo_unpin(head->image);
1302 nouveau_bo_ref(NULL, &head->image);
1303 }
1304
1305 static int
1306 nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
1307 uint32_t handle, uint32_t width, uint32_t height)
1308 {
1309 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1310 struct drm_gem_object *gem = NULL;
1311 struct nouveau_bo *nvbo = NULL;
1312 int ret = 0;
1313
1314 if (handle) {
1315 if (width != 64 || height != 64)
1316 return -EINVAL;
1317
1318 gem = drm_gem_object_lookup(file_priv, handle);
1319 if (unlikely(!gem))
1320 return -ENOENT;
1321 nvbo = nouveau_gem_object(gem);
1322
1323 ret = nouveau_bo_pin(nvbo, TTM_PL_FLAG_VRAM, true);
1324 }
1325
1326 if (ret == 0) {
1327 if (nv_crtc->cursor.nvbo)
1328 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1329 nouveau_bo_ref(nvbo, &nv_crtc->cursor.nvbo);
1330 }
1331 drm_gem_object_unreference_unlocked(gem);
1332
1333 nv50_crtc_cursor_show_hide(nv_crtc, true, true);
1334 return ret;
1335 }
1336
1337 static int
1338 nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1339 {
1340 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1341 struct nv50_curs *curs = nv50_curs(crtc);
1342 struct nv50_chan *chan = nv50_chan(curs);
1343 nvif_wr32(&chan->user, 0x0084, (y << 16) | (x & 0xffff));
1344 nvif_wr32(&chan->user, 0x0080, 0x00000000);
1345
1346 nv_crtc->cursor_saved_x = x;
1347 nv_crtc->cursor_saved_y = y;
1348 return 0;
1349 }
1350
1351 static int
1352 nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
1353 uint32_t size)
1354 {
1355 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1356 u32 i;
1357
1358 for (i = 0; i < size; i++) {
1359 nv_crtc->lut.r[i] = r[i];
1360 nv_crtc->lut.g[i] = g[i];
1361 nv_crtc->lut.b[i] = b[i];
1362 }
1363
1364 nv50_crtc_lut_load(crtc);
1365
1366 return 0;
1367 }
1368
1369 static void
1370 nv50_crtc_cursor_restore(struct nouveau_crtc *nv_crtc, int x, int y)
1371 {
1372 nv50_crtc_cursor_move(&nv_crtc->base, x, y);
1373
1374 nv50_crtc_cursor_show_hide(nv_crtc, true, true);
1375 }
1376
1377 static void
1378 nv50_crtc_destroy(struct drm_crtc *crtc)
1379 {
1380 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1381 struct nv50_disp *disp = nv50_disp(crtc->dev);
1382 struct nv50_head *head = nv50_head(crtc);
1383 struct nv50_fbdma *fbdma;
1384
1385 list_for_each_entry(fbdma, &disp->fbdma, head) {
1386 nvif_object_fini(&fbdma->base[nv_crtc->index]);
1387 }
1388
1389 nv50_dmac_destroy(&head->ovly.base, disp->disp);
1390 nv50_pioc_destroy(&head->oimm.base);
1391 nv50_dmac_destroy(&head->sync.base, disp->disp);
1392 nv50_pioc_destroy(&head->curs.base);
1393
1394 /*XXX: this shouldn't be necessary, but the core doesn't call
1395 * disconnect() during the cleanup paths
1396 */
1397 if (head->image)
1398 nouveau_bo_unpin(head->image);
1399 nouveau_bo_ref(NULL, &head->image);
1400
1401 /*XXX: ditto */
1402 if (nv_crtc->cursor.nvbo)
1403 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1404 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
1405
1406 nouveau_bo_unmap(nv_crtc->lut.nvbo);
1407 if (nv_crtc->lut.nvbo)
1408 nouveau_bo_unpin(nv_crtc->lut.nvbo);
1409 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
1410
1411 drm_crtc_cleanup(crtc);
1412 kfree(crtc);
1413 }
1414
1415 static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = {
1416 .dpms = nv50_crtc_dpms,
1417 .prepare = nv50_crtc_prepare,
1418 .commit = nv50_crtc_commit,
1419 .mode_fixup = nv50_crtc_mode_fixup,
1420 .mode_set = nv50_crtc_mode_set,
1421 .mode_set_base = nv50_crtc_mode_set_base,
1422 .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
1423 .load_lut = nv50_crtc_lut_load,
1424 .disable = nv50_crtc_disable,
1425 };
1426
1427 static const struct drm_crtc_funcs nv50_crtc_func = {
1428 .cursor_set = nv50_crtc_cursor_set,
1429 .cursor_move = nv50_crtc_cursor_move,
1430 .gamma_set = nv50_crtc_gamma_set,
1431 .set_config = nouveau_crtc_set_config,
1432 .destroy = nv50_crtc_destroy,
1433 .page_flip = nouveau_crtc_page_flip,
1434 };
1435
1436 static int
1437 nv50_crtc_create(struct drm_device *dev, int index)
1438 {
1439 struct nouveau_drm *drm = nouveau_drm(dev);
1440 struct nvif_device *device = &drm->device;
1441 struct nv50_disp *disp = nv50_disp(dev);
1442 struct nv50_head *head;
1443 struct drm_crtc *crtc;
1444 int ret, i;
1445
1446 head = kzalloc(sizeof(*head), GFP_KERNEL);
1447 if (!head)
1448 return -ENOMEM;
1449
1450 head->base.index = index;
1451 head->base.set_dither = nv50_crtc_set_dither;
1452 head->base.set_scale = nv50_crtc_set_scale;
1453 head->base.set_color_vibrance = nv50_crtc_set_color_vibrance;
1454 head->base.color_vibrance = 50;
1455 head->base.vibrant_hue = 0;
1456 head->base.cursor.set_pos = nv50_crtc_cursor_restore;
1457 for (i = 0; i < 256; i++) {
1458 head->base.lut.r[i] = i << 8;
1459 head->base.lut.g[i] = i << 8;
1460 head->base.lut.b[i] = i << 8;
1461 }
1462
1463 crtc = &head->base.base;
1464 drm_crtc_init(dev, crtc, &nv50_crtc_func);
1465 drm_crtc_helper_add(crtc, &nv50_crtc_hfunc);
1466 drm_mode_crtc_set_gamma_size(crtc, 256);
1467
1468 ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
1469 0, 0x0000, NULL, NULL, &head->base.lut.nvbo);
1470 if (!ret) {
1471 ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM, true);
1472 if (!ret) {
1473 ret = nouveau_bo_map(head->base.lut.nvbo);
1474 if (ret)
1475 nouveau_bo_unpin(head->base.lut.nvbo);
1476 }
1477 if (ret)
1478 nouveau_bo_ref(NULL, &head->base.lut.nvbo);
1479 }
1480
1481 if (ret)
1482 goto out;
1483
1484 /* allocate cursor resources */
1485 ret = nv50_curs_create(device, disp->disp, index, &head->curs);
1486 if (ret)
1487 goto out;
1488
1489 /* allocate page flip / sync resources */
1490 ret = nv50_base_create(device, disp->disp, index, disp->sync->bo.offset,
1491 &head->sync);
1492 if (ret)
1493 goto out;
1494
1495 head->sync.addr = EVO_FLIP_SEM0(index);
1496 head->sync.data = 0x00000000;
1497
1498 /* allocate overlay resources */
1499 ret = nv50_oimm_create(device, disp->disp, index, &head->oimm);
1500 if (ret)
1501 goto out;
1502
1503 ret = nv50_ovly_create(device, disp->disp, index, disp->sync->bo.offset,
1504 &head->ovly);
1505 if (ret)
1506 goto out;
1507
1508 out:
1509 if (ret)
1510 nv50_crtc_destroy(crtc);
1511 return ret;
1512 }
1513
1514 /******************************************************************************
1515 * Encoder helpers
1516 *****************************************************************************/
1517 static bool
1518 nv50_encoder_mode_fixup(struct drm_encoder *encoder,
1519 const struct drm_display_mode *mode,
1520 struct drm_display_mode *adjusted_mode)
1521 {
1522 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1523 struct nouveau_connector *nv_connector;
1524
1525 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1526 if (nv_connector && nv_connector->native_mode) {
1527 nv_connector->scaling_full = false;
1528 if (nv_connector->scaling_mode == DRM_MODE_SCALE_NONE) {
1529 switch (nv_connector->type) {
1530 case DCB_CONNECTOR_LVDS:
1531 case DCB_CONNECTOR_LVDS_SPWG:
1532 case DCB_CONNECTOR_eDP:
1533 /* force use of scaler for non-edid modes */
1534 if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
1535 return true;
1536 nv_connector->scaling_full = true;
1537 break;
1538 default:
1539 return true;
1540 }
1541 }
1542
1543 drm_mode_copy(adjusted_mode, nv_connector->native_mode);
1544 }
1545
1546 return true;
1547 }
1548
1549 /******************************************************************************
1550 * DAC
1551 *****************************************************************************/
1552 static void
1553 nv50_dac_dpms(struct drm_encoder *encoder, int mode)
1554 {
1555 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1556 struct nv50_disp *disp = nv50_disp(encoder->dev);
1557 struct {
1558 struct nv50_disp_mthd_v1 base;
1559 struct nv50_disp_dac_pwr_v0 pwr;
1560 } args = {
1561 .base.version = 1,
1562 .base.method = NV50_DISP_MTHD_V1_DAC_PWR,
1563 .base.hasht = nv_encoder->dcb->hasht,
1564 .base.hashm = nv_encoder->dcb->hashm,
1565 .pwr.state = 1,
1566 .pwr.data = 1,
1567 .pwr.vsync = (mode != DRM_MODE_DPMS_SUSPEND &&
1568 mode != DRM_MODE_DPMS_OFF),
1569 .pwr.hsync = (mode != DRM_MODE_DPMS_STANDBY &&
1570 mode != DRM_MODE_DPMS_OFF),
1571 };
1572
1573 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1574 }
1575
1576 static void
1577 nv50_dac_commit(struct drm_encoder *encoder)
1578 {
1579 }
1580
1581 static void
1582 nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1583 struct drm_display_mode *adjusted_mode)
1584 {
1585 struct nv50_mast *mast = nv50_mast(encoder->dev);
1586 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1587 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1588 u32 *push;
1589
1590 nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1591
1592 push = evo_wait(mast, 8);
1593 if (push) {
1594 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1595 u32 syncs = 0x00000000;
1596
1597 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1598 syncs |= 0x00000001;
1599 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1600 syncs |= 0x00000002;
1601
1602 evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
1603 evo_data(push, 1 << nv_crtc->index);
1604 evo_data(push, syncs);
1605 } else {
1606 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1607 u32 syncs = 0x00000001;
1608
1609 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1610 syncs |= 0x00000008;
1611 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1612 syncs |= 0x00000010;
1613
1614 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1615 magic |= 0x00000001;
1616
1617 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1618 evo_data(push, syncs);
1619 evo_data(push, magic);
1620 evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
1621 evo_data(push, 1 << nv_crtc->index);
1622 }
1623
1624 evo_kick(push, mast);
1625 }
1626
1627 nv_encoder->crtc = encoder->crtc;
1628 }
1629
1630 static void
1631 nv50_dac_disconnect(struct drm_encoder *encoder)
1632 {
1633 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1634 struct nv50_mast *mast = nv50_mast(encoder->dev);
1635 const int or = nv_encoder->or;
1636 u32 *push;
1637
1638 if (nv_encoder->crtc) {
1639 nv50_crtc_prepare(nv_encoder->crtc);
1640
1641 push = evo_wait(mast, 4);
1642 if (push) {
1643 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1644 evo_mthd(push, 0x0400 + (or * 0x080), 1);
1645 evo_data(push, 0x00000000);
1646 } else {
1647 evo_mthd(push, 0x0180 + (or * 0x020), 1);
1648 evo_data(push, 0x00000000);
1649 }
1650 evo_kick(push, mast);
1651 }
1652 }
1653
1654 nv_encoder->crtc = NULL;
1655 }
1656
1657 static enum drm_connector_status
1658 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1659 {
1660 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1661 struct nv50_disp *disp = nv50_disp(encoder->dev);
1662 struct {
1663 struct nv50_disp_mthd_v1 base;
1664 struct nv50_disp_dac_load_v0 load;
1665 } args = {
1666 .base.version = 1,
1667 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
1668 .base.hasht = nv_encoder->dcb->hasht,
1669 .base.hashm = nv_encoder->dcb->hashm,
1670 };
1671 int ret;
1672
1673 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
1674 if (args.load.data == 0)
1675 args.load.data = 340;
1676
1677 ret = nvif_mthd(disp->disp, 0, &args, sizeof(args));
1678 if (ret || !args.load.load)
1679 return connector_status_disconnected;
1680
1681 return connector_status_connected;
1682 }
1683
1684 static void
1685 nv50_dac_destroy(struct drm_encoder *encoder)
1686 {
1687 drm_encoder_cleanup(encoder);
1688 kfree(encoder);
1689 }
1690
1691 static const struct drm_encoder_helper_funcs nv50_dac_hfunc = {
1692 .dpms = nv50_dac_dpms,
1693 .mode_fixup = nv50_encoder_mode_fixup,
1694 .prepare = nv50_dac_disconnect,
1695 .commit = nv50_dac_commit,
1696 .mode_set = nv50_dac_mode_set,
1697 .disable = nv50_dac_disconnect,
1698 .get_crtc = nv50_display_crtc_get,
1699 .detect = nv50_dac_detect
1700 };
1701
1702 static const struct drm_encoder_funcs nv50_dac_func = {
1703 .destroy = nv50_dac_destroy,
1704 };
1705
1706 static int
1707 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
1708 {
1709 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1710 struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
1711 struct nvkm_i2c_bus *bus;
1712 struct nouveau_encoder *nv_encoder;
1713 struct drm_encoder *encoder;
1714 int type = DRM_MODE_ENCODER_DAC;
1715
1716 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1717 if (!nv_encoder)
1718 return -ENOMEM;
1719 nv_encoder->dcb = dcbe;
1720 nv_encoder->or = ffs(dcbe->or) - 1;
1721
1722 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1723 if (bus)
1724 nv_encoder->i2c = &bus->i2c;
1725
1726 encoder = to_drm_encoder(nv_encoder);
1727 encoder->possible_crtcs = dcbe->heads;
1728 encoder->possible_clones = 0;
1729 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type, NULL);
1730 drm_encoder_helper_add(encoder, &nv50_dac_hfunc);
1731
1732 drm_mode_connector_attach_encoder(connector, encoder);
1733 return 0;
1734 }
1735
1736 /******************************************************************************
1737 * Audio
1738 *****************************************************************************/
1739 static void
1740 nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1741 {
1742 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1743 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1744 struct nouveau_connector *nv_connector;
1745 struct nv50_disp *disp = nv50_disp(encoder->dev);
1746 struct __packed {
1747 struct {
1748 struct nv50_disp_mthd_v1 mthd;
1749 struct nv50_disp_sor_hda_eld_v0 eld;
1750 } base;
1751 u8 data[sizeof(nv_connector->base.eld)];
1752 } args = {
1753 .base.mthd.version = 1,
1754 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
1755 .base.mthd.hasht = nv_encoder->dcb->hasht,
1756 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
1757 (0x0100 << nv_crtc->index),
1758 };
1759
1760 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1761 if (!drm_detect_monitor_audio(nv_connector->edid))
1762 return;
1763
1764 drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
1765 memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
1766
1767 nvif_mthd(disp->disp, 0, &args,
1768 sizeof(args.base) + drm_eld_size(args.data));
1769 }
1770
1771 static void
1772 nv50_audio_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
1773 {
1774 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1775 struct nv50_disp *disp = nv50_disp(encoder->dev);
1776 struct {
1777 struct nv50_disp_mthd_v1 base;
1778 struct nv50_disp_sor_hda_eld_v0 eld;
1779 } args = {
1780 .base.version = 1,
1781 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
1782 .base.hasht = nv_encoder->dcb->hasht,
1783 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
1784 (0x0100 << nv_crtc->index),
1785 };
1786
1787 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1788 }
1789
1790 /******************************************************************************
1791 * HDMI
1792 *****************************************************************************/
1793 static void
1794 nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1795 {
1796 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1797 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1798 struct nv50_disp *disp = nv50_disp(encoder->dev);
1799 struct {
1800 struct nv50_disp_mthd_v1 base;
1801 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
1802 } args = {
1803 .base.version = 1,
1804 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
1805 .base.hasht = nv_encoder->dcb->hasht,
1806 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
1807 (0x0100 << nv_crtc->index),
1808 .pwr.state = 1,
1809 .pwr.rekey = 56, /* binary driver, and tegra, constant */
1810 };
1811 struct nouveau_connector *nv_connector;
1812 u32 max_ac_packet;
1813
1814 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1815 if (!drm_detect_hdmi_monitor(nv_connector->edid))
1816 return;
1817
1818 max_ac_packet = mode->htotal - mode->hdisplay;
1819 max_ac_packet -= args.pwr.rekey;
1820 max_ac_packet -= 18; /* constant from tegra */
1821 args.pwr.max_ac_packet = max_ac_packet / 32;
1822
1823 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1824 nv50_audio_mode_set(encoder, mode);
1825 }
1826
1827 static void
1828 nv50_hdmi_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
1829 {
1830 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1831 struct nv50_disp *disp = nv50_disp(encoder->dev);
1832 struct {
1833 struct nv50_disp_mthd_v1 base;
1834 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
1835 } args = {
1836 .base.version = 1,
1837 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
1838 .base.hasht = nv_encoder->dcb->hasht,
1839 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
1840 (0x0100 << nv_crtc->index),
1841 };
1842
1843 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1844 }
1845
1846 /******************************************************************************
1847 * SOR
1848 *****************************************************************************/
1849 static void
1850 nv50_sor_dpms(struct drm_encoder *encoder, int mode)
1851 {
1852 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1853 struct nv50_disp *disp = nv50_disp(encoder->dev);
1854 struct {
1855 struct nv50_disp_mthd_v1 base;
1856 struct nv50_disp_sor_pwr_v0 pwr;
1857 } args = {
1858 .base.version = 1,
1859 .base.method = NV50_DISP_MTHD_V1_SOR_PWR,
1860 .base.hasht = nv_encoder->dcb->hasht,
1861 .base.hashm = nv_encoder->dcb->hashm,
1862 .pwr.state = mode == DRM_MODE_DPMS_ON,
1863 };
1864 struct {
1865 struct nv50_disp_mthd_v1 base;
1866 struct nv50_disp_sor_dp_pwr_v0 pwr;
1867 } link = {
1868 .base.version = 1,
1869 .base.method = NV50_DISP_MTHD_V1_SOR_DP_PWR,
1870 .base.hasht = nv_encoder->dcb->hasht,
1871 .base.hashm = nv_encoder->dcb->hashm,
1872 .pwr.state = mode == DRM_MODE_DPMS_ON,
1873 };
1874 struct drm_device *dev = encoder->dev;
1875 struct drm_encoder *partner;
1876
1877 nv_encoder->last_dpms = mode;
1878
1879 list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
1880 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
1881
1882 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
1883 continue;
1884
1885 if (nv_partner != nv_encoder &&
1886 nv_partner->dcb->or == nv_encoder->dcb->or) {
1887 if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
1888 return;
1889 break;
1890 }
1891 }
1892
1893 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
1894 args.pwr.state = 1;
1895 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1896 nvif_mthd(disp->disp, 0, &link, sizeof(link));
1897 } else {
1898 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1899 }
1900 }
1901
1902 static void
1903 nv50_sor_ctrl(struct nouveau_encoder *nv_encoder, u32 mask, u32 data)
1904 {
1905 struct nv50_mast *mast = nv50_mast(nv_encoder->base.base.dev);
1906 u32 temp = (nv_encoder->ctrl & ~mask) | (data & mask), *push;
1907 if (temp != nv_encoder->ctrl && (push = evo_wait(mast, 2))) {
1908 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1909 evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1);
1910 evo_data(push, (nv_encoder->ctrl = temp));
1911 } else {
1912 evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
1913 evo_data(push, (nv_encoder->ctrl = temp));
1914 }
1915 evo_kick(push, mast);
1916 }
1917 }
1918
1919 static void
1920 nv50_sor_disconnect(struct drm_encoder *encoder)
1921 {
1922 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1923 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1924
1925 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1926 nv_encoder->crtc = NULL;
1927
1928 if (nv_crtc) {
1929 nv50_crtc_prepare(&nv_crtc->base);
1930 nv50_sor_ctrl(nv_encoder, 1 << nv_crtc->index, 0);
1931 nv50_audio_disconnect(encoder, nv_crtc);
1932 nv50_hdmi_disconnect(&nv_encoder->base.base, nv_crtc);
1933 }
1934 }
1935
1936 static void
1937 nv50_sor_commit(struct drm_encoder *encoder)
1938 {
1939 }
1940
1941 static void
1942 nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1943 struct drm_display_mode *mode)
1944 {
1945 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1946 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1947 struct {
1948 struct nv50_disp_mthd_v1 base;
1949 struct nv50_disp_sor_lvds_script_v0 lvds;
1950 } lvds = {
1951 .base.version = 1,
1952 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1953 .base.hasht = nv_encoder->dcb->hasht,
1954 .base.hashm = nv_encoder->dcb->hashm,
1955 };
1956 struct nv50_disp *disp = nv50_disp(encoder->dev);
1957 struct nv50_mast *mast = nv50_mast(encoder->dev);
1958 struct drm_device *dev = encoder->dev;
1959 struct nouveau_drm *drm = nouveau_drm(dev);
1960 struct nouveau_connector *nv_connector;
1961 struct nvbios *bios = &drm->vbios;
1962 u32 mask, ctrl;
1963 u8 owner = 1 << nv_crtc->index;
1964 u8 proto = 0xf;
1965 u8 depth = 0x0;
1966
1967 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1968 nv_encoder->crtc = encoder->crtc;
1969
1970 switch (nv_encoder->dcb->type) {
1971 case DCB_OUTPUT_TMDS:
1972 if (nv_encoder->dcb->sorconf.link & 1) {
1973 proto = 0x1;
1974 /* Only enable dual-link if:
1975 * - Need to (i.e. rate > 165MHz)
1976 * - DCB says we can
1977 * - Not an HDMI monitor, since there's no dual-link
1978 * on HDMI.
1979 */
1980 if (mode->clock >= 165000 &&
1981 nv_encoder->dcb->duallink_possible &&
1982 !drm_detect_hdmi_monitor(nv_connector->edid))
1983 proto |= 0x4;
1984 } else {
1985 proto = 0x2;
1986 }
1987
1988 nv50_hdmi_mode_set(&nv_encoder->base.base, mode);
1989 break;
1990 case DCB_OUTPUT_LVDS:
1991 proto = 0x0;
1992
1993 if (bios->fp_no_ddc) {
1994 if (bios->fp.dual_link)
1995 lvds.lvds.script |= 0x0100;
1996 if (bios->fp.if_is_24bit)
1997 lvds.lvds.script |= 0x0200;
1998 } else {
1999 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
2000 if (((u8 *)nv_connector->edid)[121] == 2)
2001 lvds.lvds.script |= 0x0100;
2002 } else
2003 if (mode->clock >= bios->fp.duallink_transition_clk) {
2004 lvds.lvds.script |= 0x0100;
2005 }
2006
2007 if (lvds.lvds.script & 0x0100) {
2008 if (bios->fp.strapless_is_24bit & 2)
2009 lvds.lvds.script |= 0x0200;
2010 } else {
2011 if (bios->fp.strapless_is_24bit & 1)
2012 lvds.lvds.script |= 0x0200;
2013 }
2014
2015 if (nv_connector->base.display_info.bpc == 8)
2016 lvds.lvds.script |= 0x0200;
2017 }
2018
2019 nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds));
2020 break;
2021 case DCB_OUTPUT_DP:
2022 if (nv_connector->base.display_info.bpc == 6) {
2023 nv_encoder->dp.datarate = mode->clock * 18 / 8;
2024 depth = 0x2;
2025 } else
2026 if (nv_connector->base.display_info.bpc == 8) {
2027 nv_encoder->dp.datarate = mode->clock * 24 / 8;
2028 depth = 0x5;
2029 } else {
2030 nv_encoder->dp.datarate = mode->clock * 30 / 8;
2031 depth = 0x6;
2032 }
2033
2034 if (nv_encoder->dcb->sorconf.link & 1)
2035 proto = 0x8;
2036 else
2037 proto = 0x9;
2038 nv50_audio_mode_set(encoder, mode);
2039 break;
2040 default:
2041 BUG_ON(1);
2042 break;
2043 }
2044
2045 nv50_sor_dpms(&nv_encoder->base.base, DRM_MODE_DPMS_ON);
2046
2047 if (nv50_vers(mast) >= GF110_DISP) {
2048 u32 *push = evo_wait(mast, 3);
2049 if (push) {
2050 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
2051 u32 syncs = 0x00000001;
2052
2053 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2054 syncs |= 0x00000008;
2055 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2056 syncs |= 0x00000010;
2057
2058 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2059 magic |= 0x00000001;
2060
2061 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
2062 evo_data(push, syncs | (depth << 6));
2063 evo_data(push, magic);
2064 evo_kick(push, mast);
2065 }
2066
2067 ctrl = proto << 8;
2068 mask = 0x00000f00;
2069 } else {
2070 ctrl = (depth << 16) | (proto << 8);
2071 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2072 ctrl |= 0x00001000;
2073 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2074 ctrl |= 0x00002000;
2075 mask = 0x000f3f00;
2076 }
2077
2078 nv50_sor_ctrl(nv_encoder, mask | owner, ctrl | owner);
2079 }
2080
2081 static void
2082 nv50_sor_destroy(struct drm_encoder *encoder)
2083 {
2084 drm_encoder_cleanup(encoder);
2085 kfree(encoder);
2086 }
2087
2088 static const struct drm_encoder_helper_funcs nv50_sor_hfunc = {
2089 .dpms = nv50_sor_dpms,
2090 .mode_fixup = nv50_encoder_mode_fixup,
2091 .prepare = nv50_sor_disconnect,
2092 .commit = nv50_sor_commit,
2093 .mode_set = nv50_sor_mode_set,
2094 .disable = nv50_sor_disconnect,
2095 .get_crtc = nv50_display_crtc_get,
2096 };
2097
2098 static const struct drm_encoder_funcs nv50_sor_func = {
2099 .destroy = nv50_sor_destroy,
2100 };
2101
2102 static int
2103 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
2104 {
2105 struct nouveau_drm *drm = nouveau_drm(connector->dev);
2106 struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
2107 struct nouveau_encoder *nv_encoder;
2108 struct drm_encoder *encoder;
2109 int type;
2110
2111 switch (dcbe->type) {
2112 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
2113 case DCB_OUTPUT_TMDS:
2114 case DCB_OUTPUT_DP:
2115 default:
2116 type = DRM_MODE_ENCODER_TMDS;
2117 break;
2118 }
2119
2120 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2121 if (!nv_encoder)
2122 return -ENOMEM;
2123 nv_encoder->dcb = dcbe;
2124 nv_encoder->or = ffs(dcbe->or) - 1;
2125 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
2126
2127 if (dcbe->type == DCB_OUTPUT_DP) {
2128 struct nvkm_i2c_aux *aux =
2129 nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
2130 if (aux) {
2131 nv_encoder->i2c = &aux->i2c;
2132 nv_encoder->aux = aux;
2133 }
2134 } else {
2135 struct nvkm_i2c_bus *bus =
2136 nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
2137 if (bus)
2138 nv_encoder->i2c = &bus->i2c;
2139 }
2140
2141 encoder = to_drm_encoder(nv_encoder);
2142 encoder->possible_crtcs = dcbe->heads;
2143 encoder->possible_clones = 0;
2144 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type, NULL);
2145 drm_encoder_helper_add(encoder, &nv50_sor_hfunc);
2146
2147 drm_mode_connector_attach_encoder(connector, encoder);
2148 return 0;
2149 }
2150
2151 /******************************************************************************
2152 * PIOR
2153 *****************************************************************************/
2154
2155 static void
2156 nv50_pior_dpms(struct drm_encoder *encoder, int mode)
2157 {
2158 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2159 struct nv50_disp *disp = nv50_disp(encoder->dev);
2160 struct {
2161 struct nv50_disp_mthd_v1 base;
2162 struct nv50_disp_pior_pwr_v0 pwr;
2163 } args = {
2164 .base.version = 1,
2165 .base.method = NV50_DISP_MTHD_V1_PIOR_PWR,
2166 .base.hasht = nv_encoder->dcb->hasht,
2167 .base.hashm = nv_encoder->dcb->hashm,
2168 .pwr.state = mode == DRM_MODE_DPMS_ON,
2169 .pwr.type = nv_encoder->dcb->type,
2170 };
2171
2172 nvif_mthd(disp->disp, 0, &args, sizeof(args));
2173 }
2174
2175 static bool
2176 nv50_pior_mode_fixup(struct drm_encoder *encoder,
2177 const struct drm_display_mode *mode,
2178 struct drm_display_mode *adjusted_mode)
2179 {
2180 if (!nv50_encoder_mode_fixup(encoder, mode, adjusted_mode))
2181 return false;
2182 adjusted_mode->clock *= 2;
2183 return true;
2184 }
2185
2186 static void
2187 nv50_pior_commit(struct drm_encoder *encoder)
2188 {
2189 }
2190
2191 static void
2192 nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
2193 struct drm_display_mode *adjusted_mode)
2194 {
2195 struct nv50_mast *mast = nv50_mast(encoder->dev);
2196 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2197 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2198 struct nouveau_connector *nv_connector;
2199 u8 owner = 1 << nv_crtc->index;
2200 u8 proto, depth;
2201 u32 *push;
2202
2203 nv_connector = nouveau_encoder_connector_get(nv_encoder);
2204 switch (nv_connector->base.display_info.bpc) {
2205 case 10: depth = 0x6; break;
2206 case 8: depth = 0x5; break;
2207 case 6: depth = 0x2; break;
2208 default: depth = 0x0; break;
2209 }
2210
2211 switch (nv_encoder->dcb->type) {
2212 case DCB_OUTPUT_TMDS:
2213 case DCB_OUTPUT_DP:
2214 proto = 0x0;
2215 break;
2216 default:
2217 BUG_ON(1);
2218 break;
2219 }
2220
2221 nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON);
2222
2223 push = evo_wait(mast, 8);
2224 if (push) {
2225 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2226 u32 ctrl = (depth << 16) | (proto << 8) | owner;
2227 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2228 ctrl |= 0x00001000;
2229 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2230 ctrl |= 0x00002000;
2231 evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
2232 evo_data(push, ctrl);
2233 }
2234
2235 evo_kick(push, mast);
2236 }
2237
2238 nv_encoder->crtc = encoder->crtc;
2239 }
2240
2241 static void
2242 nv50_pior_disconnect(struct drm_encoder *encoder)
2243 {
2244 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2245 struct nv50_mast *mast = nv50_mast(encoder->dev);
2246 const int or = nv_encoder->or;
2247 u32 *push;
2248
2249 if (nv_encoder->crtc) {
2250 nv50_crtc_prepare(nv_encoder->crtc);
2251
2252 push = evo_wait(mast, 4);
2253 if (push) {
2254 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2255 evo_mthd(push, 0x0700 + (or * 0x040), 1);
2256 evo_data(push, 0x00000000);
2257 }
2258 evo_kick(push, mast);
2259 }
2260 }
2261
2262 nv_encoder->crtc = NULL;
2263 }
2264
2265 static void
2266 nv50_pior_destroy(struct drm_encoder *encoder)
2267 {
2268 drm_encoder_cleanup(encoder);
2269 kfree(encoder);
2270 }
2271
2272 static const struct drm_encoder_helper_funcs nv50_pior_hfunc = {
2273 .dpms = nv50_pior_dpms,
2274 .mode_fixup = nv50_pior_mode_fixup,
2275 .prepare = nv50_pior_disconnect,
2276 .commit = nv50_pior_commit,
2277 .mode_set = nv50_pior_mode_set,
2278 .disable = nv50_pior_disconnect,
2279 .get_crtc = nv50_display_crtc_get,
2280 };
2281
2282 static const struct drm_encoder_funcs nv50_pior_func = {
2283 .destroy = nv50_pior_destroy,
2284 };
2285
2286 static int
2287 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
2288 {
2289 struct nouveau_drm *drm = nouveau_drm(connector->dev);
2290 struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
2291 struct nvkm_i2c_bus *bus = NULL;
2292 struct nvkm_i2c_aux *aux = NULL;
2293 struct i2c_adapter *ddc;
2294 struct nouveau_encoder *nv_encoder;
2295 struct drm_encoder *encoder;
2296 int type;
2297
2298 switch (dcbe->type) {
2299 case DCB_OUTPUT_TMDS:
2300 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
2301 ddc = bus ? &bus->i2c : NULL;
2302 type = DRM_MODE_ENCODER_TMDS;
2303 break;
2304 case DCB_OUTPUT_DP:
2305 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
2306 ddc = aux ? &aux->i2c : NULL;
2307 type = DRM_MODE_ENCODER_TMDS;
2308 break;
2309 default:
2310 return -ENODEV;
2311 }
2312
2313 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2314 if (!nv_encoder)
2315 return -ENOMEM;
2316 nv_encoder->dcb = dcbe;
2317 nv_encoder->or = ffs(dcbe->or) - 1;
2318 nv_encoder->i2c = ddc;
2319 nv_encoder->aux = aux;
2320
2321 encoder = to_drm_encoder(nv_encoder);
2322 encoder->possible_crtcs = dcbe->heads;
2323 encoder->possible_clones = 0;
2324 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type, NULL);
2325 drm_encoder_helper_add(encoder, &nv50_pior_hfunc);
2326
2327 drm_mode_connector_attach_encoder(connector, encoder);
2328 return 0;
2329 }
2330
2331 /******************************************************************************
2332 * Framebuffer
2333 *****************************************************************************/
2334
2335 static void
2336 nv50_fbdma_fini(struct nv50_fbdma *fbdma)
2337 {
2338 int i;
2339 for (i = 0; i < ARRAY_SIZE(fbdma->base); i++)
2340 nvif_object_fini(&fbdma->base[i]);
2341 nvif_object_fini(&fbdma->core);
2342 list_del(&fbdma->head);
2343 kfree(fbdma);
2344 }
2345
2346 static int
2347 nv50_fbdma_init(struct drm_device *dev, u32 name, u64 offset, u64 length, u8 kind)
2348 {
2349 struct nouveau_drm *drm = nouveau_drm(dev);
2350 struct nv50_disp *disp = nv50_disp(dev);
2351 struct nv50_mast *mast = nv50_mast(dev);
2352 struct __attribute__ ((packed)) {
2353 struct nv_dma_v0 base;
2354 union {
2355 struct nv50_dma_v0 nv50;
2356 struct gf100_dma_v0 gf100;
2357 struct gf119_dma_v0 gf119;
2358 };
2359 } args = {};
2360 struct nv50_fbdma *fbdma;
2361 struct drm_crtc *crtc;
2362 u32 size = sizeof(args.base);
2363 int ret;
2364
2365 list_for_each_entry(fbdma, &disp->fbdma, head) {
2366 if (fbdma->core.handle == name)
2367 return 0;
2368 }
2369
2370 fbdma = kzalloc(sizeof(*fbdma), GFP_KERNEL);
2371 if (!fbdma)
2372 return -ENOMEM;
2373 list_add(&fbdma->head, &disp->fbdma);
2374
2375 args.base.target = NV_DMA_V0_TARGET_VRAM;
2376 args.base.access = NV_DMA_V0_ACCESS_RDWR;
2377 args.base.start = offset;
2378 args.base.limit = offset + length - 1;
2379
2380 if (drm->device.info.chipset < 0x80) {
2381 args.nv50.part = NV50_DMA_V0_PART_256;
2382 size += sizeof(args.nv50);
2383 } else
2384 if (drm->device.info.chipset < 0xc0) {
2385 args.nv50.part = NV50_DMA_V0_PART_256;
2386 args.nv50.kind = kind;
2387 size += sizeof(args.nv50);
2388 } else
2389 if (drm->device.info.chipset < 0xd0) {
2390 args.gf100.kind = kind;
2391 size += sizeof(args.gf100);
2392 } else {
2393 args.gf119.page = GF119_DMA_V0_PAGE_LP;
2394 args.gf119.kind = kind;
2395 size += sizeof(args.gf119);
2396 }
2397
2398 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2399 struct nv50_head *head = nv50_head(crtc);
2400 int ret = nvif_object_init(&head->sync.base.base.user, name,
2401 NV_DMA_IN_MEMORY, &args, size,
2402 &fbdma->base[head->base.index]);
2403 if (ret) {
2404 nv50_fbdma_fini(fbdma);
2405 return ret;
2406 }
2407 }
2408
2409 ret = nvif_object_init(&mast->base.base.user, name, NV_DMA_IN_MEMORY,
2410 &args, size, &fbdma->core);
2411 if (ret) {
2412 nv50_fbdma_fini(fbdma);
2413 return ret;
2414 }
2415
2416 return 0;
2417 }
2418
2419 static void
2420 nv50_fb_dtor(struct drm_framebuffer *fb)
2421 {
2422 }
2423
2424 static int
2425 nv50_fb_ctor(struct drm_framebuffer *fb)
2426 {
2427 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
2428 struct nouveau_drm *drm = nouveau_drm(fb->dev);
2429 struct nouveau_bo *nvbo = nv_fb->nvbo;
2430 struct nv50_disp *disp = nv50_disp(fb->dev);
2431 u8 kind = nouveau_bo_tile_layout(nvbo) >> 8;
2432 u8 tile = nvbo->tile_mode;
2433
2434 if (drm->device.info.chipset >= 0xc0)
2435 tile >>= 4; /* yep.. */
2436
2437 switch (fb->depth) {
2438 case 8: nv_fb->r_format = 0x1e00; break;
2439 case 15: nv_fb->r_format = 0xe900; break;
2440 case 16: nv_fb->r_format = 0xe800; break;
2441 case 24:
2442 case 32: nv_fb->r_format = 0xcf00; break;
2443 case 30: nv_fb->r_format = 0xd100; break;
2444 default:
2445 NV_ERROR(drm, "unknown depth %d\n", fb->depth);
2446 return -EINVAL;
2447 }
2448
2449 if (disp->disp->oclass < G82_DISP) {
2450 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2451 (fb->pitches[0] | 0x00100000);
2452 nv_fb->r_format |= kind << 16;
2453 } else
2454 if (disp->disp->oclass < GF110_DISP) {
2455 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2456 (fb->pitches[0] | 0x00100000);
2457 } else {
2458 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2459 (fb->pitches[0] | 0x01000000);
2460 }
2461 nv_fb->r_handle = 0xffff0000 | kind;
2462
2463 return nv50_fbdma_init(fb->dev, nv_fb->r_handle, 0,
2464 drm->device.info.ram_user, kind);
2465 }
2466
2467 /******************************************************************************
2468 * Init
2469 *****************************************************************************/
2470
2471 void
2472 nv50_display_fini(struct drm_device *dev)
2473 {
2474 }
2475
2476 int
2477 nv50_display_init(struct drm_device *dev)
2478 {
2479 struct nv50_disp *disp = nv50_disp(dev);
2480 struct drm_crtc *crtc;
2481 u32 *push;
2482
2483 push = evo_wait(nv50_mast(dev), 32);
2484 if (!push)
2485 return -EBUSY;
2486
2487 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2488 struct nv50_sync *sync = nv50_sync(crtc);
2489
2490 nv50_crtc_lut_load(crtc);
2491 nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data);
2492 }
2493
2494 evo_mthd(push, 0x0088, 1);
2495 evo_data(push, nv50_mast(dev)->base.sync.handle);
2496 evo_kick(push, nv50_mast(dev));
2497 return 0;
2498 }
2499
2500 void
2501 nv50_display_destroy(struct drm_device *dev)
2502 {
2503 struct nv50_disp *disp = nv50_disp(dev);
2504 struct nv50_fbdma *fbdma, *fbtmp;
2505
2506 list_for_each_entry_safe(fbdma, fbtmp, &disp->fbdma, head) {
2507 nv50_fbdma_fini(fbdma);
2508 }
2509
2510 nv50_dmac_destroy(&disp->mast.base, disp->disp);
2511
2512 nouveau_bo_unmap(disp->sync);
2513 if (disp->sync)
2514 nouveau_bo_unpin(disp->sync);
2515 nouveau_bo_ref(NULL, &disp->sync);
2516
2517 nouveau_display(dev)->priv = NULL;
2518 kfree(disp);
2519 }
2520
2521 int
2522 nv50_display_create(struct drm_device *dev)
2523 {
2524 struct nvif_device *device = &nouveau_drm(dev)->device;
2525 struct nouveau_drm *drm = nouveau_drm(dev);
2526 struct dcb_table *dcb = &drm->vbios.dcb;
2527 struct drm_connector *connector, *tmp;
2528 struct nv50_disp *disp;
2529 struct dcb_output *dcbe;
2530 int crtcs, ret, i;
2531
2532 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2533 if (!disp)
2534 return -ENOMEM;
2535 INIT_LIST_HEAD(&disp->fbdma);
2536
2537 nouveau_display(dev)->priv = disp;
2538 nouveau_display(dev)->dtor = nv50_display_destroy;
2539 nouveau_display(dev)->init = nv50_display_init;
2540 nouveau_display(dev)->fini = nv50_display_fini;
2541 nouveau_display(dev)->fb_ctor = nv50_fb_ctor;
2542 nouveau_display(dev)->fb_dtor = nv50_fb_dtor;
2543 disp->disp = &nouveau_display(dev)->disp;
2544
2545 /* small shared memory area we use for notifiers and semaphores */
2546 ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2547 0, 0x0000, NULL, NULL, &disp->sync);
2548 if (!ret) {
2549 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2550 if (!ret) {
2551 ret = nouveau_bo_map(disp->sync);
2552 if (ret)
2553 nouveau_bo_unpin(disp->sync);
2554 }
2555 if (ret)
2556 nouveau_bo_ref(NULL, &disp->sync);
2557 }
2558
2559 if (ret)
2560 goto out;
2561
2562 /* allocate master evo channel */
2563 ret = nv50_core_create(device, disp->disp, disp->sync->bo.offset,
2564 &disp->mast);
2565 if (ret)
2566 goto out;
2567
2568 /* create crtc objects to represent the hw heads */
2569 if (disp->disp->oclass >= GF110_DISP)
2570 crtcs = nvif_rd32(&device->object, 0x022448);
2571 else
2572 crtcs = 2;
2573
2574 for (i = 0; i < crtcs; i++) {
2575 ret = nv50_crtc_create(dev, i);
2576 if (ret)
2577 goto out;
2578 }
2579
2580 /* create encoder/connector objects based on VBIOS DCB table */
2581 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2582 connector = nouveau_connector_create(dev, dcbe->connector);
2583 if (IS_ERR(connector))
2584 continue;
2585
2586 if (dcbe->location == DCB_LOC_ON_CHIP) {
2587 switch (dcbe->type) {
2588 case DCB_OUTPUT_TMDS:
2589 case DCB_OUTPUT_LVDS:
2590 case DCB_OUTPUT_DP:
2591 ret = nv50_sor_create(connector, dcbe);
2592 break;
2593 case DCB_OUTPUT_ANALOG:
2594 ret = nv50_dac_create(connector, dcbe);
2595 break;
2596 default:
2597 ret = -ENODEV;
2598 break;
2599 }
2600 } else {
2601 ret = nv50_pior_create(connector, dcbe);
2602 }
2603
2604 if (ret) {
2605 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2606 dcbe->location, dcbe->type,
2607 ffs(dcbe->or) - 1, ret);
2608 ret = 0;
2609 }
2610 }
2611
2612 /* cull any connectors we created that don't have an encoder */
2613 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2614 if (connector->encoder_ids[0])
2615 continue;
2616
2617 NV_WARN(drm, "%s has no encoders, removing\n",
2618 connector->name);
2619 connector->funcs->destroy(connector);
2620 }
2621
2622 out:
2623 if (ret)
2624 nv50_display_destroy(dev);
2625 return ret;
2626 }
Linux kernel - Deliverables
This page took 0.181774 seconds and 6 git commands to generate.