drivers/gpu/drm/nouveau/nv50_fence.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs <bskeggs@redhat.com>
  23  */
  24
  25 #include <core/object.h>
  26 #include <core/class.h>
  27
  28 #include "nouveau_drm.h"
  29 #include "nouveau_dma.h"
  30 #include "nouveau_fence.h"
  31
  32 struct nv50_fence_chan {
  33         struct nouveau_fence_chan base;
  34 };
  35
  36 struct nv50_fence_priv {
  37         struct nouveau_fence_priv base;
  38         struct nouveau_bo *bo;
  39         spinlock_t lock;
  40         u32 sequence;
  41 };
  42
  43 static int
  44 nv50_fence_context_new(struct nouveau_channel *chan)
  45 {
  46         struct nv50_fence_priv *priv = chan->drm->fence;
  47         struct nv50_fence_chan *fctx;
  48         struct ttm_mem_reg *mem = &priv->bo->bo.mem;
  49         struct nouveau_object *object;
  50         int ret, i;
  51
  52         fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
  53         if (!fctx)
  54                 return -ENOMEM;
  55
  56         nouveau_fence_context_new(&fctx->base);
  57
  58         ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
  59                                  NvSema, 0x0002,
  60                                  &(struct nv_dma_class) {
  61                                         .flags = NV_DMA_TARGET_VRAM |
  62                                                  NV_DMA_ACCESS_RDWR,
  63                                         .start = mem->start * PAGE_SIZE,
  64                                         .limit = mem->size - 1,
  65                                  }, sizeof(struct nv_dma_class),
  66                                  &object);
  67
  68         /* dma objects for display sync channel semaphore blocks */
  69         for (i = 0; !ret && i < chan->drm->dev->mode_config.num_crtc; i++) {
  70                 struct nouveau_bo *bo = nv50sema(chan->drm->dev, i);
  71
  72                 ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
  73                                          NvEvoSema0 + i, 0x003d,
  74                                          &(struct nv_dma_class) {
  75                                                 .flags = NV_DMA_TARGET_VRAM |
  76                                                          NV_DMA_ACCESS_RDWR,
  77                                                 .start = bo->bo.offset,
  78                                                 .limit = bo->bo.offset + 0xfff,
  79                                          }, sizeof(struct nv_dma_class),
  80                                          &object);
  81         }
  82
  83         if (ret)
  84                 nv10_fence_context_del(chan);
  85         return ret;
  86 }
  87
  88 int
  89 nv50_fence_create(struct nouveau_drm *drm)
  90 {
  91         struct nv50_fence_priv *priv;
  92         int ret = 0;
  93
  94         priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
  95         if (!priv)
  96                 return -ENOMEM;
  97
  98         priv->base.dtor = nv10_fence_destroy;
  99         priv->base.context_new = nv50_fence_context_new;
 100         priv->base.context_del = nv10_fence_context_del;
 101         priv->base.emit = nv10_fence_emit;
 102         priv->base.read = nv10_fence_read;
 103         priv->base.sync = nv17_fence_sync;
 104         spin_lock_init(&priv->lock);
 105
 106         ret = nouveau_bo_new(drm->dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
 107                              0, 0x0000, NULL, &priv->bo);
 108         if (!ret) {
 109                 ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
 110                 if (!ret)
 111                         ret = nouveau_bo_map(priv->bo);
 112                 if (ret)
 113                         nouveau_bo_ref(NULL, &priv->bo);
 114         }
 115
 116         if (ret == 0) {
 117                 nouveau_bo_wr32(priv->bo, 0x000, 0x00000000);
 118                 priv->base.sync = nv17_fence_sync;
 119         }
 120
 121         if (ret)
 122                 nv10_fence_destroy(drm);
 123         return ret;
 124 }