2 * Copyright (C) 2012 Ben Skeggs.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "nouveau_drv.h"
29 #include "nouveau_fifo.h"
30 #include "nouveau_ramht.h"
31 #include "nouveau_vm.h"
33 struct nv50_fifo_priv
{
34 struct nouveau_fifo_priv base
;
35 struct nouveau_gpuobj
*playlist
[2];
39 struct nv50_fifo_chan
{
40 struct nouveau_fifo_chan base
;
44 nv50_fifo_playlist_update(struct drm_device
*dev
)
46 struct nv50_fifo_priv
*priv
= nv_engine(dev
, NVOBJ_ENGINE_FIFO
);
47 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
48 struct nouveau_gpuobj
*cur
;
51 cur
= priv
->playlist
[priv
->cur_playlist
];
52 priv
->cur_playlist
= !priv
->cur_playlist
;
54 for (i
= 0, p
= 0; i
< priv
->base
.channels
; i
++) {
55 if (nv_rd32(dev
, 0x002600 + (i
* 4)) & 0x80000000)
56 nv_wo32(cur
, p
++ * 4, i
);
59 dev_priv
->engine
.instmem
.flush(dev
);
61 nv_wr32(dev
, 0x0032f4, cur
->vinst
>> 12);
62 nv_wr32(dev
, 0x0032ec, p
);
63 nv_wr32(dev
, 0x002500, 0x00000101);
67 nv50_fifo_context_new(struct nouveau_channel
*chan
, int engine
)
69 struct nv50_fifo_priv
*priv
= nv_engine(chan
->dev
, engine
);
70 struct nv50_fifo_chan
*fctx
;
71 struct drm_device
*dev
= chan
->dev
;
72 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
73 u64 ib_offset
= chan
->pushbuf_base
+ chan
->dma
.ib_base
* 4;
74 u64 instance
= chan
->ramin
->vinst
>> 12;
78 fctx
= chan
->engctx
[engine
] = kzalloc(sizeof(*fctx
), GFP_KERNEL
);
81 atomic_inc(&chan
->vm
->engref
[engine
]);
83 chan
->user
= ioremap(pci_resource_start(dev
->pdev
, 0) +
84 NV50_USER(chan
->id
), PAGE_SIZE
);
90 for (i
= 0; i
< 0x100; i
+= 4)
91 nv_wo32(chan
->ramin
, i
, 0x00000000);
92 nv_wo32(chan
->ramin
, 0x3c, 0x403f6078);
93 nv_wo32(chan
->ramin
, 0x40, 0x00000000);
94 nv_wo32(chan
->ramin
, 0x44, 0x01003fff);
95 nv_wo32(chan
->ramin
, 0x48, chan
->pushbuf
->cinst
>> 4);
96 nv_wo32(chan
->ramin
, 0x50, lower_32_bits(ib_offset
));
97 nv_wo32(chan
->ramin
, 0x54, upper_32_bits(ib_offset
) |
98 drm_order(chan
->dma
.ib_max
+ 1) << 16);
99 nv_wo32(chan
->ramin
, 0x60, 0x7fffffff);
100 nv_wo32(chan
->ramin
, 0x78, 0x00000000);
101 nv_wo32(chan
->ramin
, 0x7c, 0x30000001);
102 nv_wo32(chan
->ramin
, 0x80, ((chan
->ramht
->bits
- 9) << 27) |
103 (4 << 24) /* SEARCH_FULL */ |
104 (chan
->ramht
->gpuobj
->cinst
>> 4));
106 dev_priv
->engine
.instmem
.flush(dev
);
108 spin_lock_irqsave(&dev_priv
->context_switch_lock
, flags
);
109 nv_wr32(dev
, 0x002600 + (chan
->id
* 4), 0x80000000 | instance
);
110 nv50_fifo_playlist_update(dev
);
111 spin_unlock_irqrestore(&dev_priv
->context_switch_lock
, flags
);
115 priv
->base
.base
.context_del(chan
, engine
);
120 nv50_fifo_kickoff(struct nouveau_channel
*chan
)
122 struct drm_device
*dev
= chan
->dev
;
126 /* HW bug workaround:
128 * PFIFO will hang forever if the connected engines don't report
129 * that they've processed the context switch request.
131 * In order for the kickoff to work, we need to ensure all the
132 * connected engines are in a state where they can answer.
134 * Newer chipsets don't seem to suffer from this issue, and well,
135 * there's also a "ignore these engines" bitmask reg we can use
136 * if we hit the issue there..
139 /* PME: make sure engine is enabled */
140 me
= nv_mask(dev
, 0x00b860, 0x00000001, 0x00000001);
142 /* do the kickoff... */
143 nv_wr32(dev
, 0x0032fc, chan
->ramin
->vinst
>> 12);
144 if (!nv_wait_ne(dev
, 0x0032fc, 0xffffffff, 0xffffffff)) {
145 NV_INFO(dev
, "PFIFO: channel %d unload timeout\n", chan
->id
);
149 /* restore any engine states we changed, and exit */
150 nv_wr32(dev
, 0x00b860, me
);
155 nv50_fifo_context_del(struct nouveau_channel
*chan
, int engine
)
157 struct nv50_fifo_chan
*fctx
= chan
->engctx
[engine
];
158 struct drm_device
*dev
= chan
->dev
;
159 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
162 /* remove channel from playlist, will context switch if active */
163 spin_lock_irqsave(&dev_priv
->context_switch_lock
, flags
);
164 nv_mask(dev
, 0x002600 + (chan
->id
* 4), 0x80000000, 0x00000000);
165 nv50_fifo_playlist_update(dev
);
167 /* tell any engines on this channel to unload their contexts */
168 nv50_fifo_kickoff(chan
);
170 nv_wr32(dev
, 0x002600 + (chan
->id
* 4), 0x00000000);
171 spin_unlock_irqrestore(&dev_priv
->context_switch_lock
, flags
);
179 atomic_dec(&chan
->vm
->engref
[engine
]);
180 chan
->engctx
[engine
] = NULL
;
185 nv50_fifo_init(struct drm_device
*dev
, int engine
)
187 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
191 nv_mask(dev
, 0x000200, 0x00000100, 0x00000000);
192 nv_mask(dev
, 0x000200, 0x00000100, 0x00000100);
193 nv_wr32(dev
, 0x00250c, 0x6f3cfc34);
194 nv_wr32(dev
, 0x002044, 0x01003fff);
196 nv_wr32(dev
, 0x002100, 0xffffffff);
197 nv_wr32(dev
, 0x002140, 0xffffffff);
199 for (i
= 0; i
< 128; i
++) {
200 struct nouveau_channel
*chan
= dev_priv
->channels
.ptr
[i
];
201 if (chan
&& chan
->engctx
[engine
])
202 instance
= 0x80000000 | chan
->ramin
->vinst
>> 12;
204 instance
= 0x00000000;
205 nv_wr32(dev
, 0x002600 + (i
* 4), instance
);
208 nv50_fifo_playlist_update(dev
);
210 nv_wr32(dev
, 0x003200, 1);
211 nv_wr32(dev
, 0x003250, 1);
212 nv_wr32(dev
, 0x002500, 1);
217 nv50_fifo_fini(struct drm_device
*dev
, int engine
, bool suspend
)
219 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
220 struct nv50_fifo_priv
*priv
= nv_engine(dev
, engine
);
223 /* set playlist length to zero, fifo will unload context */
224 nv_wr32(dev
, 0x0032ec, 0);
226 /* tell all connected engines to unload their contexts */
227 for (i
= 0; i
< priv
->base
.channels
; i
++) {
228 struct nouveau_channel
*chan
= dev_priv
->channels
.ptr
[i
];
229 if (chan
&& !nv50_fifo_kickoff(chan
))
233 nv_wr32(dev
, 0x002140, 0);
238 nv50_fifo_tlb_flush(struct drm_device
*dev
, int engine
)
240 nv50_vm_flush_engine(dev
, 5);
244 nv50_fifo_destroy(struct drm_device
*dev
, int engine
)
246 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
247 struct nv50_fifo_priv
*priv
= nv_engine(dev
, engine
);
249 nouveau_irq_unregister(dev
, 8);
251 nouveau_gpuobj_ref(NULL
, &priv
->playlist
[0]);
252 nouveau_gpuobj_ref(NULL
, &priv
->playlist
[1]);
254 dev_priv
->eng
[engine
] = NULL
;
259 nv50_fifo_create(struct drm_device
*dev
)
261 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
262 struct nv50_fifo_priv
*priv
;
265 priv
= kzalloc(sizeof(*priv
), GFP_KERNEL
);
269 priv
->base
.base
.destroy
= nv50_fifo_destroy
;
270 priv
->base
.base
.init
= nv50_fifo_init
;
271 priv
->base
.base
.fini
= nv50_fifo_fini
;
272 priv
->base
.base
.context_new
= nv50_fifo_context_new
;
273 priv
->base
.base
.context_del
= nv50_fifo_context_del
;
274 priv
->base
.base
.tlb_flush
= nv50_fifo_tlb_flush
;
275 priv
->base
.channels
= 127;
276 dev_priv
->eng
[NVOBJ_ENGINE_FIFO
] = &priv
->base
.base
;
278 ret
= nouveau_gpuobj_new(dev
, NULL
, priv
->base
.channels
* 4, 0x1000,
279 NVOBJ_FLAG_ZERO_ALLOC
, &priv
->playlist
[0]);
283 ret
= nouveau_gpuobj_new(dev
, NULL
, priv
->base
.channels
* 4, 0x1000,
284 NVOBJ_FLAG_ZERO_ALLOC
, &priv
->playlist
[1]);
288 nouveau_irq_register(dev
, 8, nv04_fifo_isr
);
291 priv
->base
.base
.destroy(dev
, NVOBJ_ENGINE_FIFO
);
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