2 * Copyright 2010 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "nouveau_drv.h"
27 #include <nouveau_bios.h>
28 #include "nouveau_hw.h"
29 #include "nouveau_pm.h"
30 #include "nouveau_hwsq.h"
46 static u32
read_clk(struct drm_device
*, enum clk_src
);
49 read_div(struct drm_device
*dev
)
51 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
53 switch (dev_priv
->chipset
) {
54 case 0x50: /* it exists, but only has bit 31, not the dividers.. */
59 return nv_rd32(dev
, 0x004700);
63 return nv_rd32(dev
, 0x004800);
70 read_pll_src(struct drm_device
*dev
, u32 base
)
72 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
73 u32 coef
, ref
= read_clk(dev
, clk_src_crystal
);
74 u32 rsel
= nv_rd32(dev
, 0x00e18c);
77 switch (dev_priv
->chipset
) {
82 case 0x4028: id
= !!(rsel
& 0x00000004); break;
83 case 0x4008: id
= !!(rsel
& 0x00000008); break;
84 case 0x4030: id
= 0; break;
86 NV_ERROR(dev
, "ref: bad pll 0x%06x\n", base
);
90 coef
= nv_rd32(dev
, 0x00e81c + (id
* 0x0c));
91 ref
*= (coef
& 0x01000000) ? 2 : 4;
92 P
= (coef
& 0x00070000) >> 16;
93 N
= ((coef
& 0x0000ff00) >> 8) + 1;
94 M
= ((coef
& 0x000000ff) >> 0) + 1;
99 coef
= nv_rd32(dev
, 0x00e81c);
100 P
= (coef
& 0x00070000) >> 16;
101 N
= (coef
& 0x0000ff00) >> 8;
102 M
= (coef
& 0x000000ff) >> 0;
107 rsel
= nv_rd32(dev
, 0x00c050);
109 case 0x4020: rsel
= (rsel
& 0x00000003) >> 0; break;
110 case 0x4008: rsel
= (rsel
& 0x0000000c) >> 2; break;
111 case 0x4028: rsel
= (rsel
& 0x00001800) >> 11; break;
112 case 0x4030: rsel
= 3; break;
114 NV_ERROR(dev
, "ref: bad pll 0x%06x\n", base
);
119 case 0: id
= 1; break;
120 case 1: return read_clk(dev
, clk_src_crystal
);
121 case 2: return read_clk(dev
, clk_src_href
);
122 case 3: id
= 0; break;
125 coef
= nv_rd32(dev
, 0x00e81c + (id
* 0x28));
126 P
= (nv_rd32(dev
, 0x00e824 + (id
* 0x28)) >> 16) & 7;
127 P
+= (coef
& 0x00070000) >> 16;
128 N
= (coef
& 0x0000ff00) >> 8;
129 M
= (coef
& 0x000000ff) >> 0;
136 return (ref
* N
/ M
) >> P
;
141 read_pll_ref(struct drm_device
*dev
, u32 base
)
143 u32 src
, mast
= nv_rd32(dev
, 0x00c040);
147 src
= !!(mast
& 0x00200000);
150 src
= !!(mast
& 0x00400000);
153 src
= !!(mast
& 0x00010000);
156 src
= !!(mast
& 0x02000000);
159 return read_clk(dev
, clk_src_crystal
);
161 NV_ERROR(dev
, "bad pll 0x%06x\n", base
);
166 return read_clk(dev
, clk_src_href
);
167 return read_pll_src(dev
, base
);
171 read_pll(struct drm_device
*dev
, u32 base
)
173 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
174 u32 mast
= nv_rd32(dev
, 0x00c040);
175 u32 ctrl
= nv_rd32(dev
, base
+ 0);
176 u32 coef
= nv_rd32(dev
, base
+ 4);
177 u32 ref
= read_pll_ref(dev
, base
);
181 if (base
== 0x004028 && (mast
& 0x00100000)) {
182 /* wtf, appears to only disable post-divider on nva0 */
183 if (dev_priv
->chipset
!= 0xa0)
184 return read_clk(dev
, clk_src_dom6
);
187 N2
= (coef
& 0xff000000) >> 24;
188 M2
= (coef
& 0x00ff0000) >> 16;
189 N1
= (coef
& 0x0000ff00) >> 8;
190 M1
= (coef
& 0x000000ff);
191 if ((ctrl
& 0x80000000) && M1
) {
193 if ((ctrl
& 0x40000100) == 0x40000000) {
205 read_clk(struct drm_device
*dev
, enum clk_src src
)
207 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
208 u32 mast
= nv_rd32(dev
, 0x00c040);
212 case clk_src_crystal
:
213 return dev_priv
->crystal
;
215 return 100000; /* PCIE reference clock */
217 return read_clk(dev
, clk_src_href
) * 27778 / 10000;
219 return read_clk(dev
, clk_src_hclk
) * 3;
220 case clk_src_hclkm3d2
:
221 return read_clk(dev
, clk_src_hclk
) * 3 / 2;
223 switch (mast
& 0x30000000) {
224 case 0x00000000: return read_clk(dev
, clk_src_href
);
225 case 0x10000000: break;
226 case 0x20000000: /* !0x50 */
227 case 0x30000000: return read_clk(dev
, clk_src_hclk
);
231 if (!(mast
& 0x00100000))
232 P
= (nv_rd32(dev
, 0x004028) & 0x00070000) >> 16;
233 switch (mast
& 0x00000003) {
234 case 0x00000000: return read_clk(dev
, clk_src_crystal
) >> P
;
235 case 0x00000001: return read_clk(dev
, clk_src_dom6
);
236 case 0x00000002: return read_pll(dev
, 0x004020) >> P
;
237 case 0x00000003: return read_pll(dev
, 0x004028) >> P
;
241 P
= (nv_rd32(dev
, 0x004020) & 0x00070000) >> 16;
242 switch (mast
& 0x00000030) {
244 if (mast
& 0x00000080)
245 return read_clk(dev
, clk_src_host
) >> P
;
246 return read_clk(dev
, clk_src_crystal
) >> P
;
247 case 0x00000010: break;
248 case 0x00000020: return read_pll(dev
, 0x004028) >> P
;
249 case 0x00000030: return read_pll(dev
, 0x004020) >> P
;
253 P
= (nv_rd32(dev
, 0x004008) & 0x00070000) >> 16;
254 if (nv_rd32(dev
, 0x004008) & 0x00000200) {
255 switch (mast
& 0x0000c000) {
257 return read_clk(dev
, clk_src_crystal
) >> P
;
260 return read_clk(dev
, clk_src_href
) >> P
;
263 return read_pll(dev
, 0x004008) >> P
;
267 P
= (read_div(dev
) & 0x00000700) >> 8;
268 switch (dev_priv
->chipset
) {
275 switch (mast
& 0x00000c00) {
277 if (dev_priv
->chipset
== 0xa0) /* wtf?? */
278 return read_clk(dev
, clk_src_nvclk
) >> P
;
279 return read_clk(dev
, clk_src_crystal
) >> P
;
283 if (mast
& 0x01000000)
284 return read_pll(dev
, 0x004028) >> P
;
285 return read_pll(dev
, 0x004030) >> P
;
287 return read_clk(dev
, clk_src_nvclk
) >> P
;
291 switch (mast
& 0x00000c00) {
293 return read_clk(dev
, clk_src_nvclk
) >> P
;
297 return read_clk(dev
, clk_src_hclkm3d2
) >> P
;
299 return read_clk(dev
, clk_src_mclk
) >> P
;
305 switch (dev_priv
->chipset
) {
308 return read_pll(dev
, 0x00e810) >> 2;
315 P
= (read_div(dev
) & 0x00000007) >> 0;
316 switch (mast
& 0x0c000000) {
317 case 0x00000000: return read_clk(dev
, clk_src_href
);
318 case 0x04000000: break;
319 case 0x08000000: return read_clk(dev
, clk_src_hclk
);
321 return read_clk(dev
, clk_src_hclkm3
) >> P
;
331 NV_DEBUG(dev
, "unknown clock source %d 0x%08x\n", src
, mast
);
336 nv50_pm_clocks_get(struct drm_device
*dev
, struct nouveau_pm_level
*perflvl
)
338 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
339 if (dev_priv
->chipset
== 0xaa ||
340 dev_priv
->chipset
== 0xac)
343 perflvl
->core
= read_clk(dev
, clk_src_nvclk
);
344 perflvl
->shader
= read_clk(dev
, clk_src_sclk
);
345 perflvl
->memory
= read_clk(dev
, clk_src_mclk
);
346 if (dev_priv
->chipset
!= 0x50) {
347 perflvl
->vdec
= read_clk(dev
, clk_src_vdec
);
348 perflvl
->dom6
= read_clk(dev
, clk_src_dom6
);
354 struct nv50_pm_state
{
355 struct nouveau_pm_level
*perflvl
;
356 struct hwsq_ucode eclk_hwsq
;
357 struct hwsq_ucode mclk_hwsq
;
365 calc_pll(struct drm_device
*dev
, u32 reg
, struct nvbios_pll
*pll
,
366 u32 clk
, int *N1
, int *M1
, int *log2P
)
368 struct nouveau_pll_vals coef
;
371 ret
= get_pll_limits(dev
, reg
, pll
);
375 pll
->vco2
.max_freq
= 0;
376 pll
->refclk
= read_pll_ref(dev
, reg
);
380 ret
= nouveau_calc_pll_mnp(dev
, pll
, clk
, &coef
);
391 calc_div(u32 src
, u32 target
, int *div
)
393 u32 clk0
= src
, clk1
= src
;
394 for (*div
= 0; *div
<= 7; (*div
)++) {
395 if (clk0
<= target
) {
396 clk1
= clk0
<< (*div
? 1 : 0);
402 if (target
- clk0
<= clk1
- target
)
409 clk_same(u32 a
, u32 b
)
411 return ((a
/ 1000) == (b
/ 1000));
415 mclk_precharge(struct nouveau_mem_exec_func
*exec
)
417 struct nv50_pm_state
*info
= exec
->priv
;
418 struct hwsq_ucode
*hwsq
= &info
->mclk_hwsq
;
420 hwsq_wr32(hwsq
, 0x1002d4, 0x00000001);
424 mclk_refresh(struct nouveau_mem_exec_func
*exec
)
426 struct nv50_pm_state
*info
= exec
->priv
;
427 struct hwsq_ucode
*hwsq
= &info
->mclk_hwsq
;
429 hwsq_wr32(hwsq
, 0x1002d0, 0x00000001);
433 mclk_refresh_auto(struct nouveau_mem_exec_func
*exec
, bool enable
)
435 struct nv50_pm_state
*info
= exec
->priv
;
436 struct hwsq_ucode
*hwsq
= &info
->mclk_hwsq
;
438 hwsq_wr32(hwsq
, 0x100210, enable
? 0x80000000 : 0x00000000);
442 mclk_refresh_self(struct nouveau_mem_exec_func
*exec
, bool enable
)
444 struct nv50_pm_state
*info
= exec
->priv
;
445 struct hwsq_ucode
*hwsq
= &info
->mclk_hwsq
;
447 hwsq_wr32(hwsq
, 0x1002dc, enable
? 0x00000001 : 0x00000000);
451 mclk_wait(struct nouveau_mem_exec_func
*exec
, u32 nsec
)
453 struct nv50_pm_state
*info
= exec
->priv
;
454 struct hwsq_ucode
*hwsq
= &info
->mclk_hwsq
;
457 hwsq_usec(hwsq
, (nsec
+ 500) / 1000);
461 mclk_mrg(struct nouveau_mem_exec_func
*exec
, int mr
)
464 return nv_rd32(exec
->dev
, 0x1002c0 + ((mr
- 0) * 4));
466 return nv_rd32(exec
->dev
, 0x1002e0 + ((mr
- 2) * 4));
471 mclk_mrs(struct nouveau_mem_exec_func
*exec
, int mr
, u32 data
)
473 struct nv50_pm_state
*info
= exec
->priv
;
474 struct hwsq_ucode
*hwsq
= &info
->mclk_hwsq
;
477 if (nvfb_vram_rank_B(exec
->dev
))
478 hwsq_wr32(hwsq
, 0x1002c8 + ((mr
- 0) * 4), data
);
479 hwsq_wr32(hwsq
, 0x1002c0 + ((mr
- 0) * 4), data
);
482 if (nvfb_vram_rank_B(exec
->dev
))
483 hwsq_wr32(hwsq
, 0x1002e8 + ((mr
- 2) * 4), data
);
484 hwsq_wr32(hwsq
, 0x1002e0 + ((mr
- 2) * 4), data
);
489 mclk_clock_set(struct nouveau_mem_exec_func
*exec
)
491 struct nv50_pm_state
*info
= exec
->priv
;
492 struct hwsq_ucode
*hwsq
= &info
->mclk_hwsq
;
493 u32 ctrl
= nv_rd32(exec
->dev
, 0x004008);
495 info
->mmast
= nv_rd32(exec
->dev
, 0x00c040);
496 info
->mmast
&= ~0xc0000000; /* get MCLK_2 from HREF */
497 info
->mmast
|= 0x0000c000; /* use MCLK_2 as MPLL_BYPASS clock */
499 hwsq_wr32(hwsq
, 0xc040, info
->mmast
);
500 hwsq_wr32(hwsq
, 0x4008, ctrl
| 0x00000200); /* bypass MPLL */
501 if (info
->mctrl
& 0x80000000)
502 hwsq_wr32(hwsq
, 0x400c, info
->mcoef
);
503 hwsq_wr32(hwsq
, 0x4008, info
->mctrl
);
507 mclk_timing_set(struct nouveau_mem_exec_func
*exec
)
509 struct drm_device
*dev
= exec
->dev
;
510 struct nv50_pm_state
*info
= exec
->priv
;
511 struct nouveau_pm_level
*perflvl
= info
->perflvl
;
512 struct hwsq_ucode
*hwsq
= &info
->mclk_hwsq
;
515 for (i
= 0; i
< 9; i
++) {
516 u32 reg
= 0x100220 + (i
* 4);
517 u32 val
= nv_rd32(dev
, reg
);
518 if (val
!= perflvl
->timing
.reg
[i
])
519 hwsq_wr32(hwsq
, reg
, perflvl
->timing
.reg
[i
]);
524 calc_mclk(struct drm_device
*dev
, struct nouveau_pm_level
*perflvl
,
525 struct nv50_pm_state
*info
)
527 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
528 u32 crtc_mask
= nv50_display_active_crtcs(dev
);
529 struct nouveau_mem_exec_func exec
= {
531 .precharge
= mclk_precharge
,
532 .refresh
= mclk_refresh
,
533 .refresh_auto
= mclk_refresh_auto
,
534 .refresh_self
= mclk_refresh_self
,
538 .clock_set
= mclk_clock_set
,
539 .timing_set
= mclk_timing_set
,
542 struct hwsq_ucode
*hwsq
= &info
->mclk_hwsq
;
543 struct nvbios_pll pll
;
547 /* use pcie refclock if possible, otherwise use mpll */
548 info
->mctrl
= nv_rd32(dev
, 0x004008);
549 info
->mctrl
&= ~0x81ff0200;
550 if (clk_same(perflvl
->memory
, read_clk(dev
, clk_src_href
))) {
551 info
->mctrl
|= 0x00000200 | (pll
.bias_p
<< 19);
553 ret
= calc_pll(dev
, 0x4008, &pll
, perflvl
->memory
, &N
, &M
, &P
);
557 info
->mctrl
|= 0x80000000 | (P
<< 22) | (P
<< 16);
558 info
->mctrl
|= pll
.bias_p
<< 19;
559 info
->mcoef
= (N
<< 8) | M
;
562 /* build the ucode which will reclock the memory for us */
565 hwsq_op5f(hwsq
, crtc_mask
, 0x00); /* wait for scanout */
566 hwsq_op5f(hwsq
, crtc_mask
, 0x01); /* wait for vblank */
568 if (dev_priv
->chipset
>= 0x92)
569 hwsq_wr32(hwsq
, 0x611200, 0x00003300); /* disable scanout */
570 hwsq_setf(hwsq
, 0x10, 0); /* disable bus access */
571 hwsq_op5f(hwsq
, 0x00, 0x01); /* no idea :s */
573 ret
= nouveau_mem_exec(&exec
, perflvl
);
577 hwsq_setf(hwsq
, 0x10, 1); /* enable bus access */
578 hwsq_op5f(hwsq
, 0x00, 0x00); /* no idea, reverse of 0x00, 0x01? */
579 if (dev_priv
->chipset
>= 0x92)
580 hwsq_wr32(hwsq
, 0x611200, 0x00003330); /* enable scanout */
586 nv50_pm_clocks_pre(struct drm_device
*dev
, struct nouveau_pm_level
*perflvl
)
588 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
589 struct nv50_pm_state
*info
;
590 struct hwsq_ucode
*hwsq
;
591 struct nvbios_pll pll
;
592 u32 out
, mast
, divs
, ctrl
;
593 int clk
, ret
= -EINVAL
;
596 if (dev_priv
->chipset
== 0xaa ||
597 dev_priv
->chipset
== 0xac)
598 return ERR_PTR(-ENODEV
);
600 info
= kmalloc(sizeof(*info
), GFP_KERNEL
);
602 return ERR_PTR(-ENOMEM
);
603 info
->perflvl
= perflvl
;
605 /* memory: build hwsq ucode which we'll use to reclock memory.
606 * use pcie refclock if possible, otherwise use mpll */
607 info
->mclk_hwsq
.len
= 0;
608 if (perflvl
->memory
) {
609 ret
= calc_mclk(dev
, perflvl
, info
);
612 info
->mscript
= perflvl
->memscript
;
615 divs
= read_div(dev
);
618 /* start building HWSQ script for engine reclocking */
619 hwsq
= &info
->eclk_hwsq
;
621 hwsq_setf(hwsq
, 0x10, 0); /* disable bus access */
622 hwsq_op5f(hwsq
, 0x00, 0x01); /* wait for access disabled? */
624 /* vdec/dom6: switch to "safe" clocks temporarily */
635 hwsq_wr32(hwsq
, 0x00c040, mast
);
637 /* vdec: avoid modifying xpll until we know exactly how the other
638 * clock domains work, i suspect at least some of them can also be
642 /* see how close we can get using nvclk as a source */
643 clk
= calc_div(perflvl
->core
, perflvl
->vdec
, &P1
);
645 /* see how close we can get using xpll/hclk as a source */
646 if (dev_priv
->chipset
!= 0x98)
647 out
= read_pll(dev
, 0x004030);
649 out
= read_clk(dev
, clk_src_hclkm3d2
);
650 out
= calc_div(out
, perflvl
->vdec
, &P2
);
652 /* select whichever gets us closest */
653 if (abs((int)perflvl
->vdec
- clk
) <=
654 abs((int)perflvl
->vdec
- out
)) {
655 if (dev_priv
->chipset
!= 0x98)
664 /* dom6: nfi what this is, but we're limited to various combinations
665 * of the host clock frequency
668 if (clk_same(perflvl
->dom6
, read_clk(dev
, clk_src_href
))) {
671 if (clk_same(perflvl
->dom6
, read_clk(dev
, clk_src_hclk
))) {
674 clk
= read_clk(dev
, clk_src_hclk
) * 3;
675 clk
= calc_div(clk
, perflvl
->dom6
, &P1
);
682 /* vdec/dom6: complete switch to new clocks */
683 switch (dev_priv
->chipset
) {
687 hwsq_wr32(hwsq
, 0x004800, divs
);
690 hwsq_wr32(hwsq
, 0x004700, divs
);
694 hwsq_wr32(hwsq
, 0x00c040, mast
);
696 /* core/shader: make sure sclk/nvclk are disconnected from their
697 * PLLs (nvclk to dom6, sclk to hclk)
699 if (dev_priv
->chipset
< 0x92)
700 mast
= (mast
& ~0x001000b0) | 0x00100080;
702 mast
= (mast
& ~0x000000b3) | 0x00000081;
704 hwsq_wr32(hwsq
, 0x00c040, mast
);
706 /* core: for the moment at least, always use nvpll */
707 clk
= calc_pll(dev
, 0x4028, &pll
, perflvl
->core
, &N
, &M
, &P1
);
711 ctrl
= nv_rd32(dev
, 0x004028) & ~0xc03f0100;
715 hwsq_wr32(hwsq
, 0x004028, 0x80000000 | (P1
<< 19) | (P1
<< 16) | ctrl
);
716 hwsq_wr32(hwsq
, 0x00402c, (N
<< 8) | M
);
718 /* shader: tie to nvclk if possible, otherwise use spll. have to be
719 * very careful that the shader clock is at least twice the core, or
720 * some chipsets will be very unhappy. i expect most or all of these
721 * cases will be handled by tying to nvclk, but it's possible there's
724 ctrl
= nv_rd32(dev
, 0x004020) & ~0xc03f0100;
726 if (P1
-- && perflvl
->shader
== (perflvl
->core
<< 1)) {
727 hwsq_wr32(hwsq
, 0x004020, (P1
<< 19) | (P1
<< 16) | ctrl
);
728 hwsq_wr32(hwsq
, 0x00c040, 0x00000020 | mast
);
730 clk
= calc_pll(dev
, 0x4020, &pll
, perflvl
->shader
, &N
, &M
, &P1
);
735 hwsq_wr32(hwsq
, 0x004020, (P1
<< 19) | (P1
<< 16) | ctrl
);
736 hwsq_wr32(hwsq
, 0x004024, (N
<< 8) | M
);
737 hwsq_wr32(hwsq
, 0x00c040, 0x00000030 | mast
);
740 hwsq_setf(hwsq
, 0x10, 1); /* enable bus access */
741 hwsq_op5f(hwsq
, 0x00, 0x00); /* wait for access enabled? */
751 prog_hwsq(struct drm_device
*dev
, struct hwsq_ucode
*hwsq
)
753 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
754 u32 hwsq_data
, hwsq_kick
;
757 if (dev_priv
->chipset
< 0x94) {
758 hwsq_data
= 0x001400;
759 hwsq_kick
= 0x00000003;
761 hwsq_data
= 0x080000;
762 hwsq_kick
= 0x00000001;
764 /* upload hwsq ucode */
765 nv_mask(dev
, 0x001098, 0x00000008, 0x00000000);
766 nv_wr32(dev
, 0x001304, 0x00000000);
767 if (dev_priv
->chipset
>= 0x92)
768 nv_wr32(dev
, 0x001318, 0x00000000);
769 for (i
= 0; i
< hwsq
->len
/ 4; i
++)
770 nv_wr32(dev
, hwsq_data
+ (i
* 4), hwsq
->ptr
.u32
[i
]);
771 nv_mask(dev
, 0x001098, 0x00000018, 0x00000018);
773 /* launch, and wait for completion */
774 nv_wr32(dev
, 0x00130c, hwsq_kick
);
775 if (!nv_wait(dev
, 0x001308, 0x00000100, 0x00000000)) {
776 NV_ERROR(dev
, "hwsq ucode exec timed out\n");
777 NV_ERROR(dev
, "0x001308: 0x%08x\n", nv_rd32(dev
, 0x001308));
778 for (i
= 0; i
< hwsq
->len
/ 4; i
++) {
779 NV_ERROR(dev
, "0x%06x: 0x%08x\n", 0x1400 + (i
* 4),
780 nv_rd32(dev
, 0x001400 + (i
* 4)));
790 nv50_pm_clocks_set(struct drm_device
*dev
, void *data
)
792 struct nv50_pm_state
*info
= data
;
796 /* halt and idle execution engines */
797 nv_mask(dev
, 0x002504, 0x00000001, 0x00000001);
798 if (!nv_wait(dev
, 0x002504, 0x00000010, 0x00000010))
800 if (!nv_wait(dev
, 0x00251c, 0x0000003f, 0x0000003f))
803 /* program memory clock, if necessary - must come before engine clock
804 * reprogramming due to how we construct the hwsq scripts in pre()
806 if (info
->mclk_hwsq
.len
) {
807 /* execute some scripts that do ??? from the vbios.. */
808 if (!bit_table(dev
, 'M', &M
) && M
.version
== 1) {
810 nouveau_bios_init_exec(dev
, ROM16(M
.data
[5]));
812 nouveau_bios_init_exec(dev
, ROM16(M
.data
[7]));
814 nouveau_bios_init_exec(dev
, ROM16(M
.data
[9]));
815 nouveau_bios_init_exec(dev
, info
->mscript
);
818 ret
= prog_hwsq(dev
, &info
->mclk_hwsq
);
823 /* program engine clocks */
824 ret
= prog_hwsq(dev
, &info
->eclk_hwsq
);
827 nv_mask(dev
, 0x002504, 0x00000001, 0x00000000);
833 pwm_info(struct drm_device
*dev
, int *line
, int *ctrl
, int *indx
)
850 NV_ERROR(dev
, "unknown pwm ctrl for gpio %d\n", *line
);
858 nv50_pm_pwm_get(struct drm_device
*dev
, int line
, u32
*divs
, u32
*duty
)
860 int ctrl
, id
, ret
= pwm_info(dev
, &line
, &ctrl
, &id
);
864 if (nv_rd32(dev
, ctrl
) & (1 << line
)) {
865 *divs
= nv_rd32(dev
, 0x00e114 + (id
* 8));
866 *duty
= nv_rd32(dev
, 0x00e118 + (id
* 8));
874 nv50_pm_pwm_set(struct drm_device
*dev
, int line
, u32 divs
, u32 duty
)
876 int ctrl
, id
, ret
= pwm_info(dev
, &line
, &ctrl
, &id
);
880 nv_mask(dev
, ctrl
, 0x00010001 << line
, 0x00000001 << line
);
881 nv_wr32(dev
, 0x00e114 + (id
* 8), divs
);
882 nv_wr32(dev
, 0x00e118 + (id
* 8), duty
| 0x80000000);