2 * Copyright 2010 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "nouveau_drv.h"
27 #include "nouveau_util.h"
28 #include "nouveau_vm.h"
30 static void nv84_crypt_isr(struct drm_device
*);
33 nv84_crypt_create_context(struct nouveau_channel
*chan
)
35 struct drm_device
*dev
= chan
->dev
;
36 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
37 struct nouveau_gpuobj
*ramin
= chan
->ramin
;
40 NV_DEBUG(dev
, "ch%d\n", chan
->id
);
42 ret
= nouveau_gpuobj_new(dev
, chan
, 256, 0,
43 NVOBJ_FLAG_ZERO_ALLOC
| NVOBJ_FLAG_ZERO_FREE
,
48 nv_wo32(ramin
, 0xa0, 0x00190000);
49 nv_wo32(ramin
, 0xa4, chan
->crypt_ctx
->vinst
+ 0xff);
50 nv_wo32(ramin
, 0xa8, chan
->crypt_ctx
->vinst
);
51 nv_wo32(ramin
, 0xac, 0);
52 nv_wo32(ramin
, 0xb0, 0);
53 nv_wo32(ramin
, 0xb4, 0);
55 dev_priv
->engine
.instmem
.flush(dev
);
60 nv84_crypt_destroy_context(struct nouveau_channel
*chan
)
62 struct drm_device
*dev
= chan
->dev
;
68 inst
= (chan
->ramin
->vinst
>> 12);
71 /* mark context as invalid if still on the hardware, not
72 * doing this causes issues the next time PCRYPT is used,
75 nv_wr32(dev
, 0x10200c, 0x00000000);
76 if (nv_rd32(dev
, 0x102188) == inst
)
77 nv_mask(dev
, 0x102188, 0x80000000, 0x00000000);
78 if (nv_rd32(dev
, 0x10218c) == inst
)
79 nv_mask(dev
, 0x10218c, 0x80000000, 0x00000000);
80 nv_wr32(dev
, 0x10200c, 0x00000010);
82 nouveau_gpuobj_ref(NULL
, &chan
->crypt_ctx
);
86 nv84_crypt_tlb_flush(struct drm_device
*dev
)
88 nv50_vm_flush_engine(dev
, 0x0a);
92 nv84_crypt_init(struct drm_device
*dev
)
94 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
95 struct nouveau_crypt_engine
*pcrypt
= &dev_priv
->engine
.crypt
;
97 if (!pcrypt
->registered
) {
98 NVOBJ_CLASS(dev
, 0x74c1, CRYPT
);
99 pcrypt
->registered
= true;
102 nv_mask(dev
, 0x000200, 0x00004000, 0x00000000);
103 nv_mask(dev
, 0x000200, 0x00004000, 0x00004000);
105 nouveau_irq_register(dev
, 14, nv84_crypt_isr
);
106 nv_wr32(dev
, 0x102130, 0xffffffff);
107 nv_wr32(dev
, 0x102140, 0xffffffbf);
109 nv_wr32(dev
, 0x10200c, 0x00000010);
114 nv84_crypt_fini(struct drm_device
*dev
)
116 nv_wr32(dev
, 0x102140, 0x00000000);
117 nouveau_irq_unregister(dev
, 14);
121 nv84_crypt_isr(struct drm_device
*dev
)
123 u32 stat
= nv_rd32(dev
, 0x102130);
124 u32 mthd
= nv_rd32(dev
, 0x102190);
125 u32 data
= nv_rd32(dev
, 0x102194);
126 u32 inst
= nv_rd32(dev
, 0x102188) & 0x7fffffff;
127 int show
= nouveau_ratelimit();
130 NV_INFO(dev
, "PCRYPT_INTR: 0x%08x 0x%08x 0x%08x 0x%08x\n",
131 stat
, mthd
, data
, inst
);
134 nv_wr32(dev
, 0x102130, stat
);
135 nv_wr32(dev
, 0x10200c, 0x10);
137 nv50_fb_vm_trap(dev
, show
, "PCRYPT");
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