drivers/gpu/drm/nouveau/nv84_fifo.c

   1 /*
   2  * Copyright (C) 2012 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "nouveau_drv.h"
  30 #include "nouveau_fifo.h"
  31 #include "nouveau_ramht.h"
  32 #include "nouveau_vm.h"
  33
  34 struct nv84_fifo_priv {
  35         struct nouveau_fifo_priv base;
  36         struct nouveau_gpuobj *playlist[2];
  37         int cur_playlist;
  38 };
  39
  40 struct nv84_fifo_chan {
  41         struct nouveau_fifo_chan base;
  42         struct nouveau_gpuobj *ramfc;
  43         struct nouveau_gpuobj *cache;
  44 };
  45
  46 static int
  47 nv84_fifo_context_new(struct nouveau_channel *chan, int engine)
  48 {
  49         struct nv84_fifo_priv *priv = nv_engine(chan->dev, engine);
  50         struct nv84_fifo_chan *fctx;
  51         struct drm_device *dev = chan->dev;
  52         struct drm_nouveau_private *dev_priv = dev->dev_private;
  53         u64 ib_offset = chan->pushbuf_base + chan->dma.ib_base * 4;
  54         u64 instance;
  55         unsigned long flags;
  56         int ret;
  57
  58         fctx = chan->engctx[engine] = kzalloc(sizeof(*fctx), GFP_KERNEL);
  59         if (!fctx)
  60                 return -ENOMEM;
  61         atomic_inc(&chan->vm->engref[engine]);
  62
  63         chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
  64                              NV50_USER(chan->id), PAGE_SIZE);
  65         if (!chan->user) {
  66                 ret = -ENOMEM;
  67                 goto error;
  68         }
  69
  70         ret = nouveau_gpuobj_new(dev, chan, 256, 256, NVOBJ_FLAG_ZERO_ALLOC |
  71                                  NVOBJ_FLAG_ZERO_FREE, &fctx->ramfc);
  72         if (ret)
  73                 goto error;
  74
  75         instance = fctx->ramfc->vinst >> 8;
  76
  77         ret = nouveau_gpuobj_new(dev, chan, 4096, 1024, 0, &fctx->cache);
  78         if (ret)
  79                 goto error;
  80
  81         nv_wo32(fctx->ramfc, 0x3c, 0x403f6078);
  82         nv_wo32(fctx->ramfc, 0x40, 0x00000000);
  83         nv_wo32(fctx->ramfc, 0x44, 0x01003fff);
  84         nv_wo32(fctx->ramfc, 0x48, chan->pushbuf->cinst >> 4);
  85         nv_wo32(fctx->ramfc, 0x50, lower_32_bits(ib_offset));
  86         nv_wo32(fctx->ramfc, 0x54, upper_32_bits(ib_offset) |
  87                                    drm_order(chan->dma.ib_max + 1) << 16);
  88         nv_wo32(fctx->ramfc, 0x60, 0x7fffffff);
  89         nv_wo32(fctx->ramfc, 0x78, 0x00000000);
  90         nv_wo32(fctx->ramfc, 0x7c, 0x30000001);
  91         nv_wo32(fctx->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
  92                                    (4 << 24) /* SEARCH_FULL */ |
  93                                    (chan->ramht->gpuobj->cinst >> 4));
  94         nv_wo32(fctx->ramfc, 0x88, fctx->cache->vinst >> 10);
  95         nv_wo32(fctx->ramfc, 0x98, chan->ramin->vinst >> 12);
  96
  97         nv_wo32(chan->ramin, 0x00, chan->id);
  98         nv_wo32(chan->ramin, 0x04, fctx->ramfc->vinst >> 8);
  99
 100         dev_priv->engine.instmem.flush(dev);
 101
 102         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 103         nv_wr32(dev, 0x002600 + (chan->id * 4), 0x80000000 | instance);
 104         nv50_fifo_playlist_update(dev);
 105         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 106
 107 error:
 108         if (ret)
 109                 priv->base.base.context_del(chan, engine);
 110         return ret;
 111 }
 112
 113 static void
 114 nv84_fifo_context_del(struct nouveau_channel *chan, int engine)
 115 {
 116         struct nv84_fifo_chan *fctx = chan->engctx[engine];
 117         struct drm_device *dev = chan->dev;
 118         struct drm_nouveau_private *dev_priv = dev->dev_private;
 119         unsigned long flags;
 120         u32 save;
 121
 122         /* remove channel from playlist, will context switch if active */
 123         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 124         nv_mask(dev, 0x002600 + (chan->id * 4), 0x80000000, 0x00000000);
 125         nv50_fifo_playlist_update(dev);
 126
 127         save = nv_mask(dev, 0x002520, 0x0000003f, 0x15);
 128
 129         /* tell any engines on this channel to unload their contexts */
 130         nv_wr32(dev, 0x0032fc, chan->ramin->vinst >> 12);
 131         if (!nv_wait_ne(dev, 0x0032fc, 0xffffffff, 0xffffffff))
 132                 NV_INFO(dev, "PFIFO: channel %d unload timeout\n", chan->id);
 133
 134         nv_wr32(dev, 0x002520, save);
 135
 136         nv_wr32(dev, 0x002600 + (chan->id * 4), 0x00000000);
 137         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 138
 139         /* clean up */
 140         if (chan->user) {
 141                 iounmap(chan->user);
 142                 chan->user = NULL;
 143         }
 144
 145         nouveau_gpuobj_ref(NULL, &fctx->ramfc);
 146         nouveau_gpuobj_ref(NULL, &fctx->cache);
 147
 148         atomic_dec(&chan->vm->engref[engine]);
 149         chan->engctx[engine] = NULL;
 150         kfree(fctx);
 151 }
 152
 153 static int
 154 nv84_fifo_init(struct drm_device *dev, int engine)
 155 {
 156         struct drm_nouveau_private *dev_priv = dev->dev_private;
 157         struct nv84_fifo_chan *fctx;
 158         u32 instance;
 159         int i;
 160
 161         nv_mask(dev, 0x000200, 0x00000100, 0x00000000);
 162         nv_mask(dev, 0x000200, 0x00000100, 0x00000100);
 163         nv_wr32(dev, 0x00250c, 0x6f3cfc34);
 164         nv_wr32(dev, 0x002044, 0x01003fff);
 165
 166         nv_wr32(dev, 0x002100, 0xffffffff);
 167         nv_wr32(dev, 0x002140, 0xffffffff);
 168
 169         for (i = 0; i < 128; i++) {
 170                 struct nouveau_channel *chan = dev_priv->channels.ptr[i];
 171                 if (chan && (fctx = chan->engctx[engine]))
 172                         instance = 0x80000000 | fctx->ramfc->vinst >> 8;
 173                 else
 174                         instance = 0x00000000;
 175                 nv_wr32(dev, 0x002600 + (i * 4), instance);
 176         }
 177
 178         nv50_fifo_playlist_update(dev);
 179
 180         nv_wr32(dev, 0x003200, 1);
 181         nv_wr32(dev, 0x003250, 1);
 182         nv_wr32(dev, 0x002500, 1);
 183         return 0;
 184 }
 185
 186 static int
 187 nv84_fifo_fini(struct drm_device *dev, int engine, bool suspend)
 188 {
 189         struct drm_nouveau_private *dev_priv = dev->dev_private;
 190         struct nv84_fifo_priv *priv = nv_engine(dev, engine);
 191         int i;
 192         u32 save;
 193
 194         /* set playlist length to zero, fifo will unload context */
 195         nv_wr32(dev, 0x0032ec, 0);
 196
 197         save = nv_mask(dev, 0x002520, 0x0000003f, 0x15);
 198
 199         /* tell all connected engines to unload their contexts */
 200         for (i = 0; i < priv->base.channels; i++) {
 201                 struct nouveau_channel *chan = dev_priv->channels.ptr[i];
 202                 if (chan)
 203                         nv_wr32(dev, 0x0032fc, chan->ramin->vinst >> 12);
 204                 if (!nv_wait_ne(dev, 0x0032fc, 0xffffffff, 0xffffffff)) {
 205                         NV_INFO(dev, "PFIFO: channel %d unload timeout\n", i);
 206                         return -EBUSY;
 207                 }
 208         }
 209
 210         nv_wr32(dev, 0x002520, save);
 211         nv_wr32(dev, 0x002140, 0);
 212         return 0;
 213 }
 214
 215 int
 216 nv84_fifo_create(struct drm_device *dev)
 217 {
 218         struct drm_nouveau_private *dev_priv = dev->dev_private;
 219         struct nv84_fifo_priv *priv;
 220         int ret;
 221
 222         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 223         if (!priv)
 224                 return -ENOMEM;
 225
 226         priv->base.base.destroy = nv50_fifo_destroy;
 227         priv->base.base.init = nv84_fifo_init;
 228         priv->base.base.fini = nv84_fifo_fini;
 229         priv->base.base.context_new = nv84_fifo_context_new;
 230         priv->base.base.context_del = nv84_fifo_context_del;
 231         priv->base.base.tlb_flush = nv50_fifo_tlb_flush;
 232         priv->base.channels = 127;
 233         dev_priv->eng[NVOBJ_ENGINE_FIFO] = &priv->base.base;
 234
 235         ret = nouveau_gpuobj_new(dev, NULL, priv->base.channels * 4, 0x1000,
 236                                  NVOBJ_FLAG_ZERO_ALLOC, &priv->playlist[0]);
 237         if (ret)
 238                 goto error;
 239
 240         ret = nouveau_gpuobj_new(dev, NULL, priv->base.channels * 4, 0x1000,
 241                                  NVOBJ_FLAG_ZERO_ALLOC, &priv->playlist[1]);
 242         if (ret)
 243                 goto error;
 244
 245         nouveau_irq_register(dev, 8, nv04_fifo_isr);
 246 error:
 247         if (ret)
 248                 priv->base.base.destroy(dev, NVOBJ_ENGINE_FIFO);
 249         return ret;
 250 }