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drm/nouveau: port all engines to new engine module format
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvd0_display.c
1 /*
2 * Copyright 2011 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <linux/dma-mapping.h>
26
27 #include "drmP.h"
28 #include "drm_crtc_helper.h"
29
30 #include "nouveau_drv.h"
31 #include "nouveau_connector.h"
32 #include "nouveau_encoder.h"
33 #include "nouveau_crtc.h"
34 #include "nouveau_fb.h"
35 #include "nouveau_fence.h"
36 #include "nv50_display.h"
37
38 #define EVO_DMA_NR 9
39
40 #define EVO_MASTER (0x00)
41 #define EVO_FLIP(c) (0x01 + (c))
42 #define EVO_OVLY(c) (0x05 + (c))
43 #define EVO_OIMM(c) (0x09 + (c))
44 #define EVO_CURS(c) (0x0d + (c))
45
46 /* offsets in shared sync bo of various structures */
47 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
48 #define EVO_MAST_NTFY EVO_SYNC( 0, 0x00)
49 #define EVO_FLIP_SEM0(c) EVO_SYNC((c), 0x00)
50 #define EVO_FLIP_SEM1(c) EVO_SYNC((c), 0x10)
51
52 struct evo {
53 int idx;
54 dma_addr_t handle;
55 u32 *ptr;
56 struct {
57 u32 offset;
58 u16 value;
59 } sem;
60 };
61
62 struct nvd0_display {
63 struct nouveau_gpuobj *mem;
64 struct nouveau_bo *sync;
65 struct evo evo[9];
66
67 struct tasklet_struct tasklet;
68 u32 modeset;
69 };
70
71 static struct nvd0_display *
72 nvd0_display(struct drm_device *dev)
73 {
74 struct drm_nouveau_private *dev_priv = dev->dev_private;
75 return dev_priv->engine.display.priv;
76 }
77
78 static struct drm_crtc *
79 nvd0_display_crtc_get(struct drm_encoder *encoder)
80 {
81 return nouveau_encoder(encoder)->crtc;
82 }
83
84 /******************************************************************************
85 * EVO channel helpers
86 *****************************************************************************/
87 static inline int
88 evo_icmd(struct drm_device *dev, int id, u32 mthd, u32 data)
89 {
90 int ret = 0;
91 nv_mask(dev, 0x610700 + (id * 0x10), 0x00000001, 0x00000001);
92 nv_wr32(dev, 0x610704 + (id * 0x10), data);
93 nv_mask(dev, 0x610704 + (id * 0x10), 0x80000ffc, 0x80000000 | mthd);
94 if (!nv_wait(dev, 0x610704 + (id * 0x10), 0x80000000, 0x00000000))
95 ret = -EBUSY;
96 nv_mask(dev, 0x610700 + (id * 0x10), 0x00000001, 0x00000000);
97 return ret;
98 }
99
100 static u32 *
101 evo_wait(struct drm_device *dev, int id, int nr)
102 {
103 struct nvd0_display *disp = nvd0_display(dev);
104 u32 put = nv_rd32(dev, 0x640000 + (id * 0x1000)) / 4;
105
106 if (put + nr >= (PAGE_SIZE / 4)) {
107 disp->evo[id].ptr[put] = 0x20000000;
108
109 nv_wr32(dev, 0x640000 + (id * 0x1000), 0x00000000);
110 if (!nv_wait(dev, 0x640004 + (id * 0x1000), ~0, 0x00000000)) {
111 NV_ERROR(dev, "evo %d dma stalled\n", id);
112 return NULL;
113 }
114
115 put = 0;
116 }
117
118 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
119 NV_INFO(dev, "Evo%d: %p START\n", id, disp->evo[id].ptr + put);
120
121 return disp->evo[id].ptr + put;
122 }
123
124 static void
125 evo_kick(u32 *push, struct drm_device *dev, int id)
126 {
127 struct nvd0_display *disp = nvd0_display(dev);
128
129 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO) {
130 u32 curp = nv_rd32(dev, 0x640000 + (id * 0x1000)) >> 2;
131 u32 *cur = disp->evo[id].ptr + curp;
132
133 while (cur < push)
134 NV_INFO(dev, "Evo%d: 0x%08x\n", id, *cur++);
135 NV_INFO(dev, "Evo%d: %p KICK!\n", id, push);
136 }
137
138 nv_wr32(dev, 0x640000 + (id * 0x1000), (push - disp->evo[id].ptr) << 2);
139 }
140
141 #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
142 #define evo_data(p,d) *((p)++) = (d)
143
144 static int
145 evo_init_dma(struct drm_device *dev, int ch)
146 {
147 struct nvd0_display *disp = nvd0_display(dev);
148 u32 flags;
149
150 flags = 0x00000000;
151 if (ch == EVO_MASTER)
152 flags |= 0x01000000;
153
154 nv_wr32(dev, 0x610494 + (ch * 0x0010), (disp->evo[ch].handle >> 8) | 3);
155 nv_wr32(dev, 0x610498 + (ch * 0x0010), 0x00010000);
156 nv_wr32(dev, 0x61049c + (ch * 0x0010), 0x00000001);
157 nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000010, 0x00000010);
158 nv_wr32(dev, 0x640000 + (ch * 0x1000), 0x00000000);
159 nv_wr32(dev, 0x610490 + (ch * 0x0010), 0x00000013 | flags);
160 if (!nv_wait(dev, 0x610490 + (ch * 0x0010), 0x80000000, 0x00000000)) {
161 NV_ERROR(dev, "PDISP: ch%d 0x%08x\n", ch,
162 nv_rd32(dev, 0x610490 + (ch * 0x0010)));
163 return -EBUSY;
164 }
165
166 nv_mask(dev, 0x610090, (1 << ch), (1 << ch));
167 nv_mask(dev, 0x6100a0, (1 << ch), (1 << ch));
168 return 0;
169 }
170
171 static void
172 evo_fini_dma(struct drm_device *dev, int ch)
173 {
174 if (!(nv_rd32(dev, 0x610490 + (ch * 0x0010)) & 0x00000010))
175 return;
176
177 nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000010, 0x00000000);
178 nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000003, 0x00000000);
179 nv_wait(dev, 0x610490 + (ch * 0x0010), 0x80000000, 0x00000000);
180 nv_mask(dev, 0x610090, (1 << ch), 0x00000000);
181 nv_mask(dev, 0x6100a0, (1 << ch), 0x00000000);
182 }
183
184 static inline void
185 evo_piow(struct drm_device *dev, int ch, u16 mthd, u32 data)
186 {
187 nv_wr32(dev, 0x640000 + (ch * 0x1000) + mthd, data);
188 }
189
190 static int
191 evo_init_pio(struct drm_device *dev, int ch)
192 {
193 nv_wr32(dev, 0x610490 + (ch * 0x0010), 0x00000001);
194 if (!nv_wait(dev, 0x610490 + (ch * 0x0010), 0x00010000, 0x00010000)) {
195 NV_ERROR(dev, "PDISP: ch%d 0x%08x\n", ch,
196 nv_rd32(dev, 0x610490 + (ch * 0x0010)));
197 return -EBUSY;
198 }
199
200 nv_mask(dev, 0x610090, (1 << ch), (1 << ch));
201 nv_mask(dev, 0x6100a0, (1 << ch), (1 << ch));
202 return 0;
203 }
204
205 static void
206 evo_fini_pio(struct drm_device *dev, int ch)
207 {
208 if (!(nv_rd32(dev, 0x610490 + (ch * 0x0010)) & 0x00000001))
209 return;
210
211 nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000010, 0x00000010);
212 nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000001, 0x00000000);
213 nv_wait(dev, 0x610490 + (ch * 0x0010), 0x00010000, 0x00000000);
214 nv_mask(dev, 0x610090, (1 << ch), 0x00000000);
215 nv_mask(dev, 0x6100a0, (1 << ch), 0x00000000);
216 }
217
218 static bool
219 evo_sync_wait(void *data)
220 {
221 return nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000;
222 }
223
224 static int
225 evo_sync(struct drm_device *dev, int ch)
226 {
227 struct nvd0_display *disp = nvd0_display(dev);
228 u32 *push = evo_wait(dev, ch, 8);
229 if (push) {
230 nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
231 evo_mthd(push, 0x0084, 1);
232 evo_data(push, 0x80000000 | EVO_MAST_NTFY);
233 evo_mthd(push, 0x0080, 2);
234 evo_data(push, 0x00000000);
235 evo_data(push, 0x00000000);
236 evo_kick(push, dev, ch);
237 if (nv_wait_cb(dev, evo_sync_wait, disp->sync))
238 return 0;
239 }
240
241 return -EBUSY;
242 }
243
244 /******************************************************************************
245 * Page flipping channel
246 *****************************************************************************/
247 struct nouveau_bo *
248 nvd0_display_crtc_sema(struct drm_device *dev, int crtc)
249 {
250 return nvd0_display(dev)->sync;
251 }
252
253 void
254 nvd0_display_flip_stop(struct drm_crtc *crtc)
255 {
256 struct nvd0_display *disp = nvd0_display(crtc->dev);
257 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
258 struct evo *evo = &disp->evo[EVO_FLIP(nv_crtc->index)];
259 u32 *push;
260
261 push = evo_wait(crtc->dev, evo->idx, 8);
262 if (push) {
263 evo_mthd(push, 0x0084, 1);
264 evo_data(push, 0x00000000);
265 evo_mthd(push, 0x0094, 1);
266 evo_data(push, 0x00000000);
267 evo_mthd(push, 0x00c0, 1);
268 evo_data(push, 0x00000000);
269 evo_mthd(push, 0x0080, 1);
270 evo_data(push, 0x00000000);
271 evo_kick(push, crtc->dev, evo->idx);
272 }
273 }
274
275 int
276 nvd0_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
277 struct nouveau_channel *chan, u32 swap_interval)
278 {
279 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
280 struct nvd0_display *disp = nvd0_display(crtc->dev);
281 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
282 struct evo *evo = &disp->evo[EVO_FLIP(nv_crtc->index)];
283 u64 offset;
284 u32 *push;
285 int ret;
286
287 swap_interval <<= 4;
288 if (swap_interval == 0)
289 swap_interval |= 0x100;
290
291 push = evo_wait(crtc->dev, evo->idx, 128);
292 if (unlikely(push == NULL))
293 return -EBUSY;
294
295 /* synchronise with the rendering channel, if necessary */
296 if (likely(chan)) {
297 ret = RING_SPACE(chan, 10);
298 if (ret)
299 return ret;
300
301
302 offset = nvc0_fence_crtc(chan, nv_crtc->index);
303 offset += evo->sem.offset;
304
305 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
306 OUT_RING (chan, upper_32_bits(offset));
307 OUT_RING (chan, lower_32_bits(offset));
308 OUT_RING (chan, 0xf00d0000 | evo->sem.value);
309 OUT_RING (chan, 0x1002);
310 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
311 OUT_RING (chan, upper_32_bits(offset));
312 OUT_RING (chan, lower_32_bits(offset ^ 0x10));
313 OUT_RING (chan, 0x74b1e000);
314 OUT_RING (chan, 0x1001);
315 FIRE_RING (chan);
316 } else {
317 nouveau_bo_wr32(disp->sync, evo->sem.offset / 4,
318 0xf00d0000 | evo->sem.value);
319 evo_sync(crtc->dev, EVO_MASTER);
320 }
321
322 /* queue the flip */
323 evo_mthd(push, 0x0100, 1);
324 evo_data(push, 0xfffe0000);
325 evo_mthd(push, 0x0084, 1);
326 evo_data(push, swap_interval);
327 if (!(swap_interval & 0x00000100)) {
328 evo_mthd(push, 0x00e0, 1);
329 evo_data(push, 0x40000000);
330 }
331 evo_mthd(push, 0x0088, 4);
332 evo_data(push, evo->sem.offset);
333 evo_data(push, 0xf00d0000 | evo->sem.value);
334 evo_data(push, 0x74b1e000);
335 evo_data(push, NvEvoSync);
336 evo_mthd(push, 0x00a0, 2);
337 evo_data(push, 0x00000000);
338 evo_data(push, 0x00000000);
339 evo_mthd(push, 0x00c0, 1);
340 evo_data(push, nv_fb->r_dma);
341 evo_mthd(push, 0x0110, 2);
342 evo_data(push, 0x00000000);
343 evo_data(push, 0x00000000);
344 evo_mthd(push, 0x0400, 5);
345 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
346 evo_data(push, 0);
347 evo_data(push, (fb->height << 16) | fb->width);
348 evo_data(push, nv_fb->r_pitch);
349 evo_data(push, nv_fb->r_format);
350 evo_mthd(push, 0x0080, 1);
351 evo_data(push, 0x00000000);
352 evo_kick(push, crtc->dev, evo->idx);
353
354 evo->sem.offset ^= 0x10;
355 evo->sem.value++;
356 return 0;
357 }
358
359 /******************************************************************************
360 * CRTC
361 *****************************************************************************/
362 static int
363 nvd0_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
364 {
365 struct drm_nouveau_private *dev_priv = nv_crtc->base.dev->dev_private;
366 struct drm_device *dev = nv_crtc->base.dev;
367 struct nouveau_connector *nv_connector;
368 struct drm_connector *connector;
369 u32 *push, mode = 0x00;
370 u32 mthd;
371
372 nv_connector = nouveau_crtc_connector_get(nv_crtc);
373 connector = &nv_connector->base;
374 if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
375 if (nv_crtc->base.fb->depth > connector->display_info.bpc * 3)
376 mode = DITHERING_MODE_DYNAMIC2X2;
377 } else {
378 mode = nv_connector->dithering_mode;
379 }
380
381 if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
382 if (connector->display_info.bpc >= 8)
383 mode |= DITHERING_DEPTH_8BPC;
384 } else {
385 mode |= nv_connector->dithering_depth;
386 }
387
388 if (dev_priv->card_type < NV_E0)
389 mthd = 0x0490 + (nv_crtc->index * 0x0300);
390 else
391 mthd = 0x04a0 + (nv_crtc->index * 0x0300);
392
393 push = evo_wait(dev, EVO_MASTER, 4);
394 if (push) {
395 evo_mthd(push, mthd, 1);
396 evo_data(push, mode);
397 if (update) {
398 evo_mthd(push, 0x0080, 1);
399 evo_data(push, 0x00000000);
400 }
401 evo_kick(push, dev, EVO_MASTER);
402 }
403
404 return 0;
405 }
406
407 static int
408 nvd0_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
409 {
410 struct drm_display_mode *omode, *umode = &nv_crtc->base.mode;
411 struct drm_device *dev = nv_crtc->base.dev;
412 struct drm_crtc *crtc = &nv_crtc->base;
413 struct nouveau_connector *nv_connector;
414 int mode = DRM_MODE_SCALE_NONE;
415 u32 oX, oY, *push;
416
417 /* start off at the resolution we programmed the crtc for, this
418 * effectively handles NONE/FULL scaling
419 */
420 nv_connector = nouveau_crtc_connector_get(nv_crtc);
421 if (nv_connector && nv_connector->native_mode)
422 mode = nv_connector->scaling_mode;
423
424 if (mode != DRM_MODE_SCALE_NONE)
425 omode = nv_connector->native_mode;
426 else
427 omode = umode;
428
429 oX = omode->hdisplay;
430 oY = omode->vdisplay;
431 if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
432 oY *= 2;
433
434 /* add overscan compensation if necessary, will keep the aspect
435 * ratio the same as the backend mode unless overridden by the
436 * user setting both hborder and vborder properties.
437 */
438 if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON ||
439 (nv_connector->underscan == UNDERSCAN_AUTO &&
440 nv_connector->edid &&
441 drm_detect_hdmi_monitor(nv_connector->edid)))) {
442 u32 bX = nv_connector->underscan_hborder;
443 u32 bY = nv_connector->underscan_vborder;
444 u32 aspect = (oY << 19) / oX;
445
446 if (bX) {
447 oX -= (bX * 2);
448 if (bY) oY -= (bY * 2);
449 else oY = ((oX * aspect) + (aspect / 2)) >> 19;
450 } else {
451 oX -= (oX >> 4) + 32;
452 if (bY) oY -= (bY * 2);
453 else oY = ((oX * aspect) + (aspect / 2)) >> 19;
454 }
455 }
456
457 /* handle CENTER/ASPECT scaling, taking into account the areas
458 * removed already for overscan compensation
459 */
460 switch (mode) {
461 case DRM_MODE_SCALE_CENTER:
462 oX = min((u32)umode->hdisplay, oX);
463 oY = min((u32)umode->vdisplay, oY);
464 /* fall-through */
465 case DRM_MODE_SCALE_ASPECT:
466 if (oY < oX) {
467 u32 aspect = (umode->hdisplay << 19) / umode->vdisplay;
468 oX = ((oY * aspect) + (aspect / 2)) >> 19;
469 } else {
470 u32 aspect = (umode->vdisplay << 19) / umode->hdisplay;
471 oY = ((oX * aspect) + (aspect / 2)) >> 19;
472 }
473 break;
474 default:
475 break;
476 }
477
478 push = evo_wait(dev, EVO_MASTER, 8);
479 if (push) {
480 evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
481 evo_data(push, (oY << 16) | oX);
482 evo_data(push, (oY << 16) | oX);
483 evo_data(push, (oY << 16) | oX);
484 evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
485 evo_data(push, 0x00000000);
486 evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
487 evo_data(push, (umode->vdisplay << 16) | umode->hdisplay);
488 evo_kick(push, dev, EVO_MASTER);
489 if (update) {
490 nvd0_display_flip_stop(crtc);
491 nvd0_display_flip_next(crtc, crtc->fb, NULL, 1);
492 }
493 }
494
495 return 0;
496 }
497
498 static int
499 nvd0_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
500 int x, int y, bool update)
501 {
502 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
503 u32 *push;
504
505 push = evo_wait(fb->dev, EVO_MASTER, 16);
506 if (push) {
507 evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
508 evo_data(push, nvfb->nvbo->bo.offset >> 8);
509 evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
510 evo_data(push, (fb->height << 16) | fb->width);
511 evo_data(push, nvfb->r_pitch);
512 evo_data(push, nvfb->r_format);
513 evo_data(push, nvfb->r_dma);
514 evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
515 evo_data(push, (y << 16) | x);
516 if (update) {
517 evo_mthd(push, 0x0080, 1);
518 evo_data(push, 0x00000000);
519 }
520 evo_kick(push, fb->dev, EVO_MASTER);
521 }
522
523 nv_crtc->fb.tile_flags = nvfb->r_dma;
524 return 0;
525 }
526
527 static void
528 nvd0_crtc_cursor_show(struct nouveau_crtc *nv_crtc, bool show, bool update)
529 {
530 struct drm_device *dev = nv_crtc->base.dev;
531 u32 *push = evo_wait(dev, EVO_MASTER, 16);
532 if (push) {
533 if (show) {
534 evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
535 evo_data(push, 0x85000000);
536 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
537 evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
538 evo_data(push, NvEvoVRAM);
539 } else {
540 evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
541 evo_data(push, 0x05000000);
542 evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
543 evo_data(push, 0x00000000);
544 }
545
546 if (update) {
547 evo_mthd(push, 0x0080, 1);
548 evo_data(push, 0x00000000);
549 }
550
551 evo_kick(push, dev, EVO_MASTER);
552 }
553 }
554
555 static void
556 nvd0_crtc_dpms(struct drm_crtc *crtc, int mode)
557 {
558 }
559
560 static void
561 nvd0_crtc_prepare(struct drm_crtc *crtc)
562 {
563 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
564 u32 *push;
565
566 nvd0_display_flip_stop(crtc);
567
568 push = evo_wait(crtc->dev, EVO_MASTER, 2);
569 if (push) {
570 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
571 evo_data(push, 0x00000000);
572 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
573 evo_data(push, 0x03000000);
574 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
575 evo_data(push, 0x00000000);
576 evo_kick(push, crtc->dev, EVO_MASTER);
577 }
578
579 nvd0_crtc_cursor_show(nv_crtc, false, false);
580 }
581
582 static void
583 nvd0_crtc_commit(struct drm_crtc *crtc)
584 {
585 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
586 u32 *push;
587
588 push = evo_wait(crtc->dev, EVO_MASTER, 32);
589 if (push) {
590 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
591 evo_data(push, nv_crtc->fb.tile_flags);
592 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
593 evo_data(push, 0x83000000);
594 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
595 evo_data(push, 0x00000000);
596 evo_data(push, 0x00000000);
597 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
598 evo_data(push, NvEvoVRAM);
599 evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
600 evo_data(push, 0xffffff00);
601 evo_kick(push, crtc->dev, EVO_MASTER);
602 }
603
604 nvd0_crtc_cursor_show(nv_crtc, nv_crtc->cursor.visible, true);
605 nvd0_display_flip_next(crtc, crtc->fb, NULL, 1);
606 }
607
608 static bool
609 nvd0_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
610 struct drm_display_mode *adjusted_mode)
611 {
612 return true;
613 }
614
615 static int
616 nvd0_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
617 {
618 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->fb);
619 int ret;
620
621 ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM);
622 if (ret)
623 return ret;
624
625 if (old_fb) {
626 nvfb = nouveau_framebuffer(old_fb);
627 nouveau_bo_unpin(nvfb->nvbo);
628 }
629
630 return 0;
631 }
632
633 static int
634 nvd0_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
635 struct drm_display_mode *mode, int x, int y,
636 struct drm_framebuffer *old_fb)
637 {
638 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
639 struct nouveau_connector *nv_connector;
640 u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
641 u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
642 u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
643 u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
644 u32 vblan2e = 0, vblan2s = 1;
645 u32 *push;
646 int ret;
647
648 hactive = mode->htotal;
649 hsynce = mode->hsync_end - mode->hsync_start - 1;
650 hbackp = mode->htotal - mode->hsync_end;
651 hblanke = hsynce + hbackp;
652 hfrontp = mode->hsync_start - mode->hdisplay;
653 hblanks = mode->htotal - hfrontp - 1;
654
655 vactive = mode->vtotal * vscan / ilace;
656 vsynce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
657 vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace;
658 vblanke = vsynce + vbackp;
659 vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
660 vblanks = vactive - vfrontp - 1;
661 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
662 vblan2e = vactive + vsynce + vbackp;
663 vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
664 vactive = (vactive * 2) + 1;
665 }
666
667 ret = nvd0_crtc_swap_fbs(crtc, old_fb);
668 if (ret)
669 return ret;
670
671 push = evo_wait(crtc->dev, EVO_MASTER, 64);
672 if (push) {
673 evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6);
674 evo_data(push, 0x00000000);
675 evo_data(push, (vactive << 16) | hactive);
676 evo_data(push, ( vsynce << 16) | hsynce);
677 evo_data(push, (vblanke << 16) | hblanke);
678 evo_data(push, (vblanks << 16) | hblanks);
679 evo_data(push, (vblan2e << 16) | vblan2s);
680 evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
681 evo_data(push, 0x00000000); /* ??? */
682 evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
683 evo_data(push, mode->clock * 1000);
684 evo_data(push, 0x00200000); /* ??? */
685 evo_data(push, mode->clock * 1000);
686 evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2);
687 evo_data(push, 0x00000311);
688 evo_data(push, 0x00000100);
689 evo_kick(push, crtc->dev, EVO_MASTER);
690 }
691
692 nv_connector = nouveau_crtc_connector_get(nv_crtc);
693 nvd0_crtc_set_dither(nv_crtc, false);
694 nvd0_crtc_set_scale(nv_crtc, false);
695 nvd0_crtc_set_image(nv_crtc, crtc->fb, x, y, false);
696 return 0;
697 }
698
699 static int
700 nvd0_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
701 struct drm_framebuffer *old_fb)
702 {
703 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
704 int ret;
705
706 if (!crtc->fb) {
707 NV_DEBUG_KMS(crtc->dev, "No FB bound\n");
708 return 0;
709 }
710
711 ret = nvd0_crtc_swap_fbs(crtc, old_fb);
712 if (ret)
713 return ret;
714
715 nvd0_display_flip_stop(crtc);
716 nvd0_crtc_set_image(nv_crtc, crtc->fb, x, y, true);
717 nvd0_display_flip_next(crtc, crtc->fb, NULL, 1);
718 return 0;
719 }
720
721 static int
722 nvd0_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
723 struct drm_framebuffer *fb, int x, int y,
724 enum mode_set_atomic state)
725 {
726 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
727 nvd0_display_flip_stop(crtc);
728 nvd0_crtc_set_image(nv_crtc, fb, x, y, true);
729 return 0;
730 }
731
732 static void
733 nvd0_crtc_lut_load(struct drm_crtc *crtc)
734 {
735 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
736 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
737 int i;
738
739 for (i = 0; i < 256; i++) {
740 writew(0x6000 + (nv_crtc->lut.r[i] >> 2), lut + (i * 0x20) + 0);
741 writew(0x6000 + (nv_crtc->lut.g[i] >> 2), lut + (i * 0x20) + 2);
742 writew(0x6000 + (nv_crtc->lut.b[i] >> 2), lut + (i * 0x20) + 4);
743 }
744 }
745
746 static int
747 nvd0_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
748 uint32_t handle, uint32_t width, uint32_t height)
749 {
750 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
751 struct drm_device *dev = crtc->dev;
752 struct drm_gem_object *gem;
753 struct nouveau_bo *nvbo;
754 bool visible = (handle != 0);
755 int i, ret = 0;
756
757 if (visible) {
758 if (width != 64 || height != 64)
759 return -EINVAL;
760
761 gem = drm_gem_object_lookup(dev, file_priv, handle);
762 if (unlikely(!gem))
763 return -ENOENT;
764 nvbo = nouveau_gem_object(gem);
765
766 ret = nouveau_bo_map(nvbo);
767 if (ret == 0) {
768 for (i = 0; i < 64 * 64; i++) {
769 u32 v = nouveau_bo_rd32(nvbo, i);
770 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v);
771 }
772 nouveau_bo_unmap(nvbo);
773 }
774
775 drm_gem_object_unreference_unlocked(gem);
776 }
777
778 if (visible != nv_crtc->cursor.visible) {
779 nvd0_crtc_cursor_show(nv_crtc, visible, true);
780 nv_crtc->cursor.visible = visible;
781 }
782
783 return ret;
784 }
785
786 static int
787 nvd0_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
788 {
789 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
790 int ch = EVO_CURS(nv_crtc->index);
791
792 evo_piow(crtc->dev, ch, 0x0084, (y << 16) | (x & 0xffff));
793 evo_piow(crtc->dev, ch, 0x0080, 0x00000000);
794 return 0;
795 }
796
797 static void
798 nvd0_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
799 uint32_t start, uint32_t size)
800 {
801 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
802 u32 end = max(start + size, (u32)256);
803 u32 i;
804
805 for (i = start; i < end; i++) {
806 nv_crtc->lut.r[i] = r[i];
807 nv_crtc->lut.g[i] = g[i];
808 nv_crtc->lut.b[i] = b[i];
809 }
810
811 nvd0_crtc_lut_load(crtc);
812 }
813
814 static void
815 nvd0_crtc_destroy(struct drm_crtc *crtc)
816 {
817 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
818 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
819 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
820 nouveau_bo_unmap(nv_crtc->lut.nvbo);
821 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
822 drm_crtc_cleanup(crtc);
823 kfree(crtc);
824 }
825
826 static const struct drm_crtc_helper_funcs nvd0_crtc_hfunc = {
827 .dpms = nvd0_crtc_dpms,
828 .prepare = nvd0_crtc_prepare,
829 .commit = nvd0_crtc_commit,
830 .mode_fixup = nvd0_crtc_mode_fixup,
831 .mode_set = nvd0_crtc_mode_set,
832 .mode_set_base = nvd0_crtc_mode_set_base,
833 .mode_set_base_atomic = nvd0_crtc_mode_set_base_atomic,
834 .load_lut = nvd0_crtc_lut_load,
835 };
836
837 static const struct drm_crtc_funcs nvd0_crtc_func = {
838 .cursor_set = nvd0_crtc_cursor_set,
839 .cursor_move = nvd0_crtc_cursor_move,
840 .gamma_set = nvd0_crtc_gamma_set,
841 .set_config = drm_crtc_helper_set_config,
842 .destroy = nvd0_crtc_destroy,
843 .page_flip = nouveau_crtc_page_flip,
844 };
845
846 static void
847 nvd0_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
848 {
849 }
850
851 static void
852 nvd0_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
853 {
854 }
855
856 static int
857 nvd0_crtc_create(struct drm_device *dev, int index)
858 {
859 struct nouveau_crtc *nv_crtc;
860 struct drm_crtc *crtc;
861 int ret, i;
862
863 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
864 if (!nv_crtc)
865 return -ENOMEM;
866
867 nv_crtc->index = index;
868 nv_crtc->set_dither = nvd0_crtc_set_dither;
869 nv_crtc->set_scale = nvd0_crtc_set_scale;
870 nv_crtc->cursor.set_offset = nvd0_cursor_set_offset;
871 nv_crtc->cursor.set_pos = nvd0_cursor_set_pos;
872 for (i = 0; i < 256; i++) {
873 nv_crtc->lut.r[i] = i << 8;
874 nv_crtc->lut.g[i] = i << 8;
875 nv_crtc->lut.b[i] = i << 8;
876 }
877
878 crtc = &nv_crtc->base;
879 drm_crtc_init(dev, crtc, &nvd0_crtc_func);
880 drm_crtc_helper_add(crtc, &nvd0_crtc_hfunc);
881 drm_mode_crtc_set_gamma_size(crtc, 256);
882
883 ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM,
884 0, 0x0000, NULL, &nv_crtc->cursor.nvbo);
885 if (!ret) {
886 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
887 if (!ret)
888 ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
889 if (ret)
890 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
891 }
892
893 if (ret)
894 goto out;
895
896 ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
897 0, 0x0000, NULL, &nv_crtc->lut.nvbo);
898 if (!ret) {
899 ret = nouveau_bo_pin(nv_crtc->lut.nvbo, TTM_PL_FLAG_VRAM);
900 if (!ret)
901 ret = nouveau_bo_map(nv_crtc->lut.nvbo);
902 if (ret)
903 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
904 }
905
906 if (ret)
907 goto out;
908
909 nvd0_crtc_lut_load(crtc);
910
911 out:
912 if (ret)
913 nvd0_crtc_destroy(crtc);
914 return ret;
915 }
916
917 /******************************************************************************
918 * DAC
919 *****************************************************************************/
920 static void
921 nvd0_dac_dpms(struct drm_encoder *encoder, int mode)
922 {
923 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
924 struct drm_device *dev = encoder->dev;
925 int or = nv_encoder->or;
926 u32 dpms_ctrl;
927
928 dpms_ctrl = 0x80000000;
929 if (mode == DRM_MODE_DPMS_STANDBY || mode == DRM_MODE_DPMS_OFF)
930 dpms_ctrl |= 0x00000001;
931 if (mode == DRM_MODE_DPMS_SUSPEND || mode == DRM_MODE_DPMS_OFF)
932 dpms_ctrl |= 0x00000004;
933
934 nv_wait(dev, 0x61a004 + (or * 0x0800), 0x80000000, 0x00000000);
935 nv_mask(dev, 0x61a004 + (or * 0x0800), 0xc000007f, dpms_ctrl);
936 nv_wait(dev, 0x61a004 + (or * 0x0800), 0x80000000, 0x00000000);
937 }
938
939 static bool
940 nvd0_dac_mode_fixup(struct drm_encoder *encoder,
941 const struct drm_display_mode *mode,
942 struct drm_display_mode *adjusted_mode)
943 {
944 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
945 struct nouveau_connector *nv_connector;
946
947 nv_connector = nouveau_encoder_connector_get(nv_encoder);
948 if (nv_connector && nv_connector->native_mode) {
949 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
950 int id = adjusted_mode->base.id;
951 *adjusted_mode = *nv_connector->native_mode;
952 adjusted_mode->base.id = id;
953 }
954 }
955
956 return true;
957 }
958
959 static void
960 nvd0_dac_commit(struct drm_encoder *encoder)
961 {
962 }
963
964 static void
965 nvd0_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
966 struct drm_display_mode *adjusted_mode)
967 {
968 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
969 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
970 u32 syncs, magic, *push;
971
972 syncs = 0x00000001;
973 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
974 syncs |= 0x00000008;
975 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
976 syncs |= 0x00000010;
977
978 magic = 0x31ec6000 | (nv_crtc->index << 25);
979 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
980 magic |= 0x00000001;
981
982 nvd0_dac_dpms(encoder, DRM_MODE_DPMS_ON);
983
984 push = evo_wait(encoder->dev, EVO_MASTER, 8);
985 if (push) {
986 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
987 evo_data(push, syncs);
988 evo_data(push, magic);
989 evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 2);
990 evo_data(push, 1 << nv_crtc->index);
991 evo_data(push, 0x00ff);
992 evo_kick(push, encoder->dev, EVO_MASTER);
993 }
994
995 nv_encoder->crtc = encoder->crtc;
996 }
997
998 static void
999 nvd0_dac_disconnect(struct drm_encoder *encoder)
1000 {
1001 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1002 struct drm_device *dev = encoder->dev;
1003 u32 *push;
1004
1005 if (nv_encoder->crtc) {
1006 nvd0_crtc_prepare(nv_encoder->crtc);
1007
1008 push = evo_wait(dev, EVO_MASTER, 4);
1009 if (push) {
1010 evo_mthd(push, 0x0180 + (nv_encoder->or * 0x20), 1);
1011 evo_data(push, 0x00000000);
1012 evo_mthd(push, 0x0080, 1);
1013 evo_data(push, 0x00000000);
1014 evo_kick(push, dev, EVO_MASTER);
1015 }
1016
1017 nv_encoder->crtc = NULL;
1018 }
1019 }
1020
1021 static enum drm_connector_status
1022 nvd0_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1023 {
1024 enum drm_connector_status status = connector_status_disconnected;
1025 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1026 struct drm_device *dev = encoder->dev;
1027 int or = nv_encoder->or;
1028 u32 load;
1029
1030 nv_wr32(dev, 0x61a00c + (or * 0x800), 0x00100000);
1031 udelay(9500);
1032 nv_wr32(dev, 0x61a00c + (or * 0x800), 0x80000000);
1033
1034 load = nv_rd32(dev, 0x61a00c + (or * 0x800));
1035 if ((load & 0x38000000) == 0x38000000)
1036 status = connector_status_connected;
1037
1038 nv_wr32(dev, 0x61a00c + (or * 0x800), 0x00000000);
1039 return status;
1040 }
1041
1042 static void
1043 nvd0_dac_destroy(struct drm_encoder *encoder)
1044 {
1045 drm_encoder_cleanup(encoder);
1046 kfree(encoder);
1047 }
1048
1049 static const struct drm_encoder_helper_funcs nvd0_dac_hfunc = {
1050 .dpms = nvd0_dac_dpms,
1051 .mode_fixup = nvd0_dac_mode_fixup,
1052 .prepare = nvd0_dac_disconnect,
1053 .commit = nvd0_dac_commit,
1054 .mode_set = nvd0_dac_mode_set,
1055 .disable = nvd0_dac_disconnect,
1056 .get_crtc = nvd0_display_crtc_get,
1057 .detect = nvd0_dac_detect
1058 };
1059
1060 static const struct drm_encoder_funcs nvd0_dac_func = {
1061 .destroy = nvd0_dac_destroy,
1062 };
1063
1064 static int
1065 nvd0_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
1066 {
1067 struct drm_device *dev = connector->dev;
1068 struct nouveau_encoder *nv_encoder;
1069 struct drm_encoder *encoder;
1070
1071 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1072 if (!nv_encoder)
1073 return -ENOMEM;
1074 nv_encoder->dcb = dcbe;
1075 nv_encoder->or = ffs(dcbe->or) - 1;
1076
1077 encoder = to_drm_encoder(nv_encoder);
1078 encoder->possible_crtcs = dcbe->heads;
1079 encoder->possible_clones = 0;
1080 drm_encoder_init(dev, encoder, &nvd0_dac_func, DRM_MODE_ENCODER_DAC);
1081 drm_encoder_helper_add(encoder, &nvd0_dac_hfunc);
1082
1083 drm_mode_connector_attach_encoder(connector, encoder);
1084 return 0;
1085 }
1086
1087 /******************************************************************************
1088 * Audio
1089 *****************************************************************************/
1090 static void
1091 nvd0_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1092 {
1093 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1094 struct nouveau_connector *nv_connector;
1095 struct drm_device *dev = encoder->dev;
1096 int i, or = nv_encoder->or * 0x30;
1097
1098 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1099 if (!drm_detect_monitor_audio(nv_connector->edid))
1100 return;
1101
1102 nv_mask(dev, 0x10ec10 + or, 0x80000003, 0x80000001);
1103
1104 drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
1105 if (nv_connector->base.eld[0]) {
1106 u8 *eld = nv_connector->base.eld;
1107
1108 for (i = 0; i < eld[2] * 4; i++)
1109 nv_wr32(dev, 0x10ec00 + or, (i << 8) | eld[i]);
1110 for (i = eld[2] * 4; i < 0x60; i++)
1111 nv_wr32(dev, 0x10ec00 + or, (i << 8) | 0x00);
1112
1113 nv_mask(dev, 0x10ec10 + or, 0x80000002, 0x80000002);
1114 }
1115 }
1116
1117 static void
1118 nvd0_audio_disconnect(struct drm_encoder *encoder)
1119 {
1120 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1121 struct drm_device *dev = encoder->dev;
1122 int or = nv_encoder->or * 0x30;
1123
1124 nv_mask(dev, 0x10ec10 + or, 0x80000003, 0x80000000);
1125 }
1126
1127 /******************************************************************************
1128 * HDMI
1129 *****************************************************************************/
1130 static void
1131 nvd0_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1132 {
1133 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1134 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1135 struct nouveau_connector *nv_connector;
1136 struct drm_device *dev = encoder->dev;
1137 int head = nv_crtc->index * 0x800;
1138 u32 rekey = 56; /* binary driver, and tegra constant */
1139 u32 max_ac_packet;
1140
1141 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1142 if (!drm_detect_hdmi_monitor(nv_connector->edid))
1143 return;
1144
1145 max_ac_packet = mode->htotal - mode->hdisplay;
1146 max_ac_packet -= rekey;
1147 max_ac_packet -= 18; /* constant from tegra */
1148 max_ac_packet /= 32;
1149
1150 /* AVI InfoFrame */
1151 nv_mask(dev, 0x616714 + head, 0x00000001, 0x00000000);
1152 nv_wr32(dev, 0x61671c + head, 0x000d0282);
1153 nv_wr32(dev, 0x616720 + head, 0x0000006f);
1154 nv_wr32(dev, 0x616724 + head, 0x00000000);
1155 nv_wr32(dev, 0x616728 + head, 0x00000000);
1156 nv_wr32(dev, 0x61672c + head, 0x00000000);
1157 nv_mask(dev, 0x616714 + head, 0x00000001, 0x00000001);
1158
1159 /* ??? InfoFrame? */
1160 nv_mask(dev, 0x6167a4 + head, 0x00000001, 0x00000000);
1161 nv_wr32(dev, 0x6167ac + head, 0x00000010);
1162 nv_mask(dev, 0x6167a4 + head, 0x00000001, 0x00000001);
1163
1164 /* HDMI_CTRL */
1165 nv_mask(dev, 0x616798 + head, 0x401f007f, 0x40000000 | rekey |
1166 max_ac_packet << 16);
1167
1168 /* NFI, audio doesn't work without it though.. */
1169 nv_mask(dev, 0x616548 + head, 0x00000070, 0x00000000);
1170
1171 nvd0_audio_mode_set(encoder, mode);
1172 }
1173
1174 static void
1175 nvd0_hdmi_disconnect(struct drm_encoder *encoder)
1176 {
1177 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1178 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1179 struct drm_device *dev = encoder->dev;
1180 int head = nv_crtc->index * 0x800;
1181
1182 nvd0_audio_disconnect(encoder);
1183
1184 nv_mask(dev, 0x616798 + head, 0x40000000, 0x00000000);
1185 nv_mask(dev, 0x6167a4 + head, 0x00000001, 0x00000000);
1186 nv_mask(dev, 0x616714 + head, 0x00000001, 0x00000000);
1187 }
1188
1189 /******************************************************************************
1190 * SOR
1191 *****************************************************************************/
1192 static inline u32
1193 nvd0_sor_dp_lane_map(struct drm_device *dev, struct dcb_output *dcb, u8 lane)
1194 {
1195 static const u8 nvd0[] = { 16, 8, 0, 24 };
1196 return nvd0[lane];
1197 }
1198
1199 static void
1200 nvd0_sor_dp_train_set(struct drm_device *dev, struct dcb_output *dcb, u8 pattern)
1201 {
1202 const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
1203 const u32 loff = (or * 0x800) + (link * 0x80);
1204 nv_mask(dev, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern);
1205 }
1206
1207 static void
1208 nvd0_sor_dp_train_adj(struct drm_device *dev, struct dcb_output *dcb,
1209 u8 lane, u8 swing, u8 preem)
1210 {
1211 const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
1212 const u32 loff = (or * 0x800) + (link * 0x80);
1213 u32 shift = nvd0_sor_dp_lane_map(dev, dcb, lane);
1214 u32 mask = 0x000000ff << shift;
1215 u8 *table, *entry, *config = NULL;
1216
1217 switch (swing) {
1218 case 0: preem += 0; break;
1219 case 1: preem += 4; break;
1220 case 2: preem += 7; break;
1221 case 3: preem += 9; break;
1222 }
1223
1224 table = nouveau_dp_bios_data(dev, dcb, &entry);
1225 if (table) {
1226 if (table[0] == 0x30) {
1227 config = entry + table[4];
1228 config += table[5] * preem;
1229 } else
1230 if (table[0] == 0x40) {
1231 config = table + table[1];
1232 config += table[2] * table[3];
1233 config += table[6] * preem;
1234 }
1235 }
1236
1237 if (!config) {
1238 NV_ERROR(dev, "PDISP: unsupported DP table for chipset\n");
1239 return;
1240 }
1241
1242 nv_mask(dev, 0x61c118 + loff, mask, config[1] << shift);
1243 nv_mask(dev, 0x61c120 + loff, mask, config[2] << shift);
1244 nv_mask(dev, 0x61c130 + loff, 0x0000ff00, config[3] << 8);
1245 nv_mask(dev, 0x61c13c + loff, 0x00000000, 0x00000000);
1246 }
1247
1248 static void
1249 nvd0_sor_dp_link_set(struct drm_device *dev, struct dcb_output *dcb, int crtc,
1250 int link_nr, u32 link_bw, bool enhframe)
1251 {
1252 const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
1253 const u32 loff = (or * 0x800) + (link * 0x80);
1254 const u32 soff = (or * 0x800);
1255 u32 dpctrl = nv_rd32(dev, 0x61c10c + loff) & ~0x001f4000;
1256 u32 clksor = nv_rd32(dev, 0x612300 + soff) & ~0x007c0000;
1257 u32 script = 0x0000, lane_mask = 0;
1258 u8 *table, *entry;
1259 int i;
1260
1261 link_bw /= 27000;
1262
1263 table = nouveau_dp_bios_data(dev, dcb, &entry);
1264 if (table) {
1265 if (table[0] == 0x30) entry = ROMPTR(dev, entry[10]);
1266 else if (table[0] == 0x40) entry = ROMPTR(dev, entry[9]);
1267 else entry = NULL;
1268
1269 while (entry) {
1270 if (entry[0] >= link_bw)
1271 break;
1272 entry += 3;
1273 }
1274
1275 nouveau_bios_run_init_table(dev, script, dcb, crtc);
1276 }
1277
1278 clksor |= link_bw << 18;
1279 dpctrl |= ((1 << link_nr) - 1) << 16;
1280 if (enhframe)
1281 dpctrl |= 0x00004000;
1282
1283 for (i = 0; i < link_nr; i++)
1284 lane_mask |= 1 << (nvd0_sor_dp_lane_map(dev, dcb, i) >> 3);
1285
1286 nv_wr32(dev, 0x612300 + soff, clksor);
1287 nv_wr32(dev, 0x61c10c + loff, dpctrl);
1288 nv_mask(dev, 0x61c130 + loff, 0x0000000f, lane_mask);
1289 }
1290
1291 static void
1292 nvd0_sor_dp_link_get(struct drm_device *dev, struct dcb_output *dcb,
1293 u32 *link_nr, u32 *link_bw)
1294 {
1295 const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
1296 const u32 loff = (or * 0x800) + (link * 0x80);
1297 const u32 soff = (or * 0x800);
1298 u32 dpctrl = nv_rd32(dev, 0x61c10c + loff) & 0x000f0000;
1299 u32 clksor = nv_rd32(dev, 0x612300 + soff);
1300
1301 if (dpctrl > 0x00030000) *link_nr = 4;
1302 else if (dpctrl > 0x00010000) *link_nr = 2;
1303 else *link_nr = 1;
1304
1305 *link_bw = (clksor & 0x007c0000) >> 18;
1306 *link_bw *= 27000;
1307 }
1308
1309 static void
1310 nvd0_sor_dp_calc_tu(struct drm_device *dev, struct dcb_output *dcb,
1311 u32 crtc, u32 datarate)
1312 {
1313 const u32 symbol = 100000;
1314 const u32 TU = 64;
1315 u32 link_nr, link_bw;
1316 u64 ratio, value;
1317
1318 nvd0_sor_dp_link_get(dev, dcb, &link_nr, &link_bw);
1319
1320 ratio = datarate;
1321 ratio *= symbol;
1322 do_div(ratio, link_nr * link_bw);
1323
1324 value = (symbol - ratio) * TU;
1325 value *= ratio;
1326 do_div(value, symbol);
1327 do_div(value, symbol);
1328
1329 value += 5;
1330 value |= 0x08000000;
1331
1332 nv_wr32(dev, 0x616610 + (crtc * 0x800), value);
1333 }
1334
1335 static void
1336 nvd0_sor_dpms(struct drm_encoder *encoder, int mode)
1337 {
1338 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1339 struct drm_device *dev = encoder->dev;
1340 struct drm_encoder *partner;
1341 int or = nv_encoder->or;
1342 u32 dpms_ctrl;
1343
1344 nv_encoder->last_dpms = mode;
1345
1346 list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
1347 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
1348
1349 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
1350 continue;
1351
1352 if (nv_partner != nv_encoder &&
1353 nv_partner->dcb->or == nv_encoder->dcb->or) {
1354 if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
1355 return;
1356 break;
1357 }
1358 }
1359
1360 dpms_ctrl = (mode == DRM_MODE_DPMS_ON);
1361 dpms_ctrl |= 0x80000000;
1362
1363 nv_wait(dev, 0x61c004 + (or * 0x0800), 0x80000000, 0x00000000);
1364 nv_mask(dev, 0x61c004 + (or * 0x0800), 0x80000001, dpms_ctrl);
1365 nv_wait(dev, 0x61c004 + (or * 0x0800), 0x80000000, 0x00000000);
1366 nv_wait(dev, 0x61c030 + (or * 0x0800), 0x10000000, 0x00000000);
1367
1368 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
1369 struct dp_train_func func = {
1370 .link_set = nvd0_sor_dp_link_set,
1371 .train_set = nvd0_sor_dp_train_set,
1372 .train_adj = nvd0_sor_dp_train_adj
1373 };
1374
1375 nouveau_dp_dpms(encoder, mode, nv_encoder->dp.datarate, &func);
1376 }
1377 }
1378
1379 static bool
1380 nvd0_sor_mode_fixup(struct drm_encoder *encoder,
1381 const struct drm_display_mode *mode,
1382 struct drm_display_mode *adjusted_mode)
1383 {
1384 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1385 struct nouveau_connector *nv_connector;
1386
1387 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1388 if (nv_connector && nv_connector->native_mode) {
1389 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1390 int id = adjusted_mode->base.id;
1391 *adjusted_mode = *nv_connector->native_mode;
1392 adjusted_mode->base.id = id;
1393 }
1394 }
1395
1396 return true;
1397 }
1398
1399 static void
1400 nvd0_sor_disconnect(struct drm_encoder *encoder)
1401 {
1402 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1403 struct drm_device *dev = encoder->dev;
1404 u32 *push;
1405
1406 if (nv_encoder->crtc) {
1407 nvd0_crtc_prepare(nv_encoder->crtc);
1408
1409 push = evo_wait(dev, EVO_MASTER, 4);
1410 if (push) {
1411 evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
1412 evo_data(push, 0x00000000);
1413 evo_mthd(push, 0x0080, 1);
1414 evo_data(push, 0x00000000);
1415 evo_kick(push, dev, EVO_MASTER);
1416 }
1417
1418 nvd0_hdmi_disconnect(encoder);
1419
1420 nv_encoder->crtc = NULL;
1421 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1422 }
1423 }
1424
1425 static void
1426 nvd0_sor_prepare(struct drm_encoder *encoder)
1427 {
1428 nvd0_sor_disconnect(encoder);
1429 if (nouveau_encoder(encoder)->dcb->type == DCB_OUTPUT_DP)
1430 evo_sync(encoder->dev, EVO_MASTER);
1431 }
1432
1433 static void
1434 nvd0_sor_commit(struct drm_encoder *encoder)
1435 {
1436 }
1437
1438 static void
1439 nvd0_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1440 struct drm_display_mode *mode)
1441 {
1442 struct drm_device *dev = encoder->dev;
1443 struct drm_nouveau_private *dev_priv = dev->dev_private;
1444 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1445 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1446 struct nouveau_connector *nv_connector;
1447 struct nvbios *bios = &dev_priv->vbios;
1448 u32 mode_ctrl = (1 << nv_crtc->index);
1449 u32 syncs, magic, *push;
1450 u32 or_config;
1451
1452 syncs = 0x00000001;
1453 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1454 syncs |= 0x00000008;
1455 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1456 syncs |= 0x00000010;
1457
1458 magic = 0x31ec6000 | (nv_crtc->index << 25);
1459 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1460 magic |= 0x00000001;
1461
1462 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1463 switch (nv_encoder->dcb->type) {
1464 case DCB_OUTPUT_TMDS:
1465 if (nv_encoder->dcb->sorconf.link & 1) {
1466 if (mode->clock < 165000)
1467 mode_ctrl |= 0x00000100;
1468 else
1469 mode_ctrl |= 0x00000500;
1470 } else {
1471 mode_ctrl |= 0x00000200;
1472 }
1473
1474 or_config = (mode_ctrl & 0x00000f00) >> 8;
1475 if (mode->clock >= 165000)
1476 or_config |= 0x0100;
1477
1478 nvd0_hdmi_mode_set(encoder, mode);
1479 break;
1480 case DCB_OUTPUT_LVDS:
1481 or_config = (mode_ctrl & 0x00000f00) >> 8;
1482 if (bios->fp_no_ddc) {
1483 if (bios->fp.dual_link)
1484 or_config |= 0x0100;
1485 if (bios->fp.if_is_24bit)
1486 or_config |= 0x0200;
1487 } else {
1488 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1489 if (((u8 *)nv_connector->edid)[121] == 2)
1490 or_config |= 0x0100;
1491 } else
1492 if (mode->clock >= bios->fp.duallink_transition_clk) {
1493 or_config |= 0x0100;
1494 }
1495
1496 if (or_config & 0x0100) {
1497 if (bios->fp.strapless_is_24bit & 2)
1498 or_config |= 0x0200;
1499 } else {
1500 if (bios->fp.strapless_is_24bit & 1)
1501 or_config |= 0x0200;
1502 }
1503
1504 if (nv_connector->base.display_info.bpc == 8)
1505 or_config |= 0x0200;
1506
1507 }
1508 break;
1509 case DCB_OUTPUT_DP:
1510 if (nv_connector->base.display_info.bpc == 6) {
1511 nv_encoder->dp.datarate = mode->clock * 18 / 8;
1512 syncs |= 0x00000002 << 6;
1513 } else {
1514 nv_encoder->dp.datarate = mode->clock * 24 / 8;
1515 syncs |= 0x00000005 << 6;
1516 }
1517
1518 if (nv_encoder->dcb->sorconf.link & 1)
1519 mode_ctrl |= 0x00000800;
1520 else
1521 mode_ctrl |= 0x00000900;
1522
1523 or_config = (mode_ctrl & 0x00000f00) >> 8;
1524 break;
1525 default:
1526 BUG_ON(1);
1527 break;
1528 }
1529
1530 nvd0_sor_dpms(encoder, DRM_MODE_DPMS_ON);
1531
1532 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
1533 nvd0_sor_dp_calc_tu(dev, nv_encoder->dcb, nv_crtc->index,
1534 nv_encoder->dp.datarate);
1535 }
1536
1537 push = evo_wait(dev, EVO_MASTER, 8);
1538 if (push) {
1539 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1540 evo_data(push, syncs);
1541 evo_data(push, magic);
1542 evo_mthd(push, 0x0200 + (nv_encoder->or * 0x020), 2);
1543 evo_data(push, mode_ctrl);
1544 evo_data(push, or_config);
1545 evo_kick(push, dev, EVO_MASTER);
1546 }
1547
1548 nv_encoder->crtc = encoder->crtc;
1549 }
1550
1551 static void
1552 nvd0_sor_destroy(struct drm_encoder *encoder)
1553 {
1554 drm_encoder_cleanup(encoder);
1555 kfree(encoder);
1556 }
1557
1558 static const struct drm_encoder_helper_funcs nvd0_sor_hfunc = {
1559 .dpms = nvd0_sor_dpms,
1560 .mode_fixup = nvd0_sor_mode_fixup,
1561 .prepare = nvd0_sor_prepare,
1562 .commit = nvd0_sor_commit,
1563 .mode_set = nvd0_sor_mode_set,
1564 .disable = nvd0_sor_disconnect,
1565 .get_crtc = nvd0_display_crtc_get,
1566 };
1567
1568 static const struct drm_encoder_funcs nvd0_sor_func = {
1569 .destroy = nvd0_sor_destroy,
1570 };
1571
1572 static int
1573 nvd0_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1574 {
1575 struct drm_device *dev = connector->dev;
1576 struct nouveau_encoder *nv_encoder;
1577 struct drm_encoder *encoder;
1578
1579 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1580 if (!nv_encoder)
1581 return -ENOMEM;
1582 nv_encoder->dcb = dcbe;
1583 nv_encoder->or = ffs(dcbe->or) - 1;
1584 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1585
1586 encoder = to_drm_encoder(nv_encoder);
1587 encoder->possible_crtcs = dcbe->heads;
1588 encoder->possible_clones = 0;
1589 drm_encoder_init(dev, encoder, &nvd0_sor_func, DRM_MODE_ENCODER_TMDS);
1590 drm_encoder_helper_add(encoder, &nvd0_sor_hfunc);
1591
1592 drm_mode_connector_attach_encoder(connector, encoder);
1593 return 0;
1594 }
1595
1596 /******************************************************************************
1597 * IRQ
1598 *****************************************************************************/
1599 static struct dcb_output *
1600 lookup_dcb(struct drm_device *dev, int id, u32 mc)
1601 {
1602 struct drm_nouveau_private *dev_priv = dev->dev_private;
1603 int type, or, i, link = -1;
1604
1605 if (id < 4) {
1606 type = DCB_OUTPUT_ANALOG;
1607 or = id;
1608 } else {
1609 switch (mc & 0x00000f00) {
1610 case 0x00000000: link = 0; type = DCB_OUTPUT_LVDS; break;
1611 case 0x00000100: link = 0; type = DCB_OUTPUT_TMDS; break;
1612 case 0x00000200: link = 1; type = DCB_OUTPUT_TMDS; break;
1613 case 0x00000500: link = 0; type = DCB_OUTPUT_TMDS; break;
1614 case 0x00000800: link = 0; type = DCB_OUTPUT_DP; break;
1615 case 0x00000900: link = 1; type = DCB_OUTPUT_DP; break;
1616 default:
1617 NV_ERROR(dev, "PDISP: unknown SOR mc 0x%08x\n", mc);
1618 return NULL;
1619 }
1620
1621 or = id - 4;
1622 }
1623
1624 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
1625 struct dcb_output *dcb = &dev_priv->vbios.dcb.entry[i];
1626 if (dcb->type == type && (dcb->or & (1 << or)) &&
1627 (link < 0 || link == !(dcb->sorconf.link & 1)))
1628 return dcb;
1629 }
1630
1631 NV_ERROR(dev, "PDISP: DCB for %d/0x%08x not found\n", id, mc);
1632 return NULL;
1633 }
1634
1635 static void
1636 nvd0_display_unk1_handler(struct drm_device *dev, u32 crtc, u32 mask)
1637 {
1638 struct dcb_output *dcb;
1639 int i;
1640
1641 for (i = 0; mask && i < 8; i++) {
1642 u32 mcc = nv_rd32(dev, 0x640180 + (i * 0x20));
1643 if (!(mcc & (1 << crtc)))
1644 continue;
1645
1646 dcb = lookup_dcb(dev, i, mcc);
1647 if (!dcb)
1648 continue;
1649
1650 nouveau_bios_run_display_table(dev, 0x0000, -1, dcb, crtc);
1651 }
1652
1653 nv_wr32(dev, 0x6101d4, 0x00000000);
1654 nv_wr32(dev, 0x6109d4, 0x00000000);
1655 nv_wr32(dev, 0x6101d0, 0x80000000);
1656 }
1657
1658 static void
1659 nvd0_display_unk2_handler(struct drm_device *dev, u32 crtc, u32 mask)
1660 {
1661 struct dcb_output *dcb;
1662 u32 or, tmp, pclk;
1663 int i;
1664
1665 for (i = 0; mask && i < 8; i++) {
1666 u32 mcc = nv_rd32(dev, 0x640180 + (i * 0x20));
1667 if (!(mcc & (1 << crtc)))
1668 continue;
1669
1670 dcb = lookup_dcb(dev, i, mcc);
1671 if (!dcb)
1672 continue;
1673
1674 nouveau_bios_run_display_table(dev, 0x0000, -2, dcb, crtc);
1675 }
1676
1677 pclk = nv_rd32(dev, 0x660450 + (crtc * 0x300)) / 1000;
1678 NV_DEBUG_KMS(dev, "PDISP: crtc %d pclk %d mask 0x%08x\n",
1679 crtc, pclk, mask);
1680 if (pclk && (mask & 0x00010000)) {
1681 nv50_crtc_set_clock(dev, crtc, pclk);
1682 }
1683
1684 for (i = 0; mask && i < 8; i++) {
1685 u32 mcp = nv_rd32(dev, 0x660180 + (i * 0x20));
1686 u32 cfg = nv_rd32(dev, 0x660184 + (i * 0x20));
1687 if (!(mcp & (1 << crtc)))
1688 continue;
1689
1690 dcb = lookup_dcb(dev, i, mcp);
1691 if (!dcb)
1692 continue;
1693 or = ffs(dcb->or) - 1;
1694
1695 nouveau_bios_run_display_table(dev, cfg, pclk, dcb, crtc);
1696
1697 nv_wr32(dev, 0x612200 + (crtc * 0x800), 0x00000000);
1698 switch (dcb->type) {
1699 case DCB_OUTPUT_ANALOG:
1700 nv_wr32(dev, 0x612280 + (or * 0x800), 0x00000000);
1701 break;
1702 case DCB_OUTPUT_TMDS:
1703 case DCB_OUTPUT_LVDS:
1704 case DCB_OUTPUT_DP:
1705 if (cfg & 0x00000100)
1706 tmp = 0x00000101;
1707 else
1708 tmp = 0x00000000;
1709
1710 nv_mask(dev, 0x612300 + (or * 0x800), 0x00000707, tmp);
1711 break;
1712 default:
1713 break;
1714 }
1715
1716 break;
1717 }
1718
1719 nv_wr32(dev, 0x6101d4, 0x00000000);
1720 nv_wr32(dev, 0x6109d4, 0x00000000);
1721 nv_wr32(dev, 0x6101d0, 0x80000000);
1722 }
1723
1724 static void
1725 nvd0_display_unk4_handler(struct drm_device *dev, u32 crtc, u32 mask)
1726 {
1727 struct dcb_output *dcb;
1728 int pclk, i;
1729
1730 pclk = nv_rd32(dev, 0x660450 + (crtc * 0x300)) / 1000;
1731
1732 for (i = 0; mask && i < 8; i++) {
1733 u32 mcp = nv_rd32(dev, 0x660180 + (i * 0x20));
1734 u32 cfg = nv_rd32(dev, 0x660184 + (i * 0x20));
1735 if (!(mcp & (1 << crtc)))
1736 continue;
1737
1738 dcb = lookup_dcb(dev, i, mcp);
1739 if (!dcb)
1740 continue;
1741
1742 nouveau_bios_run_display_table(dev, cfg, -pclk, dcb, crtc);
1743 }
1744
1745 nv_wr32(dev, 0x6101d4, 0x00000000);
1746 nv_wr32(dev, 0x6109d4, 0x00000000);
1747 nv_wr32(dev, 0x6101d0, 0x80000000);
1748 }
1749
1750 static void
1751 nvd0_display_bh(unsigned long data)
1752 {
1753 struct drm_device *dev = (struct drm_device *)data;
1754 struct nvd0_display *disp = nvd0_display(dev);
1755 u32 mask = 0, crtc = ~0;
1756 int i;
1757
1758 if (drm_debug & (DRM_UT_DRIVER | DRM_UT_KMS)) {
1759 NV_INFO(dev, "PDISP: modeset req %d\n", disp->modeset);
1760 NV_INFO(dev, " STAT: 0x%08x 0x%08x 0x%08x\n",
1761 nv_rd32(dev, 0x6101d0),
1762 nv_rd32(dev, 0x6101d4), nv_rd32(dev, 0x6109d4));
1763 for (i = 0; i < 8; i++) {
1764 NV_INFO(dev, " %s%d: 0x%08x 0x%08x\n",
1765 i < 4 ? "DAC" : "SOR", i,
1766 nv_rd32(dev, 0x640180 + (i * 0x20)),
1767 nv_rd32(dev, 0x660180 + (i * 0x20)));
1768 }
1769 }
1770
1771 while (!mask && ++crtc < dev->mode_config.num_crtc)
1772 mask = nv_rd32(dev, 0x6101d4 + (crtc * 0x800));
1773
1774 if (disp->modeset & 0x00000001)
1775 nvd0_display_unk1_handler(dev, crtc, mask);
1776 if (disp->modeset & 0x00000002)
1777 nvd0_display_unk2_handler(dev, crtc, mask);
1778 if (disp->modeset & 0x00000004)
1779 nvd0_display_unk4_handler(dev, crtc, mask);
1780 }
1781
1782 static void
1783 nvd0_display_intr(struct drm_device *dev)
1784 {
1785 struct nvd0_display *disp = nvd0_display(dev);
1786 u32 intr = nv_rd32(dev, 0x610088);
1787 int i;
1788
1789 if (intr & 0x00000001) {
1790 u32 stat = nv_rd32(dev, 0x61008c);
1791 nv_wr32(dev, 0x61008c, stat);
1792 intr &= ~0x00000001;
1793 }
1794
1795 if (intr & 0x00000002) {
1796 u32 stat = nv_rd32(dev, 0x61009c);
1797 int chid = ffs(stat) - 1;
1798 if (chid >= 0) {
1799 u32 mthd = nv_rd32(dev, 0x6101f0 + (chid * 12));
1800 u32 data = nv_rd32(dev, 0x6101f4 + (chid * 12));
1801 u32 unkn = nv_rd32(dev, 0x6101f8 + (chid * 12));
1802
1803 NV_INFO(dev, "EvoCh: chid %d mthd 0x%04x data 0x%08x "
1804 "0x%08x 0x%08x\n",
1805 chid, (mthd & 0x0000ffc), data, mthd, unkn);
1806 nv_wr32(dev, 0x61009c, (1 << chid));
1807 nv_wr32(dev, 0x6101f0 + (chid * 12), 0x90000000);
1808 }
1809
1810 intr &= ~0x00000002;
1811 }
1812
1813 if (intr & 0x00100000) {
1814 u32 stat = nv_rd32(dev, 0x6100ac);
1815
1816 if (stat & 0x00000007) {
1817 disp->modeset = stat;
1818 tasklet_schedule(&disp->tasklet);
1819
1820 nv_wr32(dev, 0x6100ac, (stat & 0x00000007));
1821 stat &= ~0x00000007;
1822 }
1823
1824 if (stat) {
1825 NV_INFO(dev, "PDISP: unknown intr24 0x%08x\n", stat);
1826 nv_wr32(dev, 0x6100ac, stat);
1827 }
1828
1829 intr &= ~0x00100000;
1830 }
1831
1832 intr &= ~0x0f000000; /* vblank, handled in core */
1833 if (intr)
1834 NV_INFO(dev, "PDISP: unknown intr 0x%08x\n", intr);
1835 }
1836
1837 /******************************************************************************
1838 * Init
1839 *****************************************************************************/
1840 void
1841 nvd0_display_fini(struct drm_device *dev)
1842 {
1843 int i;
1844
1845 /* fini cursors + overlays + flips */
1846 for (i = 1; i >= 0; i--) {
1847 evo_fini_pio(dev, EVO_CURS(i));
1848 evo_fini_pio(dev, EVO_OIMM(i));
1849 evo_fini_dma(dev, EVO_OVLY(i));
1850 evo_fini_dma(dev, EVO_FLIP(i));
1851 }
1852
1853 /* fini master */
1854 evo_fini_dma(dev, EVO_MASTER);
1855 }
1856
1857 int
1858 nvd0_display_init(struct drm_device *dev)
1859 {
1860 struct nvd0_display *disp = nvd0_display(dev);
1861 int ret, i;
1862 u32 *push;
1863
1864 if (nv_rd32(dev, 0x6100ac) & 0x00000100) {
1865 nv_wr32(dev, 0x6100ac, 0x00000100);
1866 nv_mask(dev, 0x6194e8, 0x00000001, 0x00000000);
1867 if (!nv_wait(dev, 0x6194e8, 0x00000002, 0x00000000)) {
1868 NV_ERROR(dev, "PDISP: 0x6194e8 0x%08x\n",
1869 nv_rd32(dev, 0x6194e8));
1870 return -EBUSY;
1871 }
1872 }
1873
1874 /* nfi what these are exactly, i do know that SOR_MODE_CTRL won't
1875 * work at all unless you do the SOR part below.
1876 */
1877 for (i = 0; i < 3; i++) {
1878 u32 dac = nv_rd32(dev, 0x61a000 + (i * 0x800));
1879 nv_wr32(dev, 0x6101c0 + (i * 0x800), dac);
1880 }
1881
1882 for (i = 0; i < 4; i++) {
1883 u32 sor = nv_rd32(dev, 0x61c000 + (i * 0x800));
1884 nv_wr32(dev, 0x6301c4 + (i * 0x800), sor);
1885 }
1886
1887 for (i = 0; i < dev->mode_config.num_crtc; i++) {
1888 u32 crtc0 = nv_rd32(dev, 0x616104 + (i * 0x800));
1889 u32 crtc1 = nv_rd32(dev, 0x616108 + (i * 0x800));
1890 u32 crtc2 = nv_rd32(dev, 0x61610c + (i * 0x800));
1891 nv_wr32(dev, 0x6101b4 + (i * 0x800), crtc0);
1892 nv_wr32(dev, 0x6101b8 + (i * 0x800), crtc1);
1893 nv_wr32(dev, 0x6101bc + (i * 0x800), crtc2);
1894 }
1895
1896 /* point at our hash table / objects, enable interrupts */
1897 nv_wr32(dev, 0x610010, (disp->mem->addr >> 8) | 9);
1898 nv_mask(dev, 0x6100b0, 0x00000307, 0x00000307);
1899
1900 /* init master */
1901 ret = evo_init_dma(dev, EVO_MASTER);
1902 if (ret)
1903 goto error;
1904
1905 /* init flips + overlays + cursors */
1906 for (i = 0; i < dev->mode_config.num_crtc; i++) {
1907 if ((ret = evo_init_dma(dev, EVO_FLIP(i))) ||
1908 (ret = evo_init_dma(dev, EVO_OVLY(i))) ||
1909 (ret = evo_init_pio(dev, EVO_OIMM(i))) ||
1910 (ret = evo_init_pio(dev, EVO_CURS(i))))
1911 goto error;
1912 }
1913
1914 push = evo_wait(dev, EVO_MASTER, 32);
1915 if (!push) {
1916 ret = -EBUSY;
1917 goto error;
1918 }
1919 evo_mthd(push, 0x0088, 1);
1920 evo_data(push, NvEvoSync);
1921 evo_mthd(push, 0x0084, 1);
1922 evo_data(push, 0x00000000);
1923 evo_mthd(push, 0x0084, 1);
1924 evo_data(push, 0x80000000);
1925 evo_mthd(push, 0x008c, 1);
1926 evo_data(push, 0x00000000);
1927 evo_kick(push, dev, EVO_MASTER);
1928
1929 error:
1930 if (ret)
1931 nvd0_display_fini(dev);
1932 return ret;
1933 }
1934
1935 void
1936 nvd0_display_destroy(struct drm_device *dev)
1937 {
1938 struct drm_nouveau_private *dev_priv = dev->dev_private;
1939 struct nvd0_display *disp = nvd0_display(dev);
1940 struct pci_dev *pdev = dev->pdev;
1941 int i;
1942
1943 for (i = 0; i < EVO_DMA_NR; i++) {
1944 struct evo *evo = &disp->evo[i];
1945 pci_free_consistent(pdev, PAGE_SIZE, evo->ptr, evo->handle);
1946 }
1947
1948 nouveau_gpuobj_ref(NULL, &disp->mem);
1949 nouveau_bo_unmap(disp->sync);
1950 nouveau_bo_ref(NULL, &disp->sync);
1951 nouveau_irq_unregister(dev, 26);
1952
1953 dev_priv->engine.display.priv = NULL;
1954 kfree(disp);
1955 }
1956
1957 int
1958 nvd0_display_create(struct drm_device *dev)
1959 {
1960 struct drm_nouveau_private *dev_priv = dev->dev_private;
1961 struct dcb_table *dcb = &dev_priv->vbios.dcb;
1962 struct drm_connector *connector, *tmp;
1963 struct pci_dev *pdev = dev->pdev;
1964 struct nvd0_display *disp;
1965 struct dcb_output *dcbe;
1966 int crtcs, ret, i;
1967
1968 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
1969 if (!disp)
1970 return -ENOMEM;
1971 dev_priv->engine.display.priv = disp;
1972
1973 /* create crtc objects to represent the hw heads */
1974 crtcs = nv_rd32(dev, 0x022448);
1975 for (i = 0; i < crtcs; i++) {
1976 ret = nvd0_crtc_create(dev, i);
1977 if (ret)
1978 goto out;
1979 }
1980
1981 /* create encoder/connector objects based on VBIOS DCB table */
1982 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
1983 connector = nouveau_connector_create(dev, dcbe->connector);
1984 if (IS_ERR(connector))
1985 continue;
1986
1987 if (dcbe->location != DCB_LOC_ON_CHIP) {
1988 NV_WARN(dev, "skipping off-chip encoder %d/%d\n",
1989 dcbe->type, ffs(dcbe->or) - 1);
1990 continue;
1991 }
1992
1993 switch (dcbe->type) {
1994 case DCB_OUTPUT_TMDS:
1995 case DCB_OUTPUT_LVDS:
1996 case DCB_OUTPUT_DP:
1997 nvd0_sor_create(connector, dcbe);
1998 break;
1999 case DCB_OUTPUT_ANALOG:
2000 nvd0_dac_create(connector, dcbe);
2001 break;
2002 default:
2003 NV_WARN(dev, "skipping unsupported encoder %d/%d\n",
2004 dcbe->type, ffs(dcbe->or) - 1);
2005 continue;
2006 }
2007 }
2008
2009 /* cull any connectors we created that don't have an encoder */
2010 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2011 if (connector->encoder_ids[0])
2012 continue;
2013
2014 NV_WARN(dev, "%s has no encoders, removing\n",
2015 drm_get_connector_name(connector));
2016 connector->funcs->destroy(connector);
2017 }
2018
2019 /* setup interrupt handling */
2020 tasklet_init(&disp->tasklet, nvd0_display_bh, (unsigned long)dev);
2021 nouveau_irq_register(dev, 26, nvd0_display_intr);
2022
2023 /* small shared memory area we use for notifiers and semaphores */
2024 ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2025 0, 0x0000, NULL, &disp->sync);
2026 if (!ret) {
2027 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM);
2028 if (!ret)
2029 ret = nouveau_bo_map(disp->sync);
2030 if (ret)
2031 nouveau_bo_ref(NULL, &disp->sync);
2032 }
2033
2034 if (ret)
2035 goto out;
2036
2037 /* hash table and dma objects for the memory areas we care about */
2038 ret = nouveau_gpuobj_new(dev, NULL, 0x4000, 0x10000,
2039 NVOBJ_FLAG_ZERO_ALLOC, &disp->mem);
2040 if (ret)
2041 goto out;
2042
2043 /* create evo dma channels */
2044 for (i = 0; i < EVO_DMA_NR; i++) {
2045 struct evo *evo = &disp->evo[i];
2046 u64 offset = disp->sync->bo.offset;
2047 u32 dmao = 0x1000 + (i * 0x100);
2048 u32 hash = 0x0000 + (i * 0x040);
2049
2050 evo->idx = i;
2051 evo->sem.offset = EVO_SYNC(evo->idx, 0x00);
2052 evo->ptr = pci_alloc_consistent(pdev, PAGE_SIZE, &evo->handle);
2053 if (!evo->ptr) {
2054 ret = -ENOMEM;
2055 goto out;
2056 }
2057
2058 nv_wo32(disp->mem, dmao + 0x00, 0x00000049);
2059 nv_wo32(disp->mem, dmao + 0x04, (offset + 0x0000) >> 8);
2060 nv_wo32(disp->mem, dmao + 0x08, (offset + 0x0fff) >> 8);
2061 nv_wo32(disp->mem, dmao + 0x0c, 0x00000000);
2062 nv_wo32(disp->mem, dmao + 0x10, 0x00000000);
2063 nv_wo32(disp->mem, dmao + 0x14, 0x00000000);
2064 nv_wo32(disp->mem, hash + 0x00, NvEvoSync);
2065 nv_wo32(disp->mem, hash + 0x04, 0x00000001 | (i << 27) |
2066 ((dmao + 0x00) << 9));
2067
2068 nv_wo32(disp->mem, dmao + 0x20, 0x00000049);
2069 nv_wo32(disp->mem, dmao + 0x24, 0x00000000);
2070 nv_wo32(disp->mem, dmao + 0x28, (nvfb_vram_size(dev) - 1) >> 8);
2071 nv_wo32(disp->mem, dmao + 0x2c, 0x00000000);
2072 nv_wo32(disp->mem, dmao + 0x30, 0x00000000);
2073 nv_wo32(disp->mem, dmao + 0x34, 0x00000000);
2074 nv_wo32(disp->mem, hash + 0x08, NvEvoVRAM);
2075 nv_wo32(disp->mem, hash + 0x0c, 0x00000001 | (i << 27) |
2076 ((dmao + 0x20) << 9));
2077
2078 nv_wo32(disp->mem, dmao + 0x40, 0x00000009);
2079 nv_wo32(disp->mem, dmao + 0x44, 0x00000000);
2080 nv_wo32(disp->mem, dmao + 0x48, (nvfb_vram_size(dev) - 1) >> 8);
2081 nv_wo32(disp->mem, dmao + 0x4c, 0x00000000);
2082 nv_wo32(disp->mem, dmao + 0x50, 0x00000000);
2083 nv_wo32(disp->mem, dmao + 0x54, 0x00000000);
2084 nv_wo32(disp->mem, hash + 0x10, NvEvoVRAM_LP);
2085 nv_wo32(disp->mem, hash + 0x14, 0x00000001 | (i << 27) |
2086 ((dmao + 0x40) << 9));
2087
2088 nv_wo32(disp->mem, dmao + 0x60, 0x0fe00009);
2089 nv_wo32(disp->mem, dmao + 0x64, 0x00000000);
2090 nv_wo32(disp->mem, dmao + 0x68, (nvfb_vram_size(dev) - 1) >> 8);
2091 nv_wo32(disp->mem, dmao + 0x6c, 0x00000000);
2092 nv_wo32(disp->mem, dmao + 0x70, 0x00000000);
2093 nv_wo32(disp->mem, dmao + 0x74, 0x00000000);
2094 nv_wo32(disp->mem, hash + 0x18, NvEvoFB32);
2095 nv_wo32(disp->mem, hash + 0x1c, 0x00000001 | (i << 27) |
2096 ((dmao + 0x60) << 9));
2097 }
2098
2099 nvimem_flush(dev);
2100
2101 out:
2102 if (ret)
2103 nvd0_display_destroy(dev);
2104 return ret;
2105 }
Linux kernel - Deliverables
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