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drm/nouveau/xtensa: convert to new-style nvkm_engine
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / engine / device / base.c
1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "priv.h"
25 #include "acpi.h"
26
27 #include <core/notify.h>
28 #include <core/option.h>
29
30 #include <subdev/bios.h>
31
32 static DEFINE_MUTEX(nv_devices_mutex);
33 static LIST_HEAD(nv_devices);
34
35 static struct nvkm_device *
36 nvkm_device_find_locked(u64 handle)
37 {
38 struct nvkm_device *device;
39 list_for_each_entry(device, &nv_devices, head) {
40 if (device->handle == handle)
41 return device;
42 }
43 return NULL;
44 }
45
46 struct nvkm_device *
47 nvkm_device_find(u64 handle)
48 {
49 struct nvkm_device *device;
50 mutex_lock(&nv_devices_mutex);
51 device = nvkm_device_find_locked(handle);
52 mutex_unlock(&nv_devices_mutex);
53 return device;
54 }
55
56 int
57 nvkm_device_list(u64 *name, int size)
58 {
59 struct nvkm_device *device;
60 int nr = 0;
61 mutex_lock(&nv_devices_mutex);
62 list_for_each_entry(device, &nv_devices, head) {
63 if (nr++ < size)
64 name[nr - 1] = device->handle;
65 }
66 mutex_unlock(&nv_devices_mutex);
67 return nr;
68 }
69
70 static const struct nvkm_device_chip
71 null_chipset = {
72 .name = "NULL",
73 .bios = nvkm_bios_new,
74 };
75
76 static const struct nvkm_device_chip
77 nv4_chipset = {
78 .name = "NV04",
79 .bios = nvkm_bios_new,
80 .bus = nv04_bus_new,
81 .clk = nv04_clk_new,
82 .devinit = nv04_devinit_new,
83 .fb = nv04_fb_new,
84 .i2c = nv04_i2c_new,
85 .imem = nv04_instmem_new,
86 .mc = nv04_mc_new,
87 .mmu = nv04_mmu_new,
88 .timer = nv04_timer_new,
89 // .disp = nv04_disp_new,
90 // .dma = nv04_dma_new,
91 // .fifo = nv04_fifo_new,
92 // .gr = nv04_gr_new,
93 // .sw = nv04_sw_new,
94 };
95
96 static const struct nvkm_device_chip
97 nv5_chipset = {
98 .name = "NV05",
99 .bios = nvkm_bios_new,
100 .bus = nv04_bus_new,
101 .clk = nv04_clk_new,
102 .devinit = nv05_devinit_new,
103 .fb = nv04_fb_new,
104 .i2c = nv04_i2c_new,
105 .imem = nv04_instmem_new,
106 .mc = nv04_mc_new,
107 .mmu = nv04_mmu_new,
108 .timer = nv04_timer_new,
109 // .disp = nv04_disp_new,
110 // .dma = nv04_dma_new,
111 // .fifo = nv04_fifo_new,
112 // .gr = nv04_gr_new,
113 // .sw = nv04_sw_new,
114 };
115
116 static const struct nvkm_device_chip
117 nv10_chipset = {
118 .name = "NV10",
119 .bios = nvkm_bios_new,
120 .bus = nv04_bus_new,
121 .clk = nv04_clk_new,
122 .devinit = nv10_devinit_new,
123 .fb = nv10_fb_new,
124 .gpio = nv10_gpio_new,
125 .i2c = nv04_i2c_new,
126 .imem = nv04_instmem_new,
127 .mc = nv04_mc_new,
128 .mmu = nv04_mmu_new,
129 .timer = nv04_timer_new,
130 // .disp = nv04_disp_new,
131 // .dma = nv04_dma_new,
132 // .gr = nv10_gr_new,
133 };
134
135 static const struct nvkm_device_chip
136 nv11_chipset = {
137 .name = "NV11",
138 .bios = nvkm_bios_new,
139 .bus = nv04_bus_new,
140 .clk = nv04_clk_new,
141 .devinit = nv10_devinit_new,
142 .fb = nv10_fb_new,
143 .gpio = nv10_gpio_new,
144 .i2c = nv04_i2c_new,
145 .imem = nv04_instmem_new,
146 .mc = nv04_mc_new,
147 .mmu = nv04_mmu_new,
148 .timer = nv04_timer_new,
149 // .disp = nv04_disp_new,
150 // .dma = nv04_dma_new,
151 // .fifo = nv10_fifo_new,
152 // .gr = nv10_gr_new,
153 // .sw = nv10_sw_new,
154 };
155
156 static const struct nvkm_device_chip
157 nv15_chipset = {
158 .name = "NV15",
159 .bios = nvkm_bios_new,
160 .bus = nv04_bus_new,
161 .clk = nv04_clk_new,
162 .devinit = nv10_devinit_new,
163 .fb = nv10_fb_new,
164 .gpio = nv10_gpio_new,
165 .i2c = nv04_i2c_new,
166 .imem = nv04_instmem_new,
167 .mc = nv04_mc_new,
168 .mmu = nv04_mmu_new,
169 .timer = nv04_timer_new,
170 // .disp = nv04_disp_new,
171 // .dma = nv04_dma_new,
172 // .fifo = nv10_fifo_new,
173 // .gr = nv10_gr_new,
174 // .sw = nv10_sw_new,
175 };
176
177 static const struct nvkm_device_chip
178 nv17_chipset = {
179 .name = "NV17",
180 .bios = nvkm_bios_new,
181 .bus = nv04_bus_new,
182 .clk = nv04_clk_new,
183 .devinit = nv10_devinit_new,
184 .fb = nv10_fb_new,
185 .gpio = nv10_gpio_new,
186 .i2c = nv04_i2c_new,
187 .imem = nv04_instmem_new,
188 .mc = nv04_mc_new,
189 .mmu = nv04_mmu_new,
190 .timer = nv04_timer_new,
191 // .disp = nv04_disp_new,
192 // .dma = nv04_dma_new,
193 // .fifo = nv17_fifo_new,
194 // .gr = nv10_gr_new,
195 // .sw = nv10_sw_new,
196 };
197
198 static const struct nvkm_device_chip
199 nv18_chipset = {
200 .name = "NV18",
201 .bios = nvkm_bios_new,
202 .bus = nv04_bus_new,
203 .clk = nv04_clk_new,
204 .devinit = nv10_devinit_new,
205 .fb = nv10_fb_new,
206 .gpio = nv10_gpio_new,
207 .i2c = nv04_i2c_new,
208 .imem = nv04_instmem_new,
209 .mc = nv04_mc_new,
210 .mmu = nv04_mmu_new,
211 .timer = nv04_timer_new,
212 // .disp = nv04_disp_new,
213 // .dma = nv04_dma_new,
214 // .fifo = nv17_fifo_new,
215 // .gr = nv10_gr_new,
216 // .sw = nv10_sw_new,
217 };
218
219 static const struct nvkm_device_chip
220 nv1a_chipset = {
221 .name = "nForce",
222 .bios = nvkm_bios_new,
223 .bus = nv04_bus_new,
224 .clk = nv04_clk_new,
225 .devinit = nv1a_devinit_new,
226 .fb = nv1a_fb_new,
227 .gpio = nv10_gpio_new,
228 .i2c = nv04_i2c_new,
229 .imem = nv04_instmem_new,
230 .mc = nv04_mc_new,
231 .mmu = nv04_mmu_new,
232 .timer = nv04_timer_new,
233 // .disp = nv04_disp_new,
234 // .dma = nv04_dma_new,
235 // .fifo = nv10_fifo_new,
236 // .gr = nv10_gr_new,
237 // .sw = nv10_sw_new,
238 };
239
240 static const struct nvkm_device_chip
241 nv1f_chipset = {
242 .name = "nForce2",
243 .bios = nvkm_bios_new,
244 .bus = nv04_bus_new,
245 .clk = nv04_clk_new,
246 .devinit = nv1a_devinit_new,
247 .fb = nv1a_fb_new,
248 .gpio = nv10_gpio_new,
249 .i2c = nv04_i2c_new,
250 .imem = nv04_instmem_new,
251 .mc = nv04_mc_new,
252 .mmu = nv04_mmu_new,
253 .timer = nv04_timer_new,
254 // .disp = nv04_disp_new,
255 // .dma = nv04_dma_new,
256 // .fifo = nv17_fifo_new,
257 // .gr = nv10_gr_new,
258 // .sw = nv10_sw_new,
259 };
260
261 static const struct nvkm_device_chip
262 nv20_chipset = {
263 .name = "NV20",
264 .bios = nvkm_bios_new,
265 .bus = nv04_bus_new,
266 .clk = nv04_clk_new,
267 .devinit = nv20_devinit_new,
268 .fb = nv20_fb_new,
269 .gpio = nv10_gpio_new,
270 .i2c = nv04_i2c_new,
271 .imem = nv04_instmem_new,
272 .mc = nv04_mc_new,
273 .mmu = nv04_mmu_new,
274 .timer = nv04_timer_new,
275 // .disp = nv04_disp_new,
276 // .dma = nv04_dma_new,
277 // .fifo = nv17_fifo_new,
278 // .gr = nv20_gr_new,
279 // .sw = nv10_sw_new,
280 };
281
282 static const struct nvkm_device_chip
283 nv25_chipset = {
284 .name = "NV25",
285 .bios = nvkm_bios_new,
286 .bus = nv04_bus_new,
287 .clk = nv04_clk_new,
288 .devinit = nv20_devinit_new,
289 .fb = nv25_fb_new,
290 .gpio = nv10_gpio_new,
291 .i2c = nv04_i2c_new,
292 .imem = nv04_instmem_new,
293 .mc = nv04_mc_new,
294 .mmu = nv04_mmu_new,
295 .timer = nv04_timer_new,
296 // .disp = nv04_disp_new,
297 // .dma = nv04_dma_new,
298 // .fifo = nv17_fifo_new,
299 // .gr = nv25_gr_new,
300 // .sw = nv10_sw_new,
301 };
302
303 static const struct nvkm_device_chip
304 nv28_chipset = {
305 .name = "NV28",
306 .bios = nvkm_bios_new,
307 .bus = nv04_bus_new,
308 .clk = nv04_clk_new,
309 .devinit = nv20_devinit_new,
310 .fb = nv25_fb_new,
311 .gpio = nv10_gpio_new,
312 .i2c = nv04_i2c_new,
313 .imem = nv04_instmem_new,
314 .mc = nv04_mc_new,
315 .mmu = nv04_mmu_new,
316 .timer = nv04_timer_new,
317 // .disp = nv04_disp_new,
318 // .dma = nv04_dma_new,
319 // .fifo = nv17_fifo_new,
320 // .gr = nv25_gr_new,
321 // .sw = nv10_sw_new,
322 };
323
324 static const struct nvkm_device_chip
325 nv2a_chipset = {
326 .name = "NV2A",
327 .bios = nvkm_bios_new,
328 .bus = nv04_bus_new,
329 .clk = nv04_clk_new,
330 .devinit = nv20_devinit_new,
331 .fb = nv25_fb_new,
332 .gpio = nv10_gpio_new,
333 .i2c = nv04_i2c_new,
334 .imem = nv04_instmem_new,
335 .mc = nv04_mc_new,
336 .mmu = nv04_mmu_new,
337 .timer = nv04_timer_new,
338 // .disp = nv04_disp_new,
339 // .dma = nv04_dma_new,
340 // .fifo = nv17_fifo_new,
341 // .gr = nv2a_gr_new,
342 // .sw = nv10_sw_new,
343 };
344
345 static const struct nvkm_device_chip
346 nv30_chipset = {
347 .name = "NV30",
348 .bios = nvkm_bios_new,
349 .bus = nv04_bus_new,
350 .clk = nv04_clk_new,
351 .devinit = nv20_devinit_new,
352 .fb = nv30_fb_new,
353 .gpio = nv10_gpio_new,
354 .i2c = nv04_i2c_new,
355 .imem = nv04_instmem_new,
356 .mc = nv04_mc_new,
357 .mmu = nv04_mmu_new,
358 .timer = nv04_timer_new,
359 // .disp = nv04_disp_new,
360 // .dma = nv04_dma_new,
361 // .fifo = nv17_fifo_new,
362 // .gr = nv30_gr_new,
363 // .sw = nv10_sw_new,
364 };
365
366 static const struct nvkm_device_chip
367 nv31_chipset = {
368 .name = "NV31",
369 .bios = nvkm_bios_new,
370 .bus = nv31_bus_new,
371 .clk = nv04_clk_new,
372 .devinit = nv20_devinit_new,
373 .fb = nv30_fb_new,
374 .gpio = nv10_gpio_new,
375 .i2c = nv04_i2c_new,
376 .imem = nv04_instmem_new,
377 .mc = nv04_mc_new,
378 .mmu = nv04_mmu_new,
379 .timer = nv04_timer_new,
380 // .disp = nv04_disp_new,
381 // .dma = nv04_dma_new,
382 // .fifo = nv17_fifo_new,
383 // .gr = nv30_gr_new,
384 // .mpeg = nv31_mpeg_new,
385 // .sw = nv10_sw_new,
386 };
387
388 static const struct nvkm_device_chip
389 nv34_chipset = {
390 .name = "NV34",
391 .bios = nvkm_bios_new,
392 .bus = nv31_bus_new,
393 .clk = nv04_clk_new,
394 .devinit = nv10_devinit_new,
395 .fb = nv10_fb_new,
396 .gpio = nv10_gpio_new,
397 .i2c = nv04_i2c_new,
398 .imem = nv04_instmem_new,
399 .mc = nv04_mc_new,
400 .mmu = nv04_mmu_new,
401 .timer = nv04_timer_new,
402 // .disp = nv04_disp_new,
403 // .dma = nv04_dma_new,
404 // .fifo = nv17_fifo_new,
405 // .gr = nv34_gr_new,
406 // .mpeg = nv31_mpeg_new,
407 // .sw = nv10_sw_new,
408 };
409
410 static const struct nvkm_device_chip
411 nv35_chipset = {
412 .name = "NV35",
413 .bios = nvkm_bios_new,
414 .bus = nv04_bus_new,
415 .clk = nv04_clk_new,
416 .devinit = nv20_devinit_new,
417 .fb = nv35_fb_new,
418 .gpio = nv10_gpio_new,
419 .i2c = nv04_i2c_new,
420 .imem = nv04_instmem_new,
421 .mc = nv04_mc_new,
422 .mmu = nv04_mmu_new,
423 .timer = nv04_timer_new,
424 // .disp = nv04_disp_new,
425 // .dma = nv04_dma_new,
426 // .fifo = nv17_fifo_new,
427 // .gr = nv35_gr_new,
428 // .sw = nv10_sw_new,
429 };
430
431 static const struct nvkm_device_chip
432 nv36_chipset = {
433 .name = "NV36",
434 .bios = nvkm_bios_new,
435 .bus = nv31_bus_new,
436 .clk = nv04_clk_new,
437 .devinit = nv20_devinit_new,
438 .fb = nv36_fb_new,
439 .gpio = nv10_gpio_new,
440 .i2c = nv04_i2c_new,
441 .imem = nv04_instmem_new,
442 .mc = nv04_mc_new,
443 .mmu = nv04_mmu_new,
444 .timer = nv04_timer_new,
445 // .disp = nv04_disp_new,
446 // .dma = nv04_dma_new,
447 // .fifo = nv17_fifo_new,
448 // .gr = nv35_gr_new,
449 // .mpeg = nv31_mpeg_new,
450 // .sw = nv10_sw_new,
451 };
452
453 static const struct nvkm_device_chip
454 nv40_chipset = {
455 .name = "NV40",
456 .bios = nvkm_bios_new,
457 .bus = nv31_bus_new,
458 .clk = nv40_clk_new,
459 .devinit = nv1a_devinit_new,
460 .fb = nv40_fb_new,
461 .gpio = nv10_gpio_new,
462 .i2c = nv04_i2c_new,
463 .imem = nv40_instmem_new,
464 .mc = nv40_mc_new,
465 .mmu = nv04_mmu_new,
466 .therm = nv40_therm_new,
467 .timer = nv40_timer_new,
468 .volt = nv40_volt_new,
469 // .disp = nv04_disp_new,
470 // .dma = nv04_dma_new,
471 // .fifo = nv40_fifo_new,
472 // .gr = nv40_gr_new,
473 // .mpeg = nv40_mpeg_new,
474 // .pm = nv40_pm_new,
475 // .sw = nv10_sw_new,
476 };
477
478 static const struct nvkm_device_chip
479 nv41_chipset = {
480 .name = "NV41",
481 .bios = nvkm_bios_new,
482 .bus = nv31_bus_new,
483 .clk = nv40_clk_new,
484 .devinit = nv1a_devinit_new,
485 .fb = nv41_fb_new,
486 .gpio = nv10_gpio_new,
487 .i2c = nv04_i2c_new,
488 .imem = nv40_instmem_new,
489 .mc = nv40_mc_new,
490 .mmu = nv41_mmu_new,
491 .therm = nv40_therm_new,
492 .timer = nv41_timer_new,
493 .volt = nv40_volt_new,
494 // .disp = nv04_disp_new,
495 // .dma = nv04_dma_new,
496 // .fifo = nv40_fifo_new,
497 // .gr = nv40_gr_new,
498 // .mpeg = nv40_mpeg_new,
499 // .pm = nv40_pm_new,
500 // .sw = nv10_sw_new,
501 };
502
503 static const struct nvkm_device_chip
504 nv42_chipset = {
505 .name = "NV42",
506 .bios = nvkm_bios_new,
507 .bus = nv31_bus_new,
508 .clk = nv40_clk_new,
509 .devinit = nv1a_devinit_new,
510 .fb = nv41_fb_new,
511 .gpio = nv10_gpio_new,
512 .i2c = nv04_i2c_new,
513 .imem = nv40_instmem_new,
514 .mc = nv40_mc_new,
515 .mmu = nv41_mmu_new,
516 .therm = nv40_therm_new,
517 .timer = nv41_timer_new,
518 .volt = nv40_volt_new,
519 // .disp = nv04_disp_new,
520 // .dma = nv04_dma_new,
521 // .fifo = nv40_fifo_new,
522 // .gr = nv40_gr_new,
523 // .mpeg = nv40_mpeg_new,
524 // .pm = nv40_pm_new,
525 // .sw = nv10_sw_new,
526 };
527
528 static const struct nvkm_device_chip
529 nv43_chipset = {
530 .name = "NV43",
531 .bios = nvkm_bios_new,
532 .bus = nv31_bus_new,
533 .clk = nv40_clk_new,
534 .devinit = nv1a_devinit_new,
535 .fb = nv41_fb_new,
536 .gpio = nv10_gpio_new,
537 .i2c = nv04_i2c_new,
538 .imem = nv40_instmem_new,
539 .mc = nv40_mc_new,
540 .mmu = nv41_mmu_new,
541 .therm = nv40_therm_new,
542 .timer = nv41_timer_new,
543 .volt = nv40_volt_new,
544 // .disp = nv04_disp_new,
545 // .dma = nv04_dma_new,
546 // .fifo = nv40_fifo_new,
547 // .gr = nv40_gr_new,
548 // .mpeg = nv40_mpeg_new,
549 // .pm = nv40_pm_new,
550 // .sw = nv10_sw_new,
551 };
552
553 static const struct nvkm_device_chip
554 nv44_chipset = {
555 .name = "NV44",
556 .bios = nvkm_bios_new,
557 .bus = nv31_bus_new,
558 .clk = nv40_clk_new,
559 .devinit = nv1a_devinit_new,
560 .fb = nv44_fb_new,
561 .gpio = nv10_gpio_new,
562 .i2c = nv04_i2c_new,
563 .imem = nv40_instmem_new,
564 .mc = nv44_mc_new,
565 .mmu = nv44_mmu_new,
566 .therm = nv40_therm_new,
567 .timer = nv41_timer_new,
568 .volt = nv40_volt_new,
569 // .disp = nv04_disp_new,
570 // .dma = nv04_dma_new,
571 // .fifo = nv40_fifo_new,
572 // .gr = nv40_gr_new,
573 // .mpeg = nv44_mpeg_new,
574 // .pm = nv40_pm_new,
575 // .sw = nv10_sw_new,
576 };
577
578 static const struct nvkm_device_chip
579 nv45_chipset = {
580 .name = "NV45",
581 .bios = nvkm_bios_new,
582 .bus = nv31_bus_new,
583 .clk = nv40_clk_new,
584 .devinit = nv1a_devinit_new,
585 .fb = nv40_fb_new,
586 .gpio = nv10_gpio_new,
587 .i2c = nv04_i2c_new,
588 .imem = nv40_instmem_new,
589 .mc = nv40_mc_new,
590 .mmu = nv04_mmu_new,
591 .therm = nv40_therm_new,
592 .timer = nv41_timer_new,
593 .volt = nv40_volt_new,
594 // .disp = nv04_disp_new,
595 // .dma = nv04_dma_new,
596 // .fifo = nv40_fifo_new,
597 // .gr = nv40_gr_new,
598 // .mpeg = nv44_mpeg_new,
599 // .pm = nv40_pm_new,
600 // .sw = nv10_sw_new,
601 };
602
603 static const struct nvkm_device_chip
604 nv46_chipset = {
605 .name = "G72",
606 .bios = nvkm_bios_new,
607 .bus = nv31_bus_new,
608 .clk = nv40_clk_new,
609 .devinit = nv1a_devinit_new,
610 .fb = nv46_fb_new,
611 .gpio = nv10_gpio_new,
612 .i2c = nv04_i2c_new,
613 .imem = nv40_instmem_new,
614 .mc = nv44_mc_new,
615 .mmu = nv44_mmu_new,
616 .therm = nv40_therm_new,
617 .timer = nv41_timer_new,
618 .volt = nv40_volt_new,
619 // .disp = nv04_disp_new,
620 // .dma = nv04_dma_new,
621 // .fifo = nv40_fifo_new,
622 // .gr = nv40_gr_new,
623 // .mpeg = nv44_mpeg_new,
624 // .pm = nv40_pm_new,
625 // .sw = nv10_sw_new,
626 };
627
628 static const struct nvkm_device_chip
629 nv47_chipset = {
630 .name = "G70",
631 .bios = nvkm_bios_new,
632 .bus = nv31_bus_new,
633 .clk = nv40_clk_new,
634 .devinit = nv1a_devinit_new,
635 .fb = nv47_fb_new,
636 .gpio = nv10_gpio_new,
637 .i2c = nv04_i2c_new,
638 .imem = nv40_instmem_new,
639 .mc = nv40_mc_new,
640 .mmu = nv41_mmu_new,
641 .therm = nv40_therm_new,
642 .timer = nv41_timer_new,
643 .volt = nv40_volt_new,
644 // .disp = nv04_disp_new,
645 // .dma = nv04_dma_new,
646 // .fifo = nv40_fifo_new,
647 // .gr = nv40_gr_new,
648 // .mpeg = nv44_mpeg_new,
649 // .pm = nv40_pm_new,
650 // .sw = nv10_sw_new,
651 };
652
653 static const struct nvkm_device_chip
654 nv49_chipset = {
655 .name = "G71",
656 .bios = nvkm_bios_new,
657 .bus = nv31_bus_new,
658 .clk = nv40_clk_new,
659 .devinit = nv1a_devinit_new,
660 .fb = nv49_fb_new,
661 .gpio = nv10_gpio_new,
662 .i2c = nv04_i2c_new,
663 .imem = nv40_instmem_new,
664 .mc = nv40_mc_new,
665 .mmu = nv41_mmu_new,
666 .therm = nv40_therm_new,
667 .timer = nv41_timer_new,
668 .volt = nv40_volt_new,
669 // .disp = nv04_disp_new,
670 // .dma = nv04_dma_new,
671 // .fifo = nv40_fifo_new,
672 // .gr = nv40_gr_new,
673 // .mpeg = nv44_mpeg_new,
674 // .pm = nv40_pm_new,
675 // .sw = nv10_sw_new,
676 };
677
678 static const struct nvkm_device_chip
679 nv4a_chipset = {
680 .name = "NV44A",
681 .bios = nvkm_bios_new,
682 .bus = nv31_bus_new,
683 .clk = nv40_clk_new,
684 .devinit = nv1a_devinit_new,
685 .fb = nv44_fb_new,
686 .gpio = nv10_gpio_new,
687 .i2c = nv04_i2c_new,
688 .imem = nv40_instmem_new,
689 .mc = nv44_mc_new,
690 .mmu = nv44_mmu_new,
691 .therm = nv40_therm_new,
692 .timer = nv41_timer_new,
693 .volt = nv40_volt_new,
694 // .disp = nv04_disp_new,
695 // .dma = nv04_dma_new,
696 // .fifo = nv40_fifo_new,
697 // .gr = nv40_gr_new,
698 // .mpeg = nv44_mpeg_new,
699 // .pm = nv40_pm_new,
700 // .sw = nv10_sw_new,
701 };
702
703 static const struct nvkm_device_chip
704 nv4b_chipset = {
705 .name = "G73",
706 .bios = nvkm_bios_new,
707 .bus = nv31_bus_new,
708 .clk = nv40_clk_new,
709 .devinit = nv1a_devinit_new,
710 .fb = nv49_fb_new,
711 .gpio = nv10_gpio_new,
712 .i2c = nv04_i2c_new,
713 .imem = nv40_instmem_new,
714 .mc = nv40_mc_new,
715 .mmu = nv41_mmu_new,
716 .therm = nv40_therm_new,
717 .timer = nv41_timer_new,
718 .volt = nv40_volt_new,
719 // .disp = nv04_disp_new,
720 // .dma = nv04_dma_new,
721 // .fifo = nv40_fifo_new,
722 // .gr = nv40_gr_new,
723 // .mpeg = nv44_mpeg_new,
724 // .pm = nv40_pm_new,
725 // .sw = nv10_sw_new,
726 };
727
728 static const struct nvkm_device_chip
729 nv4c_chipset = {
730 .name = "C61",
731 .bios = nvkm_bios_new,
732 .bus = nv31_bus_new,
733 .clk = nv40_clk_new,
734 .devinit = nv1a_devinit_new,
735 .fb = nv46_fb_new,
736 .gpio = nv10_gpio_new,
737 .i2c = nv04_i2c_new,
738 .imem = nv40_instmem_new,
739 .mc = nv4c_mc_new,
740 .mmu = nv44_mmu_new,
741 .therm = nv40_therm_new,
742 .timer = nv41_timer_new,
743 .volt = nv40_volt_new,
744 // .disp = nv04_disp_new,
745 // .dma = nv04_dma_new,
746 // .fifo = nv40_fifo_new,
747 // .gr = nv40_gr_new,
748 // .mpeg = nv44_mpeg_new,
749 // .pm = nv40_pm_new,
750 // .sw = nv10_sw_new,
751 };
752
753 static const struct nvkm_device_chip
754 nv4e_chipset = {
755 .name = "C51",
756 .bios = nvkm_bios_new,
757 .bus = nv31_bus_new,
758 .clk = nv40_clk_new,
759 .devinit = nv1a_devinit_new,
760 .fb = nv4e_fb_new,
761 .gpio = nv10_gpio_new,
762 .i2c = nv4e_i2c_new,
763 .imem = nv40_instmem_new,
764 .mc = nv4c_mc_new,
765 .mmu = nv44_mmu_new,
766 .therm = nv40_therm_new,
767 .timer = nv41_timer_new,
768 .volt = nv40_volt_new,
769 // .disp = nv04_disp_new,
770 // .dma = nv04_dma_new,
771 // .fifo = nv40_fifo_new,
772 // .gr = nv40_gr_new,
773 // .mpeg = nv44_mpeg_new,
774 // .pm = nv40_pm_new,
775 // .sw = nv10_sw_new,
776 };
777
778 static const struct nvkm_device_chip
779 nv50_chipset = {
780 .name = "G80",
781 .bar = nv50_bar_new,
782 .bios = nvkm_bios_new,
783 .bus = nv50_bus_new,
784 .clk = nv50_clk_new,
785 .devinit = nv50_devinit_new,
786 .fb = nv50_fb_new,
787 .fuse = nv50_fuse_new,
788 .gpio = nv50_gpio_new,
789 .i2c = nv50_i2c_new,
790 .imem = nv50_instmem_new,
791 .mc = nv50_mc_new,
792 .mmu = nv50_mmu_new,
793 .mxm = nv50_mxm_new,
794 .therm = nv50_therm_new,
795 .timer = nv41_timer_new,
796 .volt = nv40_volt_new,
797 // .disp = nv50_disp_new,
798 // .dma = nv50_dma_new,
799 // .fifo = nv50_fifo_new,
800 // .gr = nv50_gr_new,
801 // .mpeg = nv50_mpeg_new,
802 // .pm = nv50_pm_new,
803 // .sw = nv50_sw_new,
804 };
805
806 static const struct nvkm_device_chip
807 nv63_chipset = {
808 .name = "C73",
809 .bios = nvkm_bios_new,
810 .bus = nv31_bus_new,
811 .clk = nv40_clk_new,
812 .devinit = nv1a_devinit_new,
813 .fb = nv46_fb_new,
814 .gpio = nv10_gpio_new,
815 .i2c = nv04_i2c_new,
816 .imem = nv40_instmem_new,
817 .mc = nv4c_mc_new,
818 .mmu = nv44_mmu_new,
819 .therm = nv40_therm_new,
820 .timer = nv41_timer_new,
821 .volt = nv40_volt_new,
822 // .disp = nv04_disp_new,
823 // .dma = nv04_dma_new,
824 // .fifo = nv40_fifo_new,
825 // .gr = nv40_gr_new,
826 // .mpeg = nv44_mpeg_new,
827 // .pm = nv40_pm_new,
828 // .sw = nv10_sw_new,
829 };
830
831 static const struct nvkm_device_chip
832 nv67_chipset = {
833 .name = "C67",
834 .bios = nvkm_bios_new,
835 .bus = nv31_bus_new,
836 .clk = nv40_clk_new,
837 .devinit = nv1a_devinit_new,
838 .fb = nv46_fb_new,
839 .gpio = nv10_gpio_new,
840 .i2c = nv04_i2c_new,
841 .imem = nv40_instmem_new,
842 .mc = nv4c_mc_new,
843 .mmu = nv44_mmu_new,
844 .therm = nv40_therm_new,
845 .timer = nv41_timer_new,
846 .volt = nv40_volt_new,
847 // .disp = nv04_disp_new,
848 // .dma = nv04_dma_new,
849 // .fifo = nv40_fifo_new,
850 // .gr = nv40_gr_new,
851 // .mpeg = nv44_mpeg_new,
852 // .pm = nv40_pm_new,
853 // .sw = nv10_sw_new,
854 };
855
856 static const struct nvkm_device_chip
857 nv68_chipset = {
858 .name = "C68",
859 .bios = nvkm_bios_new,
860 .bus = nv31_bus_new,
861 .clk = nv40_clk_new,
862 .devinit = nv1a_devinit_new,
863 .fb = nv46_fb_new,
864 .gpio = nv10_gpio_new,
865 .i2c = nv04_i2c_new,
866 .imem = nv40_instmem_new,
867 .mc = nv4c_mc_new,
868 .mmu = nv44_mmu_new,
869 .therm = nv40_therm_new,
870 .timer = nv41_timer_new,
871 .volt = nv40_volt_new,
872 // .disp = nv04_disp_new,
873 // .dma = nv04_dma_new,
874 // .fifo = nv40_fifo_new,
875 // .gr = nv40_gr_new,
876 // .mpeg = nv44_mpeg_new,
877 // .pm = nv40_pm_new,
878 // .sw = nv10_sw_new,
879 };
880
881 static const struct nvkm_device_chip
882 nv84_chipset = {
883 .name = "G84",
884 .bar = g84_bar_new,
885 .bios = nvkm_bios_new,
886 .bus = nv50_bus_new,
887 .clk = g84_clk_new,
888 .devinit = g84_devinit_new,
889 .fb = g84_fb_new,
890 .fuse = nv50_fuse_new,
891 .gpio = nv50_gpio_new,
892 .i2c = nv50_i2c_new,
893 .imem = nv50_instmem_new,
894 .mc = nv50_mc_new,
895 .mmu = nv50_mmu_new,
896 .mxm = nv50_mxm_new,
897 .therm = g84_therm_new,
898 .timer = nv41_timer_new,
899 .volt = nv40_volt_new,
900 .bsp = g84_bsp_new,
901 // .cipher = g84_cipher_new,
902 // .disp = g84_disp_new,
903 // .dma = nv50_dma_new,
904 // .fifo = g84_fifo_new,
905 // .gr = nv50_gr_new,
906 // .mpeg = g84_mpeg_new,
907 // .pm = g84_pm_new,
908 // .sw = nv50_sw_new,
909 .vp = g84_vp_new,
910 };
911
912 static const struct nvkm_device_chip
913 nv86_chipset = {
914 .name = "G86",
915 .bar = g84_bar_new,
916 .bios = nvkm_bios_new,
917 .bus = nv50_bus_new,
918 .clk = g84_clk_new,
919 .devinit = g84_devinit_new,
920 .fb = g84_fb_new,
921 .fuse = nv50_fuse_new,
922 .gpio = nv50_gpio_new,
923 .i2c = nv50_i2c_new,
924 .imem = nv50_instmem_new,
925 .mc = nv50_mc_new,
926 .mmu = nv50_mmu_new,
927 .mxm = nv50_mxm_new,
928 .therm = g84_therm_new,
929 .timer = nv41_timer_new,
930 .volt = nv40_volt_new,
931 .bsp = g84_bsp_new,
932 // .cipher = g84_cipher_new,
933 // .disp = g84_disp_new,
934 // .dma = nv50_dma_new,
935 // .fifo = g84_fifo_new,
936 // .gr = nv50_gr_new,
937 // .mpeg = g84_mpeg_new,
938 // .pm = g84_pm_new,
939 // .sw = nv50_sw_new,
940 .vp = g84_vp_new,
941 };
942
943 static const struct nvkm_device_chip
944 nv92_chipset = {
945 .name = "G92",
946 .bar = g84_bar_new,
947 .bios = nvkm_bios_new,
948 .bus = nv50_bus_new,
949 .clk = g84_clk_new,
950 .devinit = g84_devinit_new,
951 .fb = g84_fb_new,
952 .fuse = nv50_fuse_new,
953 .gpio = nv50_gpio_new,
954 .i2c = nv50_i2c_new,
955 .imem = nv50_instmem_new,
956 .mc = nv50_mc_new,
957 .mmu = nv50_mmu_new,
958 .mxm = nv50_mxm_new,
959 .therm = g84_therm_new,
960 .timer = nv41_timer_new,
961 .volt = nv40_volt_new,
962 .bsp = g84_bsp_new,
963 // .cipher = g84_cipher_new,
964 // .disp = g84_disp_new,
965 // .dma = nv50_dma_new,
966 // .fifo = g84_fifo_new,
967 // .gr = nv50_gr_new,
968 // .mpeg = g84_mpeg_new,
969 // .pm = g84_pm_new,
970 // .sw = nv50_sw_new,
971 .vp = g84_vp_new,
972 };
973
974 static const struct nvkm_device_chip
975 nv94_chipset = {
976 .name = "G94",
977 .bar = g84_bar_new,
978 .bios = nvkm_bios_new,
979 .bus = g94_bus_new,
980 .clk = g84_clk_new,
981 .devinit = g84_devinit_new,
982 .fb = g84_fb_new,
983 .fuse = nv50_fuse_new,
984 .gpio = g94_gpio_new,
985 .i2c = g94_i2c_new,
986 .imem = nv50_instmem_new,
987 .mc = g94_mc_new,
988 .mmu = nv50_mmu_new,
989 .mxm = nv50_mxm_new,
990 .therm = g84_therm_new,
991 .timer = nv41_timer_new,
992 .volt = nv40_volt_new,
993 .bsp = g84_bsp_new,
994 // .cipher = g84_cipher_new,
995 // .disp = g94_disp_new,
996 // .dma = nv50_dma_new,
997 // .fifo = g84_fifo_new,
998 // .gr = nv50_gr_new,
999 // .mpeg = g84_mpeg_new,
1000 // .pm = g84_pm_new,
1001 // .sw = nv50_sw_new,
1002 .vp = g84_vp_new,
1003 };
1004
1005 static const struct nvkm_device_chip
1006 nv96_chipset = {
1007 .name = "G96",
1008 .bios = nvkm_bios_new,
1009 .gpio = g94_gpio_new,
1010 .i2c = g94_i2c_new,
1011 .fuse = nv50_fuse_new,
1012 .clk = g84_clk_new,
1013 .therm = g84_therm_new,
1014 .mxm = nv50_mxm_new,
1015 .devinit = g84_devinit_new,
1016 .mc = g94_mc_new,
1017 .bus = g94_bus_new,
1018 .timer = nv41_timer_new,
1019 .fb = g84_fb_new,
1020 .imem = nv50_instmem_new,
1021 .mmu = nv50_mmu_new,
1022 .bar = g84_bar_new,
1023 .volt = nv40_volt_new,
1024 // .dma = nv50_dma_new,
1025 // .fifo = g84_fifo_new,
1026 // .sw = nv50_sw_new,
1027 // .gr = nv50_gr_new,
1028 // .mpeg = g84_mpeg_new,
1029 .vp = g84_vp_new,
1030 // .cipher = g84_cipher_new,
1031 .bsp = g84_bsp_new,
1032 // .disp = g94_disp_new,
1033 // .pm = g84_pm_new,
1034 };
1035
1036 static const struct nvkm_device_chip
1037 nv98_chipset = {
1038 .name = "G98",
1039 .bios = nvkm_bios_new,
1040 .gpio = g94_gpio_new,
1041 .i2c = g94_i2c_new,
1042 .fuse = nv50_fuse_new,
1043 .clk = g84_clk_new,
1044 .therm = g84_therm_new,
1045 .mxm = nv50_mxm_new,
1046 .devinit = g98_devinit_new,
1047 .mc = g98_mc_new,
1048 .bus = g94_bus_new,
1049 .timer = nv41_timer_new,
1050 .fb = g84_fb_new,
1051 .imem = nv50_instmem_new,
1052 .mmu = nv50_mmu_new,
1053 .bar = g84_bar_new,
1054 .volt = nv40_volt_new,
1055 // .dma = nv50_dma_new,
1056 // .fifo = g84_fifo_new,
1057 // .sw = nv50_sw_new,
1058 // .gr = nv50_gr_new,
1059 .mspdec = g98_mspdec_new,
1060 .sec = g98_sec_new,
1061 .msvld = g98_msvld_new,
1062 .msppp = g98_msppp_new,
1063 // .disp = g94_disp_new,
1064 // .pm = g84_pm_new,
1065 };
1066
1067 static const struct nvkm_device_chip
1068 nva0_chipset = {
1069 .name = "GT200",
1070 .bar = g84_bar_new,
1071 .bios = nvkm_bios_new,
1072 .bus = g94_bus_new,
1073 .clk = g84_clk_new,
1074 .devinit = g84_devinit_new,
1075 .fb = g84_fb_new,
1076 .fuse = nv50_fuse_new,
1077 .gpio = g94_gpio_new,
1078 .i2c = nv50_i2c_new,
1079 .imem = nv50_instmem_new,
1080 .mc = g98_mc_new,
1081 .mmu = nv50_mmu_new,
1082 .mxm = nv50_mxm_new,
1083 .therm = g84_therm_new,
1084 .timer = nv41_timer_new,
1085 .volt = nv40_volt_new,
1086 .bsp = g84_bsp_new,
1087 // .cipher = g84_cipher_new,
1088 // .disp = gt200_disp_new,
1089 // .dma = nv50_dma_new,
1090 // .fifo = g84_fifo_new,
1091 // .gr = nv50_gr_new,
1092 // .mpeg = g84_mpeg_new,
1093 // .pm = gt200_pm_new,
1094 // .sw = nv50_sw_new,
1095 .vp = g84_vp_new,
1096 };
1097
1098 static const struct nvkm_device_chip
1099 nva3_chipset = {
1100 .name = "GT215",
1101 .bar = g84_bar_new,
1102 .bios = nvkm_bios_new,
1103 .bus = g94_bus_new,
1104 .clk = gt215_clk_new,
1105 .devinit = gt215_devinit_new,
1106 .fb = gt215_fb_new,
1107 .fuse = nv50_fuse_new,
1108 .gpio = g94_gpio_new,
1109 .i2c = g94_i2c_new,
1110 .imem = nv50_instmem_new,
1111 .mc = g98_mc_new,
1112 .mmu = nv50_mmu_new,
1113 .mxm = nv50_mxm_new,
1114 .pmu = gt215_pmu_new,
1115 .therm = gt215_therm_new,
1116 .timer = nv41_timer_new,
1117 .volt = nv40_volt_new,
1118 .ce[0] = gt215_ce_new,
1119 // .disp = gt215_disp_new,
1120 // .dma = nv50_dma_new,
1121 // .fifo = g84_fifo_new,
1122 // .gr = nv50_gr_new,
1123 // .mpeg = g84_mpeg_new,
1124 .mspdec = gt215_mspdec_new,
1125 .msppp = gt215_msppp_new,
1126 .msvld = gt215_msvld_new,
1127 // .pm = gt215_pm_new,
1128 // .sw = nv50_sw_new,
1129 };
1130
1131 static const struct nvkm_device_chip
1132 nva5_chipset = {
1133 .name = "GT216",
1134 .bar = g84_bar_new,
1135 .bios = nvkm_bios_new,
1136 .bus = g94_bus_new,
1137 .clk = gt215_clk_new,
1138 .devinit = gt215_devinit_new,
1139 .fb = gt215_fb_new,
1140 .fuse = nv50_fuse_new,
1141 .gpio = g94_gpio_new,
1142 .i2c = g94_i2c_new,
1143 .imem = nv50_instmem_new,
1144 .mc = g98_mc_new,
1145 .mmu = nv50_mmu_new,
1146 .mxm = nv50_mxm_new,
1147 .pmu = gt215_pmu_new,
1148 .therm = gt215_therm_new,
1149 .timer = nv41_timer_new,
1150 .volt = nv40_volt_new,
1151 .ce[0] = gt215_ce_new,
1152 // .disp = gt215_disp_new,
1153 // .dma = nv50_dma_new,
1154 // .fifo = g84_fifo_new,
1155 // .gr = nv50_gr_new,
1156 .mspdec = gt215_mspdec_new,
1157 .msppp = gt215_msppp_new,
1158 .msvld = gt215_msvld_new,
1159 // .pm = gt215_pm_new,
1160 // .sw = nv50_sw_new,
1161 };
1162
1163 static const struct nvkm_device_chip
1164 nva8_chipset = {
1165 .name = "GT218",
1166 .bar = g84_bar_new,
1167 .bios = nvkm_bios_new,
1168 .bus = g94_bus_new,
1169 .clk = gt215_clk_new,
1170 .devinit = gt215_devinit_new,
1171 .fb = gt215_fb_new,
1172 .fuse = nv50_fuse_new,
1173 .gpio = g94_gpio_new,
1174 .i2c = g94_i2c_new,
1175 .imem = nv50_instmem_new,
1176 .mc = g98_mc_new,
1177 .mmu = nv50_mmu_new,
1178 .mxm = nv50_mxm_new,
1179 .pmu = gt215_pmu_new,
1180 .therm = gt215_therm_new,
1181 .timer = nv41_timer_new,
1182 .volt = nv40_volt_new,
1183 .ce[0] = gt215_ce_new,
1184 // .disp = gt215_disp_new,
1185 // .dma = nv50_dma_new,
1186 // .fifo = g84_fifo_new,
1187 // .gr = nv50_gr_new,
1188 .mspdec = gt215_mspdec_new,
1189 .msppp = gt215_msppp_new,
1190 .msvld = gt215_msvld_new,
1191 // .pm = gt215_pm_new,
1192 // .sw = nv50_sw_new,
1193 };
1194
1195 static const struct nvkm_device_chip
1196 nvaa_chipset = {
1197 .name = "MCP77/MCP78",
1198 .bar = g84_bar_new,
1199 .bios = nvkm_bios_new,
1200 .bus = g94_bus_new,
1201 .clk = mcp77_clk_new,
1202 .devinit = g98_devinit_new,
1203 .fb = mcp77_fb_new,
1204 .fuse = nv50_fuse_new,
1205 .gpio = g94_gpio_new,
1206 .i2c = g94_i2c_new,
1207 .imem = nv50_instmem_new,
1208 .mc = g98_mc_new,
1209 .mmu = nv50_mmu_new,
1210 .mxm = nv50_mxm_new,
1211 .therm = g84_therm_new,
1212 .timer = nv41_timer_new,
1213 .volt = nv40_volt_new,
1214 // .disp = g94_disp_new,
1215 // .dma = nv50_dma_new,
1216 // .fifo = g84_fifo_new,
1217 // .gr = nv50_gr_new,
1218 .mspdec = g98_mspdec_new,
1219 .msppp = g98_msppp_new,
1220 .msvld = g98_msvld_new,
1221 // .pm = g84_pm_new,
1222 .sec = g98_sec_new,
1223 // .sw = nv50_sw_new,
1224 };
1225
1226 static const struct nvkm_device_chip
1227 nvac_chipset = {
1228 .name = "MCP79/MCP7A",
1229 .bar = g84_bar_new,
1230 .bios = nvkm_bios_new,
1231 .bus = g94_bus_new,
1232 .clk = mcp77_clk_new,
1233 .devinit = g98_devinit_new,
1234 .fb = mcp77_fb_new,
1235 .fuse = nv50_fuse_new,
1236 .gpio = g94_gpio_new,
1237 .i2c = g94_i2c_new,
1238 .imem = nv50_instmem_new,
1239 .mc = g98_mc_new,
1240 .mmu = nv50_mmu_new,
1241 .mxm = nv50_mxm_new,
1242 .therm = g84_therm_new,
1243 .timer = nv41_timer_new,
1244 .volt = nv40_volt_new,
1245 // .disp = g94_disp_new,
1246 // .dma = nv50_dma_new,
1247 // .fifo = g84_fifo_new,
1248 // .gr = nv50_gr_new,
1249 .mspdec = g98_mspdec_new,
1250 .msppp = g98_msppp_new,
1251 .msvld = g98_msvld_new,
1252 // .pm = g84_pm_new,
1253 .sec = g98_sec_new,
1254 // .sw = nv50_sw_new,
1255 };
1256
1257 static const struct nvkm_device_chip
1258 nvaf_chipset = {
1259 .name = "MCP89",
1260 .bar = g84_bar_new,
1261 .bios = nvkm_bios_new,
1262 .bus = g94_bus_new,
1263 .clk = gt215_clk_new,
1264 .devinit = mcp89_devinit_new,
1265 .fb = mcp89_fb_new,
1266 .fuse = nv50_fuse_new,
1267 .gpio = g94_gpio_new,
1268 .i2c = g94_i2c_new,
1269 .imem = nv50_instmem_new,
1270 .mc = g98_mc_new,
1271 .mmu = nv50_mmu_new,
1272 .mxm = nv50_mxm_new,
1273 .pmu = gt215_pmu_new,
1274 .therm = gt215_therm_new,
1275 .timer = nv41_timer_new,
1276 .volt = nv40_volt_new,
1277 .ce[0] = gt215_ce_new,
1278 // .disp = gt215_disp_new,
1279 // .dma = nv50_dma_new,
1280 // .fifo = g84_fifo_new,
1281 // .gr = nv50_gr_new,
1282 .mspdec = gt215_mspdec_new,
1283 .msppp = gt215_msppp_new,
1284 .msvld = mcp89_msvld_new,
1285 // .pm = gt215_pm_new,
1286 // .sw = nv50_sw_new,
1287 };
1288
1289 static const struct nvkm_device_chip
1290 nvc0_chipset = {
1291 .name = "GF100",
1292 .bar = gf100_bar_new,
1293 .bios = nvkm_bios_new,
1294 .bus = gf100_bus_new,
1295 .clk = gf100_clk_new,
1296 .devinit = gf100_devinit_new,
1297 .fb = gf100_fb_new,
1298 .fuse = gf100_fuse_new,
1299 .gpio = g94_gpio_new,
1300 .i2c = g94_i2c_new,
1301 .ibus = gf100_ibus_new,
1302 .imem = nv50_instmem_new,
1303 .ltc = gf100_ltc_new,
1304 .mc = gf100_mc_new,
1305 .mmu = gf100_mmu_new,
1306 .mxm = nv50_mxm_new,
1307 .pmu = gf100_pmu_new,
1308 .therm = gt215_therm_new,
1309 .timer = nv41_timer_new,
1310 .volt = nv40_volt_new,
1311 .ce[0] = gf100_ce_new,
1312 .ce[1] = gf100_ce_new,
1313 // .disp = gt215_disp_new,
1314 // .dma = gf100_dma_new,
1315 // .fifo = gf100_fifo_new,
1316 // .gr = gf100_gr_new,
1317 .mspdec = gf100_mspdec_new,
1318 .msppp = gf100_msppp_new,
1319 .msvld = gf100_msvld_new,
1320 // .pm = gf100_pm_new,
1321 // .sw = gf100_sw_new,
1322 };
1323
1324 static const struct nvkm_device_chip
1325 nvc1_chipset = {
1326 .name = "GF108",
1327 .bar = gf100_bar_new,
1328 .bios = nvkm_bios_new,
1329 .bus = gf100_bus_new,
1330 .clk = gf100_clk_new,
1331 .devinit = gf100_devinit_new,
1332 .fb = gf100_fb_new,
1333 .fuse = gf100_fuse_new,
1334 .gpio = g94_gpio_new,
1335 .i2c = g94_i2c_new,
1336 .ibus = gf100_ibus_new,
1337 .imem = nv50_instmem_new,
1338 .ltc = gf100_ltc_new,
1339 .mc = gf106_mc_new,
1340 .mmu = gf100_mmu_new,
1341 .mxm = nv50_mxm_new,
1342 .pmu = gf100_pmu_new,
1343 .therm = gt215_therm_new,
1344 .timer = nv41_timer_new,
1345 .volt = nv40_volt_new,
1346 .ce[0] = gf100_ce_new,
1347 // .disp = gt215_disp_new,
1348 // .dma = gf100_dma_new,
1349 // .fifo = gf100_fifo_new,
1350 // .gr = gf108_gr_new,
1351 .mspdec = gf100_mspdec_new,
1352 .msppp = gf100_msppp_new,
1353 .msvld = gf100_msvld_new,
1354 // .pm = gf108_pm_new,
1355 // .sw = gf100_sw_new,
1356 };
1357
1358 static const struct nvkm_device_chip
1359 nvc3_chipset = {
1360 .name = "GF106",
1361 .bar = gf100_bar_new,
1362 .bios = nvkm_bios_new,
1363 .bus = gf100_bus_new,
1364 .clk = gf100_clk_new,
1365 .devinit = gf100_devinit_new,
1366 .fb = gf100_fb_new,
1367 .fuse = gf100_fuse_new,
1368 .gpio = g94_gpio_new,
1369 .i2c = g94_i2c_new,
1370 .ibus = gf100_ibus_new,
1371 .imem = nv50_instmem_new,
1372 .ltc = gf100_ltc_new,
1373 .mc = gf106_mc_new,
1374 .mmu = gf100_mmu_new,
1375 .mxm = nv50_mxm_new,
1376 .pmu = gf100_pmu_new,
1377 .therm = gt215_therm_new,
1378 .timer = nv41_timer_new,
1379 .volt = nv40_volt_new,
1380 .ce[0] = gf100_ce_new,
1381 // .disp = gt215_disp_new,
1382 // .dma = gf100_dma_new,
1383 // .fifo = gf100_fifo_new,
1384 // .gr = gf104_gr_new,
1385 .mspdec = gf100_mspdec_new,
1386 .msppp = gf100_msppp_new,
1387 .msvld = gf100_msvld_new,
1388 // .pm = gf100_pm_new,
1389 // .sw = gf100_sw_new,
1390 };
1391
1392 static const struct nvkm_device_chip
1393 nvc4_chipset = {
1394 .name = "GF104",
1395 .bar = gf100_bar_new,
1396 .bios = nvkm_bios_new,
1397 .bus = gf100_bus_new,
1398 .clk = gf100_clk_new,
1399 .devinit = gf100_devinit_new,
1400 .fb = gf100_fb_new,
1401 .fuse = gf100_fuse_new,
1402 .gpio = g94_gpio_new,
1403 .i2c = g94_i2c_new,
1404 .ibus = gf100_ibus_new,
1405 .imem = nv50_instmem_new,
1406 .ltc = gf100_ltc_new,
1407 .mc = gf100_mc_new,
1408 .mmu = gf100_mmu_new,
1409 .mxm = nv50_mxm_new,
1410 .pmu = gf100_pmu_new,
1411 .therm = gt215_therm_new,
1412 .timer = nv41_timer_new,
1413 .volt = nv40_volt_new,
1414 .ce[0] = gf100_ce_new,
1415 .ce[1] = gf100_ce_new,
1416 // .disp = gt215_disp_new,
1417 // .dma = gf100_dma_new,
1418 // .fifo = gf100_fifo_new,
1419 // .gr = gf104_gr_new,
1420 .mspdec = gf100_mspdec_new,
1421 .msppp = gf100_msppp_new,
1422 .msvld = gf100_msvld_new,
1423 // .pm = gf100_pm_new,
1424 // .sw = gf100_sw_new,
1425 };
1426
1427 static const struct nvkm_device_chip
1428 nvc8_chipset = {
1429 .name = "GF110",
1430 .bar = gf100_bar_new,
1431 .bios = nvkm_bios_new,
1432 .bus = gf100_bus_new,
1433 .clk = gf100_clk_new,
1434 .devinit = gf100_devinit_new,
1435 .fb = gf100_fb_new,
1436 .fuse = gf100_fuse_new,
1437 .gpio = g94_gpio_new,
1438 .i2c = g94_i2c_new,
1439 .ibus = gf100_ibus_new,
1440 .imem = nv50_instmem_new,
1441 .ltc = gf100_ltc_new,
1442 .mc = gf100_mc_new,
1443 .mmu = gf100_mmu_new,
1444 .mxm = nv50_mxm_new,
1445 .pmu = gf100_pmu_new,
1446 .therm = gt215_therm_new,
1447 .timer = nv41_timer_new,
1448 .volt = nv40_volt_new,
1449 .ce[0] = gf100_ce_new,
1450 .ce[1] = gf100_ce_new,
1451 // .disp = gt215_disp_new,
1452 // .dma = gf100_dma_new,
1453 // .fifo = gf100_fifo_new,
1454 // .gr = gf110_gr_new,
1455 .mspdec = gf100_mspdec_new,
1456 .msppp = gf100_msppp_new,
1457 .msvld = gf100_msvld_new,
1458 // .pm = gf100_pm_new,
1459 // .sw = gf100_sw_new,
1460 };
1461
1462 static const struct nvkm_device_chip
1463 nvce_chipset = {
1464 .name = "GF114",
1465 .bar = gf100_bar_new,
1466 .bios = nvkm_bios_new,
1467 .bus = gf100_bus_new,
1468 .clk = gf100_clk_new,
1469 .devinit = gf100_devinit_new,
1470 .fb = gf100_fb_new,
1471 .fuse = gf100_fuse_new,
1472 .gpio = g94_gpio_new,
1473 .i2c = g94_i2c_new,
1474 .ibus = gf100_ibus_new,
1475 .imem = nv50_instmem_new,
1476 .ltc = gf100_ltc_new,
1477 .mc = gf100_mc_new,
1478 .mmu = gf100_mmu_new,
1479 .mxm = nv50_mxm_new,
1480 .pmu = gf100_pmu_new,
1481 .therm = gt215_therm_new,
1482 .timer = nv41_timer_new,
1483 .volt = nv40_volt_new,
1484 .ce[0] = gf100_ce_new,
1485 .ce[1] = gf100_ce_new,
1486 // .disp = gt215_disp_new,
1487 // .dma = gf100_dma_new,
1488 // .fifo = gf100_fifo_new,
1489 // .gr = gf104_gr_new,
1490 .mspdec = gf100_mspdec_new,
1491 .msppp = gf100_msppp_new,
1492 .msvld = gf100_msvld_new,
1493 // .pm = gf100_pm_new,
1494 // .sw = gf100_sw_new,
1495 };
1496
1497 static const struct nvkm_device_chip
1498 nvcf_chipset = {
1499 .name = "GF116",
1500 .bar = gf100_bar_new,
1501 .bios = nvkm_bios_new,
1502 .bus = gf100_bus_new,
1503 .clk = gf100_clk_new,
1504 .devinit = gf100_devinit_new,
1505 .fb = gf100_fb_new,
1506 .fuse = gf100_fuse_new,
1507 .gpio = g94_gpio_new,
1508 .i2c = g94_i2c_new,
1509 .ibus = gf100_ibus_new,
1510 .imem = nv50_instmem_new,
1511 .ltc = gf100_ltc_new,
1512 .mc = gf106_mc_new,
1513 .mmu = gf100_mmu_new,
1514 .mxm = nv50_mxm_new,
1515 .pmu = gf100_pmu_new,
1516 .therm = gt215_therm_new,
1517 .timer = nv41_timer_new,
1518 .volt = nv40_volt_new,
1519 .ce[0] = gf100_ce_new,
1520 // .disp = gt215_disp_new,
1521 // .dma = gf100_dma_new,
1522 // .fifo = gf100_fifo_new,
1523 // .gr = gf104_gr_new,
1524 .mspdec = gf100_mspdec_new,
1525 .msppp = gf100_msppp_new,
1526 .msvld = gf100_msvld_new,
1527 // .pm = gf100_pm_new,
1528 // .sw = gf100_sw_new,
1529 };
1530
1531 static const struct nvkm_device_chip
1532 nvd7_chipset = {
1533 .name = "GF117",
1534 .bar = gf100_bar_new,
1535 .bios = nvkm_bios_new,
1536 .bus = gf100_bus_new,
1537 .clk = gf100_clk_new,
1538 .devinit = gf100_devinit_new,
1539 .fb = gf100_fb_new,
1540 .fuse = gf100_fuse_new,
1541 .gpio = gf119_gpio_new,
1542 .i2c = gf117_i2c_new,
1543 .ibus = gf100_ibus_new,
1544 .imem = nv50_instmem_new,
1545 .ltc = gf100_ltc_new,
1546 .mc = gf106_mc_new,
1547 .mmu = gf100_mmu_new,
1548 .mxm = nv50_mxm_new,
1549 .therm = gf119_therm_new,
1550 .timer = nv41_timer_new,
1551 .ce[0] = gf100_ce_new,
1552 // .disp = gf119_disp_new,
1553 // .dma = gf119_dma_new,
1554 // .fifo = gf100_fifo_new,
1555 // .gr = gf117_gr_new,
1556 .mspdec = gf100_mspdec_new,
1557 .msppp = gf100_msppp_new,
1558 .msvld = gf100_msvld_new,
1559 // .pm = gf117_pm_new,
1560 // .sw = gf100_sw_new,
1561 };
1562
1563 static const struct nvkm_device_chip
1564 nvd9_chipset = {
1565 .name = "GF119",
1566 .bar = gf100_bar_new,
1567 .bios = nvkm_bios_new,
1568 .bus = gf100_bus_new,
1569 .clk = gf100_clk_new,
1570 .devinit = gf100_devinit_new,
1571 .fb = gf100_fb_new,
1572 .fuse = gf100_fuse_new,
1573 .gpio = gf119_gpio_new,
1574 .i2c = gf119_i2c_new,
1575 .ibus = gf100_ibus_new,
1576 .imem = nv50_instmem_new,
1577 .ltc = gf100_ltc_new,
1578 .mc = gf106_mc_new,
1579 .mmu = gf100_mmu_new,
1580 .mxm = nv50_mxm_new,
1581 .pmu = gf119_pmu_new,
1582 .therm = gf119_therm_new,
1583 .timer = nv41_timer_new,
1584 .volt = nv40_volt_new,
1585 .ce[0] = gf100_ce_new,
1586 // .disp = gf119_disp_new,
1587 // .dma = gf119_dma_new,
1588 // .fifo = gf100_fifo_new,
1589 // .gr = gf119_gr_new,
1590 .mspdec = gf100_mspdec_new,
1591 .msppp = gf100_msppp_new,
1592 .msvld = gf100_msvld_new,
1593 // .pm = gf117_pm_new,
1594 // .sw = gf100_sw_new,
1595 };
1596
1597 static const struct nvkm_device_chip
1598 nve4_chipset = {
1599 .name = "GK104",
1600 .bar = gf100_bar_new,
1601 .bios = nvkm_bios_new,
1602 .bus = gf100_bus_new,
1603 .clk = gk104_clk_new,
1604 .devinit = gf100_devinit_new,
1605 .fb = gk104_fb_new,
1606 .fuse = gf100_fuse_new,
1607 .gpio = gk104_gpio_new,
1608 .i2c = gk104_i2c_new,
1609 .ibus = gk104_ibus_new,
1610 .imem = nv50_instmem_new,
1611 .ltc = gk104_ltc_new,
1612 .mc = gf106_mc_new,
1613 .mmu = gf100_mmu_new,
1614 .mxm = nv50_mxm_new,
1615 .pmu = gk104_pmu_new,
1616 .therm = gf119_therm_new,
1617 .timer = nv41_timer_new,
1618 .volt = nv40_volt_new,
1619 // .ce[0] = gk104_ce_new,
1620 // .ce[1] = gk104_ce_new,
1621 // .ce[2] = gk104_ce2_new,
1622 // .disp = gk104_disp_new,
1623 // .dma = gf119_dma_new,
1624 // .fifo = gk104_fifo_new,
1625 // .gr = gk104_gr_new,
1626 .mspdec = gk104_mspdec_new,
1627 .msppp = gf100_msppp_new,
1628 .msvld = gk104_msvld_new,
1629 // .pm = gk104_pm_new,
1630 // .sw = gf100_sw_new,
1631 };
1632
1633 static const struct nvkm_device_chip
1634 nve6_chipset = {
1635 .name = "GK106",
1636 .bar = gf100_bar_new,
1637 .bios = nvkm_bios_new,
1638 .bus = gf100_bus_new,
1639 .clk = gk104_clk_new,
1640 .devinit = gf100_devinit_new,
1641 .fb = gk104_fb_new,
1642 .fuse = gf100_fuse_new,
1643 .gpio = gk104_gpio_new,
1644 .i2c = gk104_i2c_new,
1645 .ibus = gk104_ibus_new,
1646 .imem = nv50_instmem_new,
1647 .ltc = gk104_ltc_new,
1648 .mc = gf106_mc_new,
1649 .mmu = gf100_mmu_new,
1650 .mxm = nv50_mxm_new,
1651 .pmu = gk104_pmu_new,
1652 .therm = gf119_therm_new,
1653 .timer = nv41_timer_new,
1654 .volt = nv40_volt_new,
1655 // .ce[0] = gk104_ce_new,
1656 // .ce[1] = gk104_ce_new,
1657 // .ce[2] = gk104_ce2_new,
1658 // .disp = gk104_disp_new,
1659 // .dma = gf119_dma_new,
1660 // .fifo = gk104_fifo_new,
1661 // .gr = gk104_gr_new,
1662 .mspdec = gk104_mspdec_new,
1663 .msppp = gf100_msppp_new,
1664 .msvld = gk104_msvld_new,
1665 // .pm = gk104_pm_new,
1666 // .sw = gf100_sw_new,
1667 };
1668
1669 static const struct nvkm_device_chip
1670 nve7_chipset = {
1671 .name = "GK107",
1672 .bar = gf100_bar_new,
1673 .bios = nvkm_bios_new,
1674 .bus = gf100_bus_new,
1675 .clk = gk104_clk_new,
1676 .devinit = gf100_devinit_new,
1677 .fb = gk104_fb_new,
1678 .fuse = gf100_fuse_new,
1679 .gpio = gk104_gpio_new,
1680 .i2c = gk104_i2c_new,
1681 .ibus = gk104_ibus_new,
1682 .imem = nv50_instmem_new,
1683 .ltc = gk104_ltc_new,
1684 .mc = gf106_mc_new,
1685 .mmu = gf100_mmu_new,
1686 .mxm = nv50_mxm_new,
1687 .pmu = gf119_pmu_new,
1688 .therm = gf119_therm_new,
1689 .timer = nv41_timer_new,
1690 .volt = nv40_volt_new,
1691 // .ce[0] = gk104_ce_new,
1692 // .ce[1] = gk104_ce_new,
1693 // .ce[2] = gk104_ce2_new,
1694 // .disp = gk104_disp_new,
1695 // .dma = gf119_dma_new,
1696 // .fifo = gk104_fifo_new,
1697 // .gr = gk104_gr_new,
1698 .mspdec = gk104_mspdec_new,
1699 .msppp = gf100_msppp_new,
1700 .msvld = gk104_msvld_new,
1701 // .pm = gk104_pm_new,
1702 // .sw = gf100_sw_new,
1703 };
1704
1705 static const struct nvkm_device_chip
1706 nvea_chipset = {
1707 .name = "GK20A",
1708 .bar = gk20a_bar_new,
1709 .bus = gf100_bus_new,
1710 .clk = gk20a_clk_new,
1711 .fb = gk20a_fb_new,
1712 .fuse = gf100_fuse_new,
1713 .ibus = gk20a_ibus_new,
1714 .imem = gk20a_instmem_new,
1715 .ltc = gk104_ltc_new,
1716 .mc = gk20a_mc_new,
1717 .mmu = gf100_mmu_new,
1718 .pmu = gk20a_pmu_new,
1719 .timer = gk20a_timer_new,
1720 .volt = gk20a_volt_new,
1721 // .ce[2] = gk104_ce2_new,
1722 // .dma = gf119_dma_new,
1723 // .fifo = gk20a_fifo_new,
1724 // .gr = gk20a_gr_new,
1725 // .pm = gk104_pm_new,
1726 // .sw = gf100_sw_new,
1727 };
1728
1729 static const struct nvkm_device_chip
1730 nvf0_chipset = {
1731 .name = "GK110",
1732 .bar = gf100_bar_new,
1733 .bios = nvkm_bios_new,
1734 .bus = gf100_bus_new,
1735 .clk = gk104_clk_new,
1736 .devinit = gf100_devinit_new,
1737 .fb = gk104_fb_new,
1738 .fuse = gf100_fuse_new,
1739 .gpio = gk104_gpio_new,
1740 .i2c = gk104_i2c_new,
1741 .ibus = gk104_ibus_new,
1742 .imem = nv50_instmem_new,
1743 .ltc = gk104_ltc_new,
1744 .mc = gf106_mc_new,
1745 .mmu = gf100_mmu_new,
1746 .mxm = nv50_mxm_new,
1747 .pmu = gk110_pmu_new,
1748 .therm = gf119_therm_new,
1749 .timer = nv41_timer_new,
1750 .volt = nv40_volt_new,
1751 // .ce[0] = gk104_ce_new,
1752 // .ce[1] = gk104_ce_new,
1753 // .ce[2] = gk104_ce2_new,
1754 // .disp = gk110_disp_new,
1755 // .dma = gf119_dma_new,
1756 // .fifo = gk104_fifo_new,
1757 // .gr = gk110_gr_new,
1758 .mspdec = gk104_mspdec_new,
1759 .msppp = gf100_msppp_new,
1760 .msvld = gk104_msvld_new,
1761 // .pm = gk110_pm_new,
1762 // .sw = gf100_sw_new,
1763 };
1764
1765 static const struct nvkm_device_chip
1766 nvf1_chipset = {
1767 .name = "GK110B",
1768 .bar = gf100_bar_new,
1769 .bios = nvkm_bios_new,
1770 .bus = gf100_bus_new,
1771 .clk = gk104_clk_new,
1772 .devinit = gf100_devinit_new,
1773 .fb = gk104_fb_new,
1774 .fuse = gf100_fuse_new,
1775 .gpio = gk104_gpio_new,
1776 .i2c = gf119_i2c_new,
1777 .ibus = gk104_ibus_new,
1778 .imem = nv50_instmem_new,
1779 .ltc = gk104_ltc_new,
1780 .mc = gf106_mc_new,
1781 .mmu = gf100_mmu_new,
1782 .mxm = nv50_mxm_new,
1783 .pmu = gk110_pmu_new,
1784 .therm = gf119_therm_new,
1785 .timer = nv41_timer_new,
1786 .volt = nv40_volt_new,
1787 // .ce[0] = gk104_ce_new,
1788 // .ce[1] = gk104_ce_new,
1789 // .ce[2] = gk104_ce2_new,
1790 // .disp = gk110_disp_new,
1791 // .dma = gf119_dma_new,
1792 // .fifo = gk104_fifo_new,
1793 // .gr = gk110b_gr_new,
1794 .mspdec = gk104_mspdec_new,
1795 .msppp = gf100_msppp_new,
1796 .msvld = gk104_msvld_new,
1797 // .pm = gk110_pm_new,
1798 // .sw = gf100_sw_new,
1799 };
1800
1801 static const struct nvkm_device_chip
1802 nv106_chipset = {
1803 .name = "GK208B",
1804 .bar = gf100_bar_new,
1805 .bios = nvkm_bios_new,
1806 .bus = gf100_bus_new,
1807 .clk = gk104_clk_new,
1808 .devinit = gf100_devinit_new,
1809 .fb = gk104_fb_new,
1810 .fuse = gf100_fuse_new,
1811 .gpio = gk104_gpio_new,
1812 .i2c = gk104_i2c_new,
1813 .ibus = gk104_ibus_new,
1814 .imem = nv50_instmem_new,
1815 .ltc = gk104_ltc_new,
1816 .mc = gk20a_mc_new,
1817 .mmu = gf100_mmu_new,
1818 .mxm = nv50_mxm_new,
1819 .pmu = gk208_pmu_new,
1820 .therm = gf119_therm_new,
1821 .timer = nv41_timer_new,
1822 .volt = nv40_volt_new,
1823 // .ce[0] = gk104_ce_new,
1824 // .ce[1] = gk104_ce_new,
1825 // .ce[2] = gk104_ce2_new,
1826 // .disp = gk110_disp_new,
1827 // .dma = gf119_dma_new,
1828 // .fifo = gk208_fifo_new,
1829 // .gr = gk208_gr_new,
1830 .mspdec = gk104_mspdec_new,
1831 .msppp = gf100_msppp_new,
1832 .msvld = gk104_msvld_new,
1833 // .sw = gf100_sw_new,
1834 };
1835
1836 static const struct nvkm_device_chip
1837 nv108_chipset = {
1838 .name = "GK208",
1839 .bar = gf100_bar_new,
1840 .bios = nvkm_bios_new,
1841 .bus = gf100_bus_new,
1842 .clk = gk104_clk_new,
1843 .devinit = gf100_devinit_new,
1844 .fb = gk104_fb_new,
1845 .fuse = gf100_fuse_new,
1846 .gpio = gk104_gpio_new,
1847 .i2c = gk104_i2c_new,
1848 .ibus = gk104_ibus_new,
1849 .imem = nv50_instmem_new,
1850 .ltc = gk104_ltc_new,
1851 .mc = gk20a_mc_new,
1852 .mmu = gf100_mmu_new,
1853 .mxm = nv50_mxm_new,
1854 .pmu = gk208_pmu_new,
1855 .therm = gf119_therm_new,
1856 .timer = nv41_timer_new,
1857 .volt = nv40_volt_new,
1858 // .ce[0] = gk104_ce_new,
1859 // .ce[1] = gk104_ce_new,
1860 // .ce[2] = gk104_ce2_new,
1861 // .disp = gk110_disp_new,
1862 // .dma = gf119_dma_new,
1863 // .fifo = gk208_fifo_new,
1864 // .gr = gk208_gr_new,
1865 .mspdec = gk104_mspdec_new,
1866 .msppp = gf100_msppp_new,
1867 .msvld = gk104_msvld_new,
1868 // .sw = gf100_sw_new,
1869 };
1870
1871 static const struct nvkm_device_chip
1872 nv117_chipset = {
1873 .name = "GM107",
1874 .bar = gf100_bar_new,
1875 .bios = nvkm_bios_new,
1876 .bus = gf100_bus_new,
1877 .clk = gk104_clk_new,
1878 .devinit = gm107_devinit_new,
1879 .fb = gm107_fb_new,
1880 .fuse = gm107_fuse_new,
1881 .gpio = gk104_gpio_new,
1882 .i2c = gf119_i2c_new,
1883 .ibus = gk104_ibus_new,
1884 .imem = nv50_instmem_new,
1885 .ltc = gm107_ltc_new,
1886 .mc = gk20a_mc_new,
1887 .mmu = gf100_mmu_new,
1888 .mxm = nv50_mxm_new,
1889 .pmu = gm107_pmu_new,
1890 .therm = gm107_therm_new,
1891 .timer = gk20a_timer_new,
1892 // .ce[0] = gk104_ce_new,
1893 // .ce[2] = gk104_ce2_new,
1894 // .disp = gm107_disp_new,
1895 // .dma = gf119_dma_new,
1896 // .fifo = gk208_fifo_new,
1897 // .gr = gm107_gr_new,
1898 // .sw = gf100_sw_new,
1899 };
1900
1901 static const struct nvkm_device_chip
1902 nv124_chipset = {
1903 .name = "GM204",
1904 .bar = gf100_bar_new,
1905 .bios = nvkm_bios_new,
1906 .bus = gf100_bus_new,
1907 .devinit = gm204_devinit_new,
1908 .fb = gm107_fb_new,
1909 .fuse = gm107_fuse_new,
1910 .gpio = gk104_gpio_new,
1911 .i2c = gm204_i2c_new,
1912 .ibus = gk104_ibus_new,
1913 .imem = nv50_instmem_new,
1914 .ltc = gm107_ltc_new,
1915 .mc = gk20a_mc_new,
1916 .mmu = gf100_mmu_new,
1917 .mxm = nv50_mxm_new,
1918 .pmu = gm107_pmu_new,
1919 .timer = gk20a_timer_new,
1920 // .ce[0] = gm204_ce_new,
1921 // .ce[1] = gm204_ce_new,
1922 // .ce[2] = gm204_ce2_new,
1923 // .disp = gm204_disp_new,
1924 // .dma = gf119_dma_new,
1925 // .fifo = gm204_fifo_new,
1926 // .gr = gm204_gr_new,
1927 // .sw = gf100_sw_new,
1928 };
1929
1930 static const struct nvkm_device_chip
1931 nv126_chipset = {
1932 .name = "GM206",
1933 .bar = gf100_bar_new,
1934 .bios = nvkm_bios_new,
1935 .bus = gf100_bus_new,
1936 .devinit = gm204_devinit_new,
1937 .fb = gm107_fb_new,
1938 .fuse = gm107_fuse_new,
1939 .gpio = gk104_gpio_new,
1940 .i2c = gm204_i2c_new,
1941 .ibus = gk104_ibus_new,
1942 .imem = nv50_instmem_new,
1943 .ltc = gm107_ltc_new,
1944 .mc = gk20a_mc_new,
1945 .mmu = gf100_mmu_new,
1946 .mxm = nv50_mxm_new,
1947 .pmu = gm107_pmu_new,
1948 .timer = gk20a_timer_new,
1949 // .ce[0] = gm204_ce_new,
1950 // .ce[1] = gm204_ce_new,
1951 // .ce[2] = gm204_ce2_new,
1952 // .disp = gm204_disp_new,
1953 // .dma = gf119_dma_new,
1954 // .fifo = gm204_fifo_new,
1955 // .gr = gm206_gr_new,
1956 // .sw = gf100_sw_new,
1957 };
1958
1959 static const struct nvkm_device_chip
1960 nv12b_chipset = {
1961 .name = "GM20B",
1962 .bar = gk20a_bar_new,
1963 .bus = gf100_bus_new,
1964 .fb = gk20a_fb_new,
1965 .fuse = gm107_fuse_new,
1966 .ibus = gk20a_ibus_new,
1967 .imem = gk20a_instmem_new,
1968 .ltc = gm107_ltc_new,
1969 .mc = gk20a_mc_new,
1970 .mmu = gf100_mmu_new,
1971 .mmu = gf100_mmu_new,
1972 .timer = gk20a_timer_new,
1973 // .ce[2] = gm204_ce2_new,
1974 // .dma = gf119_dma_new,
1975 // .fifo = gm20b_fifo_new,
1976 // .gr = gm20b_gr_new,
1977 // .sw = gf100_sw_new,
1978 };
1979
1980 #include <core/client.h>
1981
1982 struct nvkm_device *
1983 nv_device(void *obj)
1984 {
1985 struct nvkm_object *device = nv_object(obj);
1986
1987 if (device->engine == NULL) {
1988 while (device && device->parent) {
1989 if (!nv_iclass(device, NV_SUBDEV_CLASS) &&
1990 device->parent == &nvkm_client(device)->object) {
1991 struct {
1992 struct nvkm_object base;
1993 struct nvkm_device *device;
1994 } *udevice = (void *)device;
1995 return udevice->device;
1996 }
1997 device = device->parent;
1998 }
1999 } else {
2000 device = &nv_object(obj)->engine->subdev.object;
2001 if (device && device->parent)
2002 device = device->parent;
2003 }
2004 #if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
2005 BUG_ON(!device);
2006 #endif
2007 return (void *)device;
2008 }
2009
2010 static int
2011 nvkm_device_event_ctor(struct nvkm_object *object, void *data, u32 size,
2012 struct nvkm_notify *notify)
2013 {
2014 if (!WARN_ON(size != 0)) {
2015 notify->size = 0;
2016 notify->types = 1;
2017 notify->index = 0;
2018 return 0;
2019 }
2020 return -EINVAL;
2021 }
2022
2023 static const struct nvkm_event_func
2024 nvkm_device_event_func = {
2025 .ctor = nvkm_device_event_ctor,
2026 };
2027
2028 struct nvkm_subdev *
2029 nvkm_device_subdev(struct nvkm_device *device, int index)
2030 {
2031 struct nvkm_engine *engine;
2032
2033 if (device->disable_mask & (1ULL << index))
2034 return NULL;
2035
2036 switch (index) {
2037 #define _(n,p,m) case NVDEV_SUBDEV_##n: if (p) return (m); break
2038 _(BAR , device->bar , &device->bar->subdev);
2039 _(VBIOS , device->bios , &device->bios->subdev);
2040 _(BUS , device->bus , &device->bus->subdev);
2041 _(CLK , device->clk , &device->clk->subdev);
2042 _(DEVINIT, device->devinit, &device->devinit->subdev);
2043 _(FB , device->fb , &device->fb->subdev);
2044 _(FUSE , device->fuse , &device->fuse->subdev);
2045 _(GPIO , device->gpio , &device->gpio->subdev);
2046 _(I2C , device->i2c , &device->i2c->subdev);
2047 _(IBUS , device->ibus , device->ibus);
2048 _(INSTMEM, device->imem , &device->imem->subdev);
2049 _(LTC , device->ltc , &device->ltc->subdev);
2050 _(MC , device->mc , &device->mc->subdev);
2051 _(MMU , device->mmu , &device->mmu->subdev);
2052 _(MXM , device->mxm , device->mxm);
2053 _(PMU , device->pmu , &device->pmu->subdev);
2054 _(THERM , device->therm , &device->therm->subdev);
2055 _(TIMER , device->timer , &device->timer->subdev);
2056 _(VOLT , device->volt , &device->volt->subdev);
2057 #undef _
2058 default:
2059 engine = nvkm_device_engine(device, index);
2060 if (engine)
2061 return &engine->subdev;
2062 break;
2063 }
2064 return NULL;
2065 }
2066
2067 struct nvkm_engine *
2068 nvkm_device_engine(struct nvkm_device *device, int index)
2069 {
2070 if (device->disable_mask & (1ULL << index))
2071 return NULL;
2072
2073 switch (index) {
2074 #define _(n,p,m) case NVDEV_ENGINE_##n: if (p) return (m); break
2075 _(BSP , device->bsp , device->bsp);
2076 _(CE0 , device->ce[0] , device->ce[0]);
2077 _(CE1 , device->ce[1] , device->ce[1]);
2078 _(CE2 , device->ce[2] , device->ce[2]);
2079 _(CIPHER , device->cipher , device->cipher);
2080 _(DISP , device->disp , &device->disp->engine);
2081 _(DMAOBJ , device->dma , &device->dma->engine);
2082 _(FIFO , device->fifo , &device->fifo->engine);
2083 _(GR , device->gr , &device->gr->engine);
2084 _(IFB , device->ifb , device->ifb);
2085 _(ME , device->me , device->me);
2086 _(MPEG , device->mpeg , device->mpeg);
2087 _(MSENC , device->msenc , device->msenc);
2088 _(MSPDEC , device->mspdec , device->mspdec);
2089 _(MSPPP , device->msppp , device->msppp);
2090 _(MSVLD , device->msvld , device->msvld);
2091 _(PM , device->pm , &device->pm->engine);
2092 _(SEC , device->sec , device->sec);
2093 _(SW , device->sw , &device->sw->engine);
2094 _(VIC , device->vic , device->vic);
2095 _(VP , device->vp , device->vp);
2096 #undef _
2097 default:
2098 WARN_ON(1);
2099 break;
2100 }
2101 return NULL;
2102 }
2103
2104 int
2105 nvkm_device_fini(struct nvkm_device *device, bool suspend)
2106 {
2107 const char *action = suspend ? "suspend" : "fini";
2108 struct nvkm_subdev *subdev;
2109 int ret, i;
2110 s64 time;
2111
2112 nvdev_trace(device, "%s running...\n", action);
2113 time = ktime_to_us(ktime_get());
2114
2115 nvkm_acpi_fini(device);
2116
2117 for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) {
2118 if ((subdev = nvkm_device_subdev(device, i))) {
2119 ret = nvkm_subdev_fini(subdev, suspend);
2120 if (ret && suspend)
2121 goto fail;
2122 }
2123 }
2124
2125
2126 if (device->func->fini)
2127 device->func->fini(device, suspend);
2128
2129 time = ktime_to_us(ktime_get()) - time;
2130 nvdev_trace(device, "%s completed in %lldus...\n", action, time);
2131 return 0;
2132
2133 fail:
2134 do {
2135 if ((subdev = nvkm_device_subdev(device, i))) {
2136 int rret = nvkm_subdev_init(subdev);
2137 if (rret)
2138 nvkm_fatal(subdev, "failed restart, %d\n", ret);
2139 }
2140 } while (++i < NVDEV_SUBDEV_NR);
2141
2142 nvdev_trace(device, "%s failed with %d\n", action, ret);
2143 return ret;
2144 }
2145
2146 static int
2147 nvkm_device_preinit(struct nvkm_device *device)
2148 {
2149 struct nvkm_subdev *subdev;
2150 int ret, i;
2151 s64 time;
2152
2153 nvdev_trace(device, "preinit running...\n");
2154 time = ktime_to_us(ktime_get());
2155
2156 if (device->func->preinit) {
2157 ret = device->func->preinit(device);
2158 if (ret)
2159 goto fail;
2160 }
2161
2162 for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
2163 if ((subdev = nvkm_device_subdev(device, i))) {
2164 ret = nvkm_subdev_preinit(subdev);
2165 if (ret)
2166 goto fail;
2167 }
2168 }
2169
2170 ret = nvkm_devinit_post(device->devinit, &device->disable_mask);
2171 if (ret)
2172 goto fail;
2173
2174 time = ktime_to_us(ktime_get()) - time;
2175 nvdev_trace(device, "preinit completed in %lldus\n", time);
2176 return 0;
2177
2178 fail:
2179 nvdev_error(device, "preinit failed with %d\n", ret);
2180 return ret;
2181 }
2182
2183 int
2184 nvkm_device_init(struct nvkm_device *device)
2185 {
2186 struct nvkm_subdev *subdev;
2187 int ret, i = 0, c;
2188 s64 time;
2189
2190 ret = nvkm_device_preinit(device);
2191 if (ret)
2192 return ret;
2193
2194 nvkm_device_fini(device, false);
2195
2196 nvdev_trace(device, "init running...\n");
2197 time = ktime_to_us(ktime_get());
2198
2199 for (i = 0, c = 0; i < NVDEV_SUBDEV_NR; i++) {
2200 #define _(s,m) case s: if (device->oclass[s] && !device->m) { \
2201 ret = nvkm_object_old(nv_object(device), NULL, \
2202 device->oclass[s], NULL, (s), \
2203 (struct nvkm_object **)&device->m); \
2204 if (ret == -ENODEV) { \
2205 device->oclass[s] = NULL; \
2206 continue; \
2207 } \
2208 if (ret) \
2209 goto fail; \
2210 } break
2211 switch (i) {
2212 _(NVDEV_SUBDEV_BAR , bar);
2213 _(NVDEV_SUBDEV_VBIOS , bios);
2214 _(NVDEV_SUBDEV_BUS , bus);
2215 _(NVDEV_SUBDEV_CLK , clk);
2216 _(NVDEV_SUBDEV_DEVINIT, devinit);
2217 _(NVDEV_SUBDEV_FB , fb);
2218 _(NVDEV_SUBDEV_FUSE , fuse);
2219 _(NVDEV_SUBDEV_GPIO , gpio);
2220 _(NVDEV_SUBDEV_I2C , i2c);
2221 _(NVDEV_SUBDEV_IBUS , ibus);
2222 _(NVDEV_SUBDEV_INSTMEM, imem);
2223 _(NVDEV_SUBDEV_LTC , ltc);
2224 _(NVDEV_SUBDEV_MC , mc);
2225 _(NVDEV_SUBDEV_MMU , mmu);
2226 _(NVDEV_SUBDEV_MXM , mxm);
2227 _(NVDEV_SUBDEV_PMU , pmu);
2228 _(NVDEV_SUBDEV_THERM , therm);
2229 _(NVDEV_SUBDEV_TIMER , timer);
2230 _(NVDEV_SUBDEV_VOLT , volt);
2231 _(NVDEV_ENGINE_BSP , bsp);
2232 _(NVDEV_ENGINE_CE0 , ce[0]);
2233 _(NVDEV_ENGINE_CE1 , ce[1]);
2234 _(NVDEV_ENGINE_CE2 , ce[2]);
2235 _(NVDEV_ENGINE_CIPHER , cipher);
2236 _(NVDEV_ENGINE_DISP , disp);
2237 _(NVDEV_ENGINE_DMAOBJ , dma);
2238 _(NVDEV_ENGINE_FIFO , fifo);
2239 _(NVDEV_ENGINE_GR , gr);
2240 _(NVDEV_ENGINE_IFB , ifb);
2241 _(NVDEV_ENGINE_ME , me);
2242 _(NVDEV_ENGINE_MPEG , mpeg);
2243 _(NVDEV_ENGINE_MSENC , msenc);
2244 _(NVDEV_ENGINE_MSPDEC , mspdec);
2245 _(NVDEV_ENGINE_MSPPP , msppp);
2246 _(NVDEV_ENGINE_MSVLD , msvld);
2247 _(NVDEV_ENGINE_PM , pm);
2248 _(NVDEV_ENGINE_SEC , sec);
2249 _(NVDEV_ENGINE_SW , sw);
2250 _(NVDEV_ENGINE_VIC , vic);
2251 _(NVDEV_ENGINE_VP , vp);
2252 default:
2253 WARN_ON(1);
2254 continue;
2255 }
2256 #undef _
2257
2258 /* note: can't init *any* subdevs until devinit has been run
2259 * due to not knowing exactly what the vbios init tables will
2260 * mess with. devinit also can't be run until all of its
2261 * dependencies have been created.
2262 *
2263 * this code delays init of any subdev until all of devinit's
2264 * dependencies have been created, and then initialises each
2265 * subdev in turn as they're created.
2266 */
2267 while (i >= NVDEV_SUBDEV_DEVINIT_LAST && c <= i) {
2268 if ((subdev = nvkm_device_subdev(device, c++))) {
2269 ret = nvkm_subdev_init(subdev);
2270 if (ret)
2271 goto fail;
2272 }
2273 }
2274 }
2275
2276 nvkm_acpi_init(device);
2277
2278 time = ktime_to_us(ktime_get()) - time;
2279 nvdev_trace(device, "init completed in %lldus\n", time);
2280 return 0;
2281
2282 fail:
2283 do {
2284 if ((subdev = nvkm_device_subdev(device, i)))
2285 nvkm_subdev_fini(subdev, false);
2286 } while (--i >= 0);
2287
2288 nvdev_error(device, "init failed with %d\n", ret);
2289 return ret;
2290 }
2291
2292 resource_size_t
2293 nv_device_resource_start(struct nvkm_device *device, unsigned int bar)
2294 {
2295 if (nv_device_is_pci(device)) {
2296 return pci_resource_start(device->pdev, bar);
2297 } else {
2298 struct resource *res;
2299 res = platform_get_resource(device->platformdev,
2300 IORESOURCE_MEM, bar);
2301 if (!res)
2302 return 0;
2303 return res->start;
2304 }
2305 }
2306
2307 resource_size_t
2308 nv_device_resource_len(struct nvkm_device *device, unsigned int bar)
2309 {
2310 if (nv_device_is_pci(device)) {
2311 return pci_resource_len(device->pdev, bar);
2312 } else {
2313 struct resource *res;
2314 res = platform_get_resource(device->platformdev,
2315 IORESOURCE_MEM, bar);
2316 if (!res)
2317 return 0;
2318 return resource_size(res);
2319 }
2320 }
2321
2322 int
2323 nv_device_get_irq(struct nvkm_device *device, bool stall)
2324 {
2325 if (nv_device_is_pci(device)) {
2326 return device->pdev->irq;
2327 } else {
2328 return platform_get_irq_byname(device->platformdev,
2329 stall ? "stall" : "nonstall");
2330 }
2331 }
2332
2333 void
2334 nvkm_device_del(struct nvkm_device **pdevice)
2335 {
2336 struct nvkm_device *device = *pdevice;
2337 int i;
2338 if (device) {
2339 mutex_lock(&nv_devices_mutex);
2340 device->disable_mask = 0;
2341 for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) {
2342 struct nvkm_subdev *subdev =
2343 nvkm_device_subdev(device, i);
2344 nvkm_subdev_del(&subdev);
2345 }
2346
2347 nvkm_event_fini(&device->event);
2348
2349 if (device->pri)
2350 iounmap(device->pri);
2351 list_del(&device->head);
2352
2353 if (device->func->dtor)
2354 *pdevice = device->func->dtor(device);
2355 mutex_unlock(&nv_devices_mutex);
2356
2357 kfree(*pdevice);
2358 *pdevice = NULL;
2359 }
2360 }
2361
2362 static const struct nvkm_engine_func
2363 nvkm_device_func = {
2364 };
2365
2366 int
2367 nvkm_device_ctor(const struct nvkm_device_func *func,
2368 const struct nvkm_device_quirk *quirk,
2369 void *dev, enum nv_bus_type type, u64 handle,
2370 const char *name, const char *cfg, const char *dbg,
2371 bool detect, bool mmio, u64 subdev_mask,
2372 struct nvkm_device *device)
2373 {
2374 struct nvkm_subdev *subdev;
2375 u64 mmio_base, mmio_size;
2376 u32 boot0, strap;
2377 void __iomem *map;
2378 int ret = -EEXIST;
2379 int i;
2380
2381 mutex_lock(&nv_devices_mutex);
2382 if (nvkm_device_find_locked(handle))
2383 goto done;
2384
2385 device->func = func;
2386 device->quirk = quirk;
2387 switch (type) {
2388 case NVKM_BUS_PCI:
2389 device->pdev = dev;
2390 device->dev = &device->pdev->dev;
2391 break;
2392 case NVKM_BUS_PLATFORM:
2393 device->platformdev = dev;
2394 device->dev = &device->platformdev->dev;
2395 break;
2396 }
2397 device->handle = handle;
2398 device->cfgopt = cfg;
2399 device->dbgopt = dbg;
2400 device->name = name;
2401 list_add_tail(&device->head, &nv_devices);
2402
2403 ret = nvkm_engine_ctor(&nvkm_device_func, device, 0, 0,
2404 true, &device->engine);
2405 device->engine.subdev.object.parent = NULL;
2406 if (ret)
2407 goto done;
2408
2409 ret = nvkm_event_init(&nvkm_device_event_func, 1, 1, &device->event);
2410 if (ret)
2411 goto done;
2412
2413 mmio_base = nv_device_resource_start(device, 0);
2414 mmio_size = nv_device_resource_len(device, 0);
2415
2416 /* identify the chipset, and determine classes of subdev/engines */
2417 if (detect) {
2418 map = ioremap(mmio_base, 0x102000);
2419 if (ret = -ENOMEM, map == NULL)
2420 goto done;
2421
2422 /* switch mmio to cpu's native endianness */
2423 #ifndef __BIG_ENDIAN
2424 if (ioread32_native(map + 0x000004) != 0x00000000) {
2425 #else
2426 if (ioread32_native(map + 0x000004) == 0x00000000) {
2427 #endif
2428 iowrite32_native(0x01000001, map + 0x000004);
2429 ioread32_native(map);
2430 }
2431
2432 /* read boot0 and strapping information */
2433 boot0 = ioread32_native(map + 0x000000);
2434 strap = ioread32_native(map + 0x101000);
2435 iounmap(map);
2436
2437 /* determine chipset and derive architecture from it */
2438 if ((boot0 & 0x1f000000) > 0) {
2439 device->chipset = (boot0 & 0x1ff00000) >> 20;
2440 device->chiprev = (boot0 & 0x000000ff);
2441 switch (device->chipset & 0x1f0) {
2442 case 0x010: {
2443 if (0x461 & (1 << (device->chipset & 0xf)))
2444 device->card_type = NV_10;
2445 else
2446 device->card_type = NV_11;
2447 device->chiprev = 0x00;
2448 break;
2449 }
2450 case 0x020: device->card_type = NV_20; break;
2451 case 0x030: device->card_type = NV_30; break;
2452 case 0x040:
2453 case 0x060: device->card_type = NV_40; break;
2454 case 0x050:
2455 case 0x080:
2456 case 0x090:
2457 case 0x0a0: device->card_type = NV_50; break;
2458 case 0x0c0:
2459 case 0x0d0: device->card_type = NV_C0; break;
2460 case 0x0e0:
2461 case 0x0f0:
2462 case 0x100: device->card_type = NV_E0; break;
2463 case 0x110:
2464 case 0x120: device->card_type = GM100; break;
2465 default:
2466 break;
2467 }
2468 } else
2469 if ((boot0 & 0xff00fff0) == 0x20004000) {
2470 if (boot0 & 0x00f00000)
2471 device->chipset = 0x05;
2472 else
2473 device->chipset = 0x04;
2474 device->card_type = NV_04;
2475 }
2476
2477 switch (device->card_type) {
2478 case NV_04: ret = nv04_identify(device); break;
2479 case NV_10:
2480 case NV_11: ret = nv10_identify(device); break;
2481 case NV_20: ret = nv20_identify(device); break;
2482 case NV_30: ret = nv30_identify(device); break;
2483 case NV_40: ret = nv40_identify(device); break;
2484 case NV_50: ret = nv50_identify(device); break;
2485 case NV_C0: ret = gf100_identify(device); break;
2486 case NV_E0: ret = gk104_identify(device); break;
2487 case GM100: ret = gm100_identify(device); break;
2488 default:
2489 ret = -EINVAL;
2490 break;
2491 }
2492
2493 switch (!ret * device->chipset) {
2494 case 0x004: device->chip = &nv4_chipset; break;
2495 case 0x005: device->chip = &nv5_chipset; break;
2496 case 0x010: device->chip = &nv10_chipset; break;
2497 case 0x011: device->chip = &nv11_chipset; break;
2498 case 0x015: device->chip = &nv15_chipset; break;
2499 case 0x017: device->chip = &nv17_chipset; break;
2500 case 0x018: device->chip = &nv18_chipset; break;
2501 case 0x01a: device->chip = &nv1a_chipset; break;
2502 case 0x01f: device->chip = &nv1f_chipset; break;
2503 case 0x020: device->chip = &nv20_chipset; break;
2504 case 0x025: device->chip = &nv25_chipset; break;
2505 case 0x028: device->chip = &nv28_chipset; break;
2506 case 0x02a: device->chip = &nv2a_chipset; break;
2507 case 0x030: device->chip = &nv30_chipset; break;
2508 case 0x031: device->chip = &nv31_chipset; break;
2509 case 0x034: device->chip = &nv34_chipset; break;
2510 case 0x035: device->chip = &nv35_chipset; break;
2511 case 0x036: device->chip = &nv36_chipset; break;
2512 case 0x040: device->chip = &nv40_chipset; break;
2513 case 0x041: device->chip = &nv41_chipset; break;
2514 case 0x042: device->chip = &nv42_chipset; break;
2515 case 0x043: device->chip = &nv43_chipset; break;
2516 case 0x044: device->chip = &nv44_chipset; break;
2517 case 0x045: device->chip = &nv45_chipset; break;
2518 case 0x046: device->chip = &nv46_chipset; break;
2519 case 0x047: device->chip = &nv47_chipset; break;
2520 case 0x049: device->chip = &nv49_chipset; break;
2521 case 0x04a: device->chip = &nv4a_chipset; break;
2522 case 0x04b: device->chip = &nv4b_chipset; break;
2523 case 0x04c: device->chip = &nv4c_chipset; break;
2524 case 0x04e: device->chip = &nv4e_chipset; break;
2525 case 0x050: device->chip = &nv50_chipset; break;
2526 case 0x063: device->chip = &nv63_chipset; break;
2527 case 0x067: device->chip = &nv67_chipset; break;
2528 case 0x068: device->chip = &nv68_chipset; break;
2529 case 0x084: device->chip = &nv84_chipset; break;
2530 case 0x086: device->chip = &nv86_chipset; break;
2531 case 0x092: device->chip = &nv92_chipset; break;
2532 case 0x094: device->chip = &nv94_chipset; break;
2533 case 0x096: device->chip = &nv96_chipset; break;
2534 case 0x098: device->chip = &nv98_chipset; break;
2535 case 0x0a0: device->chip = &nva0_chipset; break;
2536 case 0x0a3: device->chip = &nva3_chipset; break;
2537 case 0x0a5: device->chip = &nva5_chipset; break;
2538 case 0x0a8: device->chip = &nva8_chipset; break;
2539 case 0x0aa: device->chip = &nvaa_chipset; break;
2540 case 0x0ac: device->chip = &nvac_chipset; break;
2541 case 0x0af: device->chip = &nvaf_chipset; break;
2542 case 0x0c0: device->chip = &nvc0_chipset; break;
2543 case 0x0c1: device->chip = &nvc1_chipset; break;
2544 case 0x0c3: device->chip = &nvc3_chipset; break;
2545 case 0x0c4: device->chip = &nvc4_chipset; break;
2546 case 0x0c8: device->chip = &nvc8_chipset; break;
2547 case 0x0ce: device->chip = &nvce_chipset; break;
2548 case 0x0cf: device->chip = &nvcf_chipset; break;
2549 case 0x0d7: device->chip = &nvd7_chipset; break;
2550 case 0x0d9: device->chip = &nvd9_chipset; break;
2551 case 0x0e4: device->chip = &nve4_chipset; break;
2552 case 0x0e6: device->chip = &nve6_chipset; break;
2553 case 0x0e7: device->chip = &nve7_chipset; break;
2554 case 0x0ea: device->chip = &nvea_chipset; break;
2555 case 0x0f0: device->chip = &nvf0_chipset; break;
2556 case 0x0f1: device->chip = &nvf1_chipset; break;
2557 case 0x106: device->chip = &nv106_chipset; break;
2558 case 0x108: device->chip = &nv108_chipset; break;
2559 case 0x117: device->chip = &nv117_chipset; break;
2560 case 0x124: device->chip = &nv124_chipset; break;
2561 case 0x126: device->chip = &nv126_chipset; break;
2562 case 0x12b: device->chip = &nv12b_chipset; break;
2563 default:
2564 nvdev_error(device, "unknown chipset (%08x)\n", boot0);
2565 goto done;
2566 }
2567
2568 nvdev_info(device, "NVIDIA %s (%08x)\n",
2569 device->chip->name, boot0);
2570
2571 /* determine frequency of timing crystal */
2572 if ( device->card_type <= NV_10 || device->chipset < 0x17 ||
2573 (device->chipset >= 0x20 && device->chipset < 0x25))
2574 strap &= 0x00000040;
2575 else
2576 strap &= 0x00400040;
2577
2578 switch (strap) {
2579 case 0x00000000: device->crystal = 13500; break;
2580 case 0x00000040: device->crystal = 14318; break;
2581 case 0x00400000: device->crystal = 27000; break;
2582 case 0x00400040: device->crystal = 25000; break;
2583 }
2584 } else {
2585 device->chip = &null_chipset;
2586 }
2587
2588 if (!device->name)
2589 device->name = device->chip->name;
2590
2591 if (mmio) {
2592 device->pri = ioremap(mmio_base, mmio_size);
2593 if (!device->pri) {
2594 nvdev_error(device, "unable to map PRI\n");
2595 return -ENOMEM;
2596 }
2597 }
2598
2599 /* disable subdevs that aren't required (used by tools) */
2600 for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
2601 if (!(subdev_mask & (1ULL << i)))
2602 device->oclass[i] = NULL;
2603 }
2604
2605 atomic_set(&device->engine.subdev.object.usecount, 2);
2606 mutex_init(&device->mutex);
2607
2608 for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
2609 #define _(s,m) case s: \
2610 if (device->chip->m && (subdev_mask & (1ULL << (s)))) { \
2611 ret = device->chip->m(device, (s), &device->m); \
2612 if (ret) { \
2613 subdev = nvkm_device_subdev(device, (s)); \
2614 nvkm_subdev_del(&subdev); \
2615 device->m = NULL; \
2616 if (ret != -ENODEV) { \
2617 nvdev_error(device, "%s ctor failed, %d\n", \
2618 nvkm_subdev_name[s], ret); \
2619 goto done; \
2620 } \
2621 } \
2622 } \
2623 break
2624 switch (i) {
2625 _(NVDEV_SUBDEV_BAR , bar);
2626 _(NVDEV_SUBDEV_VBIOS , bios);
2627 _(NVDEV_SUBDEV_BUS , bus);
2628 _(NVDEV_SUBDEV_CLK , clk);
2629 _(NVDEV_SUBDEV_DEVINIT, devinit);
2630 _(NVDEV_SUBDEV_FB , fb);
2631 _(NVDEV_SUBDEV_FUSE , fuse);
2632 _(NVDEV_SUBDEV_GPIO , gpio);
2633 _(NVDEV_SUBDEV_I2C , i2c);
2634 _(NVDEV_SUBDEV_IBUS , ibus);
2635 _(NVDEV_SUBDEV_INSTMEM, imem);
2636 _(NVDEV_SUBDEV_LTC , ltc);
2637 _(NVDEV_SUBDEV_MC , mc);
2638 _(NVDEV_SUBDEV_MMU , mmu);
2639 _(NVDEV_SUBDEV_MXM , mxm);
2640 _(NVDEV_SUBDEV_PMU , pmu);
2641 _(NVDEV_SUBDEV_THERM , therm);
2642 _(NVDEV_SUBDEV_TIMER , timer);
2643 _(NVDEV_SUBDEV_VOLT , volt);
2644 _(NVDEV_ENGINE_BSP , bsp);
2645 _(NVDEV_ENGINE_CE0 , ce[0]);
2646 _(NVDEV_ENGINE_CE1 , ce[1]);
2647 _(NVDEV_ENGINE_CE2 , ce[2]);
2648 _(NVDEV_ENGINE_CIPHER , cipher);
2649 _(NVDEV_ENGINE_DISP , disp);
2650 _(NVDEV_ENGINE_DMAOBJ , dma);
2651 _(NVDEV_ENGINE_FIFO , fifo);
2652 _(NVDEV_ENGINE_GR , gr);
2653 _(NVDEV_ENGINE_IFB , ifb);
2654 _(NVDEV_ENGINE_ME , me);
2655 _(NVDEV_ENGINE_MPEG , mpeg);
2656 _(NVDEV_ENGINE_MSENC , msenc);
2657 _(NVDEV_ENGINE_MSPDEC , mspdec);
2658 _(NVDEV_ENGINE_MSPPP , msppp);
2659 _(NVDEV_ENGINE_MSVLD , msvld);
2660 _(NVDEV_ENGINE_PM , pm);
2661 _(NVDEV_ENGINE_SEC , sec);
2662 _(NVDEV_ENGINE_SW , sw);
2663 _(NVDEV_ENGINE_VIC , vic);
2664 _(NVDEV_ENGINE_VP , vp);
2665 default:
2666 WARN_ON(1);
2667 continue;
2668 }
2669 #undef _
2670 }
2671
2672 ret = 0;
2673 done:
2674 mutex_unlock(&nv_devices_mutex);
2675 return ret;
2676 }
Linux kernel - Deliverables
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