drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "priv.h"
  25
  26 int
  27 nv40_identify(struct nvkm_device *device)
  28 {
  29         switch (device->chipset) {
  30         case 0x40:
  31                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
  32                 device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
  33                 device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
  34                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
  35                 device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
  36                 device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
  37                 break;
  38         case 0x41:
  39                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
  40                 device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
  41                 device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
  42                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
  43                 device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
  44                 device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
  45                 break;
  46         case 0x42:
  47                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
  48                 device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
  49                 device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
  50                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
  51                 device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
  52                 device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
  53                 break;
  54         case 0x43:
  55                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
  56                 device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
  57                 device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
  58                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
  59                 device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
  60                 device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
  61                 break;
  62         case 0x45:
  63                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
  64                 device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
  65                 device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
  66                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
  67                 device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
  68                 device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
  69                 break;
  70         case 0x47:
  71                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
  72                 device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
  73                 device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
  74                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
  75                 device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
  76                 device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
  77                 break;
  78         case 0x49:
  79                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
  80                 device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
  81                 device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
  82                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
  83                 device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
  84                 device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
  85                 break;
  86         case 0x4b:
  87                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
  88                 device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
  89                 device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
  90                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
  91                 device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
  92                 device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
  93                 break;
  94         case 0x44:
  95                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
  96                 device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
  97                 device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
  98                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
  99                 device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 100                 device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
 101                 break;
 102         case 0x46:
 103                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 104                 device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
 105                 device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 106                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 107                 device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 108                 device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
 109                 break;
 110         case 0x4a:
 111                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 112                 device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
 113                 device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 114                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 115                 device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 116                 device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
 117                 break;
 118         case 0x4c:
 119                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 120                 device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
 121                 device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 122                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 123                 device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 124                 device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
 125                 break;
 126         case 0x4e:
 127                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 128                 device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
 129                 device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 130                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 131                 device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 132                 device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
 133                 break;
 134         case 0x63:
 135                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 136                 device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
 137                 device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 138                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 139                 device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 140                 device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
 141                 break;
 142         case 0x67:
 143                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 144                 device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
 145                 device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 146                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 147                 device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 148                 device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
 149                 break;
 150         case 0x68:
 151                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 152                 device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
 153                 device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 154                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 155                 device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 156                 device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
 157                 break;
 158         default:
 159                 return -EINVAL;
 160         }
 161
 162         return 0;
 163 }