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drm/nouveau/gr/gf100: wait on bottom half of FE's pipeline
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / engine / gr / gf100.c
1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "gf100.h"
25 #include "ctxgf100.h"
26 #include "fuc/os.h"
27
28 #include <core/client.h>
29 #include <core/device.h>
30 #include <core/handle.h>
31 #include <core/option.h>
32 #include <engine/fifo.h>
33 #include <subdev/fb.h>
34 #include <subdev/mc.h>
35 #include <subdev/timer.h>
36
37 #include <nvif/class.h>
38 #include <nvif/unpack.h>
39
40 /*******************************************************************************
41 * Zero Bandwidth Clear
42 ******************************************************************************/
43
44 static void
45 gf100_gr_zbc_clear_color(struct gf100_gr_priv *priv, int zbc)
46 {
47 if (priv->zbc_color[zbc].format) {
48 nv_wr32(priv, 0x405804, priv->zbc_color[zbc].ds[0]);
49 nv_wr32(priv, 0x405808, priv->zbc_color[zbc].ds[1]);
50 nv_wr32(priv, 0x40580c, priv->zbc_color[zbc].ds[2]);
51 nv_wr32(priv, 0x405810, priv->zbc_color[zbc].ds[3]);
52 }
53 nv_wr32(priv, 0x405814, priv->zbc_color[zbc].format);
54 nv_wr32(priv, 0x405820, zbc);
55 nv_wr32(priv, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */
56 }
57
58 static int
59 gf100_gr_zbc_color_get(struct gf100_gr_priv *priv, int format,
60 const u32 ds[4], const u32 l2[4])
61 {
62 struct nvkm_ltc *ltc = nvkm_ltc(priv);
63 int zbc = -ENOSPC, i;
64
65 for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
66 if (priv->zbc_color[i].format) {
67 if (priv->zbc_color[i].format != format)
68 continue;
69 if (memcmp(priv->zbc_color[i].ds, ds, sizeof(
70 priv->zbc_color[i].ds)))
71 continue;
72 if (memcmp(priv->zbc_color[i].l2, l2, sizeof(
73 priv->zbc_color[i].l2))) {
74 WARN_ON(1);
75 return -EINVAL;
76 }
77 return i;
78 } else {
79 zbc = (zbc < 0) ? i : zbc;
80 }
81 }
82
83 if (zbc < 0)
84 return zbc;
85
86 memcpy(priv->zbc_color[zbc].ds, ds, sizeof(priv->zbc_color[zbc].ds));
87 memcpy(priv->zbc_color[zbc].l2, l2, sizeof(priv->zbc_color[zbc].l2));
88 priv->zbc_color[zbc].format = format;
89 ltc->zbc_color_get(ltc, zbc, l2);
90 gf100_gr_zbc_clear_color(priv, zbc);
91 return zbc;
92 }
93
94 static void
95 gf100_gr_zbc_clear_depth(struct gf100_gr_priv *priv, int zbc)
96 {
97 if (priv->zbc_depth[zbc].format)
98 nv_wr32(priv, 0x405818, priv->zbc_depth[zbc].ds);
99 nv_wr32(priv, 0x40581c, priv->zbc_depth[zbc].format);
100 nv_wr32(priv, 0x405820, zbc);
101 nv_wr32(priv, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */
102 }
103
104 static int
105 gf100_gr_zbc_depth_get(struct gf100_gr_priv *priv, int format,
106 const u32 ds, const u32 l2)
107 {
108 struct nvkm_ltc *ltc = nvkm_ltc(priv);
109 int zbc = -ENOSPC, i;
110
111 for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
112 if (priv->zbc_depth[i].format) {
113 if (priv->zbc_depth[i].format != format)
114 continue;
115 if (priv->zbc_depth[i].ds != ds)
116 continue;
117 if (priv->zbc_depth[i].l2 != l2) {
118 WARN_ON(1);
119 return -EINVAL;
120 }
121 return i;
122 } else {
123 zbc = (zbc < 0) ? i : zbc;
124 }
125 }
126
127 if (zbc < 0)
128 return zbc;
129
130 priv->zbc_depth[zbc].format = format;
131 priv->zbc_depth[zbc].ds = ds;
132 priv->zbc_depth[zbc].l2 = l2;
133 ltc->zbc_depth_get(ltc, zbc, l2);
134 gf100_gr_zbc_clear_depth(priv, zbc);
135 return zbc;
136 }
137
138 /*******************************************************************************
139 * Graphics object classes
140 ******************************************************************************/
141
142 static int
143 gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size)
144 {
145 struct gf100_gr_priv *priv = (void *)object->engine;
146 union {
147 struct fermi_a_zbc_color_v0 v0;
148 } *args = data;
149 int ret;
150
151 if (nvif_unpack(args->v0, 0, 0, false)) {
152 switch (args->v0.format) {
153 case FERMI_A_ZBC_COLOR_V0_FMT_ZERO:
154 case FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE:
155 case FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32:
156 case FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16:
157 case FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16:
158 case FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16:
159 case FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16:
160 case FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16:
161 case FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8:
162 case FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8:
163 case FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10:
164 case FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10:
165 case FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8:
166 case FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8:
167 case FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8:
168 case FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8:
169 case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8:
170 case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10:
171 case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11:
172 ret = gf100_gr_zbc_color_get(priv, args->v0.format,
173 args->v0.ds,
174 args->v0.l2);
175 if (ret >= 0) {
176 args->v0.index = ret;
177 return 0;
178 }
179 break;
180 default:
181 return -EINVAL;
182 }
183 }
184
185 return ret;
186 }
187
188 static int
189 gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size)
190 {
191 struct gf100_gr_priv *priv = (void *)object->engine;
192 union {
193 struct fermi_a_zbc_depth_v0 v0;
194 } *args = data;
195 int ret;
196
197 if (nvif_unpack(args->v0, 0, 0, false)) {
198 switch (args->v0.format) {
199 case FERMI_A_ZBC_DEPTH_V0_FMT_FP32:
200 ret = gf100_gr_zbc_depth_get(priv, args->v0.format,
201 args->v0.ds,
202 args->v0.l2);
203 return (ret >= 0) ? 0 : -ENOSPC;
204 default:
205 return -EINVAL;
206 }
207 }
208
209 return ret;
210 }
211
212 static int
213 gf100_fermi_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
214 {
215 switch (mthd) {
216 case FERMI_A_ZBC_COLOR:
217 return gf100_fermi_mthd_zbc_color(object, data, size);
218 case FERMI_A_ZBC_DEPTH:
219 return gf100_fermi_mthd_zbc_depth(object, data, size);
220 default:
221 break;
222 }
223 return -EINVAL;
224 }
225
226 struct nvkm_ofuncs
227 gf100_fermi_ofuncs = {
228 .ctor = _nvkm_object_ctor,
229 .dtor = nvkm_object_destroy,
230 .init = nvkm_object_init,
231 .fini = nvkm_object_fini,
232 .mthd = gf100_fermi_mthd,
233 };
234
235 static int
236 gf100_gr_set_shader_exceptions(struct nvkm_object *object, u32 mthd,
237 void *pdata, u32 size)
238 {
239 struct gf100_gr_priv *priv = (void *)object->engine;
240 if (size >= sizeof(u32)) {
241 u32 data = *(u32 *)pdata ? 0xffffffff : 0x00000000;
242 nv_wr32(priv, 0x419e44, data);
243 nv_wr32(priv, 0x419e4c, data);
244 return 0;
245 }
246 return -EINVAL;
247 }
248
249 struct nvkm_omthds
250 gf100_gr_9097_omthds[] = {
251 { 0x1528, 0x1528, gf100_gr_set_shader_exceptions },
252 {}
253 };
254
255 struct nvkm_omthds
256 gf100_gr_90c0_omthds[] = {
257 { 0x1528, 0x1528, gf100_gr_set_shader_exceptions },
258 {}
259 };
260
261 struct nvkm_oclass
262 gf100_gr_sclass[] = {
263 { FERMI_TWOD_A, &nvkm_object_ofuncs },
264 { FERMI_MEMORY_TO_MEMORY_FORMAT_A, &nvkm_object_ofuncs },
265 { FERMI_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
266 { FERMI_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds },
267 {}
268 };
269
270 /*******************************************************************************
271 * PGRAPH context
272 ******************************************************************************/
273
274 int
275 gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
276 struct nvkm_oclass *oclass, void *args, u32 size,
277 struct nvkm_object **pobject)
278 {
279 struct nvkm_vm *vm = nvkm_client(parent)->vm;
280 struct gf100_gr_priv *priv = (void *)engine;
281 struct gf100_gr_data *data = priv->mmio_data;
282 struct gf100_gr_mmio *mmio = priv->mmio_list;
283 struct gf100_gr_chan *chan;
284 int ret, i;
285
286 /* allocate memory for context, and fill with default values */
287 ret = nvkm_gr_context_create(parent, engine, oclass, NULL,
288 priv->size, 0x100,
289 NVOBJ_FLAG_ZERO_ALLOC, &chan);
290 *pobject = nv_object(chan);
291 if (ret)
292 return ret;
293
294 /* allocate memory for a "mmio list" buffer that's used by the HUB
295 * fuc to modify some per-context register settings on first load
296 * of the context.
297 */
298 ret = nvkm_gpuobj_new(nv_object(chan), NULL, 0x1000, 0x100, 0,
299 &chan->mmio);
300 if (ret)
301 return ret;
302
303 ret = nvkm_gpuobj_map_vm(nv_gpuobj(chan->mmio), vm,
304 NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS,
305 &chan->mmio_vma);
306 if (ret)
307 return ret;
308
309 /* allocate buffers referenced by mmio list */
310 for (i = 0; data->size && i < ARRAY_SIZE(priv->mmio_data); i++) {
311 ret = nvkm_gpuobj_new(nv_object(chan), NULL, data->size,
312 data->align, 0, &chan->data[i].mem);
313 if (ret)
314 return ret;
315
316 ret = nvkm_gpuobj_map_vm(chan->data[i].mem, vm, data->access,
317 &chan->data[i].vma);
318 if (ret)
319 return ret;
320
321 data++;
322 }
323
324 /* finally, fill in the mmio list and point the context at it */
325 for (i = 0; mmio->addr && i < ARRAY_SIZE(priv->mmio_list); i++) {
326 u32 addr = mmio->addr;
327 u32 data = mmio->data;
328
329 if (mmio->buffer >= 0) {
330 u64 info = chan->data[mmio->buffer].vma.offset;
331 data |= info >> mmio->shift;
332 }
333
334 nv_wo32(chan->mmio, chan->mmio_nr++ * 4, addr);
335 nv_wo32(chan->mmio, chan->mmio_nr++ * 4, data);
336 mmio++;
337 }
338
339 for (i = 0; i < priv->size; i += 4)
340 nv_wo32(chan, i, priv->data[i / 4]);
341
342 if (!priv->firmware) {
343 nv_wo32(chan, 0x00, chan->mmio_nr / 2);
344 nv_wo32(chan, 0x04, chan->mmio_vma.offset >> 8);
345 } else {
346 nv_wo32(chan, 0xf4, 0);
347 nv_wo32(chan, 0xf8, 0);
348 nv_wo32(chan, 0x10, chan->mmio_nr / 2);
349 nv_wo32(chan, 0x14, lower_32_bits(chan->mmio_vma.offset));
350 nv_wo32(chan, 0x18, upper_32_bits(chan->mmio_vma.offset));
351 nv_wo32(chan, 0x1c, 1);
352 nv_wo32(chan, 0x20, 0);
353 nv_wo32(chan, 0x28, 0);
354 nv_wo32(chan, 0x2c, 0);
355 }
356
357 return 0;
358 }
359
360 void
361 gf100_gr_context_dtor(struct nvkm_object *object)
362 {
363 struct gf100_gr_chan *chan = (void *)object;
364 int i;
365
366 for (i = 0; i < ARRAY_SIZE(chan->data); i++) {
367 nvkm_gpuobj_unmap(&chan->data[i].vma);
368 nvkm_gpuobj_ref(NULL, &chan->data[i].mem);
369 }
370
371 nvkm_gpuobj_unmap(&chan->mmio_vma);
372 nvkm_gpuobj_ref(NULL, &chan->mmio);
373
374 nvkm_gr_context_destroy(&chan->base);
375 }
376
377 /*******************************************************************************
378 * PGRAPH register lists
379 ******************************************************************************/
380
381 const struct gf100_gr_init
382 gf100_gr_init_main_0[] = {
383 { 0x400080, 1, 0x04, 0x003083c2 },
384 { 0x400088, 1, 0x04, 0x00006fe7 },
385 { 0x40008c, 1, 0x04, 0x00000000 },
386 { 0x400090, 1, 0x04, 0x00000030 },
387 { 0x40013c, 1, 0x04, 0x013901f7 },
388 { 0x400140, 1, 0x04, 0x00000100 },
389 { 0x400144, 1, 0x04, 0x00000000 },
390 { 0x400148, 1, 0x04, 0x00000110 },
391 { 0x400138, 1, 0x04, 0x00000000 },
392 { 0x400130, 2, 0x04, 0x00000000 },
393 { 0x400124, 1, 0x04, 0x00000002 },
394 {}
395 };
396
397 const struct gf100_gr_init
398 gf100_gr_init_fe_0[] = {
399 { 0x40415c, 1, 0x04, 0x00000000 },
400 { 0x404170, 1, 0x04, 0x00000000 },
401 {}
402 };
403
404 const struct gf100_gr_init
405 gf100_gr_init_pri_0[] = {
406 { 0x404488, 2, 0x04, 0x00000000 },
407 {}
408 };
409
410 const struct gf100_gr_init
411 gf100_gr_init_rstr2d_0[] = {
412 { 0x407808, 1, 0x04, 0x00000000 },
413 {}
414 };
415
416 const struct gf100_gr_init
417 gf100_gr_init_pd_0[] = {
418 { 0x406024, 1, 0x04, 0x00000000 },
419 {}
420 };
421
422 const struct gf100_gr_init
423 gf100_gr_init_ds_0[] = {
424 { 0x405844, 1, 0x04, 0x00ffffff },
425 { 0x405850, 1, 0x04, 0x00000000 },
426 { 0x405908, 1, 0x04, 0x00000000 },
427 {}
428 };
429
430 const struct gf100_gr_init
431 gf100_gr_init_scc_0[] = {
432 { 0x40803c, 1, 0x04, 0x00000000 },
433 {}
434 };
435
436 const struct gf100_gr_init
437 gf100_gr_init_prop_0[] = {
438 { 0x4184a0, 1, 0x04, 0x00000000 },
439 {}
440 };
441
442 const struct gf100_gr_init
443 gf100_gr_init_gpc_unk_0[] = {
444 { 0x418604, 1, 0x04, 0x00000000 },
445 { 0x418680, 1, 0x04, 0x00000000 },
446 { 0x418714, 1, 0x04, 0x80000000 },
447 { 0x418384, 1, 0x04, 0x00000000 },
448 {}
449 };
450
451 const struct gf100_gr_init
452 gf100_gr_init_setup_0[] = {
453 { 0x418814, 3, 0x04, 0x00000000 },
454 {}
455 };
456
457 const struct gf100_gr_init
458 gf100_gr_init_crstr_0[] = {
459 { 0x418b04, 1, 0x04, 0x00000000 },
460 {}
461 };
462
463 const struct gf100_gr_init
464 gf100_gr_init_setup_1[] = {
465 { 0x4188c8, 1, 0x04, 0x80000000 },
466 { 0x4188cc, 1, 0x04, 0x00000000 },
467 { 0x4188d0, 1, 0x04, 0x00010000 },
468 { 0x4188d4, 1, 0x04, 0x00000001 },
469 {}
470 };
471
472 const struct gf100_gr_init
473 gf100_gr_init_zcull_0[] = {
474 { 0x418910, 1, 0x04, 0x00010001 },
475 { 0x418914, 1, 0x04, 0x00000301 },
476 { 0x418918, 1, 0x04, 0x00800000 },
477 { 0x418980, 1, 0x04, 0x77777770 },
478 { 0x418984, 3, 0x04, 0x77777777 },
479 {}
480 };
481
482 const struct gf100_gr_init
483 gf100_gr_init_gpm_0[] = {
484 { 0x418c04, 1, 0x04, 0x00000000 },
485 { 0x418c88, 1, 0x04, 0x00000000 },
486 {}
487 };
488
489 const struct gf100_gr_init
490 gf100_gr_init_gpc_unk_1[] = {
491 { 0x418d00, 1, 0x04, 0x00000000 },
492 { 0x418f08, 1, 0x04, 0x00000000 },
493 { 0x418e00, 1, 0x04, 0x00000050 },
494 { 0x418e08, 1, 0x04, 0x00000000 },
495 {}
496 };
497
498 const struct gf100_gr_init
499 gf100_gr_init_gcc_0[] = {
500 { 0x41900c, 1, 0x04, 0x00000000 },
501 { 0x419018, 1, 0x04, 0x00000000 },
502 {}
503 };
504
505 const struct gf100_gr_init
506 gf100_gr_init_tpccs_0[] = {
507 { 0x419d08, 2, 0x04, 0x00000000 },
508 { 0x419d10, 1, 0x04, 0x00000014 },
509 {}
510 };
511
512 const struct gf100_gr_init
513 gf100_gr_init_tex_0[] = {
514 { 0x419ab0, 1, 0x04, 0x00000000 },
515 { 0x419ab8, 1, 0x04, 0x000000e7 },
516 { 0x419abc, 2, 0x04, 0x00000000 },
517 {}
518 };
519
520 const struct gf100_gr_init
521 gf100_gr_init_pe_0[] = {
522 { 0x41980c, 3, 0x04, 0x00000000 },
523 { 0x419844, 1, 0x04, 0x00000000 },
524 { 0x41984c, 1, 0x04, 0x00005bc5 },
525 { 0x419850, 4, 0x04, 0x00000000 },
526 {}
527 };
528
529 const struct gf100_gr_init
530 gf100_gr_init_l1c_0[] = {
531 { 0x419c98, 1, 0x04, 0x00000000 },
532 { 0x419ca8, 1, 0x04, 0x80000000 },
533 { 0x419cb4, 1, 0x04, 0x00000000 },
534 { 0x419cb8, 1, 0x04, 0x00008bf4 },
535 { 0x419cbc, 1, 0x04, 0x28137606 },
536 { 0x419cc0, 2, 0x04, 0x00000000 },
537 {}
538 };
539
540 const struct gf100_gr_init
541 gf100_gr_init_wwdx_0[] = {
542 { 0x419bd4, 1, 0x04, 0x00800000 },
543 { 0x419bdc, 1, 0x04, 0x00000000 },
544 {}
545 };
546
547 const struct gf100_gr_init
548 gf100_gr_init_tpccs_1[] = {
549 { 0x419d2c, 1, 0x04, 0x00000000 },
550 {}
551 };
552
553 const struct gf100_gr_init
554 gf100_gr_init_mpc_0[] = {
555 { 0x419c0c, 1, 0x04, 0x00000000 },
556 {}
557 };
558
559 static const struct gf100_gr_init
560 gf100_gr_init_sm_0[] = {
561 { 0x419e00, 1, 0x04, 0x00000000 },
562 { 0x419ea0, 1, 0x04, 0x00000000 },
563 { 0x419ea4, 1, 0x04, 0x00000100 },
564 { 0x419ea8, 1, 0x04, 0x00001100 },
565 { 0x419eac, 1, 0x04, 0x11100702 },
566 { 0x419eb0, 1, 0x04, 0x00000003 },
567 { 0x419eb4, 4, 0x04, 0x00000000 },
568 { 0x419ec8, 1, 0x04, 0x06060618 },
569 { 0x419ed0, 1, 0x04, 0x0eff0e38 },
570 { 0x419ed4, 1, 0x04, 0x011104f1 },
571 { 0x419edc, 1, 0x04, 0x00000000 },
572 { 0x419f00, 1, 0x04, 0x00000000 },
573 { 0x419f2c, 1, 0x04, 0x00000000 },
574 {}
575 };
576
577 const struct gf100_gr_init
578 gf100_gr_init_be_0[] = {
579 { 0x40880c, 1, 0x04, 0x00000000 },
580 { 0x408910, 9, 0x04, 0x00000000 },
581 { 0x408950, 1, 0x04, 0x00000000 },
582 { 0x408954, 1, 0x04, 0x0000ffff },
583 { 0x408984, 1, 0x04, 0x00000000 },
584 { 0x408988, 1, 0x04, 0x08040201 },
585 { 0x40898c, 1, 0x04, 0x80402010 },
586 {}
587 };
588
589 const struct gf100_gr_init
590 gf100_gr_init_fe_1[] = {
591 { 0x4040f0, 1, 0x04, 0x00000000 },
592 {}
593 };
594
595 const struct gf100_gr_init
596 gf100_gr_init_pe_1[] = {
597 { 0x419880, 1, 0x04, 0x00000002 },
598 {}
599 };
600
601 static const struct gf100_gr_pack
602 gf100_gr_pack_mmio[] = {
603 { gf100_gr_init_main_0 },
604 { gf100_gr_init_fe_0 },
605 { gf100_gr_init_pri_0 },
606 { gf100_gr_init_rstr2d_0 },
607 { gf100_gr_init_pd_0 },
608 { gf100_gr_init_ds_0 },
609 { gf100_gr_init_scc_0 },
610 { gf100_gr_init_prop_0 },
611 { gf100_gr_init_gpc_unk_0 },
612 { gf100_gr_init_setup_0 },
613 { gf100_gr_init_crstr_0 },
614 { gf100_gr_init_setup_1 },
615 { gf100_gr_init_zcull_0 },
616 { gf100_gr_init_gpm_0 },
617 { gf100_gr_init_gpc_unk_1 },
618 { gf100_gr_init_gcc_0 },
619 { gf100_gr_init_tpccs_0 },
620 { gf100_gr_init_tex_0 },
621 { gf100_gr_init_pe_0 },
622 { gf100_gr_init_l1c_0 },
623 { gf100_gr_init_wwdx_0 },
624 { gf100_gr_init_tpccs_1 },
625 { gf100_gr_init_mpc_0 },
626 { gf100_gr_init_sm_0 },
627 { gf100_gr_init_be_0 },
628 { gf100_gr_init_fe_1 },
629 { gf100_gr_init_pe_1 },
630 {}
631 };
632
633 /*******************************************************************************
634 * PGRAPH engine/subdev functions
635 ******************************************************************************/
636
637 void
638 gf100_gr_zbc_init(struct gf100_gr_priv *priv)
639 {
640 const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000,
641 0x00000000, 0x00000000, 0x00000000, 0x00000000 };
642 const u32 one[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
643 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff };
644 const u32 f32_0[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000,
645 0x00000000, 0x00000000, 0x00000000, 0x00000000 };
646 const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
647 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 };
648 struct nvkm_ltc *ltc = nvkm_ltc(priv);
649 int index;
650
651 if (!priv->zbc_color[0].format) {
652 gf100_gr_zbc_color_get(priv, 1, & zero[0], &zero[4]);
653 gf100_gr_zbc_color_get(priv, 2, & one[0], &one[4]);
654 gf100_gr_zbc_color_get(priv, 4, &f32_0[0], &f32_0[4]);
655 gf100_gr_zbc_color_get(priv, 4, &f32_1[0], &f32_1[4]);
656 gf100_gr_zbc_depth_get(priv, 1, 0x00000000, 0x00000000);
657 gf100_gr_zbc_depth_get(priv, 1, 0x3f800000, 0x3f800000);
658 }
659
660 for (index = ltc->zbc_min; index <= ltc->zbc_max; index++)
661 gf100_gr_zbc_clear_color(priv, index);
662 for (index = ltc->zbc_min; index <= ltc->zbc_max; index++)
663 gf100_gr_zbc_clear_depth(priv, index);
664 }
665
666 void
667 gf100_gr_mmio(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p)
668 {
669 const struct gf100_gr_pack *pack;
670 const struct gf100_gr_init *init;
671
672 pack_for_each_init(init, pack, p) {
673 u32 next = init->addr + init->count * init->pitch;
674 u32 addr = init->addr;
675 while (addr < next) {
676 nv_wr32(priv, addr, init->data);
677 addr += init->pitch;
678 }
679 }
680 }
681
682 void
683 gf100_gr_icmd(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p)
684 {
685 const struct gf100_gr_pack *pack;
686 const struct gf100_gr_init *init;
687 u32 data = 0;
688
689 nv_wr32(priv, 0x400208, 0x80000000);
690
691 pack_for_each_init(init, pack, p) {
692 u32 next = init->addr + init->count * init->pitch;
693 u32 addr = init->addr;
694
695 if ((pack == p && init == p->init) || data != init->data) {
696 nv_wr32(priv, 0x400204, init->data);
697 data = init->data;
698 }
699
700 while (addr < next) {
701 nv_wr32(priv, 0x400200, addr);
702 nv_wait(priv, 0x400700, 0x00000004, 0x00000000);
703 addr += init->pitch;
704 }
705 }
706
707 nv_wr32(priv, 0x400208, 0x00000000);
708 }
709
710 void
711 gf100_gr_mthd(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p)
712 {
713 const struct gf100_gr_pack *pack;
714 const struct gf100_gr_init *init;
715 u32 data = 0;
716
717 pack_for_each_init(init, pack, p) {
718 u32 ctrl = 0x80000000 | pack->type;
719 u32 next = init->addr + init->count * init->pitch;
720 u32 addr = init->addr;
721
722 if ((pack == p && init == p->init) || data != init->data) {
723 nv_wr32(priv, 0x40448c, init->data);
724 data = init->data;
725 }
726
727 while (addr < next) {
728 nv_wr32(priv, 0x404488, ctrl | (addr << 14));
729 addr += init->pitch;
730 }
731 }
732 }
733
734 u64
735 gf100_gr_units(struct nvkm_gr *gr)
736 {
737 struct gf100_gr_priv *priv = (void *)gr;
738 u64 cfg;
739
740 cfg = (u32)priv->gpc_nr;
741 cfg |= (u32)priv->tpc_total << 8;
742 cfg |= (u64)priv->rop_nr << 32;
743
744 return cfg;
745 }
746
747 static const struct nvkm_enum gk104_sked_error[] = {
748 { 7, "CONSTANT_BUFFER_SIZE" },
749 { 9, "LOCAL_MEMORY_SIZE_POS" },
750 { 10, "LOCAL_MEMORY_SIZE_NEG" },
751 { 11, "WARP_CSTACK_SIZE" },
752 { 12, "TOTAL_TEMP_SIZE" },
753 { 13, "REGISTER_COUNT" },
754 { 18, "TOTAL_THREADS" },
755 { 20, "PROGRAM_OFFSET" },
756 { 21, "SHARED_MEMORY_SIZE" },
757 { 25, "SHARED_CONFIG_TOO_SMALL" },
758 { 26, "TOTAL_REGISTER_COUNT" },
759 {}
760 };
761
762 static const struct nvkm_enum gf100_gpc_rop_error[] = {
763 { 1, "RT_PITCH_OVERRUN" },
764 { 4, "RT_WIDTH_OVERRUN" },
765 { 5, "RT_HEIGHT_OVERRUN" },
766 { 7, "ZETA_STORAGE_TYPE_MISMATCH" },
767 { 8, "RT_STORAGE_TYPE_MISMATCH" },
768 { 10, "RT_LINEAR_MISMATCH" },
769 {}
770 };
771
772 static void
773 gf100_gr_trap_gpc_rop(struct gf100_gr_priv *priv, int gpc)
774 {
775 u32 trap[4];
776 int i;
777
778 trap[0] = nv_rd32(priv, GPC_UNIT(gpc, 0x0420));
779 trap[1] = nv_rd32(priv, GPC_UNIT(gpc, 0x0434));
780 trap[2] = nv_rd32(priv, GPC_UNIT(gpc, 0x0438));
781 trap[3] = nv_rd32(priv, GPC_UNIT(gpc, 0x043c));
782
783 nv_error(priv, "GPC%d/PROP trap:", gpc);
784 for (i = 0; i <= 29; ++i) {
785 if (!(trap[0] & (1 << i)))
786 continue;
787 pr_cont(" ");
788 nvkm_enum_print(gf100_gpc_rop_error, i);
789 }
790 pr_cont("\n");
791
792 nv_error(priv, "x = %u, y = %u, format = %x, storage type = %x\n",
793 trap[1] & 0xffff, trap[1] >> 16, (trap[2] >> 8) & 0x3f,
794 trap[3] & 0xff);
795 nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
796 }
797
798 static const struct nvkm_enum gf100_mp_warp_error[] = {
799 { 0x00, "NO_ERROR" },
800 { 0x01, "STACK_MISMATCH" },
801 { 0x05, "MISALIGNED_PC" },
802 { 0x08, "MISALIGNED_GPR" },
803 { 0x09, "INVALID_OPCODE" },
804 { 0x0d, "GPR_OUT_OF_BOUNDS" },
805 { 0x0e, "MEM_OUT_OF_BOUNDS" },
806 { 0x0f, "UNALIGNED_MEM_ACCESS" },
807 { 0x11, "INVALID_PARAM" },
808 {}
809 };
810
811 static const struct nvkm_bitfield gf100_mp_global_error[] = {
812 { 0x00000004, "MULTIPLE_WARP_ERRORS" },
813 { 0x00000008, "OUT_OF_STACK_SPACE" },
814 {}
815 };
816
817 static void
818 gf100_gr_trap_mp(struct gf100_gr_priv *priv, int gpc, int tpc)
819 {
820 u32 werr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x648));
821 u32 gerr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x650));
822
823 nv_error(priv, "GPC%i/TPC%i/MP trap:", gpc, tpc);
824 nvkm_bitfield_print(gf100_mp_global_error, gerr);
825 if (werr) {
826 pr_cont(" ");
827 nvkm_enum_print(gf100_mp_warp_error, werr & 0xffff);
828 }
829 pr_cont("\n");
830
831 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x648), 0x00000000);
832 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x650), gerr);
833 }
834
835 static void
836 gf100_gr_trap_tpc(struct gf100_gr_priv *priv, int gpc, int tpc)
837 {
838 u32 stat = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0508));
839
840 if (stat & 0x00000001) {
841 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0224));
842 nv_error(priv, "GPC%d/TPC%d/TEX: 0x%08x\n", gpc, tpc, trap);
843 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000);
844 stat &= ~0x00000001;
845 }
846
847 if (stat & 0x00000002) {
848 gf100_gr_trap_mp(priv, gpc, tpc);
849 stat &= ~0x00000002;
850 }
851
852 if (stat & 0x00000004) {
853 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0084));
854 nv_error(priv, "GPC%d/TPC%d/POLY: 0x%08x\n", gpc, tpc, trap);
855 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000);
856 stat &= ~0x00000004;
857 }
858
859 if (stat & 0x00000008) {
860 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x048c));
861 nv_error(priv, "GPC%d/TPC%d/L1C: 0x%08x\n", gpc, tpc, trap);
862 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000);
863 stat &= ~0x00000008;
864 }
865
866 if (stat) {
867 nv_error(priv, "GPC%d/TPC%d/0x%08x: unknown\n", gpc, tpc, stat);
868 }
869 }
870
871 static void
872 gf100_gr_trap_gpc(struct gf100_gr_priv *priv, int gpc)
873 {
874 u32 stat = nv_rd32(priv, GPC_UNIT(gpc, 0x2c90));
875 int tpc;
876
877 if (stat & 0x00000001) {
878 gf100_gr_trap_gpc_rop(priv, gpc);
879 stat &= ~0x00000001;
880 }
881
882 if (stat & 0x00000002) {
883 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0900));
884 nv_error(priv, "GPC%d/ZCULL: 0x%08x\n", gpc, trap);
885 nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
886 stat &= ~0x00000002;
887 }
888
889 if (stat & 0x00000004) {
890 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x1028));
891 nv_error(priv, "GPC%d/CCACHE: 0x%08x\n", gpc, trap);
892 nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
893 stat &= ~0x00000004;
894 }
895
896 if (stat & 0x00000008) {
897 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0824));
898 nv_error(priv, "GPC%d/ESETUP: 0x%08x\n", gpc, trap);
899 nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
900 stat &= ~0x00000009;
901 }
902
903 for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
904 u32 mask = 0x00010000 << tpc;
905 if (stat & mask) {
906 gf100_gr_trap_tpc(priv, gpc, tpc);
907 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), mask);
908 stat &= ~mask;
909 }
910 }
911
912 if (stat) {
913 nv_error(priv, "GPC%d/0x%08x: unknown\n", gpc, stat);
914 }
915 }
916
917 static void
918 gf100_gr_trap_intr(struct gf100_gr_priv *priv)
919 {
920 u32 trap = nv_rd32(priv, 0x400108);
921 int rop, gpc, i;
922
923 if (trap & 0x00000001) {
924 u32 stat = nv_rd32(priv, 0x404000);
925 nv_error(priv, "DISPATCH 0x%08x\n", stat);
926 nv_wr32(priv, 0x404000, 0xc0000000);
927 nv_wr32(priv, 0x400108, 0x00000001);
928 trap &= ~0x00000001;
929 }
930
931 if (trap & 0x00000002) {
932 u32 stat = nv_rd32(priv, 0x404600);
933 nv_error(priv, "M2MF 0x%08x\n", stat);
934 nv_wr32(priv, 0x404600, 0xc0000000);
935 nv_wr32(priv, 0x400108, 0x00000002);
936 trap &= ~0x00000002;
937 }
938
939 if (trap & 0x00000008) {
940 u32 stat = nv_rd32(priv, 0x408030);
941 nv_error(priv, "CCACHE 0x%08x\n", stat);
942 nv_wr32(priv, 0x408030, 0xc0000000);
943 nv_wr32(priv, 0x400108, 0x00000008);
944 trap &= ~0x00000008;
945 }
946
947 if (trap & 0x00000010) {
948 u32 stat = nv_rd32(priv, 0x405840);
949 nv_error(priv, "SHADER 0x%08x\n", stat);
950 nv_wr32(priv, 0x405840, 0xc0000000);
951 nv_wr32(priv, 0x400108, 0x00000010);
952 trap &= ~0x00000010;
953 }
954
955 if (trap & 0x00000040) {
956 u32 stat = nv_rd32(priv, 0x40601c);
957 nv_error(priv, "UNK6 0x%08x\n", stat);
958 nv_wr32(priv, 0x40601c, 0xc0000000);
959 nv_wr32(priv, 0x400108, 0x00000040);
960 trap &= ~0x00000040;
961 }
962
963 if (trap & 0x00000080) {
964 u32 stat = nv_rd32(priv, 0x404490);
965 nv_error(priv, "MACRO 0x%08x\n", stat);
966 nv_wr32(priv, 0x404490, 0xc0000000);
967 nv_wr32(priv, 0x400108, 0x00000080);
968 trap &= ~0x00000080;
969 }
970
971 if (trap & 0x00000100) {
972 u32 stat = nv_rd32(priv, 0x407020);
973
974 nv_error(priv, "SKED:");
975 for (i = 0; i <= 29; ++i) {
976 if (!(stat & (1 << i)))
977 continue;
978 pr_cont(" ");
979 nvkm_enum_print(gk104_sked_error, i);
980 }
981 pr_cont("\n");
982
983 if (stat & 0x3fffffff)
984 nv_wr32(priv, 0x407020, 0x40000000);
985 nv_wr32(priv, 0x400108, 0x00000100);
986 trap &= ~0x00000100;
987 }
988
989 if (trap & 0x01000000) {
990 u32 stat = nv_rd32(priv, 0x400118);
991 for (gpc = 0; stat && gpc < priv->gpc_nr; gpc++) {
992 u32 mask = 0x00000001 << gpc;
993 if (stat & mask) {
994 gf100_gr_trap_gpc(priv, gpc);
995 nv_wr32(priv, 0x400118, mask);
996 stat &= ~mask;
997 }
998 }
999 nv_wr32(priv, 0x400108, 0x01000000);
1000 trap &= ~0x01000000;
1001 }
1002
1003 if (trap & 0x02000000) {
1004 for (rop = 0; rop < priv->rop_nr; rop++) {
1005 u32 statz = nv_rd32(priv, ROP_UNIT(rop, 0x070));
1006 u32 statc = nv_rd32(priv, ROP_UNIT(rop, 0x144));
1007 nv_error(priv, "ROP%d 0x%08x 0x%08x\n",
1008 rop, statz, statc);
1009 nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
1010 nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
1011 }
1012 nv_wr32(priv, 0x400108, 0x02000000);
1013 trap &= ~0x02000000;
1014 }
1015
1016 if (trap) {
1017 nv_error(priv, "TRAP UNHANDLED 0x%08x\n", trap);
1018 nv_wr32(priv, 0x400108, trap);
1019 }
1020 }
1021
1022 static void
1023 gf100_gr_ctxctl_debug_unit(struct gf100_gr_priv *priv, u32 base)
1024 {
1025 nv_error(priv, "%06x - done 0x%08x\n", base,
1026 nv_rd32(priv, base + 0x400));
1027 nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
1028 nv_rd32(priv, base + 0x800), nv_rd32(priv, base + 0x804),
1029 nv_rd32(priv, base + 0x808), nv_rd32(priv, base + 0x80c));
1030 nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
1031 nv_rd32(priv, base + 0x810), nv_rd32(priv, base + 0x814),
1032 nv_rd32(priv, base + 0x818), nv_rd32(priv, base + 0x81c));
1033 }
1034
1035 void
1036 gf100_gr_ctxctl_debug(struct gf100_gr_priv *priv)
1037 {
1038 u32 gpcnr = nv_rd32(priv, 0x409604) & 0xffff;
1039 u32 gpc;
1040
1041 gf100_gr_ctxctl_debug_unit(priv, 0x409000);
1042 for (gpc = 0; gpc < gpcnr; gpc++)
1043 gf100_gr_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000));
1044 }
1045
1046 static void
1047 gf100_gr_ctxctl_isr(struct gf100_gr_priv *priv)
1048 {
1049 u32 stat = nv_rd32(priv, 0x409c18);
1050
1051 if (stat & 0x00000001) {
1052 u32 code = nv_rd32(priv, 0x409814);
1053 if (code == E_BAD_FWMTHD) {
1054 u32 class = nv_rd32(priv, 0x409808);
1055 u32 addr = nv_rd32(priv, 0x40980c);
1056 u32 subc = (addr & 0x00070000) >> 16;
1057 u32 mthd = (addr & 0x00003ffc);
1058 u32 data = nv_rd32(priv, 0x409810);
1059
1060 nv_error(priv, "FECS MTHD subc %d class 0x%04x "
1061 "mthd 0x%04x data 0x%08x\n",
1062 subc, class, mthd, data);
1063
1064 nv_wr32(priv, 0x409c20, 0x00000001);
1065 stat &= ~0x00000001;
1066 } else {
1067 nv_error(priv, "FECS ucode error %d\n", code);
1068 }
1069 }
1070
1071 if (stat & 0x00080000) {
1072 nv_error(priv, "FECS watchdog timeout\n");
1073 gf100_gr_ctxctl_debug(priv);
1074 nv_wr32(priv, 0x409c20, 0x00080000);
1075 stat &= ~0x00080000;
1076 }
1077
1078 if (stat) {
1079 nv_error(priv, "FECS 0x%08x\n", stat);
1080 gf100_gr_ctxctl_debug(priv);
1081 nv_wr32(priv, 0x409c20, stat);
1082 }
1083 }
1084
1085 static void
1086 gf100_gr_intr(struct nvkm_subdev *subdev)
1087 {
1088 struct nvkm_fifo *pfifo = nvkm_fifo(subdev);
1089 struct nvkm_engine *engine = nv_engine(subdev);
1090 struct nvkm_object *engctx;
1091 struct nvkm_handle *handle;
1092 struct gf100_gr_priv *priv = (void *)subdev;
1093 u64 inst = nv_rd32(priv, 0x409b00) & 0x0fffffff;
1094 u32 stat = nv_rd32(priv, 0x400100);
1095 u32 addr = nv_rd32(priv, 0x400704);
1096 u32 mthd = (addr & 0x00003ffc);
1097 u32 subc = (addr & 0x00070000) >> 16;
1098 u32 data = nv_rd32(priv, 0x400708);
1099 u32 code = nv_rd32(priv, 0x400110);
1100 u32 class;
1101 int chid;
1102
1103 if (nv_device(priv)->card_type < NV_E0 || subc < 4)
1104 class = nv_rd32(priv, 0x404200 + (subc * 4));
1105 else
1106 class = 0x0000;
1107
1108 engctx = nvkm_engctx_get(engine, inst);
1109 chid = pfifo->chid(pfifo, engctx);
1110
1111 if (stat & 0x00000001) {
1112 /*
1113 * notifier interrupt, only needed for cyclestats
1114 * can be safely ignored
1115 */
1116 nv_wr32(priv, 0x400100, 0x00000001);
1117 stat &= ~0x00000001;
1118 }
1119
1120 if (stat & 0x00000010) {
1121 handle = nvkm_handle_get_class(engctx, class);
1122 if (!handle || nv_call(handle->object, mthd, data)) {
1123 nv_error(priv,
1124 "ILLEGAL_MTHD ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
1125 chid, inst << 12, nvkm_client_name(engctx),
1126 subc, class, mthd, data);
1127 }
1128 nvkm_handle_put(handle);
1129 nv_wr32(priv, 0x400100, 0x00000010);
1130 stat &= ~0x00000010;
1131 }
1132
1133 if (stat & 0x00000020) {
1134 nv_error(priv,
1135 "ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
1136 chid, inst << 12, nvkm_client_name(engctx), subc,
1137 class, mthd, data);
1138 nv_wr32(priv, 0x400100, 0x00000020);
1139 stat &= ~0x00000020;
1140 }
1141
1142 if (stat & 0x00100000) {
1143 nv_error(priv, "DATA_ERROR [");
1144 nvkm_enum_print(nv50_data_error_names, code);
1145 pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
1146 chid, inst << 12, nvkm_client_name(engctx), subc,
1147 class, mthd, data);
1148 nv_wr32(priv, 0x400100, 0x00100000);
1149 stat &= ~0x00100000;
1150 }
1151
1152 if (stat & 0x00200000) {
1153 nv_error(priv, "TRAP ch %d [0x%010llx %s]\n", chid, inst << 12,
1154 nvkm_client_name(engctx));
1155 gf100_gr_trap_intr(priv);
1156 nv_wr32(priv, 0x400100, 0x00200000);
1157 stat &= ~0x00200000;
1158 }
1159
1160 if (stat & 0x00080000) {
1161 gf100_gr_ctxctl_isr(priv);
1162 nv_wr32(priv, 0x400100, 0x00080000);
1163 stat &= ~0x00080000;
1164 }
1165
1166 if (stat) {
1167 nv_error(priv, "unknown stat 0x%08x\n", stat);
1168 nv_wr32(priv, 0x400100, stat);
1169 }
1170
1171 nv_wr32(priv, 0x400500, 0x00010001);
1172 nvkm_engctx_put(engctx);
1173 }
1174
1175 void
1176 gf100_gr_init_fw(struct gf100_gr_priv *priv, u32 fuc_base,
1177 struct gf100_gr_fuc *code, struct gf100_gr_fuc *data)
1178 {
1179 int i;
1180
1181 nv_wr32(priv, fuc_base + 0x01c0, 0x01000000);
1182 for (i = 0; i < data->size / 4; i++)
1183 nv_wr32(priv, fuc_base + 0x01c4, data->data[i]);
1184
1185 nv_wr32(priv, fuc_base + 0x0180, 0x01000000);
1186 for (i = 0; i < code->size / 4; i++) {
1187 if ((i & 0x3f) == 0)
1188 nv_wr32(priv, fuc_base + 0x0188, i >> 6);
1189 nv_wr32(priv, fuc_base + 0x0184, code->data[i]);
1190 }
1191
1192 /* code must be padded to 0x40 words */
1193 for (; i & 0x3f; i++)
1194 nv_wr32(priv, fuc_base + 0x0184, 0);
1195 }
1196
1197 static void
1198 gf100_gr_init_csdata(struct gf100_gr_priv *priv,
1199 const struct gf100_gr_pack *pack,
1200 u32 falcon, u32 starstar, u32 base)
1201 {
1202 const struct gf100_gr_pack *iter;
1203 const struct gf100_gr_init *init;
1204 u32 addr = ~0, prev = ~0, xfer = 0;
1205 u32 star, temp;
1206
1207 nv_wr32(priv, falcon + 0x01c0, 0x02000000 + starstar);
1208 star = nv_rd32(priv, falcon + 0x01c4);
1209 temp = nv_rd32(priv, falcon + 0x01c4);
1210 if (temp > star)
1211 star = temp;
1212 nv_wr32(priv, falcon + 0x01c0, 0x01000000 + star);
1213
1214 pack_for_each_init(init, iter, pack) {
1215 u32 head = init->addr - base;
1216 u32 tail = head + init->count * init->pitch;
1217 while (head < tail) {
1218 if (head != prev + 4 || xfer >= 32) {
1219 if (xfer) {
1220 u32 data = ((--xfer << 26) | addr);
1221 nv_wr32(priv, falcon + 0x01c4, data);
1222 star += 4;
1223 }
1224 addr = head;
1225 xfer = 0;
1226 }
1227 prev = head;
1228 xfer = xfer + 1;
1229 head = head + init->pitch;
1230 }
1231 }
1232
1233 nv_wr32(priv, falcon + 0x01c4, (--xfer << 26) | addr);
1234 nv_wr32(priv, falcon + 0x01c0, 0x01000004 + starstar);
1235 nv_wr32(priv, falcon + 0x01c4, star + 4);
1236 }
1237
1238 int
1239 gf100_gr_init_ctxctl(struct gf100_gr_priv *priv)
1240 {
1241 struct gf100_gr_oclass *oclass = (void *)nv_object(priv)->oclass;
1242 struct gf100_grctx_oclass *cclass = (void *)nv_engine(priv)->cclass;
1243 int i;
1244
1245 if (priv->firmware) {
1246 /* load fuc microcode */
1247 nvkm_mc(priv)->unk260(nvkm_mc(priv), 0);
1248 gf100_gr_init_fw(priv, 0x409000, &priv->fuc409c,
1249 &priv->fuc409d);
1250 gf100_gr_init_fw(priv, 0x41a000, &priv->fuc41ac,
1251 &priv->fuc41ad);
1252 nvkm_mc(priv)->unk260(nvkm_mc(priv), 1);
1253
1254 /* start both of them running */
1255 nv_wr32(priv, 0x409840, 0xffffffff);
1256 nv_wr32(priv, 0x41a10c, 0x00000000);
1257 nv_wr32(priv, 0x40910c, 0x00000000);
1258 nv_wr32(priv, 0x41a100, 0x00000002);
1259 nv_wr32(priv, 0x409100, 0x00000002);
1260 if (!nv_wait(priv, 0x409800, 0x00000001, 0x00000001))
1261 nv_warn(priv, "0x409800 wait failed\n");
1262
1263 nv_wr32(priv, 0x409840, 0xffffffff);
1264 nv_wr32(priv, 0x409500, 0x7fffffff);
1265 nv_wr32(priv, 0x409504, 0x00000021);
1266
1267 nv_wr32(priv, 0x409840, 0xffffffff);
1268 nv_wr32(priv, 0x409500, 0x00000000);
1269 nv_wr32(priv, 0x409504, 0x00000010);
1270 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
1271 nv_error(priv, "fuc09 req 0x10 timeout\n");
1272 return -EBUSY;
1273 }
1274 priv->size = nv_rd32(priv, 0x409800);
1275
1276 nv_wr32(priv, 0x409840, 0xffffffff);
1277 nv_wr32(priv, 0x409500, 0x00000000);
1278 nv_wr32(priv, 0x409504, 0x00000016);
1279 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
1280 nv_error(priv, "fuc09 req 0x16 timeout\n");
1281 return -EBUSY;
1282 }
1283
1284 nv_wr32(priv, 0x409840, 0xffffffff);
1285 nv_wr32(priv, 0x409500, 0x00000000);
1286 nv_wr32(priv, 0x409504, 0x00000025);
1287 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
1288 nv_error(priv, "fuc09 req 0x25 timeout\n");
1289 return -EBUSY;
1290 }
1291
1292 if (nv_device(priv)->chipset >= 0xe0) {
1293 nv_wr32(priv, 0x409800, 0x00000000);
1294 nv_wr32(priv, 0x409500, 0x00000001);
1295 nv_wr32(priv, 0x409504, 0x00000030);
1296 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
1297 nv_error(priv, "fuc09 req 0x30 timeout\n");
1298 return -EBUSY;
1299 }
1300
1301 nv_wr32(priv, 0x409810, 0xb00095c8);
1302 nv_wr32(priv, 0x409800, 0x00000000);
1303 nv_wr32(priv, 0x409500, 0x00000001);
1304 nv_wr32(priv, 0x409504, 0x00000031);
1305 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
1306 nv_error(priv, "fuc09 req 0x31 timeout\n");
1307 return -EBUSY;
1308 }
1309
1310 nv_wr32(priv, 0x409810, 0x00080420);
1311 nv_wr32(priv, 0x409800, 0x00000000);
1312 nv_wr32(priv, 0x409500, 0x00000001);
1313 nv_wr32(priv, 0x409504, 0x00000032);
1314 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
1315 nv_error(priv, "fuc09 req 0x32 timeout\n");
1316 return -EBUSY;
1317 }
1318
1319 nv_wr32(priv, 0x409614, 0x00000070);
1320 nv_wr32(priv, 0x409614, 0x00000770);
1321 nv_wr32(priv, 0x40802c, 0x00000001);
1322 }
1323
1324 if (priv->data == NULL) {
1325 int ret = gf100_grctx_generate(priv);
1326 if (ret) {
1327 nv_error(priv, "failed to construct context\n");
1328 return ret;
1329 }
1330 }
1331
1332 return 0;
1333 } else
1334 if (!oclass->fecs.ucode) {
1335 return -ENOSYS;
1336 }
1337
1338 /* load HUB microcode */
1339 nvkm_mc(priv)->unk260(nvkm_mc(priv), 0);
1340 nv_wr32(priv, 0x4091c0, 0x01000000);
1341 for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++)
1342 nv_wr32(priv, 0x4091c4, oclass->fecs.ucode->data.data[i]);
1343
1344 nv_wr32(priv, 0x409180, 0x01000000);
1345 for (i = 0; i < oclass->fecs.ucode->code.size / 4; i++) {
1346 if ((i & 0x3f) == 0)
1347 nv_wr32(priv, 0x409188, i >> 6);
1348 nv_wr32(priv, 0x409184, oclass->fecs.ucode->code.data[i]);
1349 }
1350
1351 /* load GPC microcode */
1352 nv_wr32(priv, 0x41a1c0, 0x01000000);
1353 for (i = 0; i < oclass->gpccs.ucode->data.size / 4; i++)
1354 nv_wr32(priv, 0x41a1c4, oclass->gpccs.ucode->data.data[i]);
1355
1356 nv_wr32(priv, 0x41a180, 0x01000000);
1357 for (i = 0; i < oclass->gpccs.ucode->code.size / 4; i++) {
1358 if ((i & 0x3f) == 0)
1359 nv_wr32(priv, 0x41a188, i >> 6);
1360 nv_wr32(priv, 0x41a184, oclass->gpccs.ucode->code.data[i]);
1361 }
1362 nvkm_mc(priv)->unk260(nvkm_mc(priv), 1);
1363
1364 /* load register lists */
1365 gf100_gr_init_csdata(priv, cclass->hub, 0x409000, 0x000, 0x000000);
1366 gf100_gr_init_csdata(priv, cclass->gpc, 0x41a000, 0x000, 0x418000);
1367 gf100_gr_init_csdata(priv, cclass->tpc, 0x41a000, 0x004, 0x419800);
1368 gf100_gr_init_csdata(priv, cclass->ppc, 0x41a000, 0x008, 0x41be00);
1369
1370 /* start HUB ucode running, it'll init the GPCs */
1371 nv_wr32(priv, 0x40910c, 0x00000000);
1372 nv_wr32(priv, 0x409100, 0x00000002);
1373 if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) {
1374 nv_error(priv, "HUB_INIT timed out\n");
1375 gf100_gr_ctxctl_debug(priv);
1376 return -EBUSY;
1377 }
1378
1379 priv->size = nv_rd32(priv, 0x409804);
1380 if (priv->data == NULL) {
1381 int ret = gf100_grctx_generate(priv);
1382 if (ret) {
1383 nv_error(priv, "failed to construct context\n");
1384 return ret;
1385 }
1386 }
1387
1388 return 0;
1389 }
1390
1391 int
1392 gf100_gr_init(struct nvkm_object *object)
1393 {
1394 struct gf100_gr_oclass *oclass = (void *)object->oclass;
1395 struct gf100_gr_priv *priv = (void *)object;
1396 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
1397 u32 data[TPC_MAX / 8] = {};
1398 u8 tpcnr[GPC_MAX];
1399 int gpc, tpc, rop;
1400 int ret, i;
1401
1402 ret = nvkm_gr_init(&priv->base);
1403 if (ret)
1404 return ret;
1405
1406 nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000);
1407 nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000);
1408 nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000);
1409 nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000);
1410 nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000);
1411 nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000);
1412 nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
1413 nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
1414
1415 gf100_gr_mmio(priv, oclass->mmio);
1416
1417 memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
1418 for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
1419 do {
1420 gpc = (gpc + 1) % priv->gpc_nr;
1421 } while (!tpcnr[gpc]);
1422 tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
1423
1424 data[i / 8] |= tpc << ((i % 8) * 4);
1425 }
1426
1427 nv_wr32(priv, GPC_BCAST(0x0980), data[0]);
1428 nv_wr32(priv, GPC_BCAST(0x0984), data[1]);
1429 nv_wr32(priv, GPC_BCAST(0x0988), data[2]);
1430 nv_wr32(priv, GPC_BCAST(0x098c), data[3]);
1431
1432 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
1433 nv_wr32(priv, GPC_UNIT(gpc, 0x0914),
1434 priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]);
1435 nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 |
1436 priv->tpc_total);
1437 nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918);
1438 }
1439
1440 if (nv_device(priv)->chipset != 0xd7)
1441 nv_wr32(priv, GPC_BCAST(0x1bd4), magicgpc918);
1442 else
1443 nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918);
1444
1445 nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800));
1446
1447 nv_wr32(priv, 0x400500, 0x00010001);
1448
1449 nv_wr32(priv, 0x400100, 0xffffffff);
1450 nv_wr32(priv, 0x40013c, 0xffffffff);
1451
1452 nv_wr32(priv, 0x409c24, 0x000f0000);
1453 nv_wr32(priv, 0x404000, 0xc0000000);
1454 nv_wr32(priv, 0x404600, 0xc0000000);
1455 nv_wr32(priv, 0x408030, 0xc0000000);
1456 nv_wr32(priv, 0x40601c, 0xc0000000);
1457 nv_wr32(priv, 0x404490, 0xc0000000);
1458 nv_wr32(priv, 0x406018, 0xc0000000);
1459 nv_wr32(priv, 0x405840, 0xc0000000);
1460 nv_wr32(priv, 0x405844, 0x00ffffff);
1461 nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008);
1462 nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000);
1463
1464 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
1465 nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
1466 nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
1467 nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
1468 nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
1469 for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
1470 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
1471 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
1472 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
1473 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
1474 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
1475 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
1476 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
1477 }
1478 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
1479 nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
1480 }
1481
1482 for (rop = 0; rop < priv->rop_nr; rop++) {
1483 nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
1484 nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
1485 nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff);
1486 nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff);
1487 }
1488
1489 nv_wr32(priv, 0x400108, 0xffffffff);
1490 nv_wr32(priv, 0x400138, 0xffffffff);
1491 nv_wr32(priv, 0x400118, 0xffffffff);
1492 nv_wr32(priv, 0x400130, 0xffffffff);
1493 nv_wr32(priv, 0x40011c, 0xffffffff);
1494 nv_wr32(priv, 0x400134, 0xffffffff);
1495
1496 nv_wr32(priv, 0x400054, 0x34ce3464);
1497
1498 gf100_gr_zbc_init(priv);
1499
1500 return gf100_gr_init_ctxctl(priv);
1501 }
1502
1503 static void
1504 gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc)
1505 {
1506 kfree(fuc->data);
1507 fuc->data = NULL;
1508 }
1509
1510 int
1511 gf100_gr_ctor_fw(struct gf100_gr_priv *priv, const char *fwname,
1512 struct gf100_gr_fuc *fuc)
1513 {
1514 struct nvkm_device *device = nv_device(priv);
1515 const struct firmware *fw;
1516 char f[32];
1517 int ret;
1518
1519 snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, fwname);
1520 ret = request_firmware(&fw, f, nv_device_base(device));
1521 if (ret) {
1522 snprintf(f, sizeof(f), "nouveau/%s", fwname);
1523 ret = request_firmware(&fw, f, nv_device_base(device));
1524 if (ret) {
1525 nv_error(priv, "failed to load %s\n", fwname);
1526 return ret;
1527 }
1528 }
1529
1530 fuc->size = fw->size;
1531 fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL);
1532 release_firmware(fw);
1533 return (fuc->data != NULL) ? 0 : -ENOMEM;
1534 }
1535
1536 void
1537 gf100_gr_dtor(struct nvkm_object *object)
1538 {
1539 struct gf100_gr_priv *priv = (void *)object;
1540
1541 kfree(priv->data);
1542
1543 gf100_gr_dtor_fw(&priv->fuc409c);
1544 gf100_gr_dtor_fw(&priv->fuc409d);
1545 gf100_gr_dtor_fw(&priv->fuc41ac);
1546 gf100_gr_dtor_fw(&priv->fuc41ad);
1547
1548 nvkm_gpuobj_ref(NULL, &priv->unk4188b8);
1549 nvkm_gpuobj_ref(NULL, &priv->unk4188b4);
1550
1551 nvkm_gr_destroy(&priv->base);
1552 }
1553
1554 int
1555 gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
1556 struct nvkm_oclass *bclass, void *data, u32 size,
1557 struct nvkm_object **pobject)
1558 {
1559 struct gf100_gr_oclass *oclass = (void *)bclass;
1560 struct nvkm_device *device = nv_device(parent);
1561 struct gf100_gr_priv *priv;
1562 bool use_ext_fw, enable;
1563 int ret, i, j;
1564
1565 use_ext_fw = nvkm_boolopt(device->cfgopt, "NvGrUseFW",
1566 oclass->fecs.ucode == NULL);
1567 enable = use_ext_fw || oclass->fecs.ucode != NULL;
1568
1569 ret = nvkm_gr_create(parent, engine, bclass, enable, &priv);
1570 *pobject = nv_object(priv);
1571 if (ret)
1572 return ret;
1573
1574 nv_subdev(priv)->unit = 0x08001000;
1575 nv_subdev(priv)->intr = gf100_gr_intr;
1576
1577 priv->base.units = gf100_gr_units;
1578
1579 if (use_ext_fw) {
1580 nv_info(priv, "using external firmware\n");
1581 if (gf100_gr_ctor_fw(priv, "fuc409c", &priv->fuc409c) ||
1582 gf100_gr_ctor_fw(priv, "fuc409d", &priv->fuc409d) ||
1583 gf100_gr_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) ||
1584 gf100_gr_ctor_fw(priv, "fuc41ad", &priv->fuc41ad))
1585 return -ENODEV;
1586 priv->firmware = true;
1587 }
1588
1589 ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
1590 &priv->unk4188b4);
1591 if (ret)
1592 return ret;
1593
1594 ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
1595 &priv->unk4188b8);
1596 if (ret)
1597 return ret;
1598
1599 for (i = 0; i < 0x1000; i += 4) {
1600 nv_wo32(priv->unk4188b4, i, 0x00000010);
1601 nv_wo32(priv->unk4188b8, i, 0x00000010);
1602 }
1603
1604 priv->rop_nr = (nv_rd32(priv, 0x409604) & 0x001f0000) >> 16;
1605 priv->gpc_nr = nv_rd32(priv, 0x409604) & 0x0000001f;
1606 for (i = 0; i < priv->gpc_nr; i++) {
1607 priv->tpc_nr[i] = nv_rd32(priv, GPC_UNIT(i, 0x2608));
1608 priv->tpc_total += priv->tpc_nr[i];
1609 priv->ppc_nr[i] = oclass->ppc_nr;
1610 for (j = 0; j < priv->ppc_nr[i]; j++) {
1611 u8 mask = nv_rd32(priv, GPC_UNIT(i, 0x0c30 + (j * 4)));
1612 priv->ppc_tpc_nr[i][j] = hweight8(mask);
1613 }
1614 }
1615
1616 /*XXX: these need figuring out... though it might not even matter */
1617 switch (nv_device(priv)->chipset) {
1618 case 0xc0:
1619 if (priv->tpc_total == 11) { /* 465, 3/4/4/0, 4 */
1620 priv->magic_not_rop_nr = 0x07;
1621 } else
1622 if (priv->tpc_total == 14) { /* 470, 3/3/4/4, 5 */
1623 priv->magic_not_rop_nr = 0x05;
1624 } else
1625 if (priv->tpc_total == 15) { /* 480, 3/4/4/4, 6 */
1626 priv->magic_not_rop_nr = 0x06;
1627 }
1628 break;
1629 case 0xc3: /* 450, 4/0/0/0, 2 */
1630 priv->magic_not_rop_nr = 0x03;
1631 break;
1632 case 0xc4: /* 460, 3/4/0/0, 4 */
1633 priv->magic_not_rop_nr = 0x01;
1634 break;
1635 case 0xc1: /* 2/0/0/0, 1 */
1636 priv->magic_not_rop_nr = 0x01;
1637 break;
1638 case 0xc8: /* 4/4/3/4, 5 */
1639 priv->magic_not_rop_nr = 0x06;
1640 break;
1641 case 0xce: /* 4/4/0/0, 4 */
1642 priv->magic_not_rop_nr = 0x03;
1643 break;
1644 case 0xcf: /* 4/0/0/0, 3 */
1645 priv->magic_not_rop_nr = 0x03;
1646 break;
1647 case 0xd7:
1648 case 0xd9: /* 1/0/0/0, 1 */
1649 priv->magic_not_rop_nr = 0x01;
1650 break;
1651 }
1652
1653 nv_engine(priv)->cclass = *oclass->cclass;
1654 nv_engine(priv)->sclass = oclass->sclass;
1655 return 0;
1656 }
1657
1658 #include "fuc/hubgf100.fuc3.h"
1659
1660 struct gf100_gr_ucode
1661 gf100_gr_fecs_ucode = {
1662 .code.data = gf100_grhub_code,
1663 .code.size = sizeof(gf100_grhub_code),
1664 .data.data = gf100_grhub_data,
1665 .data.size = sizeof(gf100_grhub_data),
1666 };
1667
1668 #include "fuc/gpcgf100.fuc3.h"
1669
1670 struct gf100_gr_ucode
1671 gf100_gr_gpccs_ucode = {
1672 .code.data = gf100_grgpc_code,
1673 .code.size = sizeof(gf100_grgpc_code),
1674 .data.data = gf100_grgpc_data,
1675 .data.size = sizeof(gf100_grgpc_data),
1676 };
1677
1678 struct nvkm_oclass *
1679 gf100_gr_oclass = &(struct gf100_gr_oclass) {
1680 .base.handle = NV_ENGINE(GR, 0xc0),
1681 .base.ofuncs = &(struct nvkm_ofuncs) {
1682 .ctor = gf100_gr_ctor,
1683 .dtor = gf100_gr_dtor,
1684 .init = gf100_gr_init,
1685 .fini = _nvkm_gr_fini,
1686 },
1687 .cclass = &gf100_grctx_oclass,
1688 .sclass = gf100_gr_sclass,
1689 .mmio = gf100_gr_pack_mmio,
1690 .fecs.ucode = &gf100_gr_fecs_ucode,
1691 .gpccs.ucode = &gf100_gr_gpccs_ucode,
1692 }.base;
Linux kernel - Deliverables
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