drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c

   1 /*
   2  * Copyright 2014 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "priv.h"
  25
  26 #include <subdev/fb.h>
  27 #include <subdev/timer.h>
  28
  29 void
  30 gm107_ltc_cbc_clear(struct nvkm_ltc *ltc, u32 start, u32 limit)
  31 {
  32         struct nvkm_device *device = ltc->subdev.device;
  33         nvkm_wr32(device, 0x17e270, start);
  34         nvkm_wr32(device, 0x17e274, limit);
  35         nvkm_mask(device, 0x17e26c, 0x00000000, 0x00000004);
  36 }
  37
  38 void
  39 gm107_ltc_cbc_wait(struct nvkm_ltc *ltc)
  40 {
  41         struct nvkm_device *device = ltc->subdev.device;
  42         int c, s;
  43         for (c = 0; c < ltc->ltc_nr; c++) {
  44                 for (s = 0; s < ltc->lts_nr; s++) {
  45                         const u32 addr = 0x14046c + (c * 0x2000) + (s * 0x200);
  46                         nvkm_wait_msec(device, 2000, addr,
  47                                        0x00000004, 0x00000000);
  48                 }
  49         }
  50 }
  51
  52 void
  53 gm107_ltc_zbc_clear_color(struct nvkm_ltc *ltc, int i, const u32 color[4])
  54 {
  55         struct nvkm_device *device = ltc->subdev.device;
  56         nvkm_mask(device, 0x17e338, 0x0000000f, i);
  57         nvkm_wr32(device, 0x17e33c, color[0]);
  58         nvkm_wr32(device, 0x17e340, color[1]);
  59         nvkm_wr32(device, 0x17e344, color[2]);
  60         nvkm_wr32(device, 0x17e348, color[3]);
  61 }
  62
  63 void
  64 gm107_ltc_zbc_clear_depth(struct nvkm_ltc *ltc, int i, const u32 depth)
  65 {
  66         struct nvkm_device *device = ltc->subdev.device;
  67         nvkm_mask(device, 0x17e338, 0x0000000f, i);
  68         nvkm_wr32(device, 0x17e34c, depth);
  69 }
  70
  71 static void
  72 gm107_ltc_lts_isr(struct nvkm_ltc *ltc, int c, int s)
  73 {
  74         struct nvkm_subdev *subdev = &ltc->subdev;
  75         struct nvkm_device *device = subdev->device;
  76         u32 base = 0x140000 + (c * 0x2000) + (s * 0x200);
  77         u32 stat = nvkm_rd32(device, base + 0x00c);
  78
  79         if (stat) {
  80                 nvkm_error(subdev, "LTC%d_LTS%d: %08x\n", c, s, stat);
  81                 nvkm_wr32(device, base + 0x00c, stat);
  82         }
  83 }
  84
  85 void
  86 gm107_ltc_intr(struct nvkm_ltc *ltc)
  87 {
  88         struct nvkm_device *device = ltc->subdev.device;
  89         u32 mask;
  90
  91         mask = nvkm_rd32(device, 0x00017c);
  92         while (mask) {
  93                 u32 s, c = __ffs(mask);
  94                 for (s = 0; s < ltc->lts_nr; s++)
  95                         gm107_ltc_lts_isr(ltc, c, s);
  96                 mask &= ~(1 << c);
  97         }
  98 }
  99
 100 static int
 101 gm107_ltc_oneinit(struct nvkm_ltc *ltc)
 102 {
 103         struct nvkm_device *device = ltc->subdev.device;
 104         const u32 parts = nvkm_rd32(device, 0x022438);
 105         const u32  mask = nvkm_rd32(device, 0x021c14);
 106         const u32 slice = nvkm_rd32(device, 0x17e280) >> 28;
 107         int i;
 108
 109         for (i = 0; i < parts; i++) {
 110                 if (!(mask & (1 << i)))
 111                         ltc->ltc_nr++;
 112         }
 113         ltc->lts_nr = slice;
 114
 115         return gf100_ltc_oneinit_tag_ram(ltc);
 116 }
 117
 118 static void
 119 gm107_ltc_init(struct nvkm_ltc *ltc)
 120 {
 121         struct nvkm_device *device = ltc->subdev.device;
 122         u32 lpg128 = !(nvkm_rd32(device, 0x100c80) & 0x00000001);
 123
 124         nvkm_wr32(device, 0x17e27c, ltc->ltc_nr);
 125         nvkm_wr32(device, 0x17e278, ltc->tag_base);
 126         nvkm_mask(device, 0x17e264, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
 127 }
 128
 129 static const struct nvkm_ltc_func
 130 gm107_ltc = {
 131         .oneinit = gm107_ltc_oneinit,
 132         .init = gm107_ltc_init,
 133         .intr = gm107_ltc_intr,
 134         .cbc_clear = gm107_ltc_cbc_clear,
 135         .cbc_wait = gm107_ltc_cbc_wait,
 136         .zbc = 16,
 137         .zbc_clear_color = gm107_ltc_zbc_clear_color,
 138         .zbc_clear_depth = gm107_ltc_zbc_clear_depth,
 139         .invalidate = gf100_ltc_invalidate,
 140         .flush = gf100_ltc_flush,
 141 };
 142
 143 int
 144 gm107_ltc_new(struct nvkm_device *device, int index, struct nvkm_ltc **pltc)
 145 {
 146         return nvkm_ltc_new_(&gm107_ltc, device, index, pltc);
 147 }