2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
25 #include <core/gpuobj.h>
28 * The BL header format used by GM20B's firmware is slightly different
29 * from the one of GM200. Fix the differences here.
31 struct gm20b_flcn_bl_desc
{
37 u32 non_sec_code_size
;
46 * gm20b_secboot_fixup_bl_desc - adapt BL descriptor to format used by GM20B FW
48 * There is only a slight format difference (DMA addresses being 32-bits and
49 * 256B-aligned) to address.
52 gm20b_secboot_fixup_bl_desc(const struct gm200_flcn_bl_desc
*desc
, void *ret
)
54 struct gm20b_flcn_bl_desc
*gdesc
= ret
;
57 memcpy(gdesc
->reserved
, desc
->reserved
, sizeof(gdesc
->reserved
));
58 memcpy(gdesc
->signature
, desc
->signature
, sizeof(gdesc
->signature
));
59 gdesc
->ctx_dma
= desc
->ctx_dma
;
60 addr
= desc
->code_dma_base
.hi
;
62 addr
|= desc
->code_dma_base
.lo
;
63 gdesc
->code_dma_base
= lower_32_bits(addr
>> 8);
64 gdesc
->non_sec_code_off
= desc
->non_sec_code_off
;
65 gdesc
->non_sec_code_size
= desc
->non_sec_code_size
;
66 gdesc
->sec_code_off
= desc
->sec_code_off
;
67 gdesc
->sec_code_size
= desc
->sec_code_size
;
68 gdesc
->code_entry_point
= desc
->code_entry_point
;
69 addr
= desc
->data_dma_base
.hi
;
71 addr
|= desc
->data_dma_base
.lo
;
72 gdesc
->data_dma_base
= lower_32_bits(addr
>> 8);
73 gdesc
->data_size
= desc
->data_size
;
77 gm20b_secboot_fixup_hs_desc(struct gm200_secboot
*gsb
,
78 struct hsflcn_acr_desc
*desc
)
80 desc
->ucode_blob_base
= gsb
->ls_blob
->addr
;
81 desc
->ucode_blob_size
= gsb
->ls_blob
->size
;
86 static const struct gm200_secboot_func
87 gm20b_secboot_func
= {
88 .bl_desc_size
= sizeof(struct gm20b_flcn_bl_desc
),
89 .fixup_bl_desc
= gm20b_secboot_fixup_bl_desc
,
90 .fixup_hs_desc
= gm20b_secboot_fixup_hs_desc
,
94 #ifdef CONFIG_ARCH_TEGRA
95 #define TEGRA_MC_BASE 0x70019000
96 #define MC_SECURITY_CARVEOUT2_CFG0 0xc58
97 #define MC_SECURITY_CARVEOUT2_BOM_0 0xc5c
98 #define MC_SECURITY_CARVEOUT2_BOM_HI_0 0xc60
99 #define MC_SECURITY_CARVEOUT2_SIZE_128K 0xc64
100 #define TEGRA_MC_SECURITY_CARVEOUT_CFG_LOCKED (1 << 1)
102 * sb_tegra_read_wpr() - read the WPR registers on Tegra
104 * On dGPU, we can manage the WPR region ourselves, but on Tegra the WPR region
105 * is reserved from system memory by the bootloader and irreversibly locked.
106 * This function reads the address and size of the pre-configured WPR region.
109 gm20b_tegra_read_wpr(struct gm200_secboot
*gsb
)
111 struct nvkm_secboot
*sb
= &gsb
->base
;
115 mc
= ioremap(TEGRA_MC_BASE
, 0xd00);
117 nvkm_error(&sb
->subdev
, "Cannot map Tegra MC registers\n");
120 gsb
->wpr_addr
= ioread32_native(mc
+ MC_SECURITY_CARVEOUT2_BOM_0
) |
121 ((u64
)ioread32_native(mc
+ MC_SECURITY_CARVEOUT2_BOM_HI_0
) << 32);
122 gsb
->wpr_size
= ioread32_native(mc
+ MC_SECURITY_CARVEOUT2_SIZE_128K
)
124 cfg
= ioread32_native(mc
+ MC_SECURITY_CARVEOUT2_CFG0
);
127 /* Check that WPR settings are valid */
128 if (gsb
->wpr_size
== 0) {
129 nvkm_error(&sb
->subdev
, "WPR region is empty\n");
133 if (!(cfg
& TEGRA_MC_SECURITY_CARVEOUT_CFG_LOCKED
)) {
134 nvkm_error(&sb
->subdev
, "WPR region not locked\n");
142 gm20b_tegra_read_wpr(struct gm200_secboot
*gsb
)
144 nvkm_error(&gsb
->base
.subdev
, "Tegra support not compiled in\n");
150 gm20b_secboot_prepare_blobs(struct nvkm_secboot
*sb
)
152 struct gm200_secboot
*gsb
= gm200_secboot(sb
);
156 ret
= gm20x_secboot_prepare_blobs(gsb
);
160 acr_size
= gsb
->acr_load_blob
->size
;
162 * On Tegra the WPR region is set by the bootloader. It is illegal for
163 * the HS blob to be larger than this region.
165 if (acr_size
> gsb
->wpr_size
) {
166 nvkm_error(&sb
->subdev
, "WPR region too small for FW blob!\n");
167 nvkm_error(&sb
->subdev
, "required: %dB\n", acr_size
);
168 nvkm_error(&sb
->subdev
, "WPR size: %dB\n", gsb
->wpr_size
);
176 gm20b_secboot_init(struct nvkm_secboot
*sb
)
178 struct gm200_secboot
*gsb
= gm200_secboot(sb
);
181 ret
= gm20b_tegra_read_wpr(gsb
);
185 return gm200_secboot_init(sb
);
188 static const struct nvkm_secboot_func
190 .dtor
= gm200_secboot_dtor
,
191 .init
= gm20b_secboot_init
,
192 .prepare_blobs
= gm20b_secboot_prepare_blobs
,
193 .reset
= gm200_secboot_reset
,
194 .start
= gm200_secboot_start
,
195 .managed_falcons
= BIT(NVKM_SECBOOT_FALCON_FECS
),
196 .boot_falcon
= NVKM_SECBOOT_FALCON_PMU
,
200 gm20b_secboot_new(struct nvkm_device
*device
, int index
,
201 struct nvkm_secboot
**psb
)
204 struct gm200_secboot
*gsb
;
206 gsb
= kzalloc(sizeof(*gsb
), GFP_KERNEL
);
213 ret
= nvkm_secboot_ctor(&gm20b_secboot
, device
, index
, &gsb
->base
);
217 gsb
->func
= &gm20b_secboot_func
;
222 MODULE_FIRMWARE("nvidia/gm20b/acr/bl.bin");
223 MODULE_FIRMWARE("nvidia/gm20b/acr/ucode_load.bin");
224 MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_bl.bin");
225 MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_inst.bin");
226 MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_data.bin");
227 MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_sig.bin");
228 MODULE_FIRMWARE("nvidia/gm20b/gr/gpccs_inst.bin");
229 MODULE_FIRMWARE("nvidia/gm20b/gr/gpccs_data.bin");
230 MODULE_FIRMWARE("nvidia/gm20b/gr/sw_ctx.bin");
231 MODULE_FIRMWARE("nvidia/gm20b/gr/sw_nonctx.bin");
232 MODULE_FIRMWARE("nvidia/gm20b/gr/sw_bundle_init.bin");
233 MODULE_FIRMWARE("nvidia/gm20b/gr/sw_method_init.bin");