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drm/omap: Remove regulator API abuse
[deliverable/linux.git] / drivers / gpu / drm / omapdrm / dss / dsi.c
1 /*
2 * linux/drivers/video/omap2/dss/dsi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #define DSS_SUBSYS_NAME "DSI"
21
22 #include <linux/kernel.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/module.h>
31 #include <linux/semaphore.h>
32 #include <linux/seq_file.h>
33 #include <linux/platform_device.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/wait.h>
36 #include <linux/workqueue.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39 #include <linux/debugfs.h>
40 #include <linux/pm_runtime.h>
41 #include <linux/of.h>
42 #include <linux/of_platform.h>
43 #include <linux/component.h>
44
45 #include <video/omapdss.h>
46 #include <video/mipi_display.h>
47
48 #include "dss.h"
49 #include "dss_features.h"
50
51 #define DSI_CATCH_MISSING_TE
52
53 struct dsi_reg { u16 module; u16 idx; };
54
55 #define DSI_REG(mod, idx) ((const struct dsi_reg) { mod, idx })
56
57 /* DSI Protocol Engine */
58
59 #define DSI_PROTO 0
60 #define DSI_PROTO_SZ 0x200
61
62 #define DSI_REVISION DSI_REG(DSI_PROTO, 0x0000)
63 #define DSI_SYSCONFIG DSI_REG(DSI_PROTO, 0x0010)
64 #define DSI_SYSSTATUS DSI_REG(DSI_PROTO, 0x0014)
65 #define DSI_IRQSTATUS DSI_REG(DSI_PROTO, 0x0018)
66 #define DSI_IRQENABLE DSI_REG(DSI_PROTO, 0x001C)
67 #define DSI_CTRL DSI_REG(DSI_PROTO, 0x0040)
68 #define DSI_GNQ DSI_REG(DSI_PROTO, 0x0044)
69 #define DSI_COMPLEXIO_CFG1 DSI_REG(DSI_PROTO, 0x0048)
70 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(DSI_PROTO, 0x004C)
71 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(DSI_PROTO, 0x0050)
72 #define DSI_CLK_CTRL DSI_REG(DSI_PROTO, 0x0054)
73 #define DSI_TIMING1 DSI_REG(DSI_PROTO, 0x0058)
74 #define DSI_TIMING2 DSI_REG(DSI_PROTO, 0x005C)
75 #define DSI_VM_TIMING1 DSI_REG(DSI_PROTO, 0x0060)
76 #define DSI_VM_TIMING2 DSI_REG(DSI_PROTO, 0x0064)
77 #define DSI_VM_TIMING3 DSI_REG(DSI_PROTO, 0x0068)
78 #define DSI_CLK_TIMING DSI_REG(DSI_PROTO, 0x006C)
79 #define DSI_TX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0070)
80 #define DSI_RX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0074)
81 #define DSI_COMPLEXIO_CFG2 DSI_REG(DSI_PROTO, 0x0078)
82 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(DSI_PROTO, 0x007C)
83 #define DSI_VM_TIMING4 DSI_REG(DSI_PROTO, 0x0080)
84 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(DSI_PROTO, 0x0084)
85 #define DSI_VM_TIMING5 DSI_REG(DSI_PROTO, 0x0088)
86 #define DSI_VM_TIMING6 DSI_REG(DSI_PROTO, 0x008C)
87 #define DSI_VM_TIMING7 DSI_REG(DSI_PROTO, 0x0090)
88 #define DSI_STOPCLK_TIMING DSI_REG(DSI_PROTO, 0x0094)
89 #define DSI_VC_CTRL(n) DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20))
90 #define DSI_VC_TE(n) DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20))
91 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20))
92 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(DSI_PROTO, 0x010C + (n * 0x20))
93 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20))
94 #define DSI_VC_IRQSTATUS(n) DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20))
95 #define DSI_VC_IRQENABLE(n) DSI_REG(DSI_PROTO, 0x011C + (n * 0x20))
96
97 /* DSIPHY_SCP */
98
99 #define DSI_PHY 1
100 #define DSI_PHY_OFFSET 0x200
101 #define DSI_PHY_SZ 0x40
102
103 #define DSI_DSIPHY_CFG0 DSI_REG(DSI_PHY, 0x0000)
104 #define DSI_DSIPHY_CFG1 DSI_REG(DSI_PHY, 0x0004)
105 #define DSI_DSIPHY_CFG2 DSI_REG(DSI_PHY, 0x0008)
106 #define DSI_DSIPHY_CFG5 DSI_REG(DSI_PHY, 0x0014)
107 #define DSI_DSIPHY_CFG10 DSI_REG(DSI_PHY, 0x0028)
108
109 /* DSI_PLL_CTRL_SCP */
110
111 #define DSI_PLL 2
112 #define DSI_PLL_OFFSET 0x300
113 #define DSI_PLL_SZ 0x20
114
115 #define DSI_PLL_CONTROL DSI_REG(DSI_PLL, 0x0000)
116 #define DSI_PLL_STATUS DSI_REG(DSI_PLL, 0x0004)
117 #define DSI_PLL_GO DSI_REG(DSI_PLL, 0x0008)
118 #define DSI_PLL_CONFIGURATION1 DSI_REG(DSI_PLL, 0x000C)
119 #define DSI_PLL_CONFIGURATION2 DSI_REG(DSI_PLL, 0x0010)
120
121 #define REG_GET(dsidev, idx, start, end) \
122 FLD_GET(dsi_read_reg(dsidev, idx), start, end)
123
124 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
125 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
126
127 /* Global interrupts */
128 #define DSI_IRQ_VC0 (1 << 0)
129 #define DSI_IRQ_VC1 (1 << 1)
130 #define DSI_IRQ_VC2 (1 << 2)
131 #define DSI_IRQ_VC3 (1 << 3)
132 #define DSI_IRQ_WAKEUP (1 << 4)
133 #define DSI_IRQ_RESYNC (1 << 5)
134 #define DSI_IRQ_PLL_LOCK (1 << 7)
135 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
136 #define DSI_IRQ_PLL_RECALL (1 << 9)
137 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
138 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
139 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
140 #define DSI_IRQ_TE_TRIGGER (1 << 16)
141 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
142 #define DSI_IRQ_SYNC_LOST (1 << 18)
143 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
144 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
145 #define DSI_IRQ_ERROR_MASK \
146 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
147 DSI_IRQ_TA_TIMEOUT)
148 #define DSI_IRQ_CHANNEL_MASK 0xf
149
150 /* Virtual channel interrupts */
151 #define DSI_VC_IRQ_CS (1 << 0)
152 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
153 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
154 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
155 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
156 #define DSI_VC_IRQ_BTA (1 << 5)
157 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
158 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
159 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
160 #define DSI_VC_IRQ_ERROR_MASK \
161 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
162 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
163 DSI_VC_IRQ_FIFO_TX_UDF)
164
165 /* ComplexIO interrupts */
166 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
167 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
168 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
169 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
170 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
171 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
172 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
173 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
174 #define DSI_CIO_IRQ_ERRESC4 (1 << 8)
175 #define DSI_CIO_IRQ_ERRESC5 (1 << 9)
176 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
177 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
178 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
179 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
180 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
181 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
182 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
183 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
184 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
185 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
186 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
187 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
188 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
189 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
190 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
191 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
192 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
193 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
194 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
195 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
196 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
197 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
198 #define DSI_CIO_IRQ_ERROR_MASK \
199 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
200 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
201 DSI_CIO_IRQ_ERRSYNCESC5 | \
202 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
203 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
204 DSI_CIO_IRQ_ERRESC5 | \
205 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
206 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
207 DSI_CIO_IRQ_ERRCONTROL5 | \
208 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
209 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
210 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
211 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
212 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
213
214 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
215
216 static int dsi_display_init_dispc(struct platform_device *dsidev,
217 enum omap_channel channel);
218 static void dsi_display_uninit_dispc(struct platform_device *dsidev,
219 enum omap_channel channel);
220
221 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
222
223 /* DSI PLL HSDIV indices */
224 #define HSDIV_DISPC 0
225 #define HSDIV_DSI 1
226
227 #define DSI_MAX_NR_ISRS 2
228 #define DSI_MAX_NR_LANES 5
229
230 enum dsi_lane_function {
231 DSI_LANE_UNUSED = 0,
232 DSI_LANE_CLK,
233 DSI_LANE_DATA1,
234 DSI_LANE_DATA2,
235 DSI_LANE_DATA3,
236 DSI_LANE_DATA4,
237 };
238
239 struct dsi_lane_config {
240 enum dsi_lane_function function;
241 u8 polarity;
242 };
243
244 struct dsi_isr_data {
245 omap_dsi_isr_t isr;
246 void *arg;
247 u32 mask;
248 };
249
250 enum fifo_size {
251 DSI_FIFO_SIZE_0 = 0,
252 DSI_FIFO_SIZE_32 = 1,
253 DSI_FIFO_SIZE_64 = 2,
254 DSI_FIFO_SIZE_96 = 3,
255 DSI_FIFO_SIZE_128 = 4,
256 };
257
258 enum dsi_vc_source {
259 DSI_VC_SOURCE_L4 = 0,
260 DSI_VC_SOURCE_VP,
261 };
262
263 struct dsi_irq_stats {
264 unsigned long last_reset;
265 unsigned irq_count;
266 unsigned dsi_irqs[32];
267 unsigned vc_irqs[4][32];
268 unsigned cio_irqs[32];
269 };
270
271 struct dsi_isr_tables {
272 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
273 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
274 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
275 };
276
277 struct dsi_clk_calc_ctx {
278 struct platform_device *dsidev;
279 struct dss_pll *pll;
280
281 /* inputs */
282
283 const struct omap_dss_dsi_config *config;
284
285 unsigned long req_pck_min, req_pck_nom, req_pck_max;
286
287 /* outputs */
288
289 struct dss_pll_clock_info dsi_cinfo;
290 struct dispc_clock_info dispc_cinfo;
291
292 struct omap_video_timings dispc_vm;
293 struct omap_dss_dsi_videomode_timings dsi_vm;
294 };
295
296 struct dsi_lp_clock_info {
297 unsigned long lp_clk;
298 u16 lp_clk_div;
299 };
300
301 struct dsi_data {
302 struct platform_device *pdev;
303 void __iomem *proto_base;
304 void __iomem *phy_base;
305 void __iomem *pll_base;
306
307 int module_id;
308
309 int irq;
310
311 bool is_enabled;
312
313 struct clk *dss_clk;
314
315 struct dispc_clock_info user_dispc_cinfo;
316 struct dss_pll_clock_info user_dsi_cinfo;
317
318 struct dsi_lp_clock_info user_lp_cinfo;
319 struct dsi_lp_clock_info current_lp_cinfo;
320
321 struct dss_pll pll;
322
323 bool vdds_dsi_enabled;
324 struct regulator *vdds_dsi_reg;
325
326 struct {
327 enum dsi_vc_source source;
328 struct omap_dss_device *dssdev;
329 enum fifo_size tx_fifo_size;
330 enum fifo_size rx_fifo_size;
331 int vc_id;
332 } vc[4];
333
334 struct mutex lock;
335 struct semaphore bus_lock;
336
337 spinlock_t irq_lock;
338 struct dsi_isr_tables isr_tables;
339 /* space for a copy used by the interrupt handler */
340 struct dsi_isr_tables isr_tables_copy;
341
342 int update_channel;
343 #ifdef DSI_PERF_MEASURE
344 unsigned update_bytes;
345 #endif
346
347 bool te_enabled;
348 bool ulps_enabled;
349
350 void (*framedone_callback)(int, void *);
351 void *framedone_data;
352
353 struct delayed_work framedone_timeout_work;
354
355 #ifdef DSI_CATCH_MISSING_TE
356 struct timer_list te_timer;
357 #endif
358
359 unsigned long cache_req_pck;
360 unsigned long cache_clk_freq;
361 struct dss_pll_clock_info cache_cinfo;
362
363 u32 errors;
364 spinlock_t errors_lock;
365 #ifdef DSI_PERF_MEASURE
366 ktime_t perf_setup_time;
367 ktime_t perf_start_time;
368 #endif
369 int debug_read;
370 int debug_write;
371
372 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
373 spinlock_t irq_stats_lock;
374 struct dsi_irq_stats irq_stats;
375 #endif
376
377 unsigned num_lanes_supported;
378 unsigned line_buffer_size;
379
380 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
381 unsigned num_lanes_used;
382
383 unsigned scp_clk_refcount;
384
385 struct dss_lcd_mgr_config mgr_config;
386 struct omap_video_timings timings;
387 enum omap_dss_dsi_pixel_format pix_fmt;
388 enum omap_dss_dsi_mode mode;
389 struct omap_dss_dsi_videomode_timings vm_timings;
390
391 struct omap_dss_device output;
392 };
393
394 struct dsi_packet_sent_handler_data {
395 struct platform_device *dsidev;
396 struct completion *completion;
397 };
398
399 struct dsi_module_id_data {
400 u32 address;
401 int id;
402 };
403
404 static const struct of_device_id dsi_of_match[];
405
406 #ifdef DSI_PERF_MEASURE
407 static bool dsi_perf;
408 module_param(dsi_perf, bool, 0644);
409 #endif
410
411 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
412 {
413 return dev_get_drvdata(&dsidev->dev);
414 }
415
416 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
417 {
418 return to_platform_device(dssdev->dev);
419 }
420
421 static struct platform_device *dsi_get_dsidev_from_id(int module)
422 {
423 struct omap_dss_device *out;
424 enum omap_dss_output_id id;
425
426 switch (module) {
427 case 0:
428 id = OMAP_DSS_OUTPUT_DSI1;
429 break;
430 case 1:
431 id = OMAP_DSS_OUTPUT_DSI2;
432 break;
433 default:
434 return NULL;
435 }
436
437 out = omap_dss_get_output(id);
438
439 return out ? to_platform_device(out->dev) : NULL;
440 }
441
442 static inline void dsi_write_reg(struct platform_device *dsidev,
443 const struct dsi_reg idx, u32 val)
444 {
445 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
446 void __iomem *base;
447
448 switch(idx.module) {
449 case DSI_PROTO: base = dsi->proto_base; break;
450 case DSI_PHY: base = dsi->phy_base; break;
451 case DSI_PLL: base = dsi->pll_base; break;
452 default: return;
453 }
454
455 __raw_writel(val, base + idx.idx);
456 }
457
458 static inline u32 dsi_read_reg(struct platform_device *dsidev,
459 const struct dsi_reg idx)
460 {
461 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
462 void __iomem *base;
463
464 switch(idx.module) {
465 case DSI_PROTO: base = dsi->proto_base; break;
466 case DSI_PHY: base = dsi->phy_base; break;
467 case DSI_PLL: base = dsi->pll_base; break;
468 default: return 0;
469 }
470
471 return __raw_readl(base + idx.idx);
472 }
473
474 static void dsi_bus_lock(struct omap_dss_device *dssdev)
475 {
476 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
477 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
478
479 down(&dsi->bus_lock);
480 }
481
482 static void dsi_bus_unlock(struct omap_dss_device *dssdev)
483 {
484 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
485 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
486
487 up(&dsi->bus_lock);
488 }
489
490 static bool dsi_bus_is_locked(struct platform_device *dsidev)
491 {
492 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
493
494 return dsi->bus_lock.count == 0;
495 }
496
497 static void dsi_completion_handler(void *data, u32 mask)
498 {
499 complete((struct completion *)data);
500 }
501
502 static inline int wait_for_bit_change(struct platform_device *dsidev,
503 const struct dsi_reg idx, int bitnum, int value)
504 {
505 unsigned long timeout;
506 ktime_t wait;
507 int t;
508
509 /* first busyloop to see if the bit changes right away */
510 t = 100;
511 while (t-- > 0) {
512 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
513 return value;
514 }
515
516 /* then loop for 500ms, sleeping for 1ms in between */
517 timeout = jiffies + msecs_to_jiffies(500);
518 while (time_before(jiffies, timeout)) {
519 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
520 return value;
521
522 wait = ns_to_ktime(1000 * 1000);
523 set_current_state(TASK_UNINTERRUPTIBLE);
524 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
525 }
526
527 return !value;
528 }
529
530 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
531 {
532 switch (fmt) {
533 case OMAP_DSS_DSI_FMT_RGB888:
534 case OMAP_DSS_DSI_FMT_RGB666:
535 return 24;
536 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
537 return 18;
538 case OMAP_DSS_DSI_FMT_RGB565:
539 return 16;
540 default:
541 BUG();
542 return 0;
543 }
544 }
545
546 #ifdef DSI_PERF_MEASURE
547 static void dsi_perf_mark_setup(struct platform_device *dsidev)
548 {
549 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
550 dsi->perf_setup_time = ktime_get();
551 }
552
553 static void dsi_perf_mark_start(struct platform_device *dsidev)
554 {
555 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
556 dsi->perf_start_time = ktime_get();
557 }
558
559 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
560 {
561 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
562 ktime_t t, setup_time, trans_time;
563 u32 total_bytes;
564 u32 setup_us, trans_us, total_us;
565
566 if (!dsi_perf)
567 return;
568
569 t = ktime_get();
570
571 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
572 setup_us = (u32)ktime_to_us(setup_time);
573 if (setup_us == 0)
574 setup_us = 1;
575
576 trans_time = ktime_sub(t, dsi->perf_start_time);
577 trans_us = (u32)ktime_to_us(trans_time);
578 if (trans_us == 0)
579 trans_us = 1;
580
581 total_us = setup_us + trans_us;
582
583 total_bytes = dsi->update_bytes;
584
585 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
586 "%u bytes, %u kbytes/sec\n",
587 name,
588 setup_us,
589 trans_us,
590 total_us,
591 1000*1000 / total_us,
592 total_bytes,
593 total_bytes * 1000 / total_us);
594 }
595 #else
596 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
597 {
598 }
599
600 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
601 {
602 }
603
604 static inline void dsi_perf_show(struct platform_device *dsidev,
605 const char *name)
606 {
607 }
608 #endif
609
610 static int verbose_irq;
611
612 static void print_irq_status(u32 status)
613 {
614 if (status == 0)
615 return;
616
617 if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0)
618 return;
619
620 #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : ""
621
622 pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
623 status,
624 verbose_irq ? PIS(VC0) : "",
625 verbose_irq ? PIS(VC1) : "",
626 verbose_irq ? PIS(VC2) : "",
627 verbose_irq ? PIS(VC3) : "",
628 PIS(WAKEUP),
629 PIS(RESYNC),
630 PIS(PLL_LOCK),
631 PIS(PLL_UNLOCK),
632 PIS(PLL_RECALL),
633 PIS(COMPLEXIO_ERR),
634 PIS(HS_TX_TIMEOUT),
635 PIS(LP_RX_TIMEOUT),
636 PIS(TE_TRIGGER),
637 PIS(ACK_TRIGGER),
638 PIS(SYNC_LOST),
639 PIS(LDO_POWER_GOOD),
640 PIS(TA_TIMEOUT));
641 #undef PIS
642 }
643
644 static void print_irq_status_vc(int channel, u32 status)
645 {
646 if (status == 0)
647 return;
648
649 if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
650 return;
651
652 #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : ""
653
654 pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n",
655 channel,
656 status,
657 PIS(CS),
658 PIS(ECC_CORR),
659 PIS(ECC_NO_CORR),
660 verbose_irq ? PIS(PACKET_SENT) : "",
661 PIS(BTA),
662 PIS(FIFO_TX_OVF),
663 PIS(FIFO_RX_OVF),
664 PIS(FIFO_TX_UDF),
665 PIS(PP_BUSY_CHANGE));
666 #undef PIS
667 }
668
669 static void print_irq_status_cio(u32 status)
670 {
671 if (status == 0)
672 return;
673
674 #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : ""
675
676 pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
677 status,
678 PIS(ERRSYNCESC1),
679 PIS(ERRSYNCESC2),
680 PIS(ERRSYNCESC3),
681 PIS(ERRESC1),
682 PIS(ERRESC2),
683 PIS(ERRESC3),
684 PIS(ERRCONTROL1),
685 PIS(ERRCONTROL2),
686 PIS(ERRCONTROL3),
687 PIS(STATEULPS1),
688 PIS(STATEULPS2),
689 PIS(STATEULPS3),
690 PIS(ERRCONTENTIONLP0_1),
691 PIS(ERRCONTENTIONLP1_1),
692 PIS(ERRCONTENTIONLP0_2),
693 PIS(ERRCONTENTIONLP1_2),
694 PIS(ERRCONTENTIONLP0_3),
695 PIS(ERRCONTENTIONLP1_3),
696 PIS(ULPSACTIVENOT_ALL0),
697 PIS(ULPSACTIVENOT_ALL1));
698 #undef PIS
699 }
700
701 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
702 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
703 u32 *vcstatus, u32 ciostatus)
704 {
705 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
706 int i;
707
708 spin_lock(&dsi->irq_stats_lock);
709
710 dsi->irq_stats.irq_count++;
711 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
712
713 for (i = 0; i < 4; ++i)
714 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
715
716 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
717
718 spin_unlock(&dsi->irq_stats_lock);
719 }
720 #else
721 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
722 #endif
723
724 static int debug_irq;
725
726 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
727 u32 *vcstatus, u32 ciostatus)
728 {
729 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
730 int i;
731
732 if (irqstatus & DSI_IRQ_ERROR_MASK) {
733 DSSERR("DSI error, irqstatus %x\n", irqstatus);
734 print_irq_status(irqstatus);
735 spin_lock(&dsi->errors_lock);
736 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
737 spin_unlock(&dsi->errors_lock);
738 } else if (debug_irq) {
739 print_irq_status(irqstatus);
740 }
741
742 for (i = 0; i < 4; ++i) {
743 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
744 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
745 i, vcstatus[i]);
746 print_irq_status_vc(i, vcstatus[i]);
747 } else if (debug_irq) {
748 print_irq_status_vc(i, vcstatus[i]);
749 }
750 }
751
752 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
753 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
754 print_irq_status_cio(ciostatus);
755 } else if (debug_irq) {
756 print_irq_status_cio(ciostatus);
757 }
758 }
759
760 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
761 unsigned isr_array_size, u32 irqstatus)
762 {
763 struct dsi_isr_data *isr_data;
764 int i;
765
766 for (i = 0; i < isr_array_size; i++) {
767 isr_data = &isr_array[i];
768 if (isr_data->isr && isr_data->mask & irqstatus)
769 isr_data->isr(isr_data->arg, irqstatus);
770 }
771 }
772
773 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
774 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
775 {
776 int i;
777
778 dsi_call_isrs(isr_tables->isr_table,
779 ARRAY_SIZE(isr_tables->isr_table),
780 irqstatus);
781
782 for (i = 0; i < 4; ++i) {
783 if (vcstatus[i] == 0)
784 continue;
785 dsi_call_isrs(isr_tables->isr_table_vc[i],
786 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
787 vcstatus[i]);
788 }
789
790 if (ciostatus != 0)
791 dsi_call_isrs(isr_tables->isr_table_cio,
792 ARRAY_SIZE(isr_tables->isr_table_cio),
793 ciostatus);
794 }
795
796 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
797 {
798 struct platform_device *dsidev;
799 struct dsi_data *dsi;
800 u32 irqstatus, vcstatus[4], ciostatus;
801 int i;
802
803 dsidev = (struct platform_device *) arg;
804 dsi = dsi_get_dsidrv_data(dsidev);
805
806 if (!dsi->is_enabled)
807 return IRQ_NONE;
808
809 spin_lock(&dsi->irq_lock);
810
811 irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
812
813 /* IRQ is not for us */
814 if (!irqstatus) {
815 spin_unlock(&dsi->irq_lock);
816 return IRQ_NONE;
817 }
818
819 dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
820 /* flush posted write */
821 dsi_read_reg(dsidev, DSI_IRQSTATUS);
822
823 for (i = 0; i < 4; ++i) {
824 if ((irqstatus & (1 << i)) == 0) {
825 vcstatus[i] = 0;
826 continue;
827 }
828
829 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
830
831 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
832 /* flush posted write */
833 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
834 }
835
836 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
837 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
838
839 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
840 /* flush posted write */
841 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
842 } else {
843 ciostatus = 0;
844 }
845
846 #ifdef DSI_CATCH_MISSING_TE
847 if (irqstatus & DSI_IRQ_TE_TRIGGER)
848 del_timer(&dsi->te_timer);
849 #endif
850
851 /* make a copy and unlock, so that isrs can unregister
852 * themselves */
853 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
854 sizeof(dsi->isr_tables));
855
856 spin_unlock(&dsi->irq_lock);
857
858 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
859
860 dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
861
862 dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
863
864 return IRQ_HANDLED;
865 }
866
867 /* dsi->irq_lock has to be locked by the caller */
868 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
869 struct dsi_isr_data *isr_array,
870 unsigned isr_array_size, u32 default_mask,
871 const struct dsi_reg enable_reg,
872 const struct dsi_reg status_reg)
873 {
874 struct dsi_isr_data *isr_data;
875 u32 mask;
876 u32 old_mask;
877 int i;
878
879 mask = default_mask;
880
881 for (i = 0; i < isr_array_size; i++) {
882 isr_data = &isr_array[i];
883
884 if (isr_data->isr == NULL)
885 continue;
886
887 mask |= isr_data->mask;
888 }
889
890 old_mask = dsi_read_reg(dsidev, enable_reg);
891 /* clear the irqstatus for newly enabled irqs */
892 dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
893 dsi_write_reg(dsidev, enable_reg, mask);
894
895 /* flush posted writes */
896 dsi_read_reg(dsidev, enable_reg);
897 dsi_read_reg(dsidev, status_reg);
898 }
899
900 /* dsi->irq_lock has to be locked by the caller */
901 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
902 {
903 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
904 u32 mask = DSI_IRQ_ERROR_MASK;
905 #ifdef DSI_CATCH_MISSING_TE
906 mask |= DSI_IRQ_TE_TRIGGER;
907 #endif
908 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
909 ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
910 DSI_IRQENABLE, DSI_IRQSTATUS);
911 }
912
913 /* dsi->irq_lock has to be locked by the caller */
914 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
915 {
916 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
917
918 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
919 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
920 DSI_VC_IRQ_ERROR_MASK,
921 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
922 }
923
924 /* dsi->irq_lock has to be locked by the caller */
925 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
926 {
927 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
928
929 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
930 ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
931 DSI_CIO_IRQ_ERROR_MASK,
932 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
933 }
934
935 static void _dsi_initialize_irq(struct platform_device *dsidev)
936 {
937 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
938 unsigned long flags;
939 int vc;
940
941 spin_lock_irqsave(&dsi->irq_lock, flags);
942
943 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
944
945 _omap_dsi_set_irqs(dsidev);
946 for (vc = 0; vc < 4; ++vc)
947 _omap_dsi_set_irqs_vc(dsidev, vc);
948 _omap_dsi_set_irqs_cio(dsidev);
949
950 spin_unlock_irqrestore(&dsi->irq_lock, flags);
951 }
952
953 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
954 struct dsi_isr_data *isr_array, unsigned isr_array_size)
955 {
956 struct dsi_isr_data *isr_data;
957 int free_idx;
958 int i;
959
960 BUG_ON(isr == NULL);
961
962 /* check for duplicate entry and find a free slot */
963 free_idx = -1;
964 for (i = 0; i < isr_array_size; i++) {
965 isr_data = &isr_array[i];
966
967 if (isr_data->isr == isr && isr_data->arg == arg &&
968 isr_data->mask == mask) {
969 return -EINVAL;
970 }
971
972 if (isr_data->isr == NULL && free_idx == -1)
973 free_idx = i;
974 }
975
976 if (free_idx == -1)
977 return -EBUSY;
978
979 isr_data = &isr_array[free_idx];
980 isr_data->isr = isr;
981 isr_data->arg = arg;
982 isr_data->mask = mask;
983
984 return 0;
985 }
986
987 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
988 struct dsi_isr_data *isr_array, unsigned isr_array_size)
989 {
990 struct dsi_isr_data *isr_data;
991 int i;
992
993 for (i = 0; i < isr_array_size; i++) {
994 isr_data = &isr_array[i];
995 if (isr_data->isr != isr || isr_data->arg != arg ||
996 isr_data->mask != mask)
997 continue;
998
999 isr_data->isr = NULL;
1000 isr_data->arg = NULL;
1001 isr_data->mask = 0;
1002
1003 return 0;
1004 }
1005
1006 return -EINVAL;
1007 }
1008
1009 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
1010 void *arg, u32 mask)
1011 {
1012 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1013 unsigned long flags;
1014 int r;
1015
1016 spin_lock_irqsave(&dsi->irq_lock, flags);
1017
1018 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
1019 ARRAY_SIZE(dsi->isr_tables.isr_table));
1020
1021 if (r == 0)
1022 _omap_dsi_set_irqs(dsidev);
1023
1024 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1025
1026 return r;
1027 }
1028
1029 static int dsi_unregister_isr(struct platform_device *dsidev,
1030 omap_dsi_isr_t isr, void *arg, u32 mask)
1031 {
1032 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1033 unsigned long flags;
1034 int r;
1035
1036 spin_lock_irqsave(&dsi->irq_lock, flags);
1037
1038 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
1039 ARRAY_SIZE(dsi->isr_tables.isr_table));
1040
1041 if (r == 0)
1042 _omap_dsi_set_irqs(dsidev);
1043
1044 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1045
1046 return r;
1047 }
1048
1049 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
1050 omap_dsi_isr_t isr, void *arg, u32 mask)
1051 {
1052 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1053 unsigned long flags;
1054 int r;
1055
1056 spin_lock_irqsave(&dsi->irq_lock, flags);
1057
1058 r = _dsi_register_isr(isr, arg, mask,
1059 dsi->isr_tables.isr_table_vc[channel],
1060 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1061
1062 if (r == 0)
1063 _omap_dsi_set_irqs_vc(dsidev, channel);
1064
1065 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1066
1067 return r;
1068 }
1069
1070 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
1071 omap_dsi_isr_t isr, void *arg, u32 mask)
1072 {
1073 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1074 unsigned long flags;
1075 int r;
1076
1077 spin_lock_irqsave(&dsi->irq_lock, flags);
1078
1079 r = _dsi_unregister_isr(isr, arg, mask,
1080 dsi->isr_tables.isr_table_vc[channel],
1081 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1082
1083 if (r == 0)
1084 _omap_dsi_set_irqs_vc(dsidev, channel);
1085
1086 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1087
1088 return r;
1089 }
1090
1091 static int dsi_register_isr_cio(struct platform_device *dsidev,
1092 omap_dsi_isr_t isr, void *arg, u32 mask)
1093 {
1094 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1095 unsigned long flags;
1096 int r;
1097
1098 spin_lock_irqsave(&dsi->irq_lock, flags);
1099
1100 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1101 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1102
1103 if (r == 0)
1104 _omap_dsi_set_irqs_cio(dsidev);
1105
1106 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1107
1108 return r;
1109 }
1110
1111 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1112 omap_dsi_isr_t isr, void *arg, u32 mask)
1113 {
1114 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1115 unsigned long flags;
1116 int r;
1117
1118 spin_lock_irqsave(&dsi->irq_lock, flags);
1119
1120 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1121 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1122
1123 if (r == 0)
1124 _omap_dsi_set_irqs_cio(dsidev);
1125
1126 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1127
1128 return r;
1129 }
1130
1131 static u32 dsi_get_errors(struct platform_device *dsidev)
1132 {
1133 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1134 unsigned long flags;
1135 u32 e;
1136 spin_lock_irqsave(&dsi->errors_lock, flags);
1137 e = dsi->errors;
1138 dsi->errors = 0;
1139 spin_unlock_irqrestore(&dsi->errors_lock, flags);
1140 return e;
1141 }
1142
1143 static int dsi_runtime_get(struct platform_device *dsidev)
1144 {
1145 int r;
1146 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1147
1148 DSSDBG("dsi_runtime_get\n");
1149
1150 r = pm_runtime_get_sync(&dsi->pdev->dev);
1151 WARN_ON(r < 0);
1152 return r < 0 ? r : 0;
1153 }
1154
1155 static void dsi_runtime_put(struct platform_device *dsidev)
1156 {
1157 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1158 int r;
1159
1160 DSSDBG("dsi_runtime_put\n");
1161
1162 r = pm_runtime_put_sync(&dsi->pdev->dev);
1163 WARN_ON(r < 0 && r != -ENOSYS);
1164 }
1165
1166 static int dsi_regulator_init(struct platform_device *dsidev)
1167 {
1168 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1169 struct regulator *vdds_dsi;
1170 int r;
1171
1172 if (dsi->vdds_dsi_reg != NULL)
1173 return 0;
1174
1175 vdds_dsi = devm_regulator_get(&dsi->pdev->dev, "vdd");
1176
1177 if (IS_ERR(vdds_dsi)) {
1178 if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER)
1179 DSSERR("can't get DSI VDD regulator\n");
1180 return PTR_ERR(vdds_dsi);
1181 }
1182
1183 dsi->vdds_dsi_reg = vdds_dsi;
1184
1185 return 0;
1186 }
1187
1188 static void _dsi_print_reset_status(struct platform_device *dsidev)
1189 {
1190 u32 l;
1191 int b0, b1, b2;
1192
1193 /* A dummy read using the SCP interface to any DSIPHY register is
1194 * required after DSIPHY reset to complete the reset of the DSI complex
1195 * I/O. */
1196 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1197
1198 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1199 b0 = 28;
1200 b1 = 27;
1201 b2 = 26;
1202 } else {
1203 b0 = 24;
1204 b1 = 25;
1205 b2 = 26;
1206 }
1207
1208 #define DSI_FLD_GET(fld, start, end)\
1209 FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end)
1210
1211 pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n",
1212 DSI_FLD_GET(PLL_STATUS, 0, 0),
1213 DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29),
1214 DSI_FLD_GET(DSIPHY_CFG5, b0, b0),
1215 DSI_FLD_GET(DSIPHY_CFG5, b1, b1),
1216 DSI_FLD_GET(DSIPHY_CFG5, b2, b2),
1217 DSI_FLD_GET(DSIPHY_CFG5, 29, 29),
1218 DSI_FLD_GET(DSIPHY_CFG5, 30, 30),
1219 DSI_FLD_GET(DSIPHY_CFG5, 31, 31));
1220
1221 #undef DSI_FLD_GET
1222 }
1223
1224 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1225 {
1226 DSSDBG("dsi_if_enable(%d)\n", enable);
1227
1228 enable = enable ? 1 : 0;
1229 REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1230
1231 if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1232 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1233 return -EIO;
1234 }
1235
1236 return 0;
1237 }
1238
1239 static unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1240 {
1241 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1242
1243 return dsi->pll.cinfo.clkout[HSDIV_DISPC];
1244 }
1245
1246 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1247 {
1248 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1249
1250 return dsi->pll.cinfo.clkout[HSDIV_DSI];
1251 }
1252
1253 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1254 {
1255 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1256
1257 return dsi->pll.cinfo.clkdco / 16;
1258 }
1259
1260 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1261 {
1262 unsigned long r;
1263 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1264
1265 if (dss_get_dsi_clk_source(dsi->module_id) == OMAP_DSS_CLK_SRC_FCK) {
1266 /* DSI FCLK source is DSS_CLK_FCK */
1267 r = clk_get_rate(dsi->dss_clk);
1268 } else {
1269 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1270 r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1271 }
1272
1273 return r;
1274 }
1275
1276 static int dsi_lp_clock_calc(unsigned long dsi_fclk,
1277 unsigned long lp_clk_min, unsigned long lp_clk_max,
1278 struct dsi_lp_clock_info *lp_cinfo)
1279 {
1280 unsigned lp_clk_div;
1281 unsigned long lp_clk;
1282
1283 lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2);
1284 lp_clk = dsi_fclk / 2 / lp_clk_div;
1285
1286 if (lp_clk < lp_clk_min || lp_clk > lp_clk_max)
1287 return -EINVAL;
1288
1289 lp_cinfo->lp_clk_div = lp_clk_div;
1290 lp_cinfo->lp_clk = lp_clk;
1291
1292 return 0;
1293 }
1294
1295 static int dsi_set_lp_clk_divisor(struct platform_device *dsidev)
1296 {
1297 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1298 unsigned long dsi_fclk;
1299 unsigned lp_clk_div;
1300 unsigned long lp_clk;
1301 unsigned lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
1302
1303
1304 lp_clk_div = dsi->user_lp_cinfo.lp_clk_div;
1305
1306 if (lp_clk_div == 0 || lp_clk_div > lpdiv_max)
1307 return -EINVAL;
1308
1309 dsi_fclk = dsi_fclk_rate(dsidev);
1310
1311 lp_clk = dsi_fclk / 2 / lp_clk_div;
1312
1313 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1314 dsi->current_lp_cinfo.lp_clk = lp_clk;
1315 dsi->current_lp_cinfo.lp_clk_div = lp_clk_div;
1316
1317 /* LP_CLK_DIVISOR */
1318 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1319
1320 /* LP_RX_SYNCHRO_ENABLE */
1321 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1322
1323 return 0;
1324 }
1325
1326 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1327 {
1328 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1329
1330 if (dsi->scp_clk_refcount++ == 0)
1331 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1332 }
1333
1334 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1335 {
1336 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1337
1338 WARN_ON(dsi->scp_clk_refcount == 0);
1339 if (--dsi->scp_clk_refcount == 0)
1340 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1341 }
1342
1343 enum dsi_pll_power_state {
1344 DSI_PLL_POWER_OFF = 0x0,
1345 DSI_PLL_POWER_ON_HSCLK = 0x1,
1346 DSI_PLL_POWER_ON_ALL = 0x2,
1347 DSI_PLL_POWER_ON_DIV = 0x3,
1348 };
1349
1350 static int dsi_pll_power(struct platform_device *dsidev,
1351 enum dsi_pll_power_state state)
1352 {
1353 int t = 0;
1354
1355 /* DSI-PLL power command 0x3 is not working */
1356 if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1357 state == DSI_PLL_POWER_ON_DIV)
1358 state = DSI_PLL_POWER_ON_ALL;
1359
1360 /* PLL_PWR_CMD */
1361 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1362
1363 /* PLL_PWR_STATUS */
1364 while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1365 if (++t > 1000) {
1366 DSSERR("Failed to set DSI PLL power mode to %d\n",
1367 state);
1368 return -ENODEV;
1369 }
1370 udelay(1);
1371 }
1372
1373 return 0;
1374 }
1375
1376
1377 static void dsi_pll_calc_dsi_fck(struct dss_pll_clock_info *cinfo)
1378 {
1379 unsigned long max_dsi_fck;
1380
1381 max_dsi_fck = dss_feat_get_param_max(FEAT_PARAM_DSI_FCK);
1382
1383 cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck);
1384 cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI];
1385 }
1386
1387 static int dsi_pll_enable(struct dss_pll *pll)
1388 {
1389 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
1390 struct platform_device *dsidev = dsi->pdev;
1391 int r = 0;
1392
1393 DSSDBG("PLL init\n");
1394
1395 r = dsi_regulator_init(dsidev);
1396 if (r)
1397 return r;
1398
1399 r = dsi_runtime_get(dsidev);
1400 if (r)
1401 return r;
1402
1403 /*
1404 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1405 */
1406 dsi_enable_scp_clk(dsidev);
1407
1408 if (!dsi->vdds_dsi_enabled) {
1409 r = regulator_enable(dsi->vdds_dsi_reg);
1410 if (r)
1411 goto err0;
1412 dsi->vdds_dsi_enabled = true;
1413 }
1414
1415 /* XXX PLL does not come out of reset without this... */
1416 dispc_pck_free_enable(1);
1417
1418 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1419 DSSERR("PLL not coming out of reset.\n");
1420 r = -ENODEV;
1421 dispc_pck_free_enable(0);
1422 goto err1;
1423 }
1424
1425 /* XXX ... but if left on, we get problems when planes do not
1426 * fill the whole display. No idea about this */
1427 dispc_pck_free_enable(0);
1428
1429 r = dsi_pll_power(dsidev, DSI_PLL_POWER_ON_ALL);
1430
1431 if (r)
1432 goto err1;
1433
1434 DSSDBG("PLL init done\n");
1435
1436 return 0;
1437 err1:
1438 if (dsi->vdds_dsi_enabled) {
1439 regulator_disable(dsi->vdds_dsi_reg);
1440 dsi->vdds_dsi_enabled = false;
1441 }
1442 err0:
1443 dsi_disable_scp_clk(dsidev);
1444 dsi_runtime_put(dsidev);
1445 return r;
1446 }
1447
1448 static void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1449 {
1450 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1451
1452 dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1453 if (disconnect_lanes) {
1454 WARN_ON(!dsi->vdds_dsi_enabled);
1455 regulator_disable(dsi->vdds_dsi_reg);
1456 dsi->vdds_dsi_enabled = false;
1457 }
1458
1459 dsi_disable_scp_clk(dsidev);
1460 dsi_runtime_put(dsidev);
1461
1462 DSSDBG("PLL uninit done\n");
1463 }
1464
1465 static void dsi_pll_disable(struct dss_pll *pll)
1466 {
1467 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
1468 struct platform_device *dsidev = dsi->pdev;
1469
1470 dsi_pll_uninit(dsidev, true);
1471 }
1472
1473 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1474 struct seq_file *s)
1475 {
1476 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1477 struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo;
1478 enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1479 int dsi_module = dsi->module_id;
1480 struct dss_pll *pll = &dsi->pll;
1481
1482 dispc_clk_src = dss_get_dispc_clk_source();
1483 dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1484
1485 if (dsi_runtime_get(dsidev))
1486 return;
1487
1488 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1);
1489
1490 seq_printf(s, "dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin));
1491
1492 seq_printf(s, "Fint\t\t%-16lun %u\n", cinfo->fint, cinfo->n);
1493
1494 seq_printf(s, "CLKIN4DDR\t%-16lum %u\n",
1495 cinfo->clkdco, cinfo->m);
1496
1497 seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n",
1498 dss_feat_get_clk_source_name(dsi_module == 0 ?
1499 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
1500 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC),
1501 cinfo->clkout[HSDIV_DISPC],
1502 cinfo->mX[HSDIV_DISPC],
1503 dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1504 "off" : "on");
1505
1506 seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n",
1507 dss_feat_get_clk_source_name(dsi_module == 0 ?
1508 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
1509 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI),
1510 cinfo->clkout[HSDIV_DSI],
1511 cinfo->mX[HSDIV_DSI],
1512 dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1513 "off" : "on");
1514
1515 seq_printf(s, "- DSI%d -\n", dsi_module + 1);
1516
1517 seq_printf(s, "dsi fclk source = %s (%s)\n",
1518 dss_get_generic_clk_source_name(dsi_clk_src),
1519 dss_feat_get_clk_source_name(dsi_clk_src));
1520
1521 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1522
1523 seq_printf(s, "DDR_CLK\t\t%lu\n",
1524 cinfo->clkdco / 4);
1525
1526 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1527
1528 seq_printf(s, "LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk);
1529
1530 dsi_runtime_put(dsidev);
1531 }
1532
1533 void dsi_dump_clocks(struct seq_file *s)
1534 {
1535 struct platform_device *dsidev;
1536 int i;
1537
1538 for (i = 0; i < MAX_NUM_DSI; i++) {
1539 dsidev = dsi_get_dsidev_from_id(i);
1540 if (dsidev)
1541 dsi_dump_dsidev_clocks(dsidev, s);
1542 }
1543 }
1544
1545 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1546 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1547 struct seq_file *s)
1548 {
1549 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1550 unsigned long flags;
1551 struct dsi_irq_stats stats;
1552
1553 spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1554
1555 stats = dsi->irq_stats;
1556 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1557 dsi->irq_stats.last_reset = jiffies;
1558
1559 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1560
1561 seq_printf(s, "period %u ms\n",
1562 jiffies_to_msecs(jiffies - stats.last_reset));
1563
1564 seq_printf(s, "irqs %d\n", stats.irq_count);
1565 #define PIS(x) \
1566 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1567
1568 seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1);
1569 PIS(VC0);
1570 PIS(VC1);
1571 PIS(VC2);
1572 PIS(VC3);
1573 PIS(WAKEUP);
1574 PIS(RESYNC);
1575 PIS(PLL_LOCK);
1576 PIS(PLL_UNLOCK);
1577 PIS(PLL_RECALL);
1578 PIS(COMPLEXIO_ERR);
1579 PIS(HS_TX_TIMEOUT);
1580 PIS(LP_RX_TIMEOUT);
1581 PIS(TE_TRIGGER);
1582 PIS(ACK_TRIGGER);
1583 PIS(SYNC_LOST);
1584 PIS(LDO_POWER_GOOD);
1585 PIS(TA_TIMEOUT);
1586 #undef PIS
1587
1588 #define PIS(x) \
1589 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1590 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1591 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1592 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1593 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1594
1595 seq_printf(s, "-- VC interrupts --\n");
1596 PIS(CS);
1597 PIS(ECC_CORR);
1598 PIS(PACKET_SENT);
1599 PIS(FIFO_TX_OVF);
1600 PIS(FIFO_RX_OVF);
1601 PIS(BTA);
1602 PIS(ECC_NO_CORR);
1603 PIS(FIFO_TX_UDF);
1604 PIS(PP_BUSY_CHANGE);
1605 #undef PIS
1606
1607 #define PIS(x) \
1608 seq_printf(s, "%-20s %10d\n", #x, \
1609 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1610
1611 seq_printf(s, "-- CIO interrupts --\n");
1612 PIS(ERRSYNCESC1);
1613 PIS(ERRSYNCESC2);
1614 PIS(ERRSYNCESC3);
1615 PIS(ERRESC1);
1616 PIS(ERRESC2);
1617 PIS(ERRESC3);
1618 PIS(ERRCONTROL1);
1619 PIS(ERRCONTROL2);
1620 PIS(ERRCONTROL3);
1621 PIS(STATEULPS1);
1622 PIS(STATEULPS2);
1623 PIS(STATEULPS3);
1624 PIS(ERRCONTENTIONLP0_1);
1625 PIS(ERRCONTENTIONLP1_1);
1626 PIS(ERRCONTENTIONLP0_2);
1627 PIS(ERRCONTENTIONLP1_2);
1628 PIS(ERRCONTENTIONLP0_3);
1629 PIS(ERRCONTENTIONLP1_3);
1630 PIS(ULPSACTIVENOT_ALL0);
1631 PIS(ULPSACTIVENOT_ALL1);
1632 #undef PIS
1633 }
1634
1635 static void dsi1_dump_irqs(struct seq_file *s)
1636 {
1637 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1638
1639 dsi_dump_dsidev_irqs(dsidev, s);
1640 }
1641
1642 static void dsi2_dump_irqs(struct seq_file *s)
1643 {
1644 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1645
1646 dsi_dump_dsidev_irqs(dsidev, s);
1647 }
1648 #endif
1649
1650 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
1651 struct seq_file *s)
1652 {
1653 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1654
1655 if (dsi_runtime_get(dsidev))
1656 return;
1657 dsi_enable_scp_clk(dsidev);
1658
1659 DUMPREG(DSI_REVISION);
1660 DUMPREG(DSI_SYSCONFIG);
1661 DUMPREG(DSI_SYSSTATUS);
1662 DUMPREG(DSI_IRQSTATUS);
1663 DUMPREG(DSI_IRQENABLE);
1664 DUMPREG(DSI_CTRL);
1665 DUMPREG(DSI_COMPLEXIO_CFG1);
1666 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1667 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1668 DUMPREG(DSI_CLK_CTRL);
1669 DUMPREG(DSI_TIMING1);
1670 DUMPREG(DSI_TIMING2);
1671 DUMPREG(DSI_VM_TIMING1);
1672 DUMPREG(DSI_VM_TIMING2);
1673 DUMPREG(DSI_VM_TIMING3);
1674 DUMPREG(DSI_CLK_TIMING);
1675 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1676 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1677 DUMPREG(DSI_COMPLEXIO_CFG2);
1678 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1679 DUMPREG(DSI_VM_TIMING4);
1680 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1681 DUMPREG(DSI_VM_TIMING5);
1682 DUMPREG(DSI_VM_TIMING6);
1683 DUMPREG(DSI_VM_TIMING7);
1684 DUMPREG(DSI_STOPCLK_TIMING);
1685
1686 DUMPREG(DSI_VC_CTRL(0));
1687 DUMPREG(DSI_VC_TE(0));
1688 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1689 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1690 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1691 DUMPREG(DSI_VC_IRQSTATUS(0));
1692 DUMPREG(DSI_VC_IRQENABLE(0));
1693
1694 DUMPREG(DSI_VC_CTRL(1));
1695 DUMPREG(DSI_VC_TE(1));
1696 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1697 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1698 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1699 DUMPREG(DSI_VC_IRQSTATUS(1));
1700 DUMPREG(DSI_VC_IRQENABLE(1));
1701
1702 DUMPREG(DSI_VC_CTRL(2));
1703 DUMPREG(DSI_VC_TE(2));
1704 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1705 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1706 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1707 DUMPREG(DSI_VC_IRQSTATUS(2));
1708 DUMPREG(DSI_VC_IRQENABLE(2));
1709
1710 DUMPREG(DSI_VC_CTRL(3));
1711 DUMPREG(DSI_VC_TE(3));
1712 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1713 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1714 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1715 DUMPREG(DSI_VC_IRQSTATUS(3));
1716 DUMPREG(DSI_VC_IRQENABLE(3));
1717
1718 DUMPREG(DSI_DSIPHY_CFG0);
1719 DUMPREG(DSI_DSIPHY_CFG1);
1720 DUMPREG(DSI_DSIPHY_CFG2);
1721 DUMPREG(DSI_DSIPHY_CFG5);
1722
1723 DUMPREG(DSI_PLL_CONTROL);
1724 DUMPREG(DSI_PLL_STATUS);
1725 DUMPREG(DSI_PLL_GO);
1726 DUMPREG(DSI_PLL_CONFIGURATION1);
1727 DUMPREG(DSI_PLL_CONFIGURATION2);
1728
1729 dsi_disable_scp_clk(dsidev);
1730 dsi_runtime_put(dsidev);
1731 #undef DUMPREG
1732 }
1733
1734 static void dsi1_dump_regs(struct seq_file *s)
1735 {
1736 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1737
1738 dsi_dump_dsidev_regs(dsidev, s);
1739 }
1740
1741 static void dsi2_dump_regs(struct seq_file *s)
1742 {
1743 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1744
1745 dsi_dump_dsidev_regs(dsidev, s);
1746 }
1747
1748 enum dsi_cio_power_state {
1749 DSI_COMPLEXIO_POWER_OFF = 0x0,
1750 DSI_COMPLEXIO_POWER_ON = 0x1,
1751 DSI_COMPLEXIO_POWER_ULPS = 0x2,
1752 };
1753
1754 static int dsi_cio_power(struct platform_device *dsidev,
1755 enum dsi_cio_power_state state)
1756 {
1757 int t = 0;
1758
1759 /* PWR_CMD */
1760 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
1761
1762 /* PWR_STATUS */
1763 while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
1764 26, 25) != state) {
1765 if (++t > 1000) {
1766 DSSERR("failed to set complexio power state to "
1767 "%d\n", state);
1768 return -ENODEV;
1769 }
1770 udelay(1);
1771 }
1772
1773 return 0;
1774 }
1775
1776 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
1777 {
1778 int val;
1779
1780 /* line buffer on OMAP3 is 1024 x 24bits */
1781 /* XXX: for some reason using full buffer size causes
1782 * considerable TX slowdown with update sizes that fill the
1783 * whole buffer */
1784 if (!dss_has_feature(FEAT_DSI_GNQ))
1785 return 1023 * 3;
1786
1787 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
1788
1789 switch (val) {
1790 case 1:
1791 return 512 * 3; /* 512x24 bits */
1792 case 2:
1793 return 682 * 3; /* 682x24 bits */
1794 case 3:
1795 return 853 * 3; /* 853x24 bits */
1796 case 4:
1797 return 1024 * 3; /* 1024x24 bits */
1798 case 5:
1799 return 1194 * 3; /* 1194x24 bits */
1800 case 6:
1801 return 1365 * 3; /* 1365x24 bits */
1802 case 7:
1803 return 1920 * 3; /* 1920x24 bits */
1804 default:
1805 BUG();
1806 return 0;
1807 }
1808 }
1809
1810 static int dsi_set_lane_config(struct platform_device *dsidev)
1811 {
1812 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1813 static const u8 offsets[] = { 0, 4, 8, 12, 16 };
1814 static const enum dsi_lane_function functions[] = {
1815 DSI_LANE_CLK,
1816 DSI_LANE_DATA1,
1817 DSI_LANE_DATA2,
1818 DSI_LANE_DATA3,
1819 DSI_LANE_DATA4,
1820 };
1821 u32 r;
1822 int i;
1823
1824 r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
1825
1826 for (i = 0; i < dsi->num_lanes_used; ++i) {
1827 unsigned offset = offsets[i];
1828 unsigned polarity, lane_number;
1829 unsigned t;
1830
1831 for (t = 0; t < dsi->num_lanes_supported; ++t)
1832 if (dsi->lanes[t].function == functions[i])
1833 break;
1834
1835 if (t == dsi->num_lanes_supported)
1836 return -EINVAL;
1837
1838 lane_number = t;
1839 polarity = dsi->lanes[t].polarity;
1840
1841 r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
1842 r = FLD_MOD(r, polarity, offset + 3, offset + 3);
1843 }
1844
1845 /* clear the unused lanes */
1846 for (; i < dsi->num_lanes_supported; ++i) {
1847 unsigned offset = offsets[i];
1848
1849 r = FLD_MOD(r, 0, offset + 2, offset);
1850 r = FLD_MOD(r, 0, offset + 3, offset + 3);
1851 }
1852
1853 dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
1854
1855 return 0;
1856 }
1857
1858 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
1859 {
1860 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1861
1862 /* convert time in ns to ddr ticks, rounding up */
1863 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
1864 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
1865 }
1866
1867 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
1868 {
1869 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1870
1871 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
1872 return ddr * 1000 * 1000 / (ddr_clk / 1000);
1873 }
1874
1875 static void dsi_cio_timings(struct platform_device *dsidev)
1876 {
1877 u32 r;
1878 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
1879 u32 tlpx_half, tclk_trail, tclk_zero;
1880 u32 tclk_prepare;
1881
1882 /* calculate timings */
1883
1884 /* 1 * DDR_CLK = 2 * UI */
1885
1886 /* min 40ns + 4*UI max 85ns + 6*UI */
1887 ths_prepare = ns2ddr(dsidev, 70) + 2;
1888
1889 /* min 145ns + 10*UI */
1890 ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
1891
1892 /* min max(8*UI, 60ns+4*UI) */
1893 ths_trail = ns2ddr(dsidev, 60) + 5;
1894
1895 /* min 100ns */
1896 ths_exit = ns2ddr(dsidev, 145);
1897
1898 /* tlpx min 50n */
1899 tlpx_half = ns2ddr(dsidev, 25);
1900
1901 /* min 60ns */
1902 tclk_trail = ns2ddr(dsidev, 60) + 2;
1903
1904 /* min 38ns, max 95ns */
1905 tclk_prepare = ns2ddr(dsidev, 65);
1906
1907 /* min tclk-prepare + tclk-zero = 300ns */
1908 tclk_zero = ns2ddr(dsidev, 260);
1909
1910 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1911 ths_prepare, ddr2ns(dsidev, ths_prepare),
1912 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
1913 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1914 ths_trail, ddr2ns(dsidev, ths_trail),
1915 ths_exit, ddr2ns(dsidev, ths_exit));
1916
1917 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1918 "tclk_zero %u (%uns)\n",
1919 tlpx_half, ddr2ns(dsidev, tlpx_half),
1920 tclk_trail, ddr2ns(dsidev, tclk_trail),
1921 tclk_zero, ddr2ns(dsidev, tclk_zero));
1922 DSSDBG("tclk_prepare %u (%uns)\n",
1923 tclk_prepare, ddr2ns(dsidev, tclk_prepare));
1924
1925 /* program timings */
1926
1927 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
1928 r = FLD_MOD(r, ths_prepare, 31, 24);
1929 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
1930 r = FLD_MOD(r, ths_trail, 15, 8);
1931 r = FLD_MOD(r, ths_exit, 7, 0);
1932 dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
1933
1934 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
1935 r = FLD_MOD(r, tlpx_half, 20, 16);
1936 r = FLD_MOD(r, tclk_trail, 15, 8);
1937 r = FLD_MOD(r, tclk_zero, 7, 0);
1938
1939 if (dss_has_feature(FEAT_DSI_PHY_DCC)) {
1940 r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */
1941 r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */
1942 r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */
1943 }
1944
1945 dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
1946
1947 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
1948 r = FLD_MOD(r, tclk_prepare, 7, 0);
1949 dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
1950 }
1951
1952 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
1953 static void dsi_cio_enable_lane_override(struct platform_device *dsidev,
1954 unsigned mask_p, unsigned mask_n)
1955 {
1956 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1957 int i;
1958 u32 l;
1959 u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
1960
1961 l = 0;
1962
1963 for (i = 0; i < dsi->num_lanes_supported; ++i) {
1964 unsigned p = dsi->lanes[i].polarity;
1965
1966 if (mask_p & (1 << i))
1967 l |= 1 << (i * 2 + (p ? 0 : 1));
1968
1969 if (mask_n & (1 << i))
1970 l |= 1 << (i * 2 + (p ? 1 : 0));
1971 }
1972
1973 /*
1974 * Bits in REGLPTXSCPDAT4TO0DXDY:
1975 * 17: DY0 18: DX0
1976 * 19: DY1 20: DX1
1977 * 21: DY2 22: DX2
1978 * 23: DY3 24: DX3
1979 * 25: DY4 26: DX4
1980 */
1981
1982 /* Set the lane override configuration */
1983
1984 /* REGLPTXSCPDAT4TO0DXDY */
1985 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
1986
1987 /* Enable lane override */
1988
1989 /* ENLPTXSCPDAT */
1990 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
1991 }
1992
1993 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
1994 {
1995 /* Disable lane override */
1996 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
1997 /* Reset the lane override configuration */
1998 /* REGLPTXSCPDAT4TO0DXDY */
1999 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
2000 }
2001
2002 static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev)
2003 {
2004 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2005 int t, i;
2006 bool in_use[DSI_MAX_NR_LANES];
2007 static const u8 offsets_old[] = { 28, 27, 26 };
2008 static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
2009 const u8 *offsets;
2010
2011 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC))
2012 offsets = offsets_old;
2013 else
2014 offsets = offsets_new;
2015
2016 for (i = 0; i < dsi->num_lanes_supported; ++i)
2017 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
2018
2019 t = 100000;
2020 while (true) {
2021 u32 l;
2022 int ok;
2023
2024 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2025
2026 ok = 0;
2027 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2028 if (!in_use[i] || (l & (1 << offsets[i])))
2029 ok++;
2030 }
2031
2032 if (ok == dsi->num_lanes_supported)
2033 break;
2034
2035 if (--t == 0) {
2036 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2037 if (!in_use[i] || (l & (1 << offsets[i])))
2038 continue;
2039
2040 DSSERR("CIO TXCLKESC%d domain not coming " \
2041 "out of reset\n", i);
2042 }
2043 return -EIO;
2044 }
2045 }
2046
2047 return 0;
2048 }
2049
2050 /* return bitmask of enabled lanes, lane0 being the lsb */
2051 static unsigned dsi_get_lane_mask(struct platform_device *dsidev)
2052 {
2053 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2054 unsigned mask = 0;
2055 int i;
2056
2057 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2058 if (dsi->lanes[i].function != DSI_LANE_UNUSED)
2059 mask |= 1 << i;
2060 }
2061
2062 return mask;
2063 }
2064
2065 static int dsi_cio_init(struct platform_device *dsidev)
2066 {
2067 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2068 int r;
2069 u32 l;
2070
2071 DSSDBG("DSI CIO init starts");
2072
2073 r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2074 if (r)
2075 return r;
2076
2077 dsi_enable_scp_clk(dsidev);
2078
2079 /* A dummy read using the SCP interface to any DSIPHY register is
2080 * required after DSIPHY reset to complete the reset of the DSI complex
2081 * I/O. */
2082 dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2083
2084 if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2085 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2086 r = -EIO;
2087 goto err_scp_clk_dom;
2088 }
2089
2090 r = dsi_set_lane_config(dsidev);
2091 if (r)
2092 goto err_scp_clk_dom;
2093
2094 /* set TX STOP MODE timer to maximum for this operation */
2095 l = dsi_read_reg(dsidev, DSI_TIMING1);
2096 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2097 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */
2098 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */
2099 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
2100 dsi_write_reg(dsidev, DSI_TIMING1, l);
2101
2102 if (dsi->ulps_enabled) {
2103 unsigned mask_p;
2104 int i;
2105
2106 DSSDBG("manual ulps exit\n");
2107
2108 /* ULPS is exited by Mark-1 state for 1ms, followed by
2109 * stop state. DSS HW cannot do this via the normal
2110 * ULPS exit sequence, as after reset the DSS HW thinks
2111 * that we are not in ULPS mode, and refuses to send the
2112 * sequence. So we need to send the ULPS exit sequence
2113 * manually by setting positive lines high and negative lines
2114 * low for 1ms.
2115 */
2116
2117 mask_p = 0;
2118
2119 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2120 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2121 continue;
2122 mask_p |= 1 << i;
2123 }
2124
2125 dsi_cio_enable_lane_override(dsidev, mask_p, 0);
2126 }
2127
2128 r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2129 if (r)
2130 goto err_cio_pwr;
2131
2132 if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2133 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2134 r = -ENODEV;
2135 goto err_cio_pwr_dom;
2136 }
2137
2138 dsi_if_enable(dsidev, true);
2139 dsi_if_enable(dsidev, false);
2140 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2141
2142 r = dsi_cio_wait_tx_clk_esc_reset(dsidev);
2143 if (r)
2144 goto err_tx_clk_esc_rst;
2145
2146 if (dsi->ulps_enabled) {
2147 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2148 ktime_t wait = ns_to_ktime(1000 * 1000);
2149 set_current_state(TASK_UNINTERRUPTIBLE);
2150 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2151
2152 /* Disable the override. The lanes should be set to Mark-11
2153 * state by the HW */
2154 dsi_cio_disable_lane_override(dsidev);
2155 }
2156
2157 /* FORCE_TX_STOP_MODE_IO */
2158 REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2159
2160 dsi_cio_timings(dsidev);
2161
2162 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
2163 /* DDR_CLK_ALWAYS_ON */
2164 REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
2165 dsi->vm_timings.ddr_clk_always_on, 13, 13);
2166 }
2167
2168 dsi->ulps_enabled = false;
2169
2170 DSSDBG("CIO init done\n");
2171
2172 return 0;
2173
2174 err_tx_clk_esc_rst:
2175 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2176 err_cio_pwr_dom:
2177 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2178 err_cio_pwr:
2179 if (dsi->ulps_enabled)
2180 dsi_cio_disable_lane_override(dsidev);
2181 err_scp_clk_dom:
2182 dsi_disable_scp_clk(dsidev);
2183 dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2184 return r;
2185 }
2186
2187 static void dsi_cio_uninit(struct platform_device *dsidev)
2188 {
2189 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2190
2191 /* DDR_CLK_ALWAYS_ON */
2192 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
2193
2194 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2195 dsi_disable_scp_clk(dsidev);
2196 dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2197 }
2198
2199 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2200 enum fifo_size size1, enum fifo_size size2,
2201 enum fifo_size size3, enum fifo_size size4)
2202 {
2203 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2204 u32 r = 0;
2205 int add = 0;
2206 int i;
2207
2208 dsi->vc[0].tx_fifo_size = size1;
2209 dsi->vc[1].tx_fifo_size = size2;
2210 dsi->vc[2].tx_fifo_size = size3;
2211 dsi->vc[3].tx_fifo_size = size4;
2212
2213 for (i = 0; i < 4; i++) {
2214 u8 v;
2215 int size = dsi->vc[i].tx_fifo_size;
2216
2217 if (add + size > 4) {
2218 DSSERR("Illegal FIFO configuration\n");
2219 BUG();
2220 return;
2221 }
2222
2223 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2224 r |= v << (8 * i);
2225 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2226 add += size;
2227 }
2228
2229 dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2230 }
2231
2232 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2233 enum fifo_size size1, enum fifo_size size2,
2234 enum fifo_size size3, enum fifo_size size4)
2235 {
2236 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2237 u32 r = 0;
2238 int add = 0;
2239 int i;
2240
2241 dsi->vc[0].rx_fifo_size = size1;
2242 dsi->vc[1].rx_fifo_size = size2;
2243 dsi->vc[2].rx_fifo_size = size3;
2244 dsi->vc[3].rx_fifo_size = size4;
2245
2246 for (i = 0; i < 4; i++) {
2247 u8 v;
2248 int size = dsi->vc[i].rx_fifo_size;
2249
2250 if (add + size > 4) {
2251 DSSERR("Illegal FIFO configuration\n");
2252 BUG();
2253 return;
2254 }
2255
2256 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2257 r |= v << (8 * i);
2258 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2259 add += size;
2260 }
2261
2262 dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2263 }
2264
2265 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2266 {
2267 u32 r;
2268
2269 r = dsi_read_reg(dsidev, DSI_TIMING1);
2270 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2271 dsi_write_reg(dsidev, DSI_TIMING1, r);
2272
2273 if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2274 DSSERR("TX_STOP bit not going down\n");
2275 return -EIO;
2276 }
2277
2278 return 0;
2279 }
2280
2281 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2282 {
2283 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2284 }
2285
2286 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2287 {
2288 struct dsi_packet_sent_handler_data *vp_data =
2289 (struct dsi_packet_sent_handler_data *) data;
2290 struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2291 const int channel = dsi->update_channel;
2292 u8 bit = dsi->te_enabled ? 30 : 31;
2293
2294 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2295 complete(vp_data->completion);
2296 }
2297
2298 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2299 {
2300 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2301 DECLARE_COMPLETION_ONSTACK(completion);
2302 struct dsi_packet_sent_handler_data vp_data = {
2303 .dsidev = dsidev,
2304 .completion = &completion
2305 };
2306 int r = 0;
2307 u8 bit;
2308
2309 bit = dsi->te_enabled ? 30 : 31;
2310
2311 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2312 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2313 if (r)
2314 goto err0;
2315
2316 /* Wait for completion only if TE_EN/TE_START is still set */
2317 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2318 if (wait_for_completion_timeout(&completion,
2319 msecs_to_jiffies(10)) == 0) {
2320 DSSERR("Failed to complete previous frame transfer\n");
2321 r = -EIO;
2322 goto err1;
2323 }
2324 }
2325
2326 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2327 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2328
2329 return 0;
2330 err1:
2331 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2332 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2333 err0:
2334 return r;
2335 }
2336
2337 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2338 {
2339 struct dsi_packet_sent_handler_data *l4_data =
2340 (struct dsi_packet_sent_handler_data *) data;
2341 struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2342 const int channel = dsi->update_channel;
2343
2344 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2345 complete(l4_data->completion);
2346 }
2347
2348 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2349 {
2350 DECLARE_COMPLETION_ONSTACK(completion);
2351 struct dsi_packet_sent_handler_data l4_data = {
2352 .dsidev = dsidev,
2353 .completion = &completion
2354 };
2355 int r = 0;
2356
2357 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2358 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2359 if (r)
2360 goto err0;
2361
2362 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2363 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2364 if (wait_for_completion_timeout(&completion,
2365 msecs_to_jiffies(10)) == 0) {
2366 DSSERR("Failed to complete previous l4 transfer\n");
2367 r = -EIO;
2368 goto err1;
2369 }
2370 }
2371
2372 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2373 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2374
2375 return 0;
2376 err1:
2377 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2378 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2379 err0:
2380 return r;
2381 }
2382
2383 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2384 {
2385 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2386
2387 WARN_ON(!dsi_bus_is_locked(dsidev));
2388
2389 WARN_ON(in_interrupt());
2390
2391 if (!dsi_vc_is_enabled(dsidev, channel))
2392 return 0;
2393
2394 switch (dsi->vc[channel].source) {
2395 case DSI_VC_SOURCE_VP:
2396 return dsi_sync_vc_vp(dsidev, channel);
2397 case DSI_VC_SOURCE_L4:
2398 return dsi_sync_vc_l4(dsidev, channel);
2399 default:
2400 BUG();
2401 return -EINVAL;
2402 }
2403 }
2404
2405 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2406 bool enable)
2407 {
2408 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2409 channel, enable);
2410
2411 enable = enable ? 1 : 0;
2412
2413 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2414
2415 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2416 0, enable) != enable) {
2417 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2418 return -EIO;
2419 }
2420
2421 return 0;
2422 }
2423
2424 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2425 {
2426 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2427 u32 r;
2428
2429 DSSDBG("Initial config of virtual channel %d", channel);
2430
2431 r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2432
2433 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2434 DSSERR("VC(%d) busy when trying to configure it!\n",
2435 channel);
2436
2437 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2438 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
2439 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2440 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2441 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2442 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2443 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2444 if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2445 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */
2446
2447 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2448 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2449
2450 dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2451
2452 dsi->vc[channel].source = DSI_VC_SOURCE_L4;
2453 }
2454
2455 static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2456 enum dsi_vc_source source)
2457 {
2458 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2459
2460 if (dsi->vc[channel].source == source)
2461 return 0;
2462
2463 DSSDBG("Source config of virtual channel %d", channel);
2464
2465 dsi_sync_vc(dsidev, channel);
2466
2467 dsi_vc_enable(dsidev, channel, 0);
2468
2469 /* VC_BUSY */
2470 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2471 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2472 return -EIO;
2473 }
2474
2475 /* SOURCE, 0 = L4, 1 = video port */
2476 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2477
2478 /* DCS_CMD_ENABLE */
2479 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
2480 bool enable = source == DSI_VC_SOURCE_VP;
2481 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2482 }
2483
2484 dsi_vc_enable(dsidev, channel, 1);
2485
2486 dsi->vc[channel].source = source;
2487
2488 return 0;
2489 }
2490
2491 static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2492 bool enable)
2493 {
2494 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2495 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2496
2497 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2498
2499 WARN_ON(!dsi_bus_is_locked(dsidev));
2500
2501 dsi_vc_enable(dsidev, channel, 0);
2502 dsi_if_enable(dsidev, 0);
2503
2504 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2505
2506 dsi_vc_enable(dsidev, channel, 1);
2507 dsi_if_enable(dsidev, 1);
2508
2509 dsi_force_tx_stop_mode_io(dsidev);
2510
2511 /* start the DDR clock by sending a NULL packet */
2512 if (dsi->vm_timings.ddr_clk_always_on && enable)
2513 dsi_vc_send_null(dssdev, channel);
2514 }
2515
2516 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2517 {
2518 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2519 u32 val;
2520 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2521 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2522 (val >> 0) & 0xff,
2523 (val >> 8) & 0xff,
2524 (val >> 16) & 0xff,
2525 (val >> 24) & 0xff);
2526 }
2527 }
2528
2529 static void dsi_show_rx_ack_with_err(u16 err)
2530 {
2531 DSSERR("\tACK with ERROR (%#x):\n", err);
2532 if (err & (1 << 0))
2533 DSSERR("\t\tSoT Error\n");
2534 if (err & (1 << 1))
2535 DSSERR("\t\tSoT Sync Error\n");
2536 if (err & (1 << 2))
2537 DSSERR("\t\tEoT Sync Error\n");
2538 if (err & (1 << 3))
2539 DSSERR("\t\tEscape Mode Entry Command Error\n");
2540 if (err & (1 << 4))
2541 DSSERR("\t\tLP Transmit Sync Error\n");
2542 if (err & (1 << 5))
2543 DSSERR("\t\tHS Receive Timeout Error\n");
2544 if (err & (1 << 6))
2545 DSSERR("\t\tFalse Control Error\n");
2546 if (err & (1 << 7))
2547 DSSERR("\t\t(reserved7)\n");
2548 if (err & (1 << 8))
2549 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2550 if (err & (1 << 9))
2551 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2552 if (err & (1 << 10))
2553 DSSERR("\t\tChecksum Error\n");
2554 if (err & (1 << 11))
2555 DSSERR("\t\tData type not recognized\n");
2556 if (err & (1 << 12))
2557 DSSERR("\t\tInvalid VC ID\n");
2558 if (err & (1 << 13))
2559 DSSERR("\t\tInvalid Transmission Length\n");
2560 if (err & (1 << 14))
2561 DSSERR("\t\t(reserved14)\n");
2562 if (err & (1 << 15))
2563 DSSERR("\t\tDSI Protocol Violation\n");
2564 }
2565
2566 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2567 int channel)
2568 {
2569 /* RX_FIFO_NOT_EMPTY */
2570 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2571 u32 val;
2572 u8 dt;
2573 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2574 DSSERR("\trawval %#08x\n", val);
2575 dt = FLD_GET(val, 5, 0);
2576 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2577 u16 err = FLD_GET(val, 23, 8);
2578 dsi_show_rx_ack_with_err(err);
2579 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2580 DSSERR("\tDCS short response, 1 byte: %#x\n",
2581 FLD_GET(val, 23, 8));
2582 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2583 DSSERR("\tDCS short response, 2 byte: %#x\n",
2584 FLD_GET(val, 23, 8));
2585 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2586 DSSERR("\tDCS long response, len %d\n",
2587 FLD_GET(val, 23, 8));
2588 dsi_vc_flush_long_data(dsidev, channel);
2589 } else {
2590 DSSERR("\tunknown datatype 0x%02x\n", dt);
2591 }
2592 }
2593 return 0;
2594 }
2595
2596 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2597 {
2598 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2599
2600 if (dsi->debug_write || dsi->debug_read)
2601 DSSDBG("dsi_vc_send_bta %d\n", channel);
2602
2603 WARN_ON(!dsi_bus_is_locked(dsidev));
2604
2605 /* RX_FIFO_NOT_EMPTY */
2606 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2607 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2608 dsi_vc_flush_receive_data(dsidev, channel);
2609 }
2610
2611 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2612
2613 /* flush posted write */
2614 dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2615
2616 return 0;
2617 }
2618
2619 static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2620 {
2621 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2622 DECLARE_COMPLETION_ONSTACK(completion);
2623 int r = 0;
2624 u32 err;
2625
2626 r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2627 &completion, DSI_VC_IRQ_BTA);
2628 if (r)
2629 goto err0;
2630
2631 r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2632 DSI_IRQ_ERROR_MASK);
2633 if (r)
2634 goto err1;
2635
2636 r = dsi_vc_send_bta(dsidev, channel);
2637 if (r)
2638 goto err2;
2639
2640 if (wait_for_completion_timeout(&completion,
2641 msecs_to_jiffies(500)) == 0) {
2642 DSSERR("Failed to receive BTA\n");
2643 r = -EIO;
2644 goto err2;
2645 }
2646
2647 err = dsi_get_errors(dsidev);
2648 if (err) {
2649 DSSERR("Error while sending BTA: %x\n", err);
2650 r = -EIO;
2651 goto err2;
2652 }
2653 err2:
2654 dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2655 DSI_IRQ_ERROR_MASK);
2656 err1:
2657 dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2658 &completion, DSI_VC_IRQ_BTA);
2659 err0:
2660 return r;
2661 }
2662
2663 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
2664 int channel, u8 data_type, u16 len, u8 ecc)
2665 {
2666 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2667 u32 val;
2668 u8 data_id;
2669
2670 WARN_ON(!dsi_bus_is_locked(dsidev));
2671
2672 data_id = data_type | dsi->vc[channel].vc_id << 6;
2673
2674 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2675 FLD_VAL(ecc, 31, 24);
2676
2677 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
2678 }
2679
2680 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
2681 int channel, u8 b1, u8 b2, u8 b3, u8 b4)
2682 {
2683 u32 val;
2684
2685 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
2686
2687 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2688 b1, b2, b3, b4, val); */
2689
2690 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2691 }
2692
2693 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
2694 u8 data_type, u8 *data, u16 len, u8 ecc)
2695 {
2696 /*u32 val; */
2697 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2698 int i;
2699 u8 *p;
2700 int r = 0;
2701 u8 b1, b2, b3, b4;
2702
2703 if (dsi->debug_write)
2704 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2705
2706 /* len + header */
2707 if (dsi->vc[channel].tx_fifo_size * 32 * 4 < len + 4) {
2708 DSSERR("unable to send long packet: packet too long.\n");
2709 return -EINVAL;
2710 }
2711
2712 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2713
2714 dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
2715
2716 p = data;
2717 for (i = 0; i < len >> 2; i++) {
2718 if (dsi->debug_write)
2719 DSSDBG("\tsending full packet %d\n", i);
2720
2721 b1 = *p++;
2722 b2 = *p++;
2723 b3 = *p++;
2724 b4 = *p++;
2725
2726 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
2727 }
2728
2729 i = len % 4;
2730 if (i) {
2731 b1 = 0; b2 = 0; b3 = 0;
2732
2733 if (dsi->debug_write)
2734 DSSDBG("\tsending remainder bytes %d\n", i);
2735
2736 switch (i) {
2737 case 3:
2738 b1 = *p++;
2739 b2 = *p++;
2740 b3 = *p++;
2741 break;
2742 case 2:
2743 b1 = *p++;
2744 b2 = *p++;
2745 break;
2746 case 1:
2747 b1 = *p++;
2748 break;
2749 }
2750
2751 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
2752 }
2753
2754 return r;
2755 }
2756
2757 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
2758 u8 data_type, u16 data, u8 ecc)
2759 {
2760 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2761 u32 r;
2762 u8 data_id;
2763
2764 WARN_ON(!dsi_bus_is_locked(dsidev));
2765
2766 if (dsi->debug_write)
2767 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2768 channel,
2769 data_type, data & 0xff, (data >> 8) & 0xff);
2770
2771 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2772
2773 if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
2774 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2775 return -EINVAL;
2776 }
2777
2778 data_id = data_type | dsi->vc[channel].vc_id << 6;
2779
2780 r = (data_id << 0) | (data << 8) | (ecc << 24);
2781
2782 dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
2783
2784 return 0;
2785 }
2786
2787 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
2788 {
2789 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2790
2791 return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
2792 0, 0);
2793 }
2794
2795 static int dsi_vc_write_nosync_common(struct platform_device *dsidev,
2796 int channel, u8 *data, int len, enum dss_dsi_content_type type)
2797 {
2798 int r;
2799
2800 if (len == 0) {
2801 BUG_ON(type == DSS_DSI_CONTENT_DCS);
2802 r = dsi_vc_send_short(dsidev, channel,
2803 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
2804 } else if (len == 1) {
2805 r = dsi_vc_send_short(dsidev, channel,
2806 type == DSS_DSI_CONTENT_GENERIC ?
2807 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
2808 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
2809 } else if (len == 2) {
2810 r = dsi_vc_send_short(dsidev, channel,
2811 type == DSS_DSI_CONTENT_GENERIC ?
2812 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
2813 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
2814 data[0] | (data[1] << 8), 0);
2815 } else {
2816 r = dsi_vc_send_long(dsidev, channel,
2817 type == DSS_DSI_CONTENT_GENERIC ?
2818 MIPI_DSI_GENERIC_LONG_WRITE :
2819 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
2820 }
2821
2822 return r;
2823 }
2824
2825 static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
2826 u8 *data, int len)
2827 {
2828 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2829
2830 return dsi_vc_write_nosync_common(dsidev, channel, data, len,
2831 DSS_DSI_CONTENT_DCS);
2832 }
2833
2834 static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
2835 u8 *data, int len)
2836 {
2837 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2838
2839 return dsi_vc_write_nosync_common(dsidev, channel, data, len,
2840 DSS_DSI_CONTENT_GENERIC);
2841 }
2842
2843 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
2844 u8 *data, int len, enum dss_dsi_content_type type)
2845 {
2846 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2847 int r;
2848
2849 r = dsi_vc_write_nosync_common(dsidev, channel, data, len, type);
2850 if (r)
2851 goto err;
2852
2853 r = dsi_vc_send_bta_sync(dssdev, channel);
2854 if (r)
2855 goto err;
2856
2857 /* RX_FIFO_NOT_EMPTY */
2858 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2859 DSSERR("rx fifo not empty after write, dumping data:\n");
2860 dsi_vc_flush_receive_data(dsidev, channel);
2861 r = -EIO;
2862 goto err;
2863 }
2864
2865 return 0;
2866 err:
2867 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
2868 channel, data[0], len);
2869 return r;
2870 }
2871
2872 static int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
2873 int len)
2874 {
2875 return dsi_vc_write_common(dssdev, channel, data, len,
2876 DSS_DSI_CONTENT_DCS);
2877 }
2878
2879 static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
2880 int len)
2881 {
2882 return dsi_vc_write_common(dssdev, channel, data, len,
2883 DSS_DSI_CONTENT_GENERIC);
2884 }
2885
2886 static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev,
2887 int channel, u8 dcs_cmd)
2888 {
2889 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2890 int r;
2891
2892 if (dsi->debug_read)
2893 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
2894 channel, dcs_cmd);
2895
2896 r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
2897 if (r) {
2898 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
2899 " failed\n", channel, dcs_cmd);
2900 return r;
2901 }
2902
2903 return 0;
2904 }
2905
2906 static int dsi_vc_generic_send_read_request(struct platform_device *dsidev,
2907 int channel, u8 *reqdata, int reqlen)
2908 {
2909 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2910 u16 data;
2911 u8 data_type;
2912 int r;
2913
2914 if (dsi->debug_read)
2915 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
2916 channel, reqlen);
2917
2918 if (reqlen == 0) {
2919 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
2920 data = 0;
2921 } else if (reqlen == 1) {
2922 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
2923 data = reqdata[0];
2924 } else if (reqlen == 2) {
2925 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
2926 data = reqdata[0] | (reqdata[1] << 8);
2927 } else {
2928 BUG();
2929 return -EINVAL;
2930 }
2931
2932 r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
2933 if (r) {
2934 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
2935 " failed\n", channel, reqlen);
2936 return r;
2937 }
2938
2939 return 0;
2940 }
2941
2942 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
2943 u8 *buf, int buflen, enum dss_dsi_content_type type)
2944 {
2945 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2946 u32 val;
2947 u8 dt;
2948 int r;
2949
2950 /* RX_FIFO_NOT_EMPTY */
2951 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
2952 DSSERR("RX fifo empty when trying to read.\n");
2953 r = -EIO;
2954 goto err;
2955 }
2956
2957 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2958 if (dsi->debug_read)
2959 DSSDBG("\theader: %08x\n", val);
2960 dt = FLD_GET(val, 5, 0);
2961 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2962 u16 err = FLD_GET(val, 23, 8);
2963 dsi_show_rx_ack_with_err(err);
2964 r = -EIO;
2965 goto err;
2966
2967 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
2968 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
2969 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
2970 u8 data = FLD_GET(val, 15, 8);
2971 if (dsi->debug_read)
2972 DSSDBG("\t%s short response, 1 byte: %02x\n",
2973 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
2974 "DCS", data);
2975
2976 if (buflen < 1) {
2977 r = -EIO;
2978 goto err;
2979 }
2980
2981 buf[0] = data;
2982
2983 return 1;
2984 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
2985 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
2986 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
2987 u16 data = FLD_GET(val, 23, 8);
2988 if (dsi->debug_read)
2989 DSSDBG("\t%s short response, 2 byte: %04x\n",
2990 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
2991 "DCS", data);
2992
2993 if (buflen < 2) {
2994 r = -EIO;
2995 goto err;
2996 }
2997
2998 buf[0] = data & 0xff;
2999 buf[1] = (data >> 8) & 0xff;
3000
3001 return 2;
3002 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3003 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
3004 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
3005 int w;
3006 int len = FLD_GET(val, 23, 8);
3007 if (dsi->debug_read)
3008 DSSDBG("\t%s long response, len %d\n",
3009 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3010 "DCS", len);
3011
3012 if (len > buflen) {
3013 r = -EIO;
3014 goto err;
3015 }
3016
3017 /* two byte checksum ends the packet, not included in len */
3018 for (w = 0; w < len + 2;) {
3019 int b;
3020 val = dsi_read_reg(dsidev,
3021 DSI_VC_SHORT_PACKET_HEADER(channel));
3022 if (dsi->debug_read)
3023 DSSDBG("\t\t%02x %02x %02x %02x\n",
3024 (val >> 0) & 0xff,
3025 (val >> 8) & 0xff,
3026 (val >> 16) & 0xff,
3027 (val >> 24) & 0xff);
3028
3029 for (b = 0; b < 4; ++b) {
3030 if (w < len)
3031 buf[w] = (val >> (b * 8)) & 0xff;
3032 /* we discard the 2 byte checksum */
3033 ++w;
3034 }
3035 }
3036
3037 return len;
3038 } else {
3039 DSSERR("\tunknown datatype 0x%02x\n", dt);
3040 r = -EIO;
3041 goto err;
3042 }
3043
3044 err:
3045 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3046 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3047
3048 return r;
3049 }
3050
3051 static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3052 u8 *buf, int buflen)
3053 {
3054 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3055 int r;
3056
3057 r = dsi_vc_dcs_send_read_request(dsidev, channel, dcs_cmd);
3058 if (r)
3059 goto err;
3060
3061 r = dsi_vc_send_bta_sync(dssdev, channel);
3062 if (r)
3063 goto err;
3064
3065 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3066 DSS_DSI_CONTENT_DCS);
3067 if (r < 0)
3068 goto err;
3069
3070 if (r != buflen) {
3071 r = -EIO;
3072 goto err;
3073 }
3074
3075 return 0;
3076 err:
3077 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3078 return r;
3079 }
3080
3081 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3082 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3083 {
3084 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3085 int r;
3086
3087 r = dsi_vc_generic_send_read_request(dsidev, channel, reqdata, reqlen);
3088 if (r)
3089 return r;
3090
3091 r = dsi_vc_send_bta_sync(dssdev, channel);
3092 if (r)
3093 return r;
3094
3095 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3096 DSS_DSI_CONTENT_GENERIC);
3097 if (r < 0)
3098 return r;
3099
3100 if (r != buflen) {
3101 r = -EIO;
3102 return r;
3103 }
3104
3105 return 0;
3106 }
3107
3108 static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3109 u16 len)
3110 {
3111 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3112
3113 return dsi_vc_send_short(dsidev, channel,
3114 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3115 }
3116
3117 static int dsi_enter_ulps(struct platform_device *dsidev)
3118 {
3119 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3120 DECLARE_COMPLETION_ONSTACK(completion);
3121 int r, i;
3122 unsigned mask;
3123
3124 DSSDBG("Entering ULPS");
3125
3126 WARN_ON(!dsi_bus_is_locked(dsidev));
3127
3128 WARN_ON(dsi->ulps_enabled);
3129
3130 if (dsi->ulps_enabled)
3131 return 0;
3132
3133 /* DDR_CLK_ALWAYS_ON */
3134 if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3135 dsi_if_enable(dsidev, 0);
3136 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
3137 dsi_if_enable(dsidev, 1);
3138 }
3139
3140 dsi_sync_vc(dsidev, 0);
3141 dsi_sync_vc(dsidev, 1);
3142 dsi_sync_vc(dsidev, 2);
3143 dsi_sync_vc(dsidev, 3);
3144
3145 dsi_force_tx_stop_mode_io(dsidev);
3146
3147 dsi_vc_enable(dsidev, 0, false);
3148 dsi_vc_enable(dsidev, 1, false);
3149 dsi_vc_enable(dsidev, 2, false);
3150 dsi_vc_enable(dsidev, 3, false);
3151
3152 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */
3153 DSSERR("HS busy when enabling ULPS\n");
3154 return -EIO;
3155 }
3156
3157 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */
3158 DSSERR("LP busy when enabling ULPS\n");
3159 return -EIO;
3160 }
3161
3162 r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3163 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3164 if (r)
3165 return r;
3166
3167 mask = 0;
3168
3169 for (i = 0; i < dsi->num_lanes_supported; ++i) {
3170 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
3171 continue;
3172 mask |= 1 << i;
3173 }
3174 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3175 /* LANEx_ULPS_SIG2 */
3176 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3177
3178 /* flush posted write and wait for SCP interface to finish the write */
3179 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3180
3181 if (wait_for_completion_timeout(&completion,
3182 msecs_to_jiffies(1000)) == 0) {
3183 DSSERR("ULPS enable timeout\n");
3184 r = -EIO;
3185 goto err;
3186 }
3187
3188 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3189 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3190
3191 /* Reset LANEx_ULPS_SIG2 */
3192 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3193
3194 /* flush posted write and wait for SCP interface to finish the write */
3195 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3196
3197 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3198
3199 dsi_if_enable(dsidev, false);
3200
3201 dsi->ulps_enabled = true;
3202
3203 return 0;
3204
3205 err:
3206 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3207 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3208 return r;
3209 }
3210
3211 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3212 unsigned ticks, bool x4, bool x16)
3213 {
3214 unsigned long fck;
3215 unsigned long total_ticks;
3216 u32 r;
3217
3218 BUG_ON(ticks > 0x1fff);
3219
3220 /* ticks in DSI_FCK */
3221 fck = dsi_fclk_rate(dsidev);
3222
3223 r = dsi_read_reg(dsidev, DSI_TIMING2);
3224 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
3225 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
3226 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3227 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
3228 dsi_write_reg(dsidev, DSI_TIMING2, r);
3229
3230 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3231
3232 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3233 total_ticks,
3234 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3235 (total_ticks * 1000) / (fck / 1000 / 1000));
3236 }
3237
3238 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3239 bool x8, bool x16)
3240 {
3241 unsigned long fck;
3242 unsigned long total_ticks;
3243 u32 r;
3244
3245 BUG_ON(ticks > 0x1fff);
3246
3247 /* ticks in DSI_FCK */
3248 fck = dsi_fclk_rate(dsidev);
3249
3250 r = dsi_read_reg(dsidev, DSI_TIMING1);
3251 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
3252 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
3253 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
3254 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
3255 dsi_write_reg(dsidev, DSI_TIMING1, r);
3256
3257 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3258
3259 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3260 total_ticks,
3261 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3262 (total_ticks * 1000) / (fck / 1000 / 1000));
3263 }
3264
3265 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3266 unsigned ticks, bool x4, bool x16)
3267 {
3268 unsigned long fck;
3269 unsigned long total_ticks;
3270 u32 r;
3271
3272 BUG_ON(ticks > 0x1fff);
3273
3274 /* ticks in DSI_FCK */
3275 fck = dsi_fclk_rate(dsidev);
3276
3277 r = dsi_read_reg(dsidev, DSI_TIMING1);
3278 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
3279 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
3280 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3281 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
3282 dsi_write_reg(dsidev, DSI_TIMING1, r);
3283
3284 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3285
3286 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3287 total_ticks,
3288 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3289 (total_ticks * 1000) / (fck / 1000 / 1000));
3290 }
3291
3292 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3293 unsigned ticks, bool x4, bool x16)
3294 {
3295 unsigned long fck;
3296 unsigned long total_ticks;
3297 u32 r;
3298
3299 BUG_ON(ticks > 0x1fff);
3300
3301 /* ticks in TxByteClkHS */
3302 fck = dsi_get_txbyteclkhs(dsidev);
3303
3304 r = dsi_read_reg(dsidev, DSI_TIMING2);
3305 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
3306 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
3307 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3308 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
3309 dsi_write_reg(dsidev, DSI_TIMING2, r);
3310
3311 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3312
3313 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3314 total_ticks,
3315 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3316 (total_ticks * 1000) / (fck / 1000 / 1000));
3317 }
3318
3319 static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev)
3320 {
3321 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3322 int num_line_buffers;
3323
3324 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3325 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3326 struct omap_video_timings *timings = &dsi->timings;
3327 /*
3328 * Don't use line buffers if width is greater than the video
3329 * port's line buffer size
3330 */
3331 if (dsi->line_buffer_size <= timings->x_res * bpp / 8)
3332 num_line_buffers = 0;
3333 else
3334 num_line_buffers = 2;
3335 } else {
3336 /* Use maximum number of line buffers in command mode */
3337 num_line_buffers = 2;
3338 }
3339
3340 /* LINE_BUFFER */
3341 REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
3342 }
3343
3344 static void dsi_config_vp_sync_events(struct platform_device *dsidev)
3345 {
3346 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3347 bool sync_end;
3348 u32 r;
3349
3350 if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE)
3351 sync_end = true;
3352 else
3353 sync_end = false;
3354
3355 r = dsi_read_reg(dsidev, DSI_CTRL);
3356 r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */
3357 r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */
3358 r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */
3359 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */
3360 r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */
3361 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */
3362 r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */
3363 dsi_write_reg(dsidev, DSI_CTRL, r);
3364 }
3365
3366 static void dsi_config_blanking_modes(struct platform_device *dsidev)
3367 {
3368 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3369 int blanking_mode = dsi->vm_timings.blanking_mode;
3370 int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode;
3371 int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode;
3372 int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode;
3373 u32 r;
3374
3375 /*
3376 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3377 * 1 = Long blanking packets are sent in corresponding blanking periods
3378 */
3379 r = dsi_read_reg(dsidev, DSI_CTRL);
3380 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */
3381 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */
3382 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */
3383 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */
3384 dsi_write_reg(dsidev, DSI_CTRL, r);
3385 }
3386
3387 /*
3388 * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3
3389 * results in maximum transition time for data and clock lanes to enter and
3390 * exit HS mode. Hence, this is the scenario where the least amount of command
3391 * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
3392 * clock cycles that can be used to interleave command mode data in HS so that
3393 * all scenarios are satisfied.
3394 */
3395 static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs,
3396 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post)
3397 {
3398 int transition;
3399
3400 /*
3401 * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition
3402 * time of data lanes only, if it isn't set, we need to consider HS
3403 * transition time of both data and clock lanes. HS transition time
3404 * of Scenario 3 is considered.
3405 */
3406 if (ddr_alwon) {
3407 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1;
3408 } else {
3409 int trans1, trans2;
3410 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1;
3411 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre +
3412 enter_hs + 1;
3413 transition = max(trans1, trans2);
3414 }
3415
3416 return blank > transition ? blank - transition : 0;
3417 }
3418
3419 /*
3420 * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1
3421 * results in maximum transition time for data lanes to enter and exit LP mode.
3422 * Hence, this is the scenario where the least amount of command mode data can
3423 * be interleaved. We program the minimum amount of bytes that can be
3424 * interleaved in LP so that all scenarios are satisfied.
3425 */
3426 static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs,
3427 int lp_clk_div, int tdsi_fclk)
3428 {
3429 int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */
3430 int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */
3431 int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */
3432 int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */
3433 int lp_inter; /* cmd mode data that can be interleaved, in bytes */
3434
3435 /* maximum LP transition time according to Scenario 1 */
3436 trans_lp = exit_hs + max(enter_hs, 2) + 1;
3437
3438 /* CLKIN4DDR = 16 * TXBYTECLKHS */
3439 tlp_avail = thsbyte_clk * (blank - trans_lp);
3440
3441 ttxclkesc = tdsi_fclk * lp_clk_div;
3442
3443 lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc -
3444 26) / 16;
3445
3446 return max(lp_inter, 0);
3447 }
3448
3449 static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev)
3450 {
3451 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3452 int blanking_mode;
3453 int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode;
3454 int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div;
3455 int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
3456 int tclk_trail, ths_exit, exiths_clk;
3457 bool ddr_alwon;
3458 struct omap_video_timings *timings = &dsi->timings;
3459 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3460 int ndl = dsi->num_lanes_used - 1;
3461 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1;
3462 int hsa_interleave_hs = 0, hsa_interleave_lp = 0;
3463 int hfp_interleave_hs = 0, hfp_interleave_lp = 0;
3464 int hbp_interleave_hs = 0, hbp_interleave_lp = 0;
3465 int bl_interleave_hs = 0, bl_interleave_lp = 0;
3466 u32 r;
3467
3468 r = dsi_read_reg(dsidev, DSI_CTRL);
3469 blanking_mode = FLD_GET(r, 20, 20);
3470 hfp_blanking_mode = FLD_GET(r, 21, 21);
3471 hbp_blanking_mode = FLD_GET(r, 22, 22);
3472 hsa_blanking_mode = FLD_GET(r, 23, 23);
3473
3474 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3475 hbp = FLD_GET(r, 11, 0);
3476 hfp = FLD_GET(r, 23, 12);
3477 hsa = FLD_GET(r, 31, 24);
3478
3479 r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3480 ddr_clk_post = FLD_GET(r, 7, 0);
3481 ddr_clk_pre = FLD_GET(r, 15, 8);
3482
3483 r = dsi_read_reg(dsidev, DSI_VM_TIMING7);
3484 exit_hs_mode_lat = FLD_GET(r, 15, 0);
3485 enter_hs_mode_lat = FLD_GET(r, 31, 16);
3486
3487 r = dsi_read_reg(dsidev, DSI_CLK_CTRL);
3488 lp_clk_div = FLD_GET(r, 12, 0);
3489 ddr_alwon = FLD_GET(r, 13, 13);
3490
3491 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3492 ths_exit = FLD_GET(r, 7, 0);
3493
3494 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3495 tclk_trail = FLD_GET(r, 15, 8);
3496
3497 exiths_clk = ths_exit + tclk_trail;
3498
3499 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3500 bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
3501
3502 if (!hsa_blanking_mode) {
3503 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon,
3504 enter_hs_mode_lat, exit_hs_mode_lat,
3505 exiths_clk, ddr_clk_pre, ddr_clk_post);
3506 hsa_interleave_lp = dsi_compute_interleave_lp(hsa,
3507 enter_hs_mode_lat, exit_hs_mode_lat,
3508 lp_clk_div, dsi_fclk_hsdiv);
3509 }
3510
3511 if (!hfp_blanking_mode) {
3512 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon,
3513 enter_hs_mode_lat, exit_hs_mode_lat,
3514 exiths_clk, ddr_clk_pre, ddr_clk_post);
3515 hfp_interleave_lp = dsi_compute_interleave_lp(hfp,
3516 enter_hs_mode_lat, exit_hs_mode_lat,
3517 lp_clk_div, dsi_fclk_hsdiv);
3518 }
3519
3520 if (!hbp_blanking_mode) {
3521 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon,
3522 enter_hs_mode_lat, exit_hs_mode_lat,
3523 exiths_clk, ddr_clk_pre, ddr_clk_post);
3524
3525 hbp_interleave_lp = dsi_compute_interleave_lp(hbp,
3526 enter_hs_mode_lat, exit_hs_mode_lat,
3527 lp_clk_div, dsi_fclk_hsdiv);
3528 }
3529
3530 if (!blanking_mode) {
3531 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon,
3532 enter_hs_mode_lat, exit_hs_mode_lat,
3533 exiths_clk, ddr_clk_pre, ddr_clk_post);
3534
3535 bl_interleave_lp = dsi_compute_interleave_lp(bllp,
3536 enter_hs_mode_lat, exit_hs_mode_lat,
3537 lp_clk_div, dsi_fclk_hsdiv);
3538 }
3539
3540 DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3541 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs,
3542 bl_interleave_hs);
3543
3544 DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3545 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp,
3546 bl_interleave_lp);
3547
3548 r = dsi_read_reg(dsidev, DSI_VM_TIMING4);
3549 r = FLD_MOD(r, hsa_interleave_hs, 23, 16);
3550 r = FLD_MOD(r, hfp_interleave_hs, 15, 8);
3551 r = FLD_MOD(r, hbp_interleave_hs, 7, 0);
3552 dsi_write_reg(dsidev, DSI_VM_TIMING4, r);
3553
3554 r = dsi_read_reg(dsidev, DSI_VM_TIMING5);
3555 r = FLD_MOD(r, hsa_interleave_lp, 23, 16);
3556 r = FLD_MOD(r, hfp_interleave_lp, 15, 8);
3557 r = FLD_MOD(r, hbp_interleave_lp, 7, 0);
3558 dsi_write_reg(dsidev, DSI_VM_TIMING5, r);
3559
3560 r = dsi_read_reg(dsidev, DSI_VM_TIMING6);
3561 r = FLD_MOD(r, bl_interleave_hs, 31, 15);
3562 r = FLD_MOD(r, bl_interleave_lp, 16, 0);
3563 dsi_write_reg(dsidev, DSI_VM_TIMING6, r);
3564 }
3565
3566 static int dsi_proto_config(struct platform_device *dsidev)
3567 {
3568 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3569 u32 r;
3570 int buswidth = 0;
3571
3572 dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3573 DSI_FIFO_SIZE_32,
3574 DSI_FIFO_SIZE_32,
3575 DSI_FIFO_SIZE_32);
3576
3577 dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3578 DSI_FIFO_SIZE_32,
3579 DSI_FIFO_SIZE_32,
3580 DSI_FIFO_SIZE_32);
3581
3582 /* XXX what values for the timeouts? */
3583 dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
3584 dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
3585 dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
3586 dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
3587
3588 switch (dsi_get_pixel_size(dsi->pix_fmt)) {
3589 case 16:
3590 buswidth = 0;
3591 break;
3592 case 18:
3593 buswidth = 1;
3594 break;
3595 case 24:
3596 buswidth = 2;
3597 break;
3598 default:
3599 BUG();
3600 return -EINVAL;
3601 }
3602
3603 r = dsi_read_reg(dsidev, DSI_CTRL);
3604 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
3605 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
3606 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
3607 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
3608 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3609 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
3610 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
3611 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
3612 if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
3613 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
3614 /* DCS_CMD_CODE, 1=start, 0=continue */
3615 r = FLD_MOD(r, 0, 25, 25);
3616 }
3617
3618 dsi_write_reg(dsidev, DSI_CTRL, r);
3619
3620 dsi_config_vp_num_line_buffers(dsidev);
3621
3622 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3623 dsi_config_vp_sync_events(dsidev);
3624 dsi_config_blanking_modes(dsidev);
3625 dsi_config_cmd_mode_interleaving(dsidev);
3626 }
3627
3628 dsi_vc_initial_config(dsidev, 0);
3629 dsi_vc_initial_config(dsidev, 1);
3630 dsi_vc_initial_config(dsidev, 2);
3631 dsi_vc_initial_config(dsidev, 3);
3632
3633 return 0;
3634 }
3635
3636 static void dsi_proto_timings(struct platform_device *dsidev)
3637 {
3638 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3639 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
3640 unsigned tclk_pre, tclk_post;
3641 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
3642 unsigned ths_trail, ths_exit;
3643 unsigned ddr_clk_pre, ddr_clk_post;
3644 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
3645 unsigned ths_eot;
3646 int ndl = dsi->num_lanes_used - 1;
3647 u32 r;
3648
3649 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3650 ths_prepare = FLD_GET(r, 31, 24);
3651 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3652 ths_zero = ths_prepare_ths_zero - ths_prepare;
3653 ths_trail = FLD_GET(r, 15, 8);
3654 ths_exit = FLD_GET(r, 7, 0);
3655
3656 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3657 tlpx = FLD_GET(r, 20, 16) * 2;
3658 tclk_trail = FLD_GET(r, 15, 8);
3659 tclk_zero = FLD_GET(r, 7, 0);
3660
3661 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
3662 tclk_prepare = FLD_GET(r, 7, 0);
3663
3664 /* min 8*UI */
3665 tclk_pre = 20;
3666 /* min 60ns + 52*UI */
3667 tclk_post = ns2ddr(dsidev, 60) + 26;
3668
3669 ths_eot = DIV_ROUND_UP(4, ndl);
3670
3671 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3672 4);
3673 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3674
3675 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3676 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3677
3678 r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3679 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3680 r = FLD_MOD(r, ddr_clk_post, 7, 0);
3681 dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
3682
3683 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3684 ddr_clk_pre,
3685 ddr_clk_post);
3686
3687 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3688 DIV_ROUND_UP(ths_prepare, 4) +
3689 DIV_ROUND_UP(ths_zero + 3, 4);
3690
3691 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3692
3693 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3694 FLD_VAL(exit_hs_mode_lat, 15, 0);
3695 dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
3696
3697 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3698 enter_hs_mode_lat, exit_hs_mode_lat);
3699
3700 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3701 /* TODO: Implement a video mode check_timings function */
3702 int hsa = dsi->vm_timings.hsa;
3703 int hfp = dsi->vm_timings.hfp;
3704 int hbp = dsi->vm_timings.hbp;
3705 int vsa = dsi->vm_timings.vsa;
3706 int vfp = dsi->vm_timings.vfp;
3707 int vbp = dsi->vm_timings.vbp;
3708 int window_sync = dsi->vm_timings.window_sync;
3709 bool hsync_end;
3710 struct omap_video_timings *timings = &dsi->timings;
3711 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3712 int tl, t_he, width_bytes;
3713
3714 hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE;
3715 t_he = hsync_end ?
3716 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
3717
3718 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3719
3720 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3721 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
3722 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
3723
3724 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
3725 hfp, hsync_end ? hsa : 0, tl);
3726 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
3727 vsa, timings->y_res);
3728
3729 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3730 r = FLD_MOD(r, hbp, 11, 0); /* HBP */
3731 r = FLD_MOD(r, hfp, 23, 12); /* HFP */
3732 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */
3733 dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
3734
3735 r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
3736 r = FLD_MOD(r, vbp, 7, 0); /* VBP */
3737 r = FLD_MOD(r, vfp, 15, 8); /* VFP */
3738 r = FLD_MOD(r, vsa, 23, 16); /* VSA */
3739 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */
3740 dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
3741
3742 r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
3743 r = FLD_MOD(r, timings->y_res, 14, 0); /* VACT */
3744 r = FLD_MOD(r, tl, 31, 16); /* TL */
3745 dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
3746 }
3747 }
3748
3749 static int dsi_configure_pins(struct omap_dss_device *dssdev,
3750 const struct omap_dsi_pin_config *pin_cfg)
3751 {
3752 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3753 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3754 int num_pins;
3755 const int *pins;
3756 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
3757 int num_lanes;
3758 int i;
3759
3760 static const enum dsi_lane_function functions[] = {
3761 DSI_LANE_CLK,
3762 DSI_LANE_DATA1,
3763 DSI_LANE_DATA2,
3764 DSI_LANE_DATA3,
3765 DSI_LANE_DATA4,
3766 };
3767
3768 num_pins = pin_cfg->num_pins;
3769 pins = pin_cfg->pins;
3770
3771 if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2
3772 || num_pins % 2 != 0)
3773 return -EINVAL;
3774
3775 for (i = 0; i < DSI_MAX_NR_LANES; ++i)
3776 lanes[i].function = DSI_LANE_UNUSED;
3777
3778 num_lanes = 0;
3779
3780 for (i = 0; i < num_pins; i += 2) {
3781 u8 lane, pol;
3782 int dx, dy;
3783
3784 dx = pins[i];
3785 dy = pins[i + 1];
3786
3787 if (dx < 0 || dx >= dsi->num_lanes_supported * 2)
3788 return -EINVAL;
3789
3790 if (dy < 0 || dy >= dsi->num_lanes_supported * 2)
3791 return -EINVAL;
3792
3793 if (dx & 1) {
3794 if (dy != dx - 1)
3795 return -EINVAL;
3796 pol = 1;
3797 } else {
3798 if (dy != dx + 1)
3799 return -EINVAL;
3800 pol = 0;
3801 }
3802
3803 lane = dx / 2;
3804
3805 lanes[lane].function = functions[i / 2];
3806 lanes[lane].polarity = pol;
3807 num_lanes++;
3808 }
3809
3810 memcpy(dsi->lanes, lanes, sizeof(dsi->lanes));
3811 dsi->num_lanes_used = num_lanes;
3812
3813 return 0;
3814 }
3815
3816 static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
3817 {
3818 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3819 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3820 enum omap_channel dispc_channel = dssdev->dispc_channel;
3821 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3822 struct omap_dss_device *out = &dsi->output;
3823 u8 data_type;
3824 u16 word_count;
3825 int r;
3826
3827 if (!out->dispc_channel_connected) {
3828 DSSERR("failed to enable display: no output/manager\n");
3829 return -ENODEV;
3830 }
3831
3832 r = dsi_display_init_dispc(dsidev, dispc_channel);
3833 if (r)
3834 goto err_init_dispc;
3835
3836 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3837 switch (dsi->pix_fmt) {
3838 case OMAP_DSS_DSI_FMT_RGB888:
3839 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
3840 break;
3841 case OMAP_DSS_DSI_FMT_RGB666:
3842 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
3843 break;
3844 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
3845 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
3846 break;
3847 case OMAP_DSS_DSI_FMT_RGB565:
3848 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
3849 break;
3850 default:
3851 r = -EINVAL;
3852 goto err_pix_fmt;
3853 }
3854
3855 dsi_if_enable(dsidev, false);
3856 dsi_vc_enable(dsidev, channel, false);
3857
3858 /* MODE, 1 = video mode */
3859 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
3860
3861 word_count = DIV_ROUND_UP(dsi->timings.x_res * bpp, 8);
3862
3863 dsi_vc_write_long_header(dsidev, channel, data_type,
3864 word_count, 0);
3865
3866 dsi_vc_enable(dsidev, channel, true);
3867 dsi_if_enable(dsidev, true);
3868 }
3869
3870 r = dss_mgr_enable(dispc_channel);
3871 if (r)
3872 goto err_mgr_enable;
3873
3874 return 0;
3875
3876 err_mgr_enable:
3877 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3878 dsi_if_enable(dsidev, false);
3879 dsi_vc_enable(dsidev, channel, false);
3880 }
3881 err_pix_fmt:
3882 dsi_display_uninit_dispc(dsidev, dispc_channel);
3883 err_init_dispc:
3884 return r;
3885 }
3886
3887 static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
3888 {
3889 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3890 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3891 enum omap_channel dispc_channel = dssdev->dispc_channel;
3892
3893 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3894 dsi_if_enable(dsidev, false);
3895 dsi_vc_enable(dsidev, channel, false);
3896
3897 /* MODE, 0 = command mode */
3898 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
3899
3900 dsi_vc_enable(dsidev, channel, true);
3901 dsi_if_enable(dsidev, true);
3902 }
3903
3904 dss_mgr_disable(dispc_channel);
3905
3906 dsi_display_uninit_dispc(dsidev, dispc_channel);
3907 }
3908
3909 static void dsi_update_screen_dispc(struct platform_device *dsidev)
3910 {
3911 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3912 enum omap_channel dispc_channel = dsi->output.dispc_channel;
3913 unsigned bytespp;
3914 unsigned bytespl;
3915 unsigned bytespf;
3916 unsigned total_len;
3917 unsigned packet_payload;
3918 unsigned packet_len;
3919 u32 l;
3920 int r;
3921 const unsigned channel = dsi->update_channel;
3922 const unsigned line_buf_size = dsi->line_buffer_size;
3923 u16 w = dsi->timings.x_res;
3924 u16 h = dsi->timings.y_res;
3925
3926 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
3927
3928 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
3929
3930 bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8;
3931 bytespl = w * bytespp;
3932 bytespf = bytespl * h;
3933
3934 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
3935 * number of lines in a packet. See errata about VP_CLK_RATIO */
3936
3937 if (bytespf < line_buf_size)
3938 packet_payload = bytespf;
3939 else
3940 packet_payload = (line_buf_size) / bytespl * bytespl;
3941
3942 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
3943 total_len = (bytespf / packet_payload) * packet_len;
3944
3945 if (bytespf % packet_payload)
3946 total_len += (bytespf % packet_payload) + 1;
3947
3948 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
3949 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
3950
3951 dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
3952 packet_len, 0);
3953
3954 if (dsi->te_enabled)
3955 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
3956 else
3957 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
3958 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
3959
3960 /* We put SIDLEMODE to no-idle for the duration of the transfer,
3961 * because DSS interrupts are not capable of waking up the CPU and the
3962 * framedone interrupt could be delayed for quite a long time. I think
3963 * the same goes for any DSS interrupts, but for some reason I have not
3964 * seen the problem anywhere else than here.
3965 */
3966 dispc_disable_sidle();
3967
3968 dsi_perf_mark_start(dsidev);
3969
3970 r = schedule_delayed_work(&dsi->framedone_timeout_work,
3971 msecs_to_jiffies(250));
3972 BUG_ON(r == 0);
3973
3974 dss_mgr_set_timings(dispc_channel, &dsi->timings);
3975
3976 dss_mgr_start_update(dispc_channel);
3977
3978 if (dsi->te_enabled) {
3979 /* disable LP_RX_TO, so that we can receive TE. Time to wait
3980 * for TE is longer than the timer allows */
3981 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
3982
3983 dsi_vc_send_bta(dsidev, channel);
3984
3985 #ifdef DSI_CATCH_MISSING_TE
3986 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
3987 #endif
3988 }
3989 }
3990
3991 #ifdef DSI_CATCH_MISSING_TE
3992 static void dsi_te_timeout(unsigned long arg)
3993 {
3994 DSSERR("TE not received for 250ms!\n");
3995 }
3996 #endif
3997
3998 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
3999 {
4000 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4001
4002 /* SIDLEMODE back to smart-idle */
4003 dispc_enable_sidle();
4004
4005 if (dsi->te_enabled) {
4006 /* enable LP_RX_TO again after the TE */
4007 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
4008 }
4009
4010 dsi->framedone_callback(error, dsi->framedone_data);
4011
4012 if (!error)
4013 dsi_perf_show(dsidev, "DISPC");
4014 }
4015
4016 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4017 {
4018 struct dsi_data *dsi = container_of(work, struct dsi_data,
4019 framedone_timeout_work.work);
4020 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4021 * 250ms which would conflict with this timeout work. What should be
4022 * done is first cancel the transfer on the HW, and then cancel the
4023 * possibly scheduled framedone work. However, cancelling the transfer
4024 * on the HW is buggy, and would probably require resetting the whole
4025 * DSI */
4026
4027 DSSERR("Framedone not received for 250ms!\n");
4028
4029 dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
4030 }
4031
4032 static void dsi_framedone_irq_callback(void *data)
4033 {
4034 struct platform_device *dsidev = (struct platform_device *) data;
4035 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4036
4037 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4038 * turns itself off. However, DSI still has the pixels in its buffers,
4039 * and is sending the data.
4040 */
4041
4042 cancel_delayed_work(&dsi->framedone_timeout_work);
4043
4044 dsi_handle_framedone(dsidev, 0);
4045 }
4046
4047 static int dsi_update(struct omap_dss_device *dssdev, int channel,
4048 void (*callback)(int, void *), void *data)
4049 {
4050 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4051 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4052 u16 dw, dh;
4053
4054 dsi_perf_mark_setup(dsidev);
4055
4056 dsi->update_channel = channel;
4057
4058 dsi->framedone_callback = callback;
4059 dsi->framedone_data = data;
4060
4061 dw = dsi->timings.x_res;
4062 dh = dsi->timings.y_res;
4063
4064 #ifdef DSI_PERF_MEASURE
4065 dsi->update_bytes = dw * dh *
4066 dsi_get_pixel_size(dsi->pix_fmt) / 8;
4067 #endif
4068 dsi_update_screen_dispc(dsidev);
4069
4070 return 0;
4071 }
4072
4073 /* Display funcs */
4074
4075 static int dsi_configure_dispc_clocks(struct platform_device *dsidev)
4076 {
4077 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4078 struct dispc_clock_info dispc_cinfo;
4079 int r;
4080 unsigned long fck;
4081
4082 fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4083
4084 dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div;
4085 dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div;
4086
4087 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4088 if (r) {
4089 DSSERR("Failed to calc dispc clocks\n");
4090 return r;
4091 }
4092
4093 dsi->mgr_config.clock_info = dispc_cinfo;
4094
4095 return 0;
4096 }
4097
4098 static int dsi_display_init_dispc(struct platform_device *dsidev,
4099 enum omap_channel channel)
4100 {
4101 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4102 int r;
4103
4104 dss_select_lcd_clk_source(channel, dsi->module_id == 0 ?
4105 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
4106 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC);
4107
4108 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
4109 r = dss_mgr_register_framedone_handler(channel,
4110 dsi_framedone_irq_callback, dsidev);
4111 if (r) {
4112 DSSERR("can't register FRAMEDONE handler\n");
4113 goto err;
4114 }
4115
4116 dsi->mgr_config.stallmode = true;
4117 dsi->mgr_config.fifohandcheck = true;
4118 } else {
4119 dsi->mgr_config.stallmode = false;
4120 dsi->mgr_config.fifohandcheck = false;
4121 }
4122
4123 /*
4124 * override interlace, logic level and edge related parameters in
4125 * omap_video_timings with default values
4126 */
4127 dsi->timings.interlace = false;
4128 dsi->timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4129 dsi->timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4130 dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
4131 dsi->timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH;
4132 dsi->timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE;
4133
4134 dss_mgr_set_timings(channel, &dsi->timings);
4135
4136 r = dsi_configure_dispc_clocks(dsidev);
4137 if (r)
4138 goto err1;
4139
4140 dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
4141 dsi->mgr_config.video_port_width =
4142 dsi_get_pixel_size(dsi->pix_fmt);
4143 dsi->mgr_config.lcden_sig_polarity = 0;
4144
4145 dss_mgr_set_lcd_config(channel, &dsi->mgr_config);
4146
4147 return 0;
4148 err1:
4149 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4150 dss_mgr_unregister_framedone_handler(channel,
4151 dsi_framedone_irq_callback, dsidev);
4152 err:
4153 dss_select_lcd_clk_source(channel, OMAP_DSS_CLK_SRC_FCK);
4154 return r;
4155 }
4156
4157 static void dsi_display_uninit_dispc(struct platform_device *dsidev,
4158 enum omap_channel channel)
4159 {
4160 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4161
4162 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4163 dss_mgr_unregister_framedone_handler(channel,
4164 dsi_framedone_irq_callback, dsidev);
4165
4166 dss_select_lcd_clk_source(channel, OMAP_DSS_CLK_SRC_FCK);
4167 }
4168
4169 static int dsi_configure_dsi_clocks(struct platform_device *dsidev)
4170 {
4171 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4172 struct dss_pll_clock_info cinfo;
4173 int r;
4174
4175 cinfo = dsi->user_dsi_cinfo;
4176
4177 r = dss_pll_set_config(&dsi->pll, &cinfo);
4178 if (r) {
4179 DSSERR("Failed to set dsi clocks\n");
4180 return r;
4181 }
4182
4183 return 0;
4184 }
4185
4186 static int dsi_display_init_dsi(struct platform_device *dsidev)
4187 {
4188 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4189 int r;
4190
4191 r = dss_pll_enable(&dsi->pll);
4192 if (r)
4193 goto err0;
4194
4195 r = dsi_configure_dsi_clocks(dsidev);
4196 if (r)
4197 goto err1;
4198
4199 dss_select_dsi_clk_source(dsi->module_id, dsi->module_id == 0 ?
4200 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
4201 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI);
4202
4203 DSSDBG("PLL OK\n");
4204
4205 r = dsi_cio_init(dsidev);
4206 if (r)
4207 goto err2;
4208
4209 _dsi_print_reset_status(dsidev);
4210
4211 dsi_proto_timings(dsidev);
4212 dsi_set_lp_clk_divisor(dsidev);
4213
4214 if (1)
4215 _dsi_print_reset_status(dsidev);
4216
4217 r = dsi_proto_config(dsidev);
4218 if (r)
4219 goto err3;
4220
4221 /* enable interface */
4222 dsi_vc_enable(dsidev, 0, 1);
4223 dsi_vc_enable(dsidev, 1, 1);
4224 dsi_vc_enable(dsidev, 2, 1);
4225 dsi_vc_enable(dsidev, 3, 1);
4226 dsi_if_enable(dsidev, 1);
4227 dsi_force_tx_stop_mode_io(dsidev);
4228
4229 return 0;
4230 err3:
4231 dsi_cio_uninit(dsidev);
4232 err2:
4233 dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4234 err1:
4235 dss_pll_disable(&dsi->pll);
4236 err0:
4237 return r;
4238 }
4239
4240 static void dsi_display_uninit_dsi(struct platform_device *dsidev,
4241 bool disconnect_lanes, bool enter_ulps)
4242 {
4243 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4244
4245 if (enter_ulps && !dsi->ulps_enabled)
4246 dsi_enter_ulps(dsidev);
4247
4248 /* disable interface */
4249 dsi_if_enable(dsidev, 0);
4250 dsi_vc_enable(dsidev, 0, 0);
4251 dsi_vc_enable(dsidev, 1, 0);
4252 dsi_vc_enable(dsidev, 2, 0);
4253 dsi_vc_enable(dsidev, 3, 0);
4254
4255 dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4256 dsi_cio_uninit(dsidev);
4257 dsi_pll_uninit(dsidev, disconnect_lanes);
4258 }
4259
4260 static int dsi_display_enable(struct omap_dss_device *dssdev)
4261 {
4262 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4263 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4264 int r = 0;
4265
4266 DSSDBG("dsi_display_enable\n");
4267
4268 WARN_ON(!dsi_bus_is_locked(dsidev));
4269
4270 mutex_lock(&dsi->lock);
4271
4272 r = dsi_runtime_get(dsidev);
4273 if (r)
4274 goto err_get_dsi;
4275
4276 _dsi_initialize_irq(dsidev);
4277
4278 r = dsi_display_init_dsi(dsidev);
4279 if (r)
4280 goto err_init_dsi;
4281
4282 mutex_unlock(&dsi->lock);
4283
4284 return 0;
4285
4286 err_init_dsi:
4287 dsi_runtime_put(dsidev);
4288 err_get_dsi:
4289 mutex_unlock(&dsi->lock);
4290 DSSDBG("dsi_display_enable FAILED\n");
4291 return r;
4292 }
4293
4294 static void dsi_display_disable(struct omap_dss_device *dssdev,
4295 bool disconnect_lanes, bool enter_ulps)
4296 {
4297 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4298 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4299
4300 DSSDBG("dsi_display_disable\n");
4301
4302 WARN_ON(!dsi_bus_is_locked(dsidev));
4303
4304 mutex_lock(&dsi->lock);
4305
4306 dsi_sync_vc(dsidev, 0);
4307 dsi_sync_vc(dsidev, 1);
4308 dsi_sync_vc(dsidev, 2);
4309 dsi_sync_vc(dsidev, 3);
4310
4311 dsi_display_uninit_dsi(dsidev, disconnect_lanes, enter_ulps);
4312
4313 dsi_runtime_put(dsidev);
4314
4315 mutex_unlock(&dsi->lock);
4316 }
4317
4318 static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4319 {
4320 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4321 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4322
4323 dsi->te_enabled = enable;
4324 return 0;
4325 }
4326
4327 #ifdef PRINT_VERBOSE_VM_TIMINGS
4328 static void print_dsi_vm(const char *str,
4329 const struct omap_dss_dsi_videomode_timings *t)
4330 {
4331 unsigned long byteclk = t->hsclk / 4;
4332 int bl, wc, pps, tot;
4333
4334 wc = DIV_ROUND_UP(t->hact * t->bitspp, 8);
4335 pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */
4336 bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp;
4337 tot = bl + pps;
4338
4339 #define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk))
4340
4341 pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, "
4342 "%u/%u/%u/%u/%u/%u = %u + %u = %u\n",
4343 str,
4344 byteclk,
4345 t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp,
4346 bl, pps, tot,
4347 TO_DSI_T(t->hss),
4348 TO_DSI_T(t->hsa),
4349 TO_DSI_T(t->hse),
4350 TO_DSI_T(t->hbp),
4351 TO_DSI_T(pps),
4352 TO_DSI_T(t->hfp),
4353
4354 TO_DSI_T(bl),
4355 TO_DSI_T(pps),
4356
4357 TO_DSI_T(tot));
4358 #undef TO_DSI_T
4359 }
4360
4361 static void print_dispc_vm(const char *str, const struct omap_video_timings *t)
4362 {
4363 unsigned long pck = t->pixelclock;
4364 int hact, bl, tot;
4365
4366 hact = t->x_res;
4367 bl = t->hsw + t->hbp + t->hfp;
4368 tot = hact + bl;
4369
4370 #define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck))
4371
4372 pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, "
4373 "%u/%u/%u/%u = %u + %u = %u\n",
4374 str,
4375 pck,
4376 t->hsw, t->hbp, hact, t->hfp,
4377 bl, hact, tot,
4378 TO_DISPC_T(t->hsw),
4379 TO_DISPC_T(t->hbp),
4380 TO_DISPC_T(hact),
4381 TO_DISPC_T(t->hfp),
4382 TO_DISPC_T(bl),
4383 TO_DISPC_T(hact),
4384 TO_DISPC_T(tot));
4385 #undef TO_DISPC_T
4386 }
4387
4388 /* note: this is not quite accurate */
4389 static void print_dsi_dispc_vm(const char *str,
4390 const struct omap_dss_dsi_videomode_timings *t)
4391 {
4392 struct omap_video_timings vm = { 0 };
4393 unsigned long byteclk = t->hsclk / 4;
4394 unsigned long pck;
4395 u64 dsi_tput;
4396 int dsi_hact, dsi_htot;
4397
4398 dsi_tput = (u64)byteclk * t->ndl * 8;
4399 pck = (u32)div64_u64(dsi_tput, t->bitspp);
4400 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl);
4401 dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp;
4402
4403 vm.pixelclock = pck;
4404 vm.hsw = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk);
4405 vm.hbp = div64_u64((u64)t->hbp * pck, byteclk);
4406 vm.hfp = div64_u64((u64)t->hfp * pck, byteclk);
4407 vm.x_res = t->hact;
4408
4409 print_dispc_vm(str, &vm);
4410 }
4411 #endif /* PRINT_VERBOSE_VM_TIMINGS */
4412
4413 static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4414 unsigned long pck, void *data)
4415 {
4416 struct dsi_clk_calc_ctx *ctx = data;
4417 struct omap_video_timings *t = &ctx->dispc_vm;
4418
4419 ctx->dispc_cinfo.lck_div = lckd;
4420 ctx->dispc_cinfo.pck_div = pckd;
4421 ctx->dispc_cinfo.lck = lck;
4422 ctx->dispc_cinfo.pck = pck;
4423
4424 *t = *ctx->config->timings;
4425 t->pixelclock = pck;
4426 t->x_res = ctx->config->timings->x_res;
4427 t->y_res = ctx->config->timings->y_res;
4428 t->hsw = t->hfp = t->hbp = t->vsw = 1;
4429 t->vfp = t->vbp = 0;
4430
4431 return true;
4432 }
4433
4434 static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
4435 void *data)
4436 {
4437 struct dsi_clk_calc_ctx *ctx = data;
4438
4439 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
4440 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
4441
4442 return dispc_div_calc(dispc, ctx->req_pck_min, ctx->req_pck_max,
4443 dsi_cm_calc_dispc_cb, ctx);
4444 }
4445
4446 static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint,
4447 unsigned long clkdco, void *data)
4448 {
4449 struct dsi_clk_calc_ctx *ctx = data;
4450
4451 ctx->dsi_cinfo.n = n;
4452 ctx->dsi_cinfo.m = m;
4453 ctx->dsi_cinfo.fint = fint;
4454 ctx->dsi_cinfo.clkdco = clkdco;
4455
4456 return dss_pll_hsdiv_calc(ctx->pll, clkdco, ctx->req_pck_min,
4457 dss_feat_get_param_max(FEAT_PARAM_DSS_FCK),
4458 dsi_cm_calc_hsdiv_cb, ctx);
4459 }
4460
4461 static bool dsi_cm_calc(struct dsi_data *dsi,
4462 const struct omap_dss_dsi_config *cfg,
4463 struct dsi_clk_calc_ctx *ctx)
4464 {
4465 unsigned long clkin;
4466 int bitspp, ndl;
4467 unsigned long pll_min, pll_max;
4468 unsigned long pck, txbyteclk;
4469
4470 clkin = clk_get_rate(dsi->pll.clkin);
4471 bitspp = dsi_get_pixel_size(cfg->pixel_format);
4472 ndl = dsi->num_lanes_used - 1;
4473
4474 /*
4475 * Here we should calculate minimum txbyteclk to be able to send the
4476 * frame in time, and also to handle TE. That's not very simple, though,
4477 * especially as we go to LP between each pixel packet due to HW
4478 * "feature". So let's just estimate very roughly and multiply by 1.5.
4479 */
4480 pck = cfg->timings->pixelclock;
4481 pck = pck * 3 / 2;
4482 txbyteclk = pck * bitspp / 8 / ndl;
4483
4484 memset(ctx, 0, sizeof(*ctx));
4485 ctx->dsidev = dsi->pdev;
4486 ctx->pll = &dsi->pll;
4487 ctx->config = cfg;
4488 ctx->req_pck_min = pck;
4489 ctx->req_pck_nom = pck;
4490 ctx->req_pck_max = pck * 3 / 2;
4491
4492 pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4);
4493 pll_max = cfg->hs_clk_max * 4;
4494
4495 return dss_pll_calc(ctx->pll, clkin,
4496 pll_min, pll_max,
4497 dsi_cm_calc_pll_cb, ctx);
4498 }
4499
4500 static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
4501 {
4502 struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev);
4503 const struct omap_dss_dsi_config *cfg = ctx->config;
4504 int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4505 int ndl = dsi->num_lanes_used - 1;
4506 unsigned long hsclk = ctx->dsi_cinfo.clkdco / 4;
4507 unsigned long byteclk = hsclk / 4;
4508
4509 unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max;
4510 int xres;
4511 int panel_htot, panel_hbl; /* pixels */
4512 int dispc_htot, dispc_hbl; /* pixels */
4513 int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */
4514 int hfp, hsa, hbp;
4515 const struct omap_video_timings *req_vm;
4516 struct omap_video_timings *dispc_vm;
4517 struct omap_dss_dsi_videomode_timings *dsi_vm;
4518 u64 dsi_tput, dispc_tput;
4519
4520 dsi_tput = (u64)byteclk * ndl * 8;
4521
4522 req_vm = cfg->timings;
4523 req_pck_min = ctx->req_pck_min;
4524 req_pck_max = ctx->req_pck_max;
4525 req_pck_nom = ctx->req_pck_nom;
4526
4527 dispc_pck = ctx->dispc_cinfo.pck;
4528 dispc_tput = (u64)dispc_pck * bitspp;
4529
4530 xres = req_vm->x_res;
4531
4532 panel_hbl = req_vm->hfp + req_vm->hbp + req_vm->hsw;
4533 panel_htot = xres + panel_hbl;
4534
4535 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl);
4536
4537 /*
4538 * When there are no line buffers, DISPC and DSI must have the
4539 * same tput. Otherwise DISPC tput needs to be higher than DSI's.
4540 */
4541 if (dsi->line_buffer_size < xres * bitspp / 8) {
4542 if (dispc_tput != dsi_tput)
4543 return false;
4544 } else {
4545 if (dispc_tput < dsi_tput)
4546 return false;
4547 }
4548
4549 /* DSI tput must be over the min requirement */
4550 if (dsi_tput < (u64)bitspp * req_pck_min)
4551 return false;
4552
4553 /* When non-burst mode, DSI tput must be below max requirement. */
4554 if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) {
4555 if (dsi_tput > (u64)bitspp * req_pck_max)
4556 return false;
4557 }
4558
4559 hss = DIV_ROUND_UP(4, ndl);
4560
4561 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4562 if (ndl == 3 && req_vm->hsw == 0)
4563 hse = 1;
4564 else
4565 hse = DIV_ROUND_UP(4, ndl);
4566 } else {
4567 hse = 0;
4568 }
4569
4570 /* DSI htot to match the panel's nominal pck */
4571 dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom);
4572
4573 /* fail if there would be no time for blanking */
4574 if (dsi_htot < hss + hse + dsi_hact)
4575 return false;
4576
4577 /* total DSI blanking needed to achieve panel's TL */
4578 dsi_hbl = dsi_htot - dsi_hact;
4579
4580 /* DISPC htot to match the DSI TL */
4581 dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk);
4582
4583 /* verify that the DSI and DISPC TLs are the same */
4584 if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk)
4585 return false;
4586
4587 dispc_hbl = dispc_htot - xres;
4588
4589 /* setup DSI videomode */
4590
4591 dsi_vm = &ctx->dsi_vm;
4592 memset(dsi_vm, 0, sizeof(*dsi_vm));
4593
4594 dsi_vm->hsclk = hsclk;
4595
4596 dsi_vm->ndl = ndl;
4597 dsi_vm->bitspp = bitspp;
4598
4599 if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) {
4600 hsa = 0;
4601 } else if (ndl == 3 && req_vm->hsw == 0) {
4602 hsa = 0;
4603 } else {
4604 hsa = div64_u64((u64)req_vm->hsw * byteclk, req_pck_nom);
4605 hsa = max(hsa - hse, 1);
4606 }
4607
4608 hbp = div64_u64((u64)req_vm->hbp * byteclk, req_pck_nom);
4609 hbp = max(hbp, 1);
4610
4611 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4612 if (hfp < 1) {
4613 int t;
4614 /* we need to take cycles from hbp */
4615
4616 t = 1 - hfp;
4617 hbp = max(hbp - t, 1);
4618 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4619
4620 if (hfp < 1 && hsa > 0) {
4621 /* we need to take cycles from hsa */
4622 t = 1 - hfp;
4623 hsa = max(hsa - t, 1);
4624 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4625 }
4626 }
4627
4628 if (hfp < 1)
4629 return false;
4630
4631 dsi_vm->hss = hss;
4632 dsi_vm->hsa = hsa;
4633 dsi_vm->hse = hse;
4634 dsi_vm->hbp = hbp;
4635 dsi_vm->hact = xres;
4636 dsi_vm->hfp = hfp;
4637
4638 dsi_vm->vsa = req_vm->vsw;
4639 dsi_vm->vbp = req_vm->vbp;
4640 dsi_vm->vact = req_vm->y_res;
4641 dsi_vm->vfp = req_vm->vfp;
4642
4643 dsi_vm->trans_mode = cfg->trans_mode;
4644
4645 dsi_vm->blanking_mode = 0;
4646 dsi_vm->hsa_blanking_mode = 1;
4647 dsi_vm->hfp_blanking_mode = 1;
4648 dsi_vm->hbp_blanking_mode = 1;
4649
4650 dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on;
4651 dsi_vm->window_sync = 4;
4652
4653 /* setup DISPC videomode */
4654
4655 dispc_vm = &ctx->dispc_vm;
4656 *dispc_vm = *req_vm;
4657 dispc_vm->pixelclock = dispc_pck;
4658
4659 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4660 hsa = div64_u64((u64)req_vm->hsw * dispc_pck,
4661 req_pck_nom);
4662 hsa = max(hsa, 1);
4663 } else {
4664 hsa = 1;
4665 }
4666
4667 hbp = div64_u64((u64)req_vm->hbp * dispc_pck, req_pck_nom);
4668 hbp = max(hbp, 1);
4669
4670 hfp = dispc_hbl - hsa - hbp;
4671 if (hfp < 1) {
4672 int t;
4673 /* we need to take cycles from hbp */
4674
4675 t = 1 - hfp;
4676 hbp = max(hbp - t, 1);
4677 hfp = dispc_hbl - hsa - hbp;
4678
4679 if (hfp < 1) {
4680 /* we need to take cycles from hsa */
4681 t = 1 - hfp;
4682 hsa = max(hsa - t, 1);
4683 hfp = dispc_hbl - hsa - hbp;
4684 }
4685 }
4686
4687 if (hfp < 1)
4688 return false;
4689
4690 dispc_vm->hfp = hfp;
4691 dispc_vm->hsw = hsa;
4692 dispc_vm->hbp = hbp;
4693
4694 return true;
4695 }
4696
4697
4698 static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4699 unsigned long pck, void *data)
4700 {
4701 struct dsi_clk_calc_ctx *ctx = data;
4702
4703 ctx->dispc_cinfo.lck_div = lckd;
4704 ctx->dispc_cinfo.pck_div = pckd;
4705 ctx->dispc_cinfo.lck = lck;
4706 ctx->dispc_cinfo.pck = pck;
4707
4708 if (dsi_vm_calc_blanking(ctx) == false)
4709 return false;
4710
4711 #ifdef PRINT_VERBOSE_VM_TIMINGS
4712 print_dispc_vm("dispc", &ctx->dispc_vm);
4713 print_dsi_vm("dsi ", &ctx->dsi_vm);
4714 print_dispc_vm("req ", ctx->config->timings);
4715 print_dsi_dispc_vm("act ", &ctx->dsi_vm);
4716 #endif
4717
4718 return true;
4719 }
4720
4721 static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
4722 void *data)
4723 {
4724 struct dsi_clk_calc_ctx *ctx = data;
4725 unsigned long pck_max;
4726
4727 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
4728 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
4729
4730 /*
4731 * In burst mode we can let the dispc pck be arbitrarily high, but it
4732 * limits our scaling abilities. So for now, don't aim too high.
4733 */
4734
4735 if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE)
4736 pck_max = ctx->req_pck_max + 10000000;
4737 else
4738 pck_max = ctx->req_pck_max;
4739
4740 return dispc_div_calc(dispc, ctx->req_pck_min, pck_max,
4741 dsi_vm_calc_dispc_cb, ctx);
4742 }
4743
4744 static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint,
4745 unsigned long clkdco, void *data)
4746 {
4747 struct dsi_clk_calc_ctx *ctx = data;
4748
4749 ctx->dsi_cinfo.n = n;
4750 ctx->dsi_cinfo.m = m;
4751 ctx->dsi_cinfo.fint = fint;
4752 ctx->dsi_cinfo.clkdco = clkdco;
4753
4754 return dss_pll_hsdiv_calc(ctx->pll, clkdco, ctx->req_pck_min,
4755 dss_feat_get_param_max(FEAT_PARAM_DSS_FCK),
4756 dsi_vm_calc_hsdiv_cb, ctx);
4757 }
4758
4759 static bool dsi_vm_calc(struct dsi_data *dsi,
4760 const struct omap_dss_dsi_config *cfg,
4761 struct dsi_clk_calc_ctx *ctx)
4762 {
4763 const struct omap_video_timings *t = cfg->timings;
4764 unsigned long clkin;
4765 unsigned long pll_min;
4766 unsigned long pll_max;
4767 int ndl = dsi->num_lanes_used - 1;
4768 int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4769 unsigned long byteclk_min;
4770
4771 clkin = clk_get_rate(dsi->pll.clkin);
4772
4773 memset(ctx, 0, sizeof(*ctx));
4774 ctx->dsidev = dsi->pdev;
4775 ctx->pll = &dsi->pll;
4776 ctx->config = cfg;
4777
4778 /* these limits should come from the panel driver */
4779 ctx->req_pck_min = t->pixelclock - 1000;
4780 ctx->req_pck_nom = t->pixelclock;
4781 ctx->req_pck_max = t->pixelclock + 1000;
4782
4783 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8);
4784 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4);
4785
4786 if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) {
4787 pll_max = cfg->hs_clk_max * 4;
4788 } else {
4789 unsigned long byteclk_max;
4790 byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp,
4791 ndl * 8);
4792
4793 pll_max = byteclk_max * 4 * 4;
4794 }
4795
4796 return dss_pll_calc(ctx->pll, clkin,
4797 pll_min, pll_max,
4798 dsi_vm_calc_pll_cb, ctx);
4799 }
4800
4801 static int dsi_set_config(struct omap_dss_device *dssdev,
4802 const struct omap_dss_dsi_config *config)
4803 {
4804 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4805 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4806 struct dsi_clk_calc_ctx ctx;
4807 bool ok;
4808 int r;
4809
4810 mutex_lock(&dsi->lock);
4811
4812 dsi->pix_fmt = config->pixel_format;
4813 dsi->mode = config->mode;
4814
4815 if (config->mode == OMAP_DSS_DSI_VIDEO_MODE)
4816 ok = dsi_vm_calc(dsi, config, &ctx);
4817 else
4818 ok = dsi_cm_calc(dsi, config, &ctx);
4819
4820 if (!ok) {
4821 DSSERR("failed to find suitable DSI clock settings\n");
4822 r = -EINVAL;
4823 goto err;
4824 }
4825
4826 dsi_pll_calc_dsi_fck(&ctx.dsi_cinfo);
4827
4828 r = dsi_lp_clock_calc(ctx.dsi_cinfo.clkout[HSDIV_DSI],
4829 config->lp_clk_min, config->lp_clk_max, &dsi->user_lp_cinfo);
4830 if (r) {
4831 DSSERR("failed to find suitable DSI LP clock settings\n");
4832 goto err;
4833 }
4834
4835 dsi->user_dsi_cinfo = ctx.dsi_cinfo;
4836 dsi->user_dispc_cinfo = ctx.dispc_cinfo;
4837
4838 dsi->timings = ctx.dispc_vm;
4839 dsi->vm_timings = ctx.dsi_vm;
4840
4841 mutex_unlock(&dsi->lock);
4842
4843 return 0;
4844 err:
4845 mutex_unlock(&dsi->lock);
4846
4847 return r;
4848 }
4849
4850 /*
4851 * Return a hardcoded channel for the DSI output. This should work for
4852 * current use cases, but this can be later expanded to either resolve
4853 * the channel in some more dynamic manner, or get the channel as a user
4854 * parameter.
4855 */
4856 static enum omap_channel dsi_get_channel(int module_id)
4857 {
4858 switch (omapdss_get_version()) {
4859 case OMAPDSS_VER_OMAP24xx:
4860 case OMAPDSS_VER_AM43xx:
4861 DSSWARN("DSI not supported\n");
4862 return OMAP_DSS_CHANNEL_LCD;
4863
4864 case OMAPDSS_VER_OMAP34xx_ES1:
4865 case OMAPDSS_VER_OMAP34xx_ES3:
4866 case OMAPDSS_VER_OMAP3630:
4867 case OMAPDSS_VER_AM35xx:
4868 return OMAP_DSS_CHANNEL_LCD;
4869
4870 case OMAPDSS_VER_OMAP4430_ES1:
4871 case OMAPDSS_VER_OMAP4430_ES2:
4872 case OMAPDSS_VER_OMAP4:
4873 switch (module_id) {
4874 case 0:
4875 return OMAP_DSS_CHANNEL_LCD;
4876 case 1:
4877 return OMAP_DSS_CHANNEL_LCD2;
4878 default:
4879 DSSWARN("unsupported module id\n");
4880 return OMAP_DSS_CHANNEL_LCD;
4881 }
4882
4883 case OMAPDSS_VER_OMAP5:
4884 switch (module_id) {
4885 case 0:
4886 return OMAP_DSS_CHANNEL_LCD;
4887 case 1:
4888 return OMAP_DSS_CHANNEL_LCD3;
4889 default:
4890 DSSWARN("unsupported module id\n");
4891 return OMAP_DSS_CHANNEL_LCD;
4892 }
4893
4894 default:
4895 DSSWARN("unsupported DSS version\n");
4896 return OMAP_DSS_CHANNEL_LCD;
4897 }
4898 }
4899
4900 static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
4901 {
4902 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4903 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4904 int i;
4905
4906 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4907 if (!dsi->vc[i].dssdev) {
4908 dsi->vc[i].dssdev = dssdev;
4909 *channel = i;
4910 return 0;
4911 }
4912 }
4913
4914 DSSERR("cannot get VC for display %s", dssdev->name);
4915 return -ENOSPC;
4916 }
4917
4918 static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
4919 {
4920 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4921 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4922
4923 if (vc_id < 0 || vc_id > 3) {
4924 DSSERR("VC ID out of range\n");
4925 return -EINVAL;
4926 }
4927
4928 if (channel < 0 || channel > 3) {
4929 DSSERR("Virtual Channel out of range\n");
4930 return -EINVAL;
4931 }
4932
4933 if (dsi->vc[channel].dssdev != dssdev) {
4934 DSSERR("Virtual Channel not allocated to display %s\n",
4935 dssdev->name);
4936 return -EINVAL;
4937 }
4938
4939 dsi->vc[channel].vc_id = vc_id;
4940
4941 return 0;
4942 }
4943
4944 static void dsi_release_vc(struct omap_dss_device *dssdev, int channel)
4945 {
4946 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4947 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4948
4949 if ((channel >= 0 && channel <= 3) &&
4950 dsi->vc[channel].dssdev == dssdev) {
4951 dsi->vc[channel].dssdev = NULL;
4952 dsi->vc[channel].vc_id = 0;
4953 }
4954 }
4955
4956
4957 static int dsi_get_clocks(struct platform_device *dsidev)
4958 {
4959 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4960 struct clk *clk;
4961
4962 clk = devm_clk_get(&dsidev->dev, "fck");
4963 if (IS_ERR(clk)) {
4964 DSSERR("can't get fck\n");
4965 return PTR_ERR(clk);
4966 }
4967
4968 dsi->dss_clk = clk;
4969
4970 return 0;
4971 }
4972
4973 static int dsi_connect(struct omap_dss_device *dssdev,
4974 struct omap_dss_device *dst)
4975 {
4976 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4977 enum omap_channel dispc_channel = dssdev->dispc_channel;
4978 int r;
4979
4980 r = dsi_regulator_init(dsidev);
4981 if (r)
4982 return r;
4983
4984 r = dss_mgr_connect(dispc_channel, dssdev);
4985 if (r)
4986 return r;
4987
4988 r = omapdss_output_set_device(dssdev, dst);
4989 if (r) {
4990 DSSERR("failed to connect output to new device: %s\n",
4991 dssdev->name);
4992 dss_mgr_disconnect(dispc_channel, dssdev);
4993 return r;
4994 }
4995
4996 return 0;
4997 }
4998
4999 static void dsi_disconnect(struct omap_dss_device *dssdev,
5000 struct omap_dss_device *dst)
5001 {
5002 enum omap_channel dispc_channel = dssdev->dispc_channel;
5003
5004 WARN_ON(dst != dssdev->dst);
5005
5006 if (dst != dssdev->dst)
5007 return;
5008
5009 omapdss_output_unset_device(dssdev);
5010
5011 dss_mgr_disconnect(dispc_channel, dssdev);
5012 }
5013
5014 static const struct omapdss_dsi_ops dsi_ops = {
5015 .connect = dsi_connect,
5016 .disconnect = dsi_disconnect,
5017
5018 .bus_lock = dsi_bus_lock,
5019 .bus_unlock = dsi_bus_unlock,
5020
5021 .enable = dsi_display_enable,
5022 .disable = dsi_display_disable,
5023
5024 .enable_hs = dsi_vc_enable_hs,
5025
5026 .configure_pins = dsi_configure_pins,
5027 .set_config = dsi_set_config,
5028
5029 .enable_video_output = dsi_enable_video_output,
5030 .disable_video_output = dsi_disable_video_output,
5031
5032 .update = dsi_update,
5033
5034 .enable_te = dsi_enable_te,
5035
5036 .request_vc = dsi_request_vc,
5037 .set_vc_id = dsi_set_vc_id,
5038 .release_vc = dsi_release_vc,
5039
5040 .dcs_write = dsi_vc_dcs_write,
5041 .dcs_write_nosync = dsi_vc_dcs_write_nosync,
5042 .dcs_read = dsi_vc_dcs_read,
5043
5044 .gen_write = dsi_vc_generic_write,
5045 .gen_write_nosync = dsi_vc_generic_write_nosync,
5046 .gen_read = dsi_vc_generic_read,
5047
5048 .bta_sync = dsi_vc_send_bta_sync,
5049
5050 .set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size,
5051 };
5052
5053 static void dsi_init_output(struct platform_device *dsidev)
5054 {
5055 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5056 struct omap_dss_device *out = &dsi->output;
5057
5058 out->dev = &dsidev->dev;
5059 out->id = dsi->module_id == 0 ?
5060 OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2;
5061
5062 out->output_type = OMAP_DISPLAY_TYPE_DSI;
5063 out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1";
5064 out->dispc_channel = dsi_get_channel(dsi->module_id);
5065 out->ops.dsi = &dsi_ops;
5066 out->owner = THIS_MODULE;
5067
5068 omapdss_register_output(out);
5069 }
5070
5071 static void dsi_uninit_output(struct platform_device *dsidev)
5072 {
5073 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5074 struct omap_dss_device *out = &dsi->output;
5075
5076 omapdss_unregister_output(out);
5077 }
5078
5079 static int dsi_probe_of(struct platform_device *pdev)
5080 {
5081 struct device_node *node = pdev->dev.of_node;
5082 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5083 struct property *prop;
5084 u32 lane_arr[10];
5085 int len, num_pins;
5086 int r, i;
5087 struct device_node *ep;
5088 struct omap_dsi_pin_config pin_cfg;
5089
5090 ep = omapdss_of_get_first_endpoint(node);
5091 if (!ep)
5092 return 0;
5093
5094 prop = of_find_property(ep, "lanes", &len);
5095 if (prop == NULL) {
5096 dev_err(&pdev->dev, "failed to find lane data\n");
5097 r = -EINVAL;
5098 goto err;
5099 }
5100
5101 num_pins = len / sizeof(u32);
5102
5103 if (num_pins < 4 || num_pins % 2 != 0 ||
5104 num_pins > dsi->num_lanes_supported * 2) {
5105 dev_err(&pdev->dev, "bad number of lanes\n");
5106 r = -EINVAL;
5107 goto err;
5108 }
5109
5110 r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins);
5111 if (r) {
5112 dev_err(&pdev->dev, "failed to read lane data\n");
5113 goto err;
5114 }
5115
5116 pin_cfg.num_pins = num_pins;
5117 for (i = 0; i < num_pins; ++i)
5118 pin_cfg.pins[i] = (int)lane_arr[i];
5119
5120 r = dsi_configure_pins(&dsi->output, &pin_cfg);
5121 if (r) {
5122 dev_err(&pdev->dev, "failed to configure pins");
5123 goto err;
5124 }
5125
5126 of_node_put(ep);
5127
5128 return 0;
5129
5130 err:
5131 of_node_put(ep);
5132 return r;
5133 }
5134
5135 static const struct dss_pll_ops dsi_pll_ops = {
5136 .enable = dsi_pll_enable,
5137 .disable = dsi_pll_disable,
5138 .set_config = dss_pll_write_config_type_a,
5139 };
5140
5141 static const struct dss_pll_hw dss_omap3_dsi_pll_hw = {
5142 .n_max = (1 << 7) - 1,
5143 .m_max = (1 << 11) - 1,
5144 .mX_max = (1 << 4) - 1,
5145 .fint_min = 750000,
5146 .fint_max = 2100000,
5147 .clkdco_low = 1000000000,
5148 .clkdco_max = 1800000000,
5149
5150 .n_msb = 7,
5151 .n_lsb = 1,
5152 .m_msb = 18,
5153 .m_lsb = 8,
5154
5155 .mX_msb[0] = 22,
5156 .mX_lsb[0] = 19,
5157 .mX_msb[1] = 26,
5158 .mX_lsb[1] = 23,
5159
5160 .has_stopmode = true,
5161 .has_freqsel = true,
5162 .has_selfreqdco = false,
5163 .has_refsel = false,
5164 };
5165
5166 static const struct dss_pll_hw dss_omap4_dsi_pll_hw = {
5167 .n_max = (1 << 8) - 1,
5168 .m_max = (1 << 12) - 1,
5169 .mX_max = (1 << 5) - 1,
5170 .fint_min = 500000,
5171 .fint_max = 2500000,
5172 .clkdco_low = 1000000000,
5173 .clkdco_max = 1800000000,
5174
5175 .n_msb = 8,
5176 .n_lsb = 1,
5177 .m_msb = 20,
5178 .m_lsb = 9,
5179
5180 .mX_msb[0] = 25,
5181 .mX_lsb[0] = 21,
5182 .mX_msb[1] = 30,
5183 .mX_lsb[1] = 26,
5184
5185 .has_stopmode = true,
5186 .has_freqsel = false,
5187 .has_selfreqdco = false,
5188 .has_refsel = false,
5189 };
5190
5191 static const struct dss_pll_hw dss_omap5_dsi_pll_hw = {
5192 .n_max = (1 << 8) - 1,
5193 .m_max = (1 << 12) - 1,
5194 .mX_max = (1 << 5) - 1,
5195 .fint_min = 150000,
5196 .fint_max = 52000000,
5197 .clkdco_low = 1000000000,
5198 .clkdco_max = 1800000000,
5199
5200 .n_msb = 8,
5201 .n_lsb = 1,
5202 .m_msb = 20,
5203 .m_lsb = 9,
5204
5205 .mX_msb[0] = 25,
5206 .mX_lsb[0] = 21,
5207 .mX_msb[1] = 30,
5208 .mX_lsb[1] = 26,
5209
5210 .has_stopmode = true,
5211 .has_freqsel = false,
5212 .has_selfreqdco = true,
5213 .has_refsel = true,
5214 };
5215
5216 static int dsi_init_pll_data(struct platform_device *dsidev)
5217 {
5218 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5219 struct dss_pll *pll = &dsi->pll;
5220 struct clk *clk;
5221 int r;
5222
5223 clk = devm_clk_get(&dsidev->dev, "sys_clk");
5224 if (IS_ERR(clk)) {
5225 DSSERR("can't get sys_clk\n");
5226 return PTR_ERR(clk);
5227 }
5228
5229 pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1";
5230 pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2;
5231 pll->clkin = clk;
5232 pll->base = dsi->pll_base;
5233
5234 switch (omapdss_get_version()) {
5235 case OMAPDSS_VER_OMAP34xx_ES1:
5236 case OMAPDSS_VER_OMAP34xx_ES3:
5237 case OMAPDSS_VER_OMAP3630:
5238 case OMAPDSS_VER_AM35xx:
5239 pll->hw = &dss_omap3_dsi_pll_hw;
5240 break;
5241
5242 case OMAPDSS_VER_OMAP4430_ES1:
5243 case OMAPDSS_VER_OMAP4430_ES2:
5244 case OMAPDSS_VER_OMAP4:
5245 pll->hw = &dss_omap4_dsi_pll_hw;
5246 break;
5247
5248 case OMAPDSS_VER_OMAP5:
5249 pll->hw = &dss_omap5_dsi_pll_hw;
5250 break;
5251
5252 default:
5253 return -ENODEV;
5254 }
5255
5256 pll->ops = &dsi_pll_ops;
5257
5258 r = dss_pll_register(pll);
5259 if (r)
5260 return r;
5261
5262 return 0;
5263 }
5264
5265 /* DSI1 HW IP initialisation */
5266 static int dsi_bind(struct device *dev, struct device *master, void *data)
5267 {
5268 struct platform_device *dsidev = to_platform_device(dev);
5269 u32 rev;
5270 int r, i;
5271 struct dsi_data *dsi;
5272 struct resource *dsi_mem;
5273 struct resource *res;
5274 struct resource temp_res;
5275
5276 dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL);
5277 if (!dsi)
5278 return -ENOMEM;
5279
5280 dsi->pdev = dsidev;
5281 dev_set_drvdata(&dsidev->dev, dsi);
5282
5283 spin_lock_init(&dsi->irq_lock);
5284 spin_lock_init(&dsi->errors_lock);
5285 dsi->errors = 0;
5286
5287 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5288 spin_lock_init(&dsi->irq_stats_lock);
5289 dsi->irq_stats.last_reset = jiffies;
5290 #endif
5291
5292 mutex_init(&dsi->lock);
5293 sema_init(&dsi->bus_lock, 1);
5294
5295 INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work,
5296 dsi_framedone_timeout_work_callback);
5297
5298 #ifdef DSI_CATCH_MISSING_TE
5299 init_timer(&dsi->te_timer);
5300 dsi->te_timer.function = dsi_te_timeout;
5301 dsi->te_timer.data = 0;
5302 #endif
5303
5304 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "proto");
5305 if (!res) {
5306 res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
5307 if (!res) {
5308 DSSERR("can't get IORESOURCE_MEM DSI\n");
5309 return -EINVAL;
5310 }
5311
5312 temp_res.start = res->start;
5313 temp_res.end = temp_res.start + DSI_PROTO_SZ - 1;
5314 res = &temp_res;
5315 }
5316
5317 dsi_mem = res;
5318
5319 dsi->proto_base = devm_ioremap(&dsidev->dev, res->start,
5320 resource_size(res));
5321 if (!dsi->proto_base) {
5322 DSSERR("can't ioremap DSI protocol engine\n");
5323 return -ENOMEM;
5324 }
5325
5326 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "phy");
5327 if (!res) {
5328 res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
5329 if (!res) {
5330 DSSERR("can't get IORESOURCE_MEM DSI\n");
5331 return -EINVAL;
5332 }
5333
5334 temp_res.start = res->start + DSI_PHY_OFFSET;
5335 temp_res.end = temp_res.start + DSI_PHY_SZ - 1;
5336 res = &temp_res;
5337 }
5338
5339 dsi->phy_base = devm_ioremap(&dsidev->dev, res->start,
5340 resource_size(res));
5341 if (!dsi->proto_base) {
5342 DSSERR("can't ioremap DSI PHY\n");
5343 return -ENOMEM;
5344 }
5345
5346 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "pll");
5347 if (!res) {
5348 res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
5349 if (!res) {
5350 DSSERR("can't get IORESOURCE_MEM DSI\n");
5351 return -EINVAL;
5352 }
5353
5354 temp_res.start = res->start + DSI_PLL_OFFSET;
5355 temp_res.end = temp_res.start + DSI_PLL_SZ - 1;
5356 res = &temp_res;
5357 }
5358
5359 dsi->pll_base = devm_ioremap(&dsidev->dev, res->start,
5360 resource_size(res));
5361 if (!dsi->proto_base) {
5362 DSSERR("can't ioremap DSI PLL\n");
5363 return -ENOMEM;
5364 }
5365
5366 dsi->irq = platform_get_irq(dsi->pdev, 0);
5367 if (dsi->irq < 0) {
5368 DSSERR("platform_get_irq failed\n");
5369 return -ENODEV;
5370 }
5371
5372 r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler,
5373 IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev);
5374 if (r < 0) {
5375 DSSERR("request_irq failed\n");
5376 return r;
5377 }
5378
5379 if (dsidev->dev.of_node) {
5380 const struct of_device_id *match;
5381 const struct dsi_module_id_data *d;
5382
5383 match = of_match_node(dsi_of_match, dsidev->dev.of_node);
5384 if (!match) {
5385 DSSERR("unsupported DSI module\n");
5386 return -ENODEV;
5387 }
5388
5389 d = match->data;
5390
5391 while (d->address != 0 && d->address != dsi_mem->start)
5392 d++;
5393
5394 if (d->address == 0) {
5395 DSSERR("unsupported DSI module\n");
5396 return -ENODEV;
5397 }
5398
5399 dsi->module_id = d->id;
5400 } else {
5401 dsi->module_id = dsidev->id;
5402 }
5403
5404 /* DSI VCs initialization */
5405 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
5406 dsi->vc[i].source = DSI_VC_SOURCE_L4;
5407 dsi->vc[i].dssdev = NULL;
5408 dsi->vc[i].vc_id = 0;
5409 }
5410
5411 r = dsi_get_clocks(dsidev);
5412 if (r)
5413 return r;
5414
5415 dsi_init_pll_data(dsidev);
5416
5417 pm_runtime_enable(&dsidev->dev);
5418
5419 r = dsi_runtime_get(dsidev);
5420 if (r)
5421 goto err_runtime_get;
5422
5423 rev = dsi_read_reg(dsidev, DSI_REVISION);
5424 dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
5425 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
5426
5427 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
5428 * of data to 3 by default */
5429 if (dss_has_feature(FEAT_DSI_GNQ))
5430 /* NB_DATA_LANES */
5431 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9);
5432 else
5433 dsi->num_lanes_supported = 3;
5434
5435 dsi->line_buffer_size = dsi_get_line_buf_size(dsidev);
5436
5437 dsi_init_output(dsidev);
5438
5439 if (dsidev->dev.of_node) {
5440 r = dsi_probe_of(dsidev);
5441 if (r) {
5442 DSSERR("Invalid DSI DT data\n");
5443 goto err_probe_of;
5444 }
5445
5446 r = of_platform_populate(dsidev->dev.of_node, NULL, NULL,
5447 &dsidev->dev);
5448 if (r)
5449 DSSERR("Failed to populate DSI child devices: %d\n", r);
5450 }
5451
5452 dsi_runtime_put(dsidev);
5453
5454 if (dsi->module_id == 0)
5455 dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs);
5456 else if (dsi->module_id == 1)
5457 dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs);
5458
5459 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5460 if (dsi->module_id == 0)
5461 dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs);
5462 else if (dsi->module_id == 1)
5463 dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs);
5464 #endif
5465
5466 return 0;
5467
5468 err_probe_of:
5469 dsi_uninit_output(dsidev);
5470 dsi_runtime_put(dsidev);
5471
5472 err_runtime_get:
5473 pm_runtime_disable(&dsidev->dev);
5474 return r;
5475 }
5476
5477 static void dsi_unbind(struct device *dev, struct device *master, void *data)
5478 {
5479 struct platform_device *dsidev = to_platform_device(dev);
5480 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5481
5482 of_platform_depopulate(&dsidev->dev);
5483
5484 WARN_ON(dsi->scp_clk_refcount > 0);
5485
5486 dss_pll_unregister(&dsi->pll);
5487
5488 dsi_uninit_output(dsidev);
5489
5490 pm_runtime_disable(&dsidev->dev);
5491
5492 if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) {
5493 regulator_disable(dsi->vdds_dsi_reg);
5494 dsi->vdds_dsi_enabled = false;
5495 }
5496 }
5497
5498 static const struct component_ops dsi_component_ops = {
5499 .bind = dsi_bind,
5500 .unbind = dsi_unbind,
5501 };
5502
5503 static int dsi_probe(struct platform_device *pdev)
5504 {
5505 return component_add(&pdev->dev, &dsi_component_ops);
5506 }
5507
5508 static int dsi_remove(struct platform_device *pdev)
5509 {
5510 component_del(&pdev->dev, &dsi_component_ops);
5511 return 0;
5512 }
5513
5514 static int dsi_runtime_suspend(struct device *dev)
5515 {
5516 struct platform_device *pdev = to_platform_device(dev);
5517 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5518
5519 dsi->is_enabled = false;
5520 /* ensure the irq handler sees the is_enabled value */
5521 smp_wmb();
5522 /* wait for current handler to finish before turning the DSI off */
5523 synchronize_irq(dsi->irq);
5524
5525 dispc_runtime_put();
5526
5527 return 0;
5528 }
5529
5530 static int dsi_runtime_resume(struct device *dev)
5531 {
5532 struct platform_device *pdev = to_platform_device(dev);
5533 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5534 int r;
5535
5536 r = dispc_runtime_get();
5537 if (r)
5538 return r;
5539
5540 dsi->is_enabled = true;
5541 /* ensure the irq handler sees the is_enabled value */
5542 smp_wmb();
5543
5544 return 0;
5545 }
5546
5547 static const struct dev_pm_ops dsi_pm_ops = {
5548 .runtime_suspend = dsi_runtime_suspend,
5549 .runtime_resume = dsi_runtime_resume,
5550 };
5551
5552 static const struct dsi_module_id_data dsi_of_data_omap3[] = {
5553 { .address = 0x4804fc00, .id = 0, },
5554 { },
5555 };
5556
5557 static const struct dsi_module_id_data dsi_of_data_omap4[] = {
5558 { .address = 0x58004000, .id = 0, },
5559 { .address = 0x58005000, .id = 1, },
5560 { },
5561 };
5562
5563 static const struct dsi_module_id_data dsi_of_data_omap5[] = {
5564 { .address = 0x58004000, .id = 0, },
5565 { .address = 0x58009000, .id = 1, },
5566 { },
5567 };
5568
5569 static const struct of_device_id dsi_of_match[] = {
5570 { .compatible = "ti,omap3-dsi", .data = dsi_of_data_omap3, },
5571 { .compatible = "ti,omap4-dsi", .data = dsi_of_data_omap4, },
5572 { .compatible = "ti,omap5-dsi", .data = dsi_of_data_omap5, },
5573 {},
5574 };
5575
5576 static struct platform_driver omap_dsihw_driver = {
5577 .probe = dsi_probe,
5578 .remove = dsi_remove,
5579 .driver = {
5580 .name = "omapdss_dsi",
5581 .pm = &dsi_pm_ops,
5582 .of_match_table = dsi_of_match,
5583 .suppress_bind_attrs = true,
5584 },
5585 };
5586
5587 int __init dsi_init_platform_driver(void)
5588 {
5589 return platform_driver_register(&omap_dsihw_driver);
5590 }
5591
5592 void dsi_uninit_platform_driver(void)
5593 {
5594 platform_driver_unregister(&omap_dsihw_driver);
5595 }
Linux kernel - Deliverables
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