drm/omap: Remove regulator API abuse
[deliverable/linux.git] / drivers / gpu / drm / omapdrm / dss / hdmi5.c
1 /*
2 * HDMI driver for OMAP5
3 *
4 * Copyright (C) 2014 Texas Instruments Incorporated
5 *
6 * Authors:
7 * Yong Zhi
8 * Mythri pk
9 * Archit Taneja <archit@ti.com>
10 * Tomi Valkeinen <tomi.valkeinen@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License version 2 as published by
14 * the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program. If not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #define DSS_SUBSYS_NAME "HDMI"
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/err.h>
30 #include <linux/io.h>
31 #include <linux/interrupt.h>
32 #include <linux/mutex.h>
33 #include <linux/delay.h>
34 #include <linux/string.h>
35 #include <linux/platform_device.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/clk.h>
38 #include <linux/gpio.h>
39 #include <linux/regulator/consumer.h>
40 #include <linux/component.h>
41 #include <linux/of.h>
42 #include <video/omapdss.h>
43 #include <sound/omap-hdmi-audio.h>
44
45 #include "hdmi5_core.h"
46 #include "dss.h"
47 #include "dss_features.h"
48
49 static struct omap_hdmi hdmi;
50
51 static int hdmi_runtime_get(void)
52 {
53 int r;
54
55 DSSDBG("hdmi_runtime_get\n");
56
57 r = pm_runtime_get_sync(&hdmi.pdev->dev);
58 WARN_ON(r < 0);
59 if (r < 0)
60 return r;
61
62 return 0;
63 }
64
65 static void hdmi_runtime_put(void)
66 {
67 int r;
68
69 DSSDBG("hdmi_runtime_put\n");
70
71 r = pm_runtime_put_sync(&hdmi.pdev->dev);
72 WARN_ON(r < 0 && r != -ENOSYS);
73 }
74
75 static irqreturn_t hdmi_irq_handler(int irq, void *data)
76 {
77 struct hdmi_wp_data *wp = data;
78 u32 irqstatus;
79
80 irqstatus = hdmi_wp_get_irqstatus(wp);
81 hdmi_wp_set_irqstatus(wp, irqstatus);
82
83 if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
84 irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
85 u32 v;
86 /*
87 * If we get both connect and disconnect interrupts at the same
88 * time, turn off the PHY, clear interrupts, and restart, which
89 * raises connect interrupt if a cable is connected, or nothing
90 * if cable is not connected.
91 */
92
93 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
94
95 /*
96 * We always get bogus CONNECT & DISCONNECT interrupts when
97 * setting the PHY to LDOON. To ignore those, we force the RXDET
98 * line to 0 until the PHY power state has been changed.
99 */
100 v = hdmi_read_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL);
101 v = FLD_MOD(v, 1, 15, 15); /* FORCE_RXDET_HIGH */
102 v = FLD_MOD(v, 0, 14, 7); /* RXDET_LINE */
103 hdmi_write_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v);
104
105 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |
106 HDMI_IRQ_LINK_DISCONNECT);
107
108 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
109
110 REG_FLD_MOD(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15);
111
112 } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
113 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);
114 } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
115 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
116 }
117
118 return IRQ_HANDLED;
119 }
120
121 static int hdmi_init_regulator(void)
122 {
123 int r;
124 struct regulator *reg;
125
126 if (hdmi.vdda_reg != NULL)
127 return 0;
128
129 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda");
130 if (IS_ERR(reg)) {
131 DSSERR("can't get VDDA regulator\n");
132 return PTR_ERR(reg);
133 }
134
135 hdmi.vdda_reg = reg;
136
137 return 0;
138 }
139
140 static int hdmi_power_on_core(struct omap_dss_device *dssdev)
141 {
142 int r;
143
144 r = regulator_enable(hdmi.vdda_reg);
145 if (r)
146 return r;
147
148 r = hdmi_runtime_get();
149 if (r)
150 goto err_runtime_get;
151
152 /* Make selection of HDMI in DSS */
153 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
154
155 hdmi.core_enabled = true;
156
157 return 0;
158
159 err_runtime_get:
160 regulator_disable(hdmi.vdda_reg);
161
162 return r;
163 }
164
165 static void hdmi_power_off_core(struct omap_dss_device *dssdev)
166 {
167 hdmi.core_enabled = false;
168
169 hdmi_runtime_put();
170 regulator_disable(hdmi.vdda_reg);
171 }
172
173 static int hdmi_power_on_full(struct omap_dss_device *dssdev)
174 {
175 int r;
176 struct omap_video_timings *p;
177 enum omap_channel channel = dssdev->dispc_channel;
178 struct dss_pll_clock_info hdmi_cinfo = { 0 };
179 unsigned pc;
180
181 r = hdmi_power_on_core(dssdev);
182 if (r)
183 return r;
184
185 p = &hdmi.cfg.timings;
186
187 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
188
189 pc = p->pixelclock;
190 if (p->double_pixel)
191 pc *= 2;
192
193 hdmi_pll_compute(&hdmi.pll, pc, &hdmi_cinfo);
194
195 /* disable and clear irqs */
196 hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
197 hdmi_wp_set_irqstatus(&hdmi.wp,
198 hdmi_wp_get_irqstatus(&hdmi.wp));
199
200 r = dss_pll_enable(&hdmi.pll.pll);
201 if (r) {
202 DSSERR("Failed to enable PLL\n");
203 goto err_pll_enable;
204 }
205
206 r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo);
207 if (r) {
208 DSSERR("Failed to configure PLL\n");
209 goto err_pll_cfg;
210 }
211
212 r = hdmi_phy_configure(&hdmi.phy, hdmi_cinfo.clkdco,
213 hdmi_cinfo.clkout[0]);
214 if (r) {
215 DSSDBG("Failed to start PHY\n");
216 goto err_phy_cfg;
217 }
218
219 r = hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_LDOON);
220 if (r)
221 goto err_phy_pwr;
222
223 hdmi5_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);
224
225 /* bypass TV gamma table */
226 dispc_enable_gamma_table(0);
227
228 /* tv size */
229 dss_mgr_set_timings(channel, p);
230
231 r = dss_mgr_enable(channel);
232 if (r)
233 goto err_mgr_enable;
234
235 r = hdmi_wp_video_start(&hdmi.wp);
236 if (r)
237 goto err_vid_enable;
238
239 hdmi_wp_set_irqenable(&hdmi.wp,
240 HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
241
242 return 0;
243
244 err_vid_enable:
245 dss_mgr_disable(channel);
246 err_mgr_enable:
247 hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
248 err_phy_pwr:
249 err_phy_cfg:
250 err_pll_cfg:
251 dss_pll_disable(&hdmi.pll.pll);
252 err_pll_enable:
253 hdmi_power_off_core(dssdev);
254 return -EIO;
255 }
256
257 static void hdmi_power_off_full(struct omap_dss_device *dssdev)
258 {
259 enum omap_channel channel = dssdev->dispc_channel;
260
261 hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
262
263 hdmi_wp_video_stop(&hdmi.wp);
264
265 dss_mgr_disable(channel);
266
267 hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
268
269 dss_pll_disable(&hdmi.pll.pll);
270
271 hdmi_power_off_core(dssdev);
272 }
273
274 static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
275 struct omap_video_timings *timings)
276 {
277 if (!dispc_mgr_timings_ok(dssdev->dispc_channel, timings))
278 return -EINVAL;
279
280 return 0;
281 }
282
283 static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
284 struct omap_video_timings *timings)
285 {
286 mutex_lock(&hdmi.lock);
287
288 hdmi.cfg.timings = *timings;
289
290 dispc_set_tv_pclk(timings->pixelclock);
291
292 mutex_unlock(&hdmi.lock);
293 }
294
295 static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
296 struct omap_video_timings *timings)
297 {
298 *timings = hdmi.cfg.timings;
299 }
300
301 static void hdmi_dump_regs(struct seq_file *s)
302 {
303 mutex_lock(&hdmi.lock);
304
305 if (hdmi_runtime_get()) {
306 mutex_unlock(&hdmi.lock);
307 return;
308 }
309
310 hdmi_wp_dump(&hdmi.wp, s);
311 hdmi_pll_dump(&hdmi.pll, s);
312 hdmi_phy_dump(&hdmi.phy, s);
313 hdmi5_core_dump(&hdmi.core, s);
314
315 hdmi_runtime_put();
316 mutex_unlock(&hdmi.lock);
317 }
318
319 static int read_edid(u8 *buf, int len)
320 {
321 int r;
322 int idlemode;
323
324 mutex_lock(&hdmi.lock);
325
326 r = hdmi_runtime_get();
327 BUG_ON(r);
328
329 idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);
330 /* No-idle mode */
331 REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
332
333 r = hdmi5_read_edid(&hdmi.core, buf, len);
334
335 REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2);
336
337 hdmi_runtime_put();
338 mutex_unlock(&hdmi.lock);
339
340 return r;
341 }
342
343 static void hdmi_start_audio_stream(struct omap_hdmi *hd)
344 {
345 REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
346 hdmi_wp_audio_enable(&hd->wp, true);
347 hdmi_wp_audio_core_req_enable(&hd->wp, true);
348 }
349
350 static void hdmi_stop_audio_stream(struct omap_hdmi *hd)
351 {
352 hdmi_wp_audio_core_req_enable(&hd->wp, false);
353 hdmi_wp_audio_enable(&hd->wp, false);
354 REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2);
355 }
356
357 static int hdmi_display_enable(struct omap_dss_device *dssdev)
358 {
359 struct omap_dss_device *out = &hdmi.output;
360 unsigned long flags;
361 int r = 0;
362
363 DSSDBG("ENTER hdmi_display_enable\n");
364
365 mutex_lock(&hdmi.lock);
366
367 if (!out->dispc_channel_connected) {
368 DSSERR("failed to enable display: no output/manager\n");
369 r = -ENODEV;
370 goto err0;
371 }
372
373 r = hdmi_power_on_full(dssdev);
374 if (r) {
375 DSSERR("failed to power on device\n");
376 goto err0;
377 }
378
379 if (hdmi.audio_configured) {
380 r = hdmi5_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config,
381 hdmi.cfg.timings.pixelclock);
382 if (r) {
383 DSSERR("Error restoring audio configuration: %d", r);
384 hdmi.audio_abort_cb(&hdmi.pdev->dev);
385 hdmi.audio_configured = false;
386 }
387 }
388
389 spin_lock_irqsave(&hdmi.audio_playing_lock, flags);
390 if (hdmi.audio_configured && hdmi.audio_playing)
391 hdmi_start_audio_stream(&hdmi);
392 hdmi.display_enabled = true;
393 spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags);
394
395 mutex_unlock(&hdmi.lock);
396 return 0;
397
398 err0:
399 mutex_unlock(&hdmi.lock);
400 return r;
401 }
402
403 static void hdmi_display_disable(struct omap_dss_device *dssdev)
404 {
405 unsigned long flags;
406
407 DSSDBG("Enter hdmi_display_disable\n");
408
409 mutex_lock(&hdmi.lock);
410
411 spin_lock_irqsave(&hdmi.audio_playing_lock, flags);
412 hdmi_stop_audio_stream(&hdmi);
413 hdmi.display_enabled = false;
414 spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags);
415
416 hdmi_power_off_full(dssdev);
417
418 mutex_unlock(&hdmi.lock);
419 }
420
421 static int hdmi_core_enable(struct omap_dss_device *dssdev)
422 {
423 int r = 0;
424
425 DSSDBG("ENTER omapdss_hdmi_core_enable\n");
426
427 mutex_lock(&hdmi.lock);
428
429 r = hdmi_power_on_core(dssdev);
430 if (r) {
431 DSSERR("failed to power on device\n");
432 goto err0;
433 }
434
435 mutex_unlock(&hdmi.lock);
436 return 0;
437
438 err0:
439 mutex_unlock(&hdmi.lock);
440 return r;
441 }
442
443 static void hdmi_core_disable(struct omap_dss_device *dssdev)
444 {
445 DSSDBG("Enter omapdss_hdmi_core_disable\n");
446
447 mutex_lock(&hdmi.lock);
448
449 hdmi_power_off_core(dssdev);
450
451 mutex_unlock(&hdmi.lock);
452 }
453
454 static int hdmi_connect(struct omap_dss_device *dssdev,
455 struct omap_dss_device *dst)
456 {
457 enum omap_channel channel = dssdev->dispc_channel;
458 int r;
459
460 r = hdmi_init_regulator();
461 if (r)
462 return r;
463
464 r = dss_mgr_connect(channel, dssdev);
465 if (r)
466 return r;
467
468 r = omapdss_output_set_device(dssdev, dst);
469 if (r) {
470 DSSERR("failed to connect output to new device: %s\n",
471 dst->name);
472 dss_mgr_disconnect(channel, dssdev);
473 return r;
474 }
475
476 return 0;
477 }
478
479 static void hdmi_disconnect(struct omap_dss_device *dssdev,
480 struct omap_dss_device *dst)
481 {
482 enum omap_channel channel = dssdev->dispc_channel;
483
484 WARN_ON(dst != dssdev->dst);
485
486 if (dst != dssdev->dst)
487 return;
488
489 omapdss_output_unset_device(dssdev);
490
491 dss_mgr_disconnect(channel, dssdev);
492 }
493
494 static int hdmi_read_edid(struct omap_dss_device *dssdev,
495 u8 *edid, int len)
496 {
497 bool need_enable;
498 int r;
499
500 need_enable = hdmi.core_enabled == false;
501
502 if (need_enable) {
503 r = hdmi_core_enable(dssdev);
504 if (r)
505 return r;
506 }
507
508 r = read_edid(edid, len);
509
510 if (need_enable)
511 hdmi_core_disable(dssdev);
512
513 return r;
514 }
515
516 static int hdmi_set_infoframe(struct omap_dss_device *dssdev,
517 const struct hdmi_avi_infoframe *avi)
518 {
519 hdmi.cfg.infoframe = *avi;
520 return 0;
521 }
522
523 static int hdmi_set_hdmi_mode(struct omap_dss_device *dssdev,
524 bool hdmi_mode)
525 {
526 hdmi.cfg.hdmi_dvi_mode = hdmi_mode ? HDMI_HDMI : HDMI_DVI;
527 return 0;
528 }
529
530 static const struct omapdss_hdmi_ops hdmi_ops = {
531 .connect = hdmi_connect,
532 .disconnect = hdmi_disconnect,
533
534 .enable = hdmi_display_enable,
535 .disable = hdmi_display_disable,
536
537 .check_timings = hdmi_display_check_timing,
538 .set_timings = hdmi_display_set_timing,
539 .get_timings = hdmi_display_get_timings,
540
541 .read_edid = hdmi_read_edid,
542 .set_infoframe = hdmi_set_infoframe,
543 .set_hdmi_mode = hdmi_set_hdmi_mode,
544 };
545
546 static void hdmi_init_output(struct platform_device *pdev)
547 {
548 struct omap_dss_device *out = &hdmi.output;
549
550 out->dev = &pdev->dev;
551 out->id = OMAP_DSS_OUTPUT_HDMI;
552 out->output_type = OMAP_DISPLAY_TYPE_HDMI;
553 out->name = "hdmi.0";
554 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
555 out->ops.hdmi = &hdmi_ops;
556 out->owner = THIS_MODULE;
557
558 omapdss_register_output(out);
559 }
560
561 static void hdmi_uninit_output(struct platform_device *pdev)
562 {
563 struct omap_dss_device *out = &hdmi.output;
564
565 omapdss_unregister_output(out);
566 }
567
568 static int hdmi_probe_of(struct platform_device *pdev)
569 {
570 struct device_node *node = pdev->dev.of_node;
571 struct device_node *ep;
572 int r;
573
574 ep = omapdss_of_get_first_endpoint(node);
575 if (!ep)
576 return 0;
577
578 r = hdmi_parse_lanes_of(pdev, ep, &hdmi.phy);
579 if (r)
580 goto err;
581
582 of_node_put(ep);
583 return 0;
584
585 err:
586 of_node_put(ep);
587 return r;
588 }
589
590 /* Audio callbacks */
591 static int hdmi_audio_startup(struct device *dev,
592 void (*abort_cb)(struct device *dev))
593 {
594 struct omap_hdmi *hd = dev_get_drvdata(dev);
595 int ret = 0;
596
597 mutex_lock(&hd->lock);
598
599 if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
600 ret = -EPERM;
601 goto out;
602 }
603
604 hd->audio_abort_cb = abort_cb;
605
606 out:
607 mutex_unlock(&hd->lock);
608
609 return ret;
610 }
611
612 static int hdmi_audio_shutdown(struct device *dev)
613 {
614 struct omap_hdmi *hd = dev_get_drvdata(dev);
615
616 mutex_lock(&hd->lock);
617 hd->audio_abort_cb = NULL;
618 hd->audio_configured = false;
619 hd->audio_playing = false;
620 mutex_unlock(&hd->lock);
621
622 return 0;
623 }
624
625 static int hdmi_audio_start(struct device *dev)
626 {
627 struct omap_hdmi *hd = dev_get_drvdata(dev);
628 unsigned long flags;
629
630 WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
631
632 spin_lock_irqsave(&hd->audio_playing_lock, flags);
633
634 if (hd->display_enabled)
635 hdmi_start_audio_stream(hd);
636 hd->audio_playing = true;
637
638 spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
639 return 0;
640 }
641
642 static void hdmi_audio_stop(struct device *dev)
643 {
644 struct omap_hdmi *hd = dev_get_drvdata(dev);
645 unsigned long flags;
646
647 WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
648
649 spin_lock_irqsave(&hd->audio_playing_lock, flags);
650
651 if (hd->display_enabled)
652 hdmi_stop_audio_stream(hd);
653 hd->audio_playing = false;
654
655 spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
656 }
657
658 static int hdmi_audio_config(struct device *dev,
659 struct omap_dss_audio *dss_audio)
660 {
661 struct omap_hdmi *hd = dev_get_drvdata(dev);
662 int ret;
663
664 mutex_lock(&hd->lock);
665
666 if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
667 ret = -EPERM;
668 goto out;
669 }
670
671 ret = hdmi5_audio_config(&hd->core, &hd->wp, dss_audio,
672 hd->cfg.timings.pixelclock);
673
674 if (!ret) {
675 hd->audio_configured = true;
676 hd->audio_config = *dss_audio;
677 }
678 out:
679 mutex_unlock(&hd->lock);
680
681 return ret;
682 }
683
684 static const struct omap_hdmi_audio_ops hdmi_audio_ops = {
685 .audio_startup = hdmi_audio_startup,
686 .audio_shutdown = hdmi_audio_shutdown,
687 .audio_start = hdmi_audio_start,
688 .audio_stop = hdmi_audio_stop,
689 .audio_config = hdmi_audio_config,
690 };
691
692 static int hdmi_audio_register(struct device *dev)
693 {
694 struct omap_hdmi_audio_pdata pdata = {
695 .dev = dev,
696 .dss_version = omapdss_get_version(),
697 .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi.wp),
698 .ops = &hdmi_audio_ops,
699 };
700
701 hdmi.audio_pdev = platform_device_register_data(
702 dev, "omap-hdmi-audio", PLATFORM_DEVID_AUTO,
703 &pdata, sizeof(pdata));
704
705 if (IS_ERR(hdmi.audio_pdev))
706 return PTR_ERR(hdmi.audio_pdev);
707
708 hdmi_runtime_get();
709 hdmi.wp_idlemode =
710 REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);
711 hdmi_runtime_put();
712
713 return 0;
714 }
715
716 /* HDMI HW IP initialisation */
717 static int hdmi5_bind(struct device *dev, struct device *master, void *data)
718 {
719 struct platform_device *pdev = to_platform_device(dev);
720 int r;
721 int irq;
722
723 hdmi.pdev = pdev;
724 dev_set_drvdata(&pdev->dev, &hdmi);
725
726 mutex_init(&hdmi.lock);
727 spin_lock_init(&hdmi.audio_playing_lock);
728
729 if (pdev->dev.of_node) {
730 r = hdmi_probe_of(pdev);
731 if (r)
732 return r;
733 }
734
735 r = hdmi_wp_init(pdev, &hdmi.wp);
736 if (r)
737 return r;
738
739 r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp);
740 if (r)
741 return r;
742
743 r = hdmi_phy_init(pdev, &hdmi.phy);
744 if (r)
745 goto err;
746
747 r = hdmi5_core_init(pdev, &hdmi.core);
748 if (r)
749 goto err;
750
751 irq = platform_get_irq(pdev, 0);
752 if (irq < 0) {
753 DSSERR("platform_get_irq failed\n");
754 r = -ENODEV;
755 goto err;
756 }
757
758 r = devm_request_threaded_irq(&pdev->dev, irq,
759 NULL, hdmi_irq_handler,
760 IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp);
761 if (r) {
762 DSSERR("HDMI IRQ request failed\n");
763 goto err;
764 }
765
766 pm_runtime_enable(&pdev->dev);
767
768 hdmi_init_output(pdev);
769
770 r = hdmi_audio_register(&pdev->dev);
771 if (r) {
772 DSSERR("Registering HDMI audio failed %d\n", r);
773 hdmi_uninit_output(pdev);
774 pm_runtime_disable(&pdev->dev);
775 return r;
776 }
777
778 dss_debugfs_create_file("hdmi", hdmi_dump_regs);
779
780 return 0;
781 err:
782 hdmi_pll_uninit(&hdmi.pll);
783 return r;
784 }
785
786 static void hdmi5_unbind(struct device *dev, struct device *master, void *data)
787 {
788 struct platform_device *pdev = to_platform_device(dev);
789
790 if (hdmi.audio_pdev)
791 platform_device_unregister(hdmi.audio_pdev);
792
793 hdmi_uninit_output(pdev);
794
795 hdmi_pll_uninit(&hdmi.pll);
796
797 pm_runtime_disable(&pdev->dev);
798 }
799
800 static const struct component_ops hdmi5_component_ops = {
801 .bind = hdmi5_bind,
802 .unbind = hdmi5_unbind,
803 };
804
805 static int hdmi5_probe(struct platform_device *pdev)
806 {
807 return component_add(&pdev->dev, &hdmi5_component_ops);
808 }
809
810 static int hdmi5_remove(struct platform_device *pdev)
811 {
812 component_del(&pdev->dev, &hdmi5_component_ops);
813 return 0;
814 }
815
816 static int hdmi_runtime_suspend(struct device *dev)
817 {
818 dispc_runtime_put();
819
820 return 0;
821 }
822
823 static int hdmi_runtime_resume(struct device *dev)
824 {
825 int r;
826
827 r = dispc_runtime_get();
828 if (r < 0)
829 return r;
830
831 return 0;
832 }
833
834 static const struct dev_pm_ops hdmi_pm_ops = {
835 .runtime_suspend = hdmi_runtime_suspend,
836 .runtime_resume = hdmi_runtime_resume,
837 };
838
839 static const struct of_device_id hdmi_of_match[] = {
840 { .compatible = "ti,omap5-hdmi", },
841 { .compatible = "ti,dra7-hdmi", },
842 {},
843 };
844
845 static struct platform_driver omapdss_hdmihw_driver = {
846 .probe = hdmi5_probe,
847 .remove = hdmi5_remove,
848 .driver = {
849 .name = "omapdss_hdmi5",
850 .pm = &hdmi_pm_ops,
851 .of_match_table = hdmi_of_match,
852 .suppress_bind_attrs = true,
853 },
854 };
855
856 int __init hdmi5_init_platform_driver(void)
857 {
858 return platform_driver_register(&omapdss_hdmihw_driver);
859 }
860
861 void hdmi5_uninit_platform_driver(void)
862 {
863 platform_driver_unregister(&omapdss_hdmihw_driver);
864 }
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