f94201b6e8821bd06fb53a0d437823e9f7ecc8b8
[deliverable/linux.git] / drivers / gpu / drm / panel / panel-simple.c
1 /*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <linux/backlight.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/module.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/regulator/consumer.h>
30
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_mipi_dsi.h>
34 #include <drm/drm_panel.h>
35
36 #include <video/display_timing.h>
37 #include <video/videomode.h>
38
39 struct panel_desc {
40 const struct drm_display_mode *modes;
41 unsigned int num_modes;
42 const struct display_timing *timings;
43 unsigned int num_timings;
44
45 unsigned int bpc;
46
47 struct {
48 unsigned int width;
49 unsigned int height;
50 } size;
51
52 /**
53 * @prepare: the time (in milliseconds) that it takes for the panel to
54 * become ready and start receiving video data
55 * @enable: the time (in milliseconds) that it takes for the panel to
56 * display the first valid frame after starting to receive
57 * video data
58 * @disable: the time (in milliseconds) that it takes for the panel to
59 * turn the display off (no content is visible)
60 * @unprepare: the time (in milliseconds) that it takes for the panel
61 * to power itself down completely
62 */
63 struct {
64 unsigned int prepare;
65 unsigned int enable;
66 unsigned int disable;
67 unsigned int unprepare;
68 } delay;
69
70 u32 bus_format;
71 };
72
73 struct panel_simple {
74 struct drm_panel base;
75 bool prepared;
76 bool enabled;
77
78 const struct panel_desc *desc;
79
80 struct backlight_device *backlight;
81 struct regulator *supply;
82 struct i2c_adapter *ddc;
83
84 struct gpio_desc *enable_gpio;
85 };
86
87 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
88 {
89 return container_of(panel, struct panel_simple, base);
90 }
91
92 static int panel_simple_get_fixed_modes(struct panel_simple *panel)
93 {
94 struct drm_connector *connector = panel->base.connector;
95 struct drm_device *drm = panel->base.drm;
96 struct drm_display_mode *mode;
97 unsigned int i, num = 0;
98
99 if (!panel->desc)
100 return 0;
101
102 for (i = 0; i < panel->desc->num_timings; i++) {
103 const struct display_timing *dt = &panel->desc->timings[i];
104 struct videomode vm;
105
106 videomode_from_timing(dt, &vm);
107 mode = drm_mode_create(drm);
108 if (!mode) {
109 dev_err(drm->dev, "failed to add mode %ux%u\n",
110 dt->hactive.typ, dt->vactive.typ);
111 continue;
112 }
113
114 drm_display_mode_from_videomode(&vm, mode);
115 drm_mode_set_name(mode);
116
117 drm_mode_probed_add(connector, mode);
118 num++;
119 }
120
121 for (i = 0; i < panel->desc->num_modes; i++) {
122 const struct drm_display_mode *m = &panel->desc->modes[i];
123
124 mode = drm_mode_duplicate(drm, m);
125 if (!mode) {
126 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
127 m->hdisplay, m->vdisplay, m->vrefresh);
128 continue;
129 }
130
131 drm_mode_set_name(mode);
132
133 drm_mode_probed_add(connector, mode);
134 num++;
135 }
136
137 connector->display_info.bpc = panel->desc->bpc;
138 connector->display_info.width_mm = panel->desc->size.width;
139 connector->display_info.height_mm = panel->desc->size.height;
140 if (panel->desc->bus_format)
141 drm_display_info_set_bus_formats(&connector->display_info,
142 &panel->desc->bus_format, 1);
143
144 return num;
145 }
146
147 static int panel_simple_disable(struct drm_panel *panel)
148 {
149 struct panel_simple *p = to_panel_simple(panel);
150
151 if (!p->enabled)
152 return 0;
153
154 if (p->backlight) {
155 p->backlight->props.power = FB_BLANK_POWERDOWN;
156 backlight_update_status(p->backlight);
157 }
158
159 if (p->desc->delay.disable)
160 msleep(p->desc->delay.disable);
161
162 p->enabled = false;
163
164 return 0;
165 }
166
167 static int panel_simple_unprepare(struct drm_panel *panel)
168 {
169 struct panel_simple *p = to_panel_simple(panel);
170
171 if (!p->prepared)
172 return 0;
173
174 if (p->enable_gpio)
175 gpiod_set_value_cansleep(p->enable_gpio, 0);
176
177 regulator_disable(p->supply);
178
179 if (p->desc->delay.unprepare)
180 msleep(p->desc->delay.unprepare);
181
182 p->prepared = false;
183
184 return 0;
185 }
186
187 static int panel_simple_prepare(struct drm_panel *panel)
188 {
189 struct panel_simple *p = to_panel_simple(panel);
190 int err;
191
192 if (p->prepared)
193 return 0;
194
195 err = regulator_enable(p->supply);
196 if (err < 0) {
197 dev_err(panel->dev, "failed to enable supply: %d\n", err);
198 return err;
199 }
200
201 if (p->enable_gpio)
202 gpiod_set_value_cansleep(p->enable_gpio, 1);
203
204 if (p->desc->delay.prepare)
205 msleep(p->desc->delay.prepare);
206
207 p->prepared = true;
208
209 return 0;
210 }
211
212 static int panel_simple_enable(struct drm_panel *panel)
213 {
214 struct panel_simple *p = to_panel_simple(panel);
215
216 if (p->enabled)
217 return 0;
218
219 if (p->desc->delay.enable)
220 msleep(p->desc->delay.enable);
221
222 if (p->backlight) {
223 p->backlight->props.power = FB_BLANK_UNBLANK;
224 backlight_update_status(p->backlight);
225 }
226
227 p->enabled = true;
228
229 return 0;
230 }
231
232 static int panel_simple_get_modes(struct drm_panel *panel)
233 {
234 struct panel_simple *p = to_panel_simple(panel);
235 int num = 0;
236
237 /* probe EDID if a DDC bus is available */
238 if (p->ddc) {
239 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
240 drm_mode_connector_update_edid_property(panel->connector, edid);
241 if (edid) {
242 num += drm_add_edid_modes(panel->connector, edid);
243 kfree(edid);
244 }
245 }
246
247 /* add hard-coded panel modes */
248 num += panel_simple_get_fixed_modes(p);
249
250 return num;
251 }
252
253 static int panel_simple_get_timings(struct drm_panel *panel,
254 unsigned int num_timings,
255 struct display_timing *timings)
256 {
257 struct panel_simple *p = to_panel_simple(panel);
258 unsigned int i;
259
260 if (p->desc->num_timings < num_timings)
261 num_timings = p->desc->num_timings;
262
263 if (timings)
264 for (i = 0; i < num_timings; i++)
265 timings[i] = p->desc->timings[i];
266
267 return p->desc->num_timings;
268 }
269
270 static const struct drm_panel_funcs panel_simple_funcs = {
271 .disable = panel_simple_disable,
272 .unprepare = panel_simple_unprepare,
273 .prepare = panel_simple_prepare,
274 .enable = panel_simple_enable,
275 .get_modes = panel_simple_get_modes,
276 .get_timings = panel_simple_get_timings,
277 };
278
279 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
280 {
281 struct device_node *backlight, *ddc;
282 struct panel_simple *panel;
283 int err;
284
285 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
286 if (!panel)
287 return -ENOMEM;
288
289 panel->enabled = false;
290 panel->prepared = false;
291 panel->desc = desc;
292
293 panel->supply = devm_regulator_get(dev, "power");
294 if (IS_ERR(panel->supply))
295 return PTR_ERR(panel->supply);
296
297 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
298 GPIOD_OUT_LOW);
299 if (IS_ERR(panel->enable_gpio)) {
300 err = PTR_ERR(panel->enable_gpio);
301 dev_err(dev, "failed to request GPIO: %d\n", err);
302 return err;
303 }
304
305 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
306 if (backlight) {
307 panel->backlight = of_find_backlight_by_node(backlight);
308 of_node_put(backlight);
309
310 if (!panel->backlight)
311 return -EPROBE_DEFER;
312 }
313
314 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
315 if (ddc) {
316 panel->ddc = of_find_i2c_adapter_by_node(ddc);
317 of_node_put(ddc);
318
319 if (!panel->ddc) {
320 err = -EPROBE_DEFER;
321 goto free_backlight;
322 }
323 }
324
325 drm_panel_init(&panel->base);
326 panel->base.dev = dev;
327 panel->base.funcs = &panel_simple_funcs;
328
329 err = drm_panel_add(&panel->base);
330 if (err < 0)
331 goto free_ddc;
332
333 dev_set_drvdata(dev, panel);
334
335 return 0;
336
337 free_ddc:
338 if (panel->ddc)
339 put_device(&panel->ddc->dev);
340 free_backlight:
341 if (panel->backlight)
342 put_device(&panel->backlight->dev);
343
344 return err;
345 }
346
347 static int panel_simple_remove(struct device *dev)
348 {
349 struct panel_simple *panel = dev_get_drvdata(dev);
350
351 drm_panel_detach(&panel->base);
352 drm_panel_remove(&panel->base);
353
354 panel_simple_disable(&panel->base);
355
356 if (panel->ddc)
357 put_device(&panel->ddc->dev);
358
359 if (panel->backlight)
360 put_device(&panel->backlight->dev);
361
362 return 0;
363 }
364
365 static void panel_simple_shutdown(struct device *dev)
366 {
367 struct panel_simple *panel = dev_get_drvdata(dev);
368
369 panel_simple_disable(&panel->base);
370 }
371
372 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
373 .clock = 33333,
374 .hdisplay = 800,
375 .hsync_start = 800 + 0,
376 .hsync_end = 800 + 0 + 255,
377 .htotal = 800 + 0 + 255 + 0,
378 .vdisplay = 480,
379 .vsync_start = 480 + 2,
380 .vsync_end = 480 + 2 + 45,
381 .vtotal = 480 + 2 + 45 + 0,
382 .vrefresh = 60,
383 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
384 };
385
386 static const struct panel_desc ampire_am800480r3tmqwa1h = {
387 .modes = &ampire_am800480r3tmqwa1h_mode,
388 .num_modes = 1,
389 .bpc = 6,
390 .size = {
391 .width = 152,
392 .height = 91,
393 },
394 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
395 };
396
397 static const struct drm_display_mode auo_b101aw03_mode = {
398 .clock = 51450,
399 .hdisplay = 1024,
400 .hsync_start = 1024 + 156,
401 .hsync_end = 1024 + 156 + 8,
402 .htotal = 1024 + 156 + 8 + 156,
403 .vdisplay = 600,
404 .vsync_start = 600 + 16,
405 .vsync_end = 600 + 16 + 6,
406 .vtotal = 600 + 16 + 6 + 16,
407 .vrefresh = 60,
408 };
409
410 static const struct panel_desc auo_b101aw03 = {
411 .modes = &auo_b101aw03_mode,
412 .num_modes = 1,
413 .bpc = 6,
414 .size = {
415 .width = 223,
416 .height = 125,
417 },
418 };
419
420 static const struct drm_display_mode auo_b101ean01_mode = {
421 .clock = 72500,
422 .hdisplay = 1280,
423 .hsync_start = 1280 + 119,
424 .hsync_end = 1280 + 119 + 32,
425 .htotal = 1280 + 119 + 32 + 21,
426 .vdisplay = 800,
427 .vsync_start = 800 + 4,
428 .vsync_end = 800 + 4 + 20,
429 .vtotal = 800 + 4 + 20 + 8,
430 .vrefresh = 60,
431 };
432
433 static const struct panel_desc auo_b101ean01 = {
434 .modes = &auo_b101ean01_mode,
435 .num_modes = 1,
436 .bpc = 6,
437 .size = {
438 .width = 217,
439 .height = 136,
440 },
441 };
442
443 static const struct drm_display_mode auo_b101xtn01_mode = {
444 .clock = 72000,
445 .hdisplay = 1366,
446 .hsync_start = 1366 + 20,
447 .hsync_end = 1366 + 20 + 70,
448 .htotal = 1366 + 20 + 70,
449 .vdisplay = 768,
450 .vsync_start = 768 + 14,
451 .vsync_end = 768 + 14 + 42,
452 .vtotal = 768 + 14 + 42,
453 .vrefresh = 60,
454 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
455 };
456
457 static const struct panel_desc auo_b101xtn01 = {
458 .modes = &auo_b101xtn01_mode,
459 .num_modes = 1,
460 .bpc = 6,
461 .size = {
462 .width = 223,
463 .height = 125,
464 },
465 };
466
467 static const struct drm_display_mode auo_b116xw03_mode = {
468 .clock = 70589,
469 .hdisplay = 1366,
470 .hsync_start = 1366 + 40,
471 .hsync_end = 1366 + 40 + 40,
472 .htotal = 1366 + 40 + 40 + 32,
473 .vdisplay = 768,
474 .vsync_start = 768 + 10,
475 .vsync_end = 768 + 10 + 12,
476 .vtotal = 768 + 10 + 12 + 6,
477 .vrefresh = 60,
478 };
479
480 static const struct panel_desc auo_b116xw03 = {
481 .modes = &auo_b116xw03_mode,
482 .num_modes = 1,
483 .bpc = 6,
484 .size = {
485 .width = 256,
486 .height = 144,
487 },
488 };
489
490 static const struct drm_display_mode auo_b133xtn01_mode = {
491 .clock = 69500,
492 .hdisplay = 1366,
493 .hsync_start = 1366 + 48,
494 .hsync_end = 1366 + 48 + 32,
495 .htotal = 1366 + 48 + 32 + 20,
496 .vdisplay = 768,
497 .vsync_start = 768 + 3,
498 .vsync_end = 768 + 3 + 6,
499 .vtotal = 768 + 3 + 6 + 13,
500 .vrefresh = 60,
501 };
502
503 static const struct panel_desc auo_b133xtn01 = {
504 .modes = &auo_b133xtn01_mode,
505 .num_modes = 1,
506 .bpc = 6,
507 .size = {
508 .width = 293,
509 .height = 165,
510 },
511 };
512
513 static const struct drm_display_mode auo_b133htn01_mode = {
514 .clock = 150660,
515 .hdisplay = 1920,
516 .hsync_start = 1920 + 172,
517 .hsync_end = 1920 + 172 + 80,
518 .htotal = 1920 + 172 + 80 + 60,
519 .vdisplay = 1080,
520 .vsync_start = 1080 + 25,
521 .vsync_end = 1080 + 25 + 10,
522 .vtotal = 1080 + 25 + 10 + 10,
523 .vrefresh = 60,
524 };
525
526 static const struct panel_desc auo_b133htn01 = {
527 .modes = &auo_b133htn01_mode,
528 .num_modes = 1,
529 .bpc = 6,
530 .size = {
531 .width = 293,
532 .height = 165,
533 },
534 .delay = {
535 .prepare = 105,
536 .enable = 20,
537 .unprepare = 50,
538 },
539 };
540
541 static const struct drm_display_mode avic_tm070ddh03_mode = {
542 .clock = 51200,
543 .hdisplay = 1024,
544 .hsync_start = 1024 + 160,
545 .hsync_end = 1024 + 160 + 4,
546 .htotal = 1024 + 160 + 4 + 156,
547 .vdisplay = 600,
548 .vsync_start = 600 + 17,
549 .vsync_end = 600 + 17 + 1,
550 .vtotal = 600 + 17 + 1 + 17,
551 .vrefresh = 60,
552 };
553
554 static const struct panel_desc avic_tm070ddh03 = {
555 .modes = &avic_tm070ddh03_mode,
556 .num_modes = 1,
557 .bpc = 8,
558 .size = {
559 .width = 154,
560 .height = 90,
561 },
562 .delay = {
563 .prepare = 20,
564 .enable = 200,
565 .disable = 200,
566 },
567 };
568
569 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
570 .clock = 72070,
571 .hdisplay = 1366,
572 .hsync_start = 1366 + 58,
573 .hsync_end = 1366 + 58 + 58,
574 .htotal = 1366 + 58 + 58 + 58,
575 .vdisplay = 768,
576 .vsync_start = 768 + 4,
577 .vsync_end = 768 + 4 + 4,
578 .vtotal = 768 + 4 + 4 + 4,
579 .vrefresh = 60,
580 };
581
582 static const struct panel_desc chunghwa_claa101wa01a = {
583 .modes = &chunghwa_claa101wa01a_mode,
584 .num_modes = 1,
585 .bpc = 6,
586 .size = {
587 .width = 220,
588 .height = 120,
589 },
590 };
591
592 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
593 .clock = 69300,
594 .hdisplay = 1366,
595 .hsync_start = 1366 + 48,
596 .hsync_end = 1366 + 48 + 32,
597 .htotal = 1366 + 48 + 32 + 20,
598 .vdisplay = 768,
599 .vsync_start = 768 + 16,
600 .vsync_end = 768 + 16 + 8,
601 .vtotal = 768 + 16 + 8 + 16,
602 .vrefresh = 60,
603 };
604
605 static const struct panel_desc chunghwa_claa101wb01 = {
606 .modes = &chunghwa_claa101wb01_mode,
607 .num_modes = 1,
608 .bpc = 6,
609 .size = {
610 .width = 223,
611 .height = 125,
612 },
613 };
614
615 static const struct drm_display_mode edt_et057090dhu_mode = {
616 .clock = 25175,
617 .hdisplay = 640,
618 .hsync_start = 640 + 16,
619 .hsync_end = 640 + 16 + 30,
620 .htotal = 640 + 16 + 30 + 114,
621 .vdisplay = 480,
622 .vsync_start = 480 + 10,
623 .vsync_end = 480 + 10 + 3,
624 .vtotal = 480 + 10 + 3 + 32,
625 .vrefresh = 60,
626 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
627 };
628
629 static const struct panel_desc edt_et057090dhu = {
630 .modes = &edt_et057090dhu_mode,
631 .num_modes = 1,
632 .bpc = 6,
633 .size = {
634 .width = 115,
635 .height = 86,
636 },
637 };
638
639 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
640 .clock = 33260,
641 .hdisplay = 800,
642 .hsync_start = 800 + 40,
643 .hsync_end = 800 + 40 + 128,
644 .htotal = 800 + 40 + 128 + 88,
645 .vdisplay = 480,
646 .vsync_start = 480 + 10,
647 .vsync_end = 480 + 10 + 2,
648 .vtotal = 480 + 10 + 2 + 33,
649 .vrefresh = 60,
650 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
651 };
652
653 static const struct panel_desc edt_etm0700g0dh6 = {
654 .modes = &edt_etm0700g0dh6_mode,
655 .num_modes = 1,
656 .bpc = 6,
657 .size = {
658 .width = 152,
659 .height = 91,
660 },
661 };
662
663 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
664 .clock = 32260,
665 .hdisplay = 800,
666 .hsync_start = 800 + 168,
667 .hsync_end = 800 + 168 + 64,
668 .htotal = 800 + 168 + 64 + 88,
669 .vdisplay = 480,
670 .vsync_start = 480 + 37,
671 .vsync_end = 480 + 37 + 2,
672 .vtotal = 480 + 37 + 2 + 8,
673 .vrefresh = 60,
674 };
675
676 static const struct panel_desc foxlink_fl500wvr00_a0t = {
677 .modes = &foxlink_fl500wvr00_a0t_mode,
678 .num_modes = 1,
679 .bpc = 8,
680 .size = {
681 .width = 108,
682 .height = 65,
683 },
684 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
685 };
686
687 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
688 .clock = 9000,
689 .hdisplay = 480,
690 .hsync_start = 480 + 5,
691 .hsync_end = 480 + 5 + 1,
692 .htotal = 480 + 5 + 1 + 40,
693 .vdisplay = 272,
694 .vsync_start = 272 + 8,
695 .vsync_end = 272 + 8 + 1,
696 .vtotal = 272 + 8 + 1 + 8,
697 .vrefresh = 60,
698 };
699
700 static const struct panel_desc giantplus_gpg482739qs5 = {
701 .modes = &giantplus_gpg482739qs5_mode,
702 .num_modes = 1,
703 .bpc = 8,
704 .size = {
705 .width = 95,
706 .height = 54,
707 },
708 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
709 };
710
711 static const struct display_timing hannstar_hsd070pww1_timing = {
712 .pixelclock = { 64300000, 71100000, 82000000 },
713 .hactive = { 1280, 1280, 1280 },
714 .hfront_porch = { 1, 1, 10 },
715 .hback_porch = { 1, 1, 10 },
716 .hsync_len = { 52, 158, 661 },
717 .vactive = { 800, 800, 800 },
718 .vfront_porch = { 1, 1, 10 },
719 .vback_porch = { 1, 1, 10 },
720 .vsync_len = { 1, 21, 203 },
721 .flags = DISPLAY_FLAGS_DE_HIGH,
722 };
723
724 static const struct panel_desc hannstar_hsd070pww1 = {
725 .timings = &hannstar_hsd070pww1_timing,
726 .num_timings = 1,
727 .bpc = 6,
728 .size = {
729 .width = 151,
730 .height = 94,
731 },
732 };
733
734 static const struct display_timing hannstar_hsd100pxn1_timing = {
735 .pixelclock = { 55000000, 65000000, 75000000 },
736 .hactive = { 1024, 1024, 1024 },
737 .hfront_porch = { 40, 40, 40 },
738 .hback_porch = { 220, 220, 220 },
739 .hsync_len = { 20, 60, 100 },
740 .vactive = { 768, 768, 768 },
741 .vfront_porch = { 7, 7, 7 },
742 .vback_porch = { 21, 21, 21 },
743 .vsync_len = { 10, 10, 10 },
744 .flags = DISPLAY_FLAGS_DE_HIGH,
745 };
746
747 static const struct panel_desc hannstar_hsd100pxn1 = {
748 .timings = &hannstar_hsd100pxn1_timing,
749 .num_timings = 1,
750 .bpc = 6,
751 .size = {
752 .width = 203,
753 .height = 152,
754 },
755 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
756 };
757
758 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
759 .clock = 33333,
760 .hdisplay = 800,
761 .hsync_start = 800 + 85,
762 .hsync_end = 800 + 85 + 86,
763 .htotal = 800 + 85 + 86 + 85,
764 .vdisplay = 480,
765 .vsync_start = 480 + 16,
766 .vsync_end = 480 + 16 + 13,
767 .vtotal = 480 + 16 + 13 + 16,
768 .vrefresh = 60,
769 };
770
771 static const struct panel_desc hitachi_tx23d38vm0caa = {
772 .modes = &hitachi_tx23d38vm0caa_mode,
773 .num_modes = 1,
774 .bpc = 6,
775 .size = {
776 .width = 195,
777 .height = 117,
778 },
779 };
780
781 static const struct drm_display_mode innolux_at043tn24_mode = {
782 .clock = 9000,
783 .hdisplay = 480,
784 .hsync_start = 480 + 2,
785 .hsync_end = 480 + 2 + 41,
786 .htotal = 480 + 2 + 41 + 2,
787 .vdisplay = 272,
788 .vsync_start = 272 + 2,
789 .vsync_end = 272 + 2 + 11,
790 .vtotal = 272 + 2 + 11 + 2,
791 .vrefresh = 60,
792 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
793 };
794
795 static const struct panel_desc innolux_at043tn24 = {
796 .modes = &innolux_at043tn24_mode,
797 .num_modes = 1,
798 .bpc = 8,
799 .size = {
800 .width = 95,
801 .height = 54,
802 },
803 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
804 };
805
806 static const struct drm_display_mode innolux_g121i1_l01_mode = {
807 .clock = 71000,
808 .hdisplay = 1280,
809 .hsync_start = 1280 + 64,
810 .hsync_end = 1280 + 64 + 32,
811 .htotal = 1280 + 64 + 32 + 64,
812 .vdisplay = 800,
813 .vsync_start = 800 + 9,
814 .vsync_end = 800 + 9 + 6,
815 .vtotal = 800 + 9 + 6 + 9,
816 .vrefresh = 60,
817 };
818
819 static const struct panel_desc innolux_g121i1_l01 = {
820 .modes = &innolux_g121i1_l01_mode,
821 .num_modes = 1,
822 .bpc = 6,
823 .size = {
824 .width = 261,
825 .height = 163,
826 },
827 };
828
829 static const struct drm_display_mode innolux_n116bge_mode = {
830 .clock = 76420,
831 .hdisplay = 1366,
832 .hsync_start = 1366 + 136,
833 .hsync_end = 1366 + 136 + 30,
834 .htotal = 1366 + 136 + 30 + 60,
835 .vdisplay = 768,
836 .vsync_start = 768 + 8,
837 .vsync_end = 768 + 8 + 12,
838 .vtotal = 768 + 8 + 12 + 12,
839 .vrefresh = 60,
840 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
841 };
842
843 static const struct panel_desc innolux_n116bge = {
844 .modes = &innolux_n116bge_mode,
845 .num_modes = 1,
846 .bpc = 6,
847 .size = {
848 .width = 256,
849 .height = 144,
850 },
851 };
852
853 static const struct drm_display_mode innolux_n156bge_l21_mode = {
854 .clock = 69300,
855 .hdisplay = 1366,
856 .hsync_start = 1366 + 16,
857 .hsync_end = 1366 + 16 + 34,
858 .htotal = 1366 + 16 + 34 + 50,
859 .vdisplay = 768,
860 .vsync_start = 768 + 2,
861 .vsync_end = 768 + 2 + 6,
862 .vtotal = 768 + 2 + 6 + 12,
863 .vrefresh = 60,
864 };
865
866 static const struct panel_desc innolux_n156bge_l21 = {
867 .modes = &innolux_n156bge_l21_mode,
868 .num_modes = 1,
869 .bpc = 6,
870 .size = {
871 .width = 344,
872 .height = 193,
873 },
874 };
875
876 static const struct drm_display_mode innolux_zj070na_01p_mode = {
877 .clock = 51501,
878 .hdisplay = 1024,
879 .hsync_start = 1024 + 128,
880 .hsync_end = 1024 + 128 + 64,
881 .htotal = 1024 + 128 + 64 + 128,
882 .vdisplay = 600,
883 .vsync_start = 600 + 16,
884 .vsync_end = 600 + 16 + 4,
885 .vtotal = 600 + 16 + 4 + 16,
886 .vrefresh = 60,
887 };
888
889 static const struct panel_desc innolux_zj070na_01p = {
890 .modes = &innolux_zj070na_01p_mode,
891 .num_modes = 1,
892 .bpc = 6,
893 .size = {
894 .width = 1024,
895 .height = 600,
896 },
897 };
898
899 static const struct drm_display_mode lg_lb070wv8_mode = {
900 .clock = 33246,
901 .hdisplay = 800,
902 .hsync_start = 800 + 88,
903 .hsync_end = 800 + 88 + 80,
904 .htotal = 800 + 88 + 80 + 88,
905 .vdisplay = 480,
906 .vsync_start = 480 + 10,
907 .vsync_end = 480 + 10 + 25,
908 .vtotal = 480 + 10 + 25 + 10,
909 .vrefresh = 60,
910 };
911
912 static const struct panel_desc lg_lb070wv8 = {
913 .modes = &lg_lb070wv8_mode,
914 .num_modes = 1,
915 .bpc = 16,
916 .size = {
917 .width = 151,
918 .height = 91,
919 },
920 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
921 };
922
923 static const struct drm_display_mode lg_lp129qe_mode = {
924 .clock = 285250,
925 .hdisplay = 2560,
926 .hsync_start = 2560 + 48,
927 .hsync_end = 2560 + 48 + 32,
928 .htotal = 2560 + 48 + 32 + 80,
929 .vdisplay = 1700,
930 .vsync_start = 1700 + 3,
931 .vsync_end = 1700 + 3 + 10,
932 .vtotal = 1700 + 3 + 10 + 36,
933 .vrefresh = 60,
934 };
935
936 static const struct panel_desc lg_lp129qe = {
937 .modes = &lg_lp129qe_mode,
938 .num_modes = 1,
939 .bpc = 8,
940 .size = {
941 .width = 272,
942 .height = 181,
943 },
944 };
945
946 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
947 .clock = 25000,
948 .hdisplay = 480,
949 .hsync_start = 480 + 10,
950 .hsync_end = 480 + 10 + 10,
951 .htotal = 480 + 10 + 10 + 15,
952 .vdisplay = 800,
953 .vsync_start = 800 + 3,
954 .vsync_end = 800 + 3 + 3,
955 .vtotal = 800 + 3 + 3 + 3,
956 .vrefresh = 60,
957 };
958
959 static const struct panel_desc ortustech_com43h4m85ulc = {
960 .modes = &ortustech_com43h4m85ulc_mode,
961 .num_modes = 1,
962 .bpc = 8,
963 .size = {
964 .width = 56,
965 .height = 93,
966 },
967 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
968 };
969
970 static const struct drm_display_mode samsung_ltn101nt05_mode = {
971 .clock = 54030,
972 .hdisplay = 1024,
973 .hsync_start = 1024 + 24,
974 .hsync_end = 1024 + 24 + 136,
975 .htotal = 1024 + 24 + 136 + 160,
976 .vdisplay = 600,
977 .vsync_start = 600 + 3,
978 .vsync_end = 600 + 3 + 6,
979 .vtotal = 600 + 3 + 6 + 61,
980 .vrefresh = 60,
981 };
982
983 static const struct panel_desc samsung_ltn101nt05 = {
984 .modes = &samsung_ltn101nt05_mode,
985 .num_modes = 1,
986 .bpc = 6,
987 .size = {
988 .width = 1024,
989 .height = 600,
990 },
991 };
992
993 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
994 .clock = 76300,
995 .hdisplay = 1366,
996 .hsync_start = 1366 + 64,
997 .hsync_end = 1366 + 64 + 48,
998 .htotal = 1366 + 64 + 48 + 128,
999 .vdisplay = 768,
1000 .vsync_start = 768 + 2,
1001 .vsync_end = 768 + 2 + 5,
1002 .vtotal = 768 + 2 + 5 + 17,
1003 .vrefresh = 60,
1004 };
1005
1006 static const struct panel_desc samsung_ltn140at29_301 = {
1007 .modes = &samsung_ltn140at29_301_mode,
1008 .num_modes = 1,
1009 .bpc = 6,
1010 .size = {
1011 .width = 320,
1012 .height = 187,
1013 },
1014 };
1015
1016 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
1017 .clock = 33300,
1018 .hdisplay = 800,
1019 .hsync_start = 800 + 1,
1020 .hsync_end = 800 + 1 + 64,
1021 .htotal = 800 + 1 + 64 + 64,
1022 .vdisplay = 480,
1023 .vsync_start = 480 + 1,
1024 .vsync_end = 480 + 1 + 23,
1025 .vtotal = 480 + 1 + 23 + 22,
1026 .vrefresh = 60,
1027 };
1028
1029 static const struct panel_desc shelly_sca07010_bfn_lnn = {
1030 .modes = &shelly_sca07010_bfn_lnn_mode,
1031 .num_modes = 1,
1032 .size = {
1033 .width = 152,
1034 .height = 91,
1035 },
1036 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1037 };
1038
1039 static const struct of_device_id platform_of_match[] = {
1040 {
1041 .compatible = "ampire,am800480r3tmqwa1h",
1042 .data = &ampire_am800480r3tmqwa1h,
1043 }, {
1044 .compatible = "auo,b101aw03",
1045 .data = &auo_b101aw03,
1046 }, {
1047 .compatible = "auo,b101ean01",
1048 .data = &auo_b101ean01,
1049 }, {
1050 .compatible = "auo,b101xtn01",
1051 .data = &auo_b101xtn01,
1052 }, {
1053 .compatible = "auo,b116xw03",
1054 .data = &auo_b116xw03,
1055 }, {
1056 .compatible = "auo,b133htn01",
1057 .data = &auo_b133htn01,
1058 }, {
1059 .compatible = "auo,b133xtn01",
1060 .data = &auo_b133xtn01,
1061 }, {
1062 .compatible = "avic,tm070ddh03",
1063 .data = &avic_tm070ddh03,
1064 }, {
1065 .compatible = "chunghwa,claa101wa01a",
1066 .data = &chunghwa_claa101wa01a
1067 }, {
1068 .compatible = "chunghwa,claa101wb01",
1069 .data = &chunghwa_claa101wb01
1070 }, {
1071 .compatible = "edt,et057090dhu",
1072 .data = &edt_et057090dhu,
1073 }, {
1074 .compatible = "edt,et070080dh6",
1075 .data = &edt_etm0700g0dh6,
1076 }, {
1077 .compatible = "edt,etm0700g0dh6",
1078 .data = &edt_etm0700g0dh6,
1079 }, {
1080 .compatible = "foxlink,fl500wvr00-a0t",
1081 .data = &foxlink_fl500wvr00_a0t,
1082 }, {
1083 .compatible = "giantplus,gpg482739qs5",
1084 .data = &giantplus_gpg482739qs5
1085 }, {
1086 .compatible = "hannstar,hsd070pww1",
1087 .data = &hannstar_hsd070pww1,
1088 }, {
1089 .compatible = "hannstar,hsd100pxn1",
1090 .data = &hannstar_hsd100pxn1,
1091 }, {
1092 .compatible = "hit,tx23d38vm0caa",
1093 .data = &hitachi_tx23d38vm0caa
1094 }, {
1095 .compatible = "innolux,at043tn24",
1096 .data = &innolux_at043tn24,
1097 }, {
1098 .compatible ="innolux,g121i1-l01",
1099 .data = &innolux_g121i1_l01
1100 }, {
1101 .compatible = "innolux,n116bge",
1102 .data = &innolux_n116bge,
1103 }, {
1104 .compatible = "innolux,n156bge-l21",
1105 .data = &innolux_n156bge_l21,
1106 }, {
1107 .compatible = "innolux,zj070na-01p",
1108 .data = &innolux_zj070na_01p,
1109 }, {
1110 .compatible = "lg,lb070wv8",
1111 .data = &lg_lb070wv8,
1112 }, {
1113 .compatible = "lg,lp129qe",
1114 .data = &lg_lp129qe,
1115 }, {
1116 .compatible = "ortustech,com43h4m85ulc",
1117 .data = &ortustech_com43h4m85ulc,
1118 }, {
1119 .compatible = "samsung,ltn101nt05",
1120 .data = &samsung_ltn101nt05,
1121 }, {
1122 .compatible = "samsung,ltn140at29-301",
1123 .data = &samsung_ltn140at29_301,
1124 }, {
1125 .compatible = "shelly,sca07010-bfn-lnn",
1126 .data = &shelly_sca07010_bfn_lnn,
1127 }, {
1128 /* sentinel */
1129 }
1130 };
1131 MODULE_DEVICE_TABLE(of, platform_of_match);
1132
1133 static int panel_simple_platform_probe(struct platform_device *pdev)
1134 {
1135 const struct of_device_id *id;
1136
1137 id = of_match_node(platform_of_match, pdev->dev.of_node);
1138 if (!id)
1139 return -ENODEV;
1140
1141 return panel_simple_probe(&pdev->dev, id->data);
1142 }
1143
1144 static int panel_simple_platform_remove(struct platform_device *pdev)
1145 {
1146 return panel_simple_remove(&pdev->dev);
1147 }
1148
1149 static void panel_simple_platform_shutdown(struct platform_device *pdev)
1150 {
1151 panel_simple_shutdown(&pdev->dev);
1152 }
1153
1154 static struct platform_driver panel_simple_platform_driver = {
1155 .driver = {
1156 .name = "panel-simple",
1157 .of_match_table = platform_of_match,
1158 },
1159 .probe = panel_simple_platform_probe,
1160 .remove = panel_simple_platform_remove,
1161 .shutdown = panel_simple_platform_shutdown,
1162 };
1163
1164 struct panel_desc_dsi {
1165 struct panel_desc desc;
1166
1167 unsigned long flags;
1168 enum mipi_dsi_pixel_format format;
1169 unsigned int lanes;
1170 };
1171
1172 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
1173 .clock = 71000,
1174 .hdisplay = 800,
1175 .hsync_start = 800 + 32,
1176 .hsync_end = 800 + 32 + 1,
1177 .htotal = 800 + 32 + 1 + 57,
1178 .vdisplay = 1280,
1179 .vsync_start = 1280 + 28,
1180 .vsync_end = 1280 + 28 + 1,
1181 .vtotal = 1280 + 28 + 1 + 14,
1182 .vrefresh = 60,
1183 };
1184
1185 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
1186 .desc = {
1187 .modes = &lg_ld070wx3_sl01_mode,
1188 .num_modes = 1,
1189 .bpc = 8,
1190 .size = {
1191 .width = 94,
1192 .height = 151,
1193 },
1194 },
1195 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1196 .format = MIPI_DSI_FMT_RGB888,
1197 .lanes = 4,
1198 };
1199
1200 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
1201 .clock = 67000,
1202 .hdisplay = 720,
1203 .hsync_start = 720 + 12,
1204 .hsync_end = 720 + 12 + 4,
1205 .htotal = 720 + 12 + 4 + 112,
1206 .vdisplay = 1280,
1207 .vsync_start = 1280 + 8,
1208 .vsync_end = 1280 + 8 + 4,
1209 .vtotal = 1280 + 8 + 4 + 12,
1210 .vrefresh = 60,
1211 };
1212
1213 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
1214 .desc = {
1215 .modes = &lg_lh500wx1_sd03_mode,
1216 .num_modes = 1,
1217 .bpc = 8,
1218 .size = {
1219 .width = 62,
1220 .height = 110,
1221 },
1222 },
1223 .flags = MIPI_DSI_MODE_VIDEO,
1224 .format = MIPI_DSI_FMT_RGB888,
1225 .lanes = 4,
1226 };
1227
1228 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
1229 .clock = 157200,
1230 .hdisplay = 1920,
1231 .hsync_start = 1920 + 154,
1232 .hsync_end = 1920 + 154 + 16,
1233 .htotal = 1920 + 154 + 16 + 32,
1234 .vdisplay = 1200,
1235 .vsync_start = 1200 + 17,
1236 .vsync_end = 1200 + 17 + 2,
1237 .vtotal = 1200 + 17 + 2 + 16,
1238 .vrefresh = 60,
1239 };
1240
1241 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
1242 .desc = {
1243 .modes = &panasonic_vvx10f004b00_mode,
1244 .num_modes = 1,
1245 .bpc = 8,
1246 .size = {
1247 .width = 217,
1248 .height = 136,
1249 },
1250 },
1251 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
1252 MIPI_DSI_CLOCK_NON_CONTINUOUS,
1253 .format = MIPI_DSI_FMT_RGB888,
1254 .lanes = 4,
1255 };
1256
1257 static const struct of_device_id dsi_of_match[] = {
1258 {
1259 .compatible = "lg,ld070wx3-sl01",
1260 .data = &lg_ld070wx3_sl01
1261 }, {
1262 .compatible = "lg,lh500wx1-sd03",
1263 .data = &lg_lh500wx1_sd03
1264 }, {
1265 .compatible = "panasonic,vvx10f004b00",
1266 .data = &panasonic_vvx10f004b00
1267 }, {
1268 /* sentinel */
1269 }
1270 };
1271 MODULE_DEVICE_TABLE(of, dsi_of_match);
1272
1273 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
1274 {
1275 const struct panel_desc_dsi *desc;
1276 const struct of_device_id *id;
1277 int err;
1278
1279 id = of_match_node(dsi_of_match, dsi->dev.of_node);
1280 if (!id)
1281 return -ENODEV;
1282
1283 desc = id->data;
1284
1285 err = panel_simple_probe(&dsi->dev, &desc->desc);
1286 if (err < 0)
1287 return err;
1288
1289 dsi->mode_flags = desc->flags;
1290 dsi->format = desc->format;
1291 dsi->lanes = desc->lanes;
1292
1293 return mipi_dsi_attach(dsi);
1294 }
1295
1296 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
1297 {
1298 int err;
1299
1300 err = mipi_dsi_detach(dsi);
1301 if (err < 0)
1302 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
1303
1304 return panel_simple_remove(&dsi->dev);
1305 }
1306
1307 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
1308 {
1309 panel_simple_shutdown(&dsi->dev);
1310 }
1311
1312 static struct mipi_dsi_driver panel_simple_dsi_driver = {
1313 .driver = {
1314 .name = "panel-simple-dsi",
1315 .of_match_table = dsi_of_match,
1316 },
1317 .probe = panel_simple_dsi_probe,
1318 .remove = panel_simple_dsi_remove,
1319 .shutdown = panel_simple_dsi_shutdown,
1320 };
1321
1322 static int __init panel_simple_init(void)
1323 {
1324 int err;
1325
1326 err = platform_driver_register(&panel_simple_platform_driver);
1327 if (err < 0)
1328 return err;
1329
1330 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
1331 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
1332 if (err < 0)
1333 return err;
1334 }
1335
1336 return 0;
1337 }
1338 module_init(panel_simple_init);
1339
1340 static void __exit panel_simple_exit(void)
1341 {
1342 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
1343 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
1344
1345 platform_driver_unregister(&panel_simple_platform_driver);
1346 }
1347 module_exit(panel_simple_exit);
1348
1349 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1350 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
1351 MODULE_LICENSE("GPL and additional rights");
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