2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include <drm/drm_fixed.h>
32 #include "atom-bits.h"
34 static void atombios_overscan_setup(struct drm_crtc
*crtc
,
35 struct drm_display_mode
*mode
,
36 struct drm_display_mode
*adjusted_mode
)
38 struct drm_device
*dev
= crtc
->dev
;
39 struct radeon_device
*rdev
= dev
->dev_private
;
40 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args
;
42 int index
= GetIndexIntoMasterTable(COMMAND
, SetCRTC_OverScan
);
45 memset(&args
, 0, sizeof(args
));
47 args
.ucCRTC
= radeon_crtc
->crtc_id
;
49 switch (radeon_crtc
->rmx_type
) {
51 args
.usOverscanTop
= cpu_to_le16((adjusted_mode
->crtc_vdisplay
- mode
->crtc_vdisplay
) / 2);
52 args
.usOverscanBottom
= cpu_to_le16((adjusted_mode
->crtc_vdisplay
- mode
->crtc_vdisplay
) / 2);
53 args
.usOverscanLeft
= cpu_to_le16((adjusted_mode
->crtc_hdisplay
- mode
->crtc_hdisplay
) / 2);
54 args
.usOverscanRight
= cpu_to_le16((adjusted_mode
->crtc_hdisplay
- mode
->crtc_hdisplay
) / 2);
57 a1
= mode
->crtc_vdisplay
* adjusted_mode
->crtc_hdisplay
;
58 a2
= adjusted_mode
->crtc_vdisplay
* mode
->crtc_hdisplay
;
61 args
.usOverscanLeft
= cpu_to_le16((adjusted_mode
->crtc_hdisplay
- (a2
/ mode
->crtc_vdisplay
)) / 2);
62 args
.usOverscanRight
= cpu_to_le16((adjusted_mode
->crtc_hdisplay
- (a2
/ mode
->crtc_vdisplay
)) / 2);
64 args
.usOverscanLeft
= cpu_to_le16((adjusted_mode
->crtc_vdisplay
- (a1
/ mode
->crtc_hdisplay
)) / 2);
65 args
.usOverscanRight
= cpu_to_le16((adjusted_mode
->crtc_vdisplay
- (a1
/ mode
->crtc_hdisplay
)) / 2);
70 args
.usOverscanRight
= cpu_to_le16(radeon_crtc
->h_border
);
71 args
.usOverscanLeft
= cpu_to_le16(radeon_crtc
->h_border
);
72 args
.usOverscanBottom
= cpu_to_le16(radeon_crtc
->v_border
);
73 args
.usOverscanTop
= cpu_to_le16(radeon_crtc
->v_border
);
76 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
79 static void atombios_scaler_setup(struct drm_crtc
*crtc
)
81 struct drm_device
*dev
= crtc
->dev
;
82 struct radeon_device
*rdev
= dev
->dev_private
;
83 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
84 ENABLE_SCALER_PS_ALLOCATION args
;
85 int index
= GetIndexIntoMasterTable(COMMAND
, EnableScaler
);
87 /* fixme - fill in enc_priv for atom dac */
88 enum radeon_tv_std tv_std
= TV_STD_NTSC
;
89 bool is_tv
= false, is_cv
= false;
90 struct drm_encoder
*encoder
;
92 if (!ASIC_IS_AVIVO(rdev
) && radeon_crtc
->crtc_id
)
95 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
97 if (encoder
->crtc
== crtc
) {
98 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
99 if (radeon_encoder
->active_device
& ATOM_DEVICE_TV_SUPPORT
) {
100 struct radeon_encoder_atom_dac
*tv_dac
= radeon_encoder
->enc_priv
;
101 tv_std
= tv_dac
->tv_std
;
107 memset(&args
, 0, sizeof(args
));
109 args
.ucScaler
= radeon_crtc
->crtc_id
;
115 args
.ucTVStandard
= ATOM_TV_NTSC
;
118 args
.ucTVStandard
= ATOM_TV_PAL
;
121 args
.ucTVStandard
= ATOM_TV_PALM
;
124 args
.ucTVStandard
= ATOM_TV_PAL60
;
127 args
.ucTVStandard
= ATOM_TV_NTSCJ
;
129 case TV_STD_SCART_PAL
:
130 args
.ucTVStandard
= ATOM_TV_PAL
; /* ??? */
133 args
.ucTVStandard
= ATOM_TV_SECAM
;
136 args
.ucTVStandard
= ATOM_TV_PALCN
;
139 args
.ucEnable
= SCALER_ENABLE_MULTITAP_MODE
;
141 args
.ucTVStandard
= ATOM_TV_CV
;
142 args
.ucEnable
= SCALER_ENABLE_MULTITAP_MODE
;
144 switch (radeon_crtc
->rmx_type
) {
146 args
.ucEnable
= ATOM_SCALER_EXPANSION
;
149 args
.ucEnable
= ATOM_SCALER_CENTER
;
152 args
.ucEnable
= ATOM_SCALER_EXPANSION
;
155 if (ASIC_IS_AVIVO(rdev
))
156 args
.ucEnable
= ATOM_SCALER_DISABLE
;
158 args
.ucEnable
= ATOM_SCALER_CENTER
;
162 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
164 && rdev
->family
>= CHIP_RV515
&& rdev
->family
<= CHIP_R580
) {
165 atom_rv515_force_tv_scaler(rdev
, radeon_crtc
);
169 static void atombios_lock_crtc(struct drm_crtc
*crtc
, int lock
)
171 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
172 struct drm_device
*dev
= crtc
->dev
;
173 struct radeon_device
*rdev
= dev
->dev_private
;
175 GetIndexIntoMasterTable(COMMAND
, UpdateCRTC_DoubleBufferRegisters
);
176 ENABLE_CRTC_PS_ALLOCATION args
;
178 memset(&args
, 0, sizeof(args
));
180 args
.ucCRTC
= radeon_crtc
->crtc_id
;
181 args
.ucEnable
= lock
;
183 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
186 static void atombios_enable_crtc(struct drm_crtc
*crtc
, int state
)
188 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
189 struct drm_device
*dev
= crtc
->dev
;
190 struct radeon_device
*rdev
= dev
->dev_private
;
191 int index
= GetIndexIntoMasterTable(COMMAND
, EnableCRTC
);
192 ENABLE_CRTC_PS_ALLOCATION args
;
194 memset(&args
, 0, sizeof(args
));
196 args
.ucCRTC
= radeon_crtc
->crtc_id
;
197 args
.ucEnable
= state
;
199 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
202 static void atombios_enable_crtc_memreq(struct drm_crtc
*crtc
, int state
)
204 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
205 struct drm_device
*dev
= crtc
->dev
;
206 struct radeon_device
*rdev
= dev
->dev_private
;
207 int index
= GetIndexIntoMasterTable(COMMAND
, EnableCRTCMemReq
);
208 ENABLE_CRTC_PS_ALLOCATION args
;
210 memset(&args
, 0, sizeof(args
));
212 args
.ucCRTC
= radeon_crtc
->crtc_id
;
213 args
.ucEnable
= state
;
215 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
218 static void atombios_blank_crtc(struct drm_crtc
*crtc
, int state
)
220 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
221 struct drm_device
*dev
= crtc
->dev
;
222 struct radeon_device
*rdev
= dev
->dev_private
;
223 int index
= GetIndexIntoMasterTable(COMMAND
, BlankCRTC
);
224 BLANK_CRTC_PS_ALLOCATION args
;
226 memset(&args
, 0, sizeof(args
));
228 args
.ucCRTC
= radeon_crtc
->crtc_id
;
229 args
.ucBlanking
= state
;
231 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
234 void atombios_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
236 struct drm_device
*dev
= crtc
->dev
;
237 struct radeon_device
*rdev
= dev
->dev_private
;
238 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
241 case DRM_MODE_DPMS_ON
:
242 radeon_crtc
->enabled
= true;
243 /* adjust pm to dpms changes BEFORE enabling crtcs */
244 radeon_pm_compute_clocks(rdev
);
245 atombios_enable_crtc(crtc
, ATOM_ENABLE
);
246 if (ASIC_IS_DCE3(rdev
))
247 atombios_enable_crtc_memreq(crtc
, ATOM_ENABLE
);
248 atombios_blank_crtc(crtc
, ATOM_DISABLE
);
249 drm_vblank_post_modeset(dev
, radeon_crtc
->crtc_id
);
250 radeon_crtc_load_lut(crtc
);
252 case DRM_MODE_DPMS_STANDBY
:
253 case DRM_MODE_DPMS_SUSPEND
:
254 case DRM_MODE_DPMS_OFF
:
255 drm_vblank_pre_modeset(dev
, radeon_crtc
->crtc_id
);
256 if (radeon_crtc
->enabled
)
257 atombios_blank_crtc(crtc
, ATOM_ENABLE
);
258 if (ASIC_IS_DCE3(rdev
))
259 atombios_enable_crtc_memreq(crtc
, ATOM_DISABLE
);
260 atombios_enable_crtc(crtc
, ATOM_DISABLE
);
261 radeon_crtc
->enabled
= false;
262 /* adjust pm to dpms changes AFTER disabling crtcs */
263 radeon_pm_compute_clocks(rdev
);
269 atombios_set_crtc_dtd_timing(struct drm_crtc
*crtc
,
270 struct drm_display_mode
*mode
)
272 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
273 struct drm_device
*dev
= crtc
->dev
;
274 struct radeon_device
*rdev
= dev
->dev_private
;
275 SET_CRTC_USING_DTD_TIMING_PARAMETERS args
;
276 int index
= GetIndexIntoMasterTable(COMMAND
, SetCRTC_UsingDTDTiming
);
279 memset(&args
, 0, sizeof(args
));
280 args
.usH_Size
= cpu_to_le16(mode
->crtc_hdisplay
- (radeon_crtc
->h_border
* 2));
281 args
.usH_Blanking_Time
=
282 cpu_to_le16(mode
->crtc_hblank_end
- mode
->crtc_hdisplay
+ (radeon_crtc
->h_border
* 2));
283 args
.usV_Size
= cpu_to_le16(mode
->crtc_vdisplay
- (radeon_crtc
->v_border
* 2));
284 args
.usV_Blanking_Time
=
285 cpu_to_le16(mode
->crtc_vblank_end
- mode
->crtc_vdisplay
+ (radeon_crtc
->v_border
* 2));
286 args
.usH_SyncOffset
=
287 cpu_to_le16(mode
->crtc_hsync_start
- mode
->crtc_hdisplay
+ radeon_crtc
->h_border
);
289 cpu_to_le16(mode
->crtc_hsync_end
- mode
->crtc_hsync_start
);
290 args
.usV_SyncOffset
=
291 cpu_to_le16(mode
->crtc_vsync_start
- mode
->crtc_vdisplay
+ radeon_crtc
->v_border
);
293 cpu_to_le16(mode
->crtc_vsync_end
- mode
->crtc_vsync_start
);
294 args
.ucH_Border
= radeon_crtc
->h_border
;
295 args
.ucV_Border
= radeon_crtc
->v_border
;
297 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
298 misc
|= ATOM_VSYNC_POLARITY
;
299 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
300 misc
|= ATOM_HSYNC_POLARITY
;
301 if (mode
->flags
& DRM_MODE_FLAG_CSYNC
)
302 misc
|= ATOM_COMPOSITESYNC
;
303 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
304 misc
|= ATOM_INTERLACE
;
305 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
306 misc
|= ATOM_DOUBLE_CLOCK_MODE
;
308 args
.susModeMiscInfo
.usAccess
= cpu_to_le16(misc
);
309 args
.ucCRTC
= radeon_crtc
->crtc_id
;
311 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
314 static void atombios_crtc_set_timing(struct drm_crtc
*crtc
,
315 struct drm_display_mode
*mode
)
317 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
318 struct drm_device
*dev
= crtc
->dev
;
319 struct radeon_device
*rdev
= dev
->dev_private
;
320 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args
;
321 int index
= GetIndexIntoMasterTable(COMMAND
, SetCRTC_Timing
);
324 memset(&args
, 0, sizeof(args
));
325 args
.usH_Total
= cpu_to_le16(mode
->crtc_htotal
);
326 args
.usH_Disp
= cpu_to_le16(mode
->crtc_hdisplay
);
327 args
.usH_SyncStart
= cpu_to_le16(mode
->crtc_hsync_start
);
329 cpu_to_le16(mode
->crtc_hsync_end
- mode
->crtc_hsync_start
);
330 args
.usV_Total
= cpu_to_le16(mode
->crtc_vtotal
);
331 args
.usV_Disp
= cpu_to_le16(mode
->crtc_vdisplay
);
332 args
.usV_SyncStart
= cpu_to_le16(mode
->crtc_vsync_start
);
334 cpu_to_le16(mode
->crtc_vsync_end
- mode
->crtc_vsync_start
);
336 args
.ucOverscanRight
= radeon_crtc
->h_border
;
337 args
.ucOverscanLeft
= radeon_crtc
->h_border
;
338 args
.ucOverscanBottom
= radeon_crtc
->v_border
;
339 args
.ucOverscanTop
= radeon_crtc
->v_border
;
341 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
342 misc
|= ATOM_VSYNC_POLARITY
;
343 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
344 misc
|= ATOM_HSYNC_POLARITY
;
345 if (mode
->flags
& DRM_MODE_FLAG_CSYNC
)
346 misc
|= ATOM_COMPOSITESYNC
;
347 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
348 misc
|= ATOM_INTERLACE
;
349 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
350 misc
|= ATOM_DOUBLE_CLOCK_MODE
;
352 args
.susModeMiscInfo
.usAccess
= cpu_to_le16(misc
);
353 args
.ucCRTC
= radeon_crtc
->crtc_id
;
355 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
358 static void atombios_disable_ss(struct drm_crtc
*crtc
)
360 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
361 struct drm_device
*dev
= crtc
->dev
;
362 struct radeon_device
*rdev
= dev
->dev_private
;
365 if (ASIC_IS_DCE4(rdev
)) {
366 switch (radeon_crtc
->pll_id
) {
368 ss_cntl
= RREG32(EVERGREEN_P1PLL_SS_CNTL
);
369 ss_cntl
&= ~EVERGREEN_PxPLL_SS_EN
;
370 WREG32(EVERGREEN_P1PLL_SS_CNTL
, ss_cntl
);
373 ss_cntl
= RREG32(EVERGREEN_P2PLL_SS_CNTL
);
374 ss_cntl
&= ~EVERGREEN_PxPLL_SS_EN
;
375 WREG32(EVERGREEN_P2PLL_SS_CNTL
, ss_cntl
);
378 case ATOM_PPLL_INVALID
:
381 } else if (ASIC_IS_AVIVO(rdev
)) {
382 switch (radeon_crtc
->pll_id
) {
384 ss_cntl
= RREG32(AVIVO_P1PLL_INT_SS_CNTL
);
386 WREG32(AVIVO_P1PLL_INT_SS_CNTL
, ss_cntl
);
389 ss_cntl
= RREG32(AVIVO_P2PLL_INT_SS_CNTL
);
391 WREG32(AVIVO_P2PLL_INT_SS_CNTL
, ss_cntl
);
394 case ATOM_PPLL_INVALID
:
401 union atom_enable_ss
{
402 ENABLE_LVDS_SS_PARAMETERS lvds_ss
;
403 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2
;
404 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1
;
405 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2
;
406 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3
;
409 static void atombios_crtc_program_ss(struct drm_crtc
*crtc
,
412 struct radeon_atom_ss
*ss
)
414 struct drm_device
*dev
= crtc
->dev
;
415 struct radeon_device
*rdev
= dev
->dev_private
;
416 int index
= GetIndexIntoMasterTable(COMMAND
, EnableSpreadSpectrumOnPPLL
);
417 union atom_enable_ss args
;
419 memset(&args
, 0, sizeof(args
));
421 if (ASIC_IS_DCE5(rdev
)) {
422 args
.v3
.usSpreadSpectrumAmountFrac
= cpu_to_le16(0);
423 args
.v3
.ucSpreadSpectrumType
= ss
->type
;
426 args
.v3
.ucSpreadSpectrumType
|= ATOM_PPLL_SS_TYPE_V3_P1PLL
;
427 args
.v3
.usSpreadSpectrumAmount
= cpu_to_le16(ss
->amount
);
428 args
.v3
.usSpreadSpectrumStep
= cpu_to_le16(ss
->step
);
431 args
.v3
.ucSpreadSpectrumType
|= ATOM_PPLL_SS_TYPE_V3_P2PLL
;
432 args
.v3
.usSpreadSpectrumAmount
= cpu_to_le16(ss
->amount
);
433 args
.v3
.usSpreadSpectrumStep
= cpu_to_le16(ss
->step
);
436 args
.v3
.ucSpreadSpectrumType
|= ATOM_PPLL_SS_TYPE_V3_DCPLL
;
437 args
.v3
.usSpreadSpectrumAmount
= cpu_to_le16(0);
438 args
.v3
.usSpreadSpectrumStep
= cpu_to_le16(0);
440 case ATOM_PPLL_INVALID
:
443 args
.v2
.ucEnable
= enable
;
444 } else if (ASIC_IS_DCE4(rdev
)) {
445 args
.v2
.usSpreadSpectrumPercentage
= cpu_to_le16(ss
->percentage
);
446 args
.v2
.ucSpreadSpectrumType
= ss
->type
;
449 args
.v2
.ucSpreadSpectrumType
|= ATOM_PPLL_SS_TYPE_V2_P1PLL
;
450 args
.v2
.usSpreadSpectrumAmount
= cpu_to_le16(ss
->amount
);
451 args
.v2
.usSpreadSpectrumStep
= cpu_to_le16(ss
->step
);
454 args
.v2
.ucSpreadSpectrumType
|= ATOM_PPLL_SS_TYPE_V2_P2PLL
;
455 args
.v2
.usSpreadSpectrumAmount
= cpu_to_le16(ss
->amount
);
456 args
.v2
.usSpreadSpectrumStep
= cpu_to_le16(ss
->step
);
459 args
.v2
.ucSpreadSpectrumType
|= ATOM_PPLL_SS_TYPE_V2_DCPLL
;
460 args
.v2
.usSpreadSpectrumAmount
= cpu_to_le16(0);
461 args
.v2
.usSpreadSpectrumStep
= cpu_to_le16(0);
463 case ATOM_PPLL_INVALID
:
466 args
.v2
.ucEnable
= enable
;
467 } else if (ASIC_IS_DCE3(rdev
)) {
468 args
.v1
.usSpreadSpectrumPercentage
= cpu_to_le16(ss
->percentage
);
469 args
.v1
.ucSpreadSpectrumType
= ss
->type
;
470 args
.v1
.ucSpreadSpectrumStep
= ss
->step
;
471 args
.v1
.ucSpreadSpectrumDelay
= ss
->delay
;
472 args
.v1
.ucSpreadSpectrumRange
= ss
->range
;
473 args
.v1
.ucPpll
= pll_id
;
474 args
.v1
.ucEnable
= enable
;
475 } else if (ASIC_IS_AVIVO(rdev
)) {
476 if (enable
== ATOM_DISABLE
) {
477 atombios_disable_ss(crtc
);
480 args
.lvds_ss_2
.usSpreadSpectrumPercentage
= cpu_to_le16(ss
->percentage
);
481 args
.lvds_ss_2
.ucSpreadSpectrumType
= ss
->type
;
482 args
.lvds_ss_2
.ucSpreadSpectrumStep
= ss
->step
;
483 args
.lvds_ss_2
.ucSpreadSpectrumDelay
= ss
->delay
;
484 args
.lvds_ss_2
.ucSpreadSpectrumRange
= ss
->range
;
485 args
.lvds_ss_2
.ucEnable
= enable
;
487 if (enable
== ATOM_DISABLE
) {
488 atombios_disable_ss(crtc
);
491 args
.lvds_ss
.usSpreadSpectrumPercentage
= cpu_to_le16(ss
->percentage
);
492 args
.lvds_ss
.ucSpreadSpectrumType
= ss
->type
;
493 args
.lvds_ss
.ucSpreadSpectrumStepSize_Delay
= (ss
->step
& 3) << 2;
494 args
.lvds_ss
.ucSpreadSpectrumStepSize_Delay
|= (ss
->delay
& 7) << 4;
495 args
.lvds_ss
.ucEnable
= enable
;
497 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
500 union adjust_pixel_clock
{
501 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1
;
502 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3
;
505 static u32
atombios_adjust_pll(struct drm_crtc
*crtc
,
506 struct drm_display_mode
*mode
,
507 struct radeon_pll
*pll
,
509 struct radeon_atom_ss
*ss
)
511 struct drm_device
*dev
= crtc
->dev
;
512 struct radeon_device
*rdev
= dev
->dev_private
;
513 struct drm_encoder
*encoder
= NULL
;
514 struct radeon_encoder
*radeon_encoder
= NULL
;
515 u32 adjusted_clock
= mode
->clock
;
516 int encoder_mode
= 0;
517 u32 dp_clock
= mode
->clock
;
520 /* reset the pll flags */
523 if (ASIC_IS_AVIVO(rdev
)) {
524 if ((rdev
->family
== CHIP_RS600
) ||
525 (rdev
->family
== CHIP_RS690
) ||
526 (rdev
->family
== CHIP_RS740
))
527 pll
->flags
|= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
528 RADEON_PLL_PREFER_CLOSEST_LOWER
);
530 if (ASIC_IS_DCE32(rdev
) && mode
->clock
> 200000) /* range limits??? */
531 pll
->flags
|= RADEON_PLL_PREFER_HIGH_FB_DIV
;
533 pll
->flags
|= RADEON_PLL_PREFER_LOW_REF_DIV
;
535 pll
->flags
|= RADEON_PLL_LEGACY
;
537 if (mode
->clock
> 200000) /* range limits??? */
538 pll
->flags
|= RADEON_PLL_PREFER_HIGH_FB_DIV
;
540 pll
->flags
|= RADEON_PLL_PREFER_LOW_REF_DIV
;
543 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
544 if (encoder
->crtc
== crtc
) {
545 radeon_encoder
= to_radeon_encoder(encoder
);
546 encoder_mode
= atombios_get_encoder_mode(encoder
);
547 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
| ATOM_DEVICE_DFP_SUPPORT
)) {
548 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
550 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
551 struct radeon_connector_atom_dig
*dig_connector
=
552 radeon_connector
->con_priv
;
554 dp_clock
= dig_connector
->dp_clock
;
558 /* use recommended ref_div for ss */
559 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
560 pll
->flags
|= RADEON_PLL_PREFER_MINM_OVER_MAXP
;
563 pll
->flags
|= RADEON_PLL_USE_REF_DIV
;
564 pll
->reference_div
= ss
->refdiv
;
565 if (ASIC_IS_AVIVO(rdev
))
566 pll
->flags
|= RADEON_PLL_USE_FRAC_FB_DIV
;
571 if (ASIC_IS_AVIVO(rdev
)) {
572 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
573 if (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
)
574 adjusted_clock
= mode
->clock
* 2;
575 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
576 pll
->flags
|= RADEON_PLL_PREFER_CLOSEST_LOWER
;
577 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
578 pll
->flags
|= RADEON_PLL_IS_LCD
;
580 if (encoder
->encoder_type
!= DRM_MODE_ENCODER_DAC
)
581 pll
->flags
|= RADEON_PLL_NO_ODD_POST_DIV
;
582 if (encoder
->encoder_type
== DRM_MODE_ENCODER_LVDS
)
583 pll
->flags
|= RADEON_PLL_USE_REF_DIV
;
589 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
590 * accordingly based on the encoder/transmitter to work around
591 * special hw requirements.
593 if (ASIC_IS_DCE3(rdev
)) {
594 union adjust_pixel_clock args
;
598 index
= GetIndexIntoMasterTable(COMMAND
, AdjustDisplayPll
);
599 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
,
601 return adjusted_clock
;
603 memset(&args
, 0, sizeof(args
));
610 args
.v1
.usPixelClock
= cpu_to_le16(mode
->clock
/ 10);
611 args
.v1
.ucTransmitterID
= radeon_encoder
->encoder_id
;
612 args
.v1
.ucEncodeMode
= encoder_mode
;
615 ADJUST_DISPLAY_CONFIG_SS_ENABLE
;
617 atom_execute_table(rdev
->mode_info
.atom_context
,
618 index
, (uint32_t *)&args
);
619 adjusted_clock
= le16_to_cpu(args
.v1
.usPixelClock
) * 10;
622 args
.v3
.sInput
.usPixelClock
= cpu_to_le16(mode
->clock
/ 10);
623 args
.v3
.sInput
.ucTransmitterID
= radeon_encoder
->encoder_id
;
624 args
.v3
.sInput
.ucEncodeMode
= encoder_mode
;
625 args
.v3
.sInput
.ucDispPllConfig
= 0;
627 args
.v3
.sInput
.ucDispPllConfig
|=
628 DISPPLL_CONFIG_SS_ENABLE
;
629 if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
630 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
631 if (encoder_mode
== ATOM_ENCODER_MODE_DP
) {
632 args
.v3
.sInput
.ucDispPllConfig
|=
633 DISPPLL_CONFIG_COHERENT_MODE
;
635 args
.v3
.sInput
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
637 if (encoder_mode
== ATOM_ENCODER_MODE_HDMI
) {
638 /* deep color support */
639 args
.v3
.sInput
.usPixelClock
=
640 cpu_to_le16((mode
->clock
* bpc
/ 8) / 10);
642 if (dig
->coherent_mode
)
643 args
.v3
.sInput
.ucDispPllConfig
|=
644 DISPPLL_CONFIG_COHERENT_MODE
;
645 if (mode
->clock
> 165000)
646 args
.v3
.sInput
.ucDispPllConfig
|=
647 DISPPLL_CONFIG_DUAL_LINK
;
649 } else if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
650 if (encoder_mode
== ATOM_ENCODER_MODE_DP
) {
651 args
.v3
.sInput
.ucDispPllConfig
|=
652 DISPPLL_CONFIG_COHERENT_MODE
;
654 args
.v3
.sInput
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
655 } else if (encoder_mode
!= ATOM_ENCODER_MODE_LVDS
) {
656 if (mode
->clock
> 165000)
657 args
.v3
.sInput
.ucDispPllConfig
|=
658 DISPPLL_CONFIG_DUAL_LINK
;
661 atom_execute_table(rdev
->mode_info
.atom_context
,
662 index
, (uint32_t *)&args
);
663 adjusted_clock
= le32_to_cpu(args
.v3
.sOutput
.ulDispPllFreq
) * 10;
664 if (args
.v3
.sOutput
.ucRefDiv
) {
665 pll
->flags
|= RADEON_PLL_USE_REF_DIV
;
666 pll
->reference_div
= args
.v3
.sOutput
.ucRefDiv
;
668 if (args
.v3
.sOutput
.ucPostDiv
) {
669 pll
->flags
|= RADEON_PLL_USE_POST_DIV
;
670 pll
->post_div
= args
.v3
.sOutput
.ucPostDiv
;
674 DRM_ERROR("Unknown table version %d %d\n", frev
, crev
);
675 return adjusted_clock
;
679 DRM_ERROR("Unknown table version %d %d\n", frev
, crev
);
680 return adjusted_clock
;
683 return adjusted_clock
;
686 union set_pixel_clock
{
687 SET_PIXEL_CLOCK_PS_ALLOCATION base
;
688 PIXEL_CLOCK_PARAMETERS v1
;
689 PIXEL_CLOCK_PARAMETERS_V2 v2
;
690 PIXEL_CLOCK_PARAMETERS_V3 v3
;
691 PIXEL_CLOCK_PARAMETERS_V5 v5
;
692 PIXEL_CLOCK_PARAMETERS_V6 v6
;
695 /* on DCE5, make sure the voltage is high enough to support the
698 static void atombios_crtc_set_dcpll(struct drm_crtc
*crtc
,
701 struct drm_device
*dev
= crtc
->dev
;
702 struct radeon_device
*rdev
= dev
->dev_private
;
705 union set_pixel_clock args
;
707 memset(&args
, 0, sizeof(args
));
709 index
= GetIndexIntoMasterTable(COMMAND
, SetPixelClock
);
710 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
,
718 /* if the default dcpll clock is specified,
719 * SetPixelClock provides the dividers
721 args
.v5
.ucCRTC
= ATOM_CRTC_INVALID
;
722 args
.v5
.usPixelClock
= cpu_to_le16(dispclk
);
723 args
.v5
.ucPpll
= ATOM_DCPLL
;
726 /* if the default dcpll clock is specified,
727 * SetPixelClock provides the dividers
729 args
.v6
.ulDispEngClkFreq
= cpu_to_le32(dispclk
);
730 args
.v6
.ucPpll
= ATOM_DCPLL
;
733 DRM_ERROR("Unknown table version %d %d\n", frev
, crev
);
738 DRM_ERROR("Unknown table version %d %d\n", frev
, crev
);
741 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
744 static void atombios_crtc_program_pll(struct drm_crtc
*crtc
,
755 struct drm_device
*dev
= crtc
->dev
;
756 struct radeon_device
*rdev
= dev
->dev_private
;
758 int index
= GetIndexIntoMasterTable(COMMAND
, SetPixelClock
);
759 union set_pixel_clock args
;
761 memset(&args
, 0, sizeof(args
));
763 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
,
771 if (clock
== ATOM_DISABLE
)
773 args
.v1
.usPixelClock
= cpu_to_le16(clock
/ 10);
774 args
.v1
.usRefDiv
= cpu_to_le16(ref_div
);
775 args
.v1
.usFbDiv
= cpu_to_le16(fb_div
);
776 args
.v1
.ucFracFbDiv
= frac_fb_div
;
777 args
.v1
.ucPostDiv
= post_div
;
778 args
.v1
.ucPpll
= pll_id
;
779 args
.v1
.ucCRTC
= crtc_id
;
780 args
.v1
.ucRefDivSrc
= 1;
783 args
.v2
.usPixelClock
= cpu_to_le16(clock
/ 10);
784 args
.v2
.usRefDiv
= cpu_to_le16(ref_div
);
785 args
.v2
.usFbDiv
= cpu_to_le16(fb_div
);
786 args
.v2
.ucFracFbDiv
= frac_fb_div
;
787 args
.v2
.ucPostDiv
= post_div
;
788 args
.v2
.ucPpll
= pll_id
;
789 args
.v2
.ucCRTC
= crtc_id
;
790 args
.v2
.ucRefDivSrc
= 1;
793 args
.v3
.usPixelClock
= cpu_to_le16(clock
/ 10);
794 args
.v3
.usRefDiv
= cpu_to_le16(ref_div
);
795 args
.v3
.usFbDiv
= cpu_to_le16(fb_div
);
796 args
.v3
.ucFracFbDiv
= frac_fb_div
;
797 args
.v3
.ucPostDiv
= post_div
;
798 args
.v3
.ucPpll
= pll_id
;
799 args
.v3
.ucMiscInfo
= (pll_id
<< 2);
800 args
.v3
.ucTransmitterId
= encoder_id
;
801 args
.v3
.ucEncoderMode
= encoder_mode
;
804 args
.v5
.ucCRTC
= crtc_id
;
805 args
.v5
.usPixelClock
= cpu_to_le16(clock
/ 10);
806 args
.v5
.ucRefDiv
= ref_div
;
807 args
.v5
.usFbDiv
= cpu_to_le16(fb_div
);
808 args
.v5
.ulFbDivDecFrac
= cpu_to_le32(frac_fb_div
* 100000);
809 args
.v5
.ucPostDiv
= post_div
;
810 args
.v5
.ucMiscInfo
= 0; /* HDMI depth, etc. */
811 args
.v5
.ucTransmitterID
= encoder_id
;
812 args
.v5
.ucEncoderMode
= encoder_mode
;
813 args
.v5
.ucPpll
= pll_id
;
816 args
.v6
.ulCrtcPclkFreq
.ucCRTC
= crtc_id
;
817 args
.v6
.ulCrtcPclkFreq
.ulPixelClock
= cpu_to_le32(clock
/ 10);
818 args
.v6
.ucRefDiv
= ref_div
;
819 args
.v6
.usFbDiv
= cpu_to_le16(fb_div
);
820 args
.v6
.ulFbDivDecFrac
= cpu_to_le32(frac_fb_div
* 100000);
821 args
.v6
.ucPostDiv
= post_div
;
822 args
.v6
.ucMiscInfo
= 0; /* HDMI depth, etc. */
823 args
.v6
.ucTransmitterID
= encoder_id
;
824 args
.v6
.ucEncoderMode
= encoder_mode
;
825 args
.v6
.ucPpll
= pll_id
;
828 DRM_ERROR("Unknown table version %d %d\n", frev
, crev
);
833 DRM_ERROR("Unknown table version %d %d\n", frev
, crev
);
837 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
840 static void atombios_crtc_set_pll(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
)
842 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
843 struct drm_device
*dev
= crtc
->dev
;
844 struct radeon_device
*rdev
= dev
->dev_private
;
845 struct drm_encoder
*encoder
= NULL
;
846 struct radeon_encoder
*radeon_encoder
= NULL
;
847 u32 pll_clock
= mode
->clock
;
848 u32 ref_div
= 0, fb_div
= 0, frac_fb_div
= 0, post_div
= 0;
849 struct radeon_pll
*pll
;
851 int encoder_mode
= 0;
852 struct radeon_atom_ss ss
;
853 bool ss_enabled
= false;
855 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
856 if (encoder
->crtc
== crtc
) {
857 radeon_encoder
= to_radeon_encoder(encoder
);
858 encoder_mode
= atombios_get_encoder_mode(encoder
);
866 switch (radeon_crtc
->pll_id
) {
868 pll
= &rdev
->clock
.p1pll
;
871 pll
= &rdev
->clock
.p2pll
;
874 case ATOM_PPLL_INVALID
:
876 pll
= &rdev
->clock
.dcpll
;
880 if (radeon_encoder
->active_device
&
881 (ATOM_DEVICE_LCD_SUPPORT
| ATOM_DEVICE_DFP_SUPPORT
)) {
882 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
883 struct drm_connector
*connector
=
884 radeon_get_connector_for_encoder(encoder
);
885 struct radeon_connector
*radeon_connector
=
886 to_radeon_connector(connector
);
887 struct radeon_connector_atom_dig
*dig_connector
=
888 radeon_connector
->con_priv
;
891 switch (encoder_mode
) {
892 case ATOM_ENCODER_MODE_DP
:
894 dp_clock
= dig_connector
->dp_clock
/ 10;
895 if (radeon_encoder
->active_device
& (ATOM_DEVICE_LCD_SUPPORT
)) {
896 if (ASIC_IS_DCE4(rdev
))
898 radeon_atombios_get_asic_ss_info(rdev
, &ss
,
903 radeon_atombios_get_ppll_ss_info(rdev
, &ss
,
906 if (ASIC_IS_DCE4(rdev
))
908 radeon_atombios_get_asic_ss_info(rdev
, &ss
,
909 ASIC_INTERNAL_SS_ON_DP
,
912 if (dp_clock
== 16200) {
914 radeon_atombios_get_ppll_ss_info(rdev
, &ss
,
918 radeon_atombios_get_ppll_ss_info(rdev
, &ss
,
922 radeon_atombios_get_ppll_ss_info(rdev
, &ss
,
927 case ATOM_ENCODER_MODE_LVDS
:
928 if (ASIC_IS_DCE4(rdev
))
929 ss_enabled
= radeon_atombios_get_asic_ss_info(rdev
, &ss
,
933 ss_enabled
= radeon_atombios_get_ppll_ss_info(rdev
, &ss
,
936 case ATOM_ENCODER_MODE_DVI
:
937 if (ASIC_IS_DCE4(rdev
))
939 radeon_atombios_get_asic_ss_info(rdev
, &ss
,
940 ASIC_INTERNAL_SS_ON_TMDS
,
943 case ATOM_ENCODER_MODE_HDMI
:
944 if (ASIC_IS_DCE4(rdev
))
946 radeon_atombios_get_asic_ss_info(rdev
, &ss
,
947 ASIC_INTERNAL_SS_ON_HDMI
,
955 /* adjust pixel clock as needed */
956 adjusted_clock
= atombios_adjust_pll(crtc
, mode
, pll
, ss_enabled
, &ss
);
958 if (ASIC_IS_AVIVO(rdev
))
959 radeon_compute_pll_avivo(pll
, adjusted_clock
, &pll_clock
, &fb_div
, &frac_fb_div
,
960 &ref_div
, &post_div
);
962 radeon_compute_pll_legacy(pll
, adjusted_clock
, &pll_clock
, &fb_div
, &frac_fb_div
,
963 &ref_div
, &post_div
);
965 atombios_crtc_program_ss(crtc
, ATOM_DISABLE
, radeon_crtc
->pll_id
, &ss
);
967 atombios_crtc_program_pll(crtc
, radeon_crtc
->crtc_id
, radeon_crtc
->pll_id
,
968 encoder_mode
, radeon_encoder
->encoder_id
, mode
->clock
,
969 ref_div
, fb_div
, frac_fb_div
, post_div
);
972 /* calculate ss amount and step size */
973 if (ASIC_IS_DCE4(rdev
)) {
975 u32 amount
= (((fb_div
* 10) + frac_fb_div
) * ss
.percentage
) / 10000;
976 ss
.amount
= (amount
/ 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK
;
977 ss
.amount
|= ((amount
- (ss
.amount
* 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT
) &
978 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK
;
979 if (ss
.type
& ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD
)
980 step_size
= (4 * amount
* ref_div
* (ss
.rate
* 2048)) /
981 (125 * 25 * pll
->reference_freq
/ 100);
983 step_size
= (2 * amount
* ref_div
* (ss
.rate
* 2048)) /
984 (125 * 25 * pll
->reference_freq
/ 100);
988 atombios_crtc_program_ss(crtc
, ATOM_ENABLE
, radeon_crtc
->pll_id
, &ss
);
992 static int dce4_crtc_do_set_base(struct drm_crtc
*crtc
,
993 struct drm_framebuffer
*fb
,
994 int x
, int y
, int atomic
)
996 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
997 struct drm_device
*dev
= crtc
->dev
;
998 struct radeon_device
*rdev
= dev
->dev_private
;
999 struct radeon_framebuffer
*radeon_fb
;
1000 struct drm_framebuffer
*target_fb
;
1001 struct drm_gem_object
*obj
;
1002 struct radeon_bo
*rbo
;
1003 uint64_t fb_location
;
1004 uint32_t fb_format
, fb_pitch_pixels
, tiling_flags
;
1005 u32 fb_swap
= EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE
);
1009 if (!atomic
&& !crtc
->fb
) {
1010 DRM_DEBUG_KMS("No FB bound\n");
1015 radeon_fb
= to_radeon_framebuffer(fb
);
1019 radeon_fb
= to_radeon_framebuffer(crtc
->fb
);
1020 target_fb
= crtc
->fb
;
1023 /* If atomic, assume fb object is pinned & idle & fenced and
1024 * just update base pointers
1026 obj
= radeon_fb
->obj
;
1027 rbo
= obj
->driver_private
;
1028 r
= radeon_bo_reserve(rbo
, false);
1029 if (unlikely(r
!= 0))
1033 fb_location
= radeon_bo_gpu_offset(rbo
);
1035 r
= radeon_bo_pin(rbo
, RADEON_GEM_DOMAIN_VRAM
, &fb_location
);
1036 if (unlikely(r
!= 0)) {
1037 radeon_bo_unreserve(rbo
);
1042 radeon_bo_get_tiling_flags(rbo
, &tiling_flags
, NULL
);
1043 radeon_bo_unreserve(rbo
);
1045 switch (target_fb
->bits_per_pixel
) {
1047 fb_format
= (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP
) |
1048 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED
));
1051 fb_format
= (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP
) |
1052 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555
));
1055 fb_format
= (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP
) |
1056 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565
));
1058 fb_swap
= EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16
);
1063 fb_format
= (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP
) |
1064 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888
));
1066 fb_swap
= EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32
);
1070 DRM_ERROR("Unsupported screen depth %d\n",
1071 target_fb
->bits_per_pixel
);
1075 if (tiling_flags
& RADEON_TILING_MACRO
)
1076 fb_format
|= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1
);
1077 else if (tiling_flags
& RADEON_TILING_MICRO
)
1078 fb_format
|= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1
);
1080 switch (radeon_crtc
->crtc_id
) {
1082 WREG32(AVIVO_D1VGA_CONTROL
, 0);
1085 WREG32(AVIVO_D2VGA_CONTROL
, 0);
1088 WREG32(EVERGREEN_D3VGA_CONTROL
, 0);
1091 WREG32(EVERGREEN_D4VGA_CONTROL
, 0);
1094 WREG32(EVERGREEN_D5VGA_CONTROL
, 0);
1097 WREG32(EVERGREEN_D6VGA_CONTROL
, 0);
1103 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ radeon_crtc
->crtc_offset
,
1104 upper_32_bits(fb_location
));
1105 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ radeon_crtc
->crtc_offset
,
1106 upper_32_bits(fb_location
));
1107 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ radeon_crtc
->crtc_offset
,
1108 (u32
)fb_location
& EVERGREEN_GRPH_SURFACE_ADDRESS_MASK
);
1109 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ radeon_crtc
->crtc_offset
,
1110 (u32
) fb_location
& EVERGREEN_GRPH_SURFACE_ADDRESS_MASK
);
1111 WREG32(EVERGREEN_GRPH_CONTROL
+ radeon_crtc
->crtc_offset
, fb_format
);
1112 WREG32(EVERGREEN_GRPH_SWAP_CONTROL
+ radeon_crtc
->crtc_offset
, fb_swap
);
1114 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X
+ radeon_crtc
->crtc_offset
, 0);
1115 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y
+ radeon_crtc
->crtc_offset
, 0);
1116 WREG32(EVERGREEN_GRPH_X_START
+ radeon_crtc
->crtc_offset
, 0);
1117 WREG32(EVERGREEN_GRPH_Y_START
+ radeon_crtc
->crtc_offset
, 0);
1118 WREG32(EVERGREEN_GRPH_X_END
+ radeon_crtc
->crtc_offset
, target_fb
->width
);
1119 WREG32(EVERGREEN_GRPH_Y_END
+ radeon_crtc
->crtc_offset
, target_fb
->height
);
1121 fb_pitch_pixels
= target_fb
->pitch
/ (target_fb
->bits_per_pixel
/ 8);
1122 WREG32(EVERGREEN_GRPH_PITCH
+ radeon_crtc
->crtc_offset
, fb_pitch_pixels
);
1123 WREG32(EVERGREEN_GRPH_ENABLE
+ radeon_crtc
->crtc_offset
, 1);
1125 WREG32(EVERGREEN_DESKTOP_HEIGHT
+ radeon_crtc
->crtc_offset
,
1126 crtc
->mode
.vdisplay
);
1129 WREG32(EVERGREEN_VIEWPORT_START
+ radeon_crtc
->crtc_offset
,
1131 WREG32(EVERGREEN_VIEWPORT_SIZE
+ radeon_crtc
->crtc_offset
,
1132 (crtc
->mode
.hdisplay
<< 16) | crtc
->mode
.vdisplay
);
1134 if (!atomic
&& fb
&& fb
!= crtc
->fb
) {
1135 radeon_fb
= to_radeon_framebuffer(fb
);
1136 rbo
= radeon_fb
->obj
->driver_private
;
1137 r
= radeon_bo_reserve(rbo
, false);
1138 if (unlikely(r
!= 0))
1140 radeon_bo_unpin(rbo
);
1141 radeon_bo_unreserve(rbo
);
1144 /* Bytes per pixel may have changed */
1145 radeon_bandwidth_update(rdev
);
1150 static int avivo_crtc_do_set_base(struct drm_crtc
*crtc
,
1151 struct drm_framebuffer
*fb
,
1152 int x
, int y
, int atomic
)
1154 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
1155 struct drm_device
*dev
= crtc
->dev
;
1156 struct radeon_device
*rdev
= dev
->dev_private
;
1157 struct radeon_framebuffer
*radeon_fb
;
1158 struct drm_gem_object
*obj
;
1159 struct radeon_bo
*rbo
;
1160 struct drm_framebuffer
*target_fb
;
1161 uint64_t fb_location
;
1162 uint32_t fb_format
, fb_pitch_pixels
, tiling_flags
;
1163 u32 fb_swap
= R600_D1GRPH_SWAP_ENDIAN_NONE
;
1167 if (!atomic
&& !crtc
->fb
) {
1168 DRM_DEBUG_KMS("No FB bound\n");
1173 radeon_fb
= to_radeon_framebuffer(fb
);
1177 radeon_fb
= to_radeon_framebuffer(crtc
->fb
);
1178 target_fb
= crtc
->fb
;
1181 obj
= radeon_fb
->obj
;
1182 rbo
= obj
->driver_private
;
1183 r
= radeon_bo_reserve(rbo
, false);
1184 if (unlikely(r
!= 0))
1187 /* If atomic, assume fb object is pinned & idle & fenced and
1188 * just update base pointers
1191 fb_location
= radeon_bo_gpu_offset(rbo
);
1193 r
= radeon_bo_pin(rbo
, RADEON_GEM_DOMAIN_VRAM
, &fb_location
);
1194 if (unlikely(r
!= 0)) {
1195 radeon_bo_unreserve(rbo
);
1199 radeon_bo_get_tiling_flags(rbo
, &tiling_flags
, NULL
);
1200 radeon_bo_unreserve(rbo
);
1202 switch (target_fb
->bits_per_pixel
) {
1205 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP
|
1206 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED
;
1210 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP
|
1211 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555
;
1215 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP
|
1216 AVIVO_D1GRPH_CONTROL_16BPP_RGB565
;
1218 fb_swap
= R600_D1GRPH_SWAP_ENDIAN_16BIT
;
1224 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP
|
1225 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888
;
1227 fb_swap
= R600_D1GRPH_SWAP_ENDIAN_32BIT
;
1231 DRM_ERROR("Unsupported screen depth %d\n",
1232 target_fb
->bits_per_pixel
);
1236 if (rdev
->family
>= CHIP_R600
) {
1237 if (tiling_flags
& RADEON_TILING_MACRO
)
1238 fb_format
|= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1
;
1239 else if (tiling_flags
& RADEON_TILING_MICRO
)
1240 fb_format
|= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1
;
1242 if (tiling_flags
& RADEON_TILING_MACRO
)
1243 fb_format
|= AVIVO_D1GRPH_MACRO_ADDRESS_MODE
;
1245 if (tiling_flags
& RADEON_TILING_MICRO
)
1246 fb_format
|= AVIVO_D1GRPH_TILED
;
1249 if (radeon_crtc
->crtc_id
== 0)
1250 WREG32(AVIVO_D1VGA_CONTROL
, 0);
1252 WREG32(AVIVO_D2VGA_CONTROL
, 0);
1254 if (rdev
->family
>= CHIP_RV770
) {
1255 if (radeon_crtc
->crtc_id
) {
1256 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
, upper_32_bits(fb_location
));
1257 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
, upper_32_bits(fb_location
));
1259 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
, upper_32_bits(fb_location
));
1260 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
, upper_32_bits(fb_location
));
1263 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS
+ radeon_crtc
->crtc_offset
,
1265 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS
+
1266 radeon_crtc
->crtc_offset
, (u32
) fb_location
);
1267 WREG32(AVIVO_D1GRPH_CONTROL
+ radeon_crtc
->crtc_offset
, fb_format
);
1268 if (rdev
->family
>= CHIP_R600
)
1269 WREG32(R600_D1GRPH_SWAP_CONTROL
+ radeon_crtc
->crtc_offset
, fb_swap
);
1271 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X
+ radeon_crtc
->crtc_offset
, 0);
1272 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y
+ radeon_crtc
->crtc_offset
, 0);
1273 WREG32(AVIVO_D1GRPH_X_START
+ radeon_crtc
->crtc_offset
, 0);
1274 WREG32(AVIVO_D1GRPH_Y_START
+ radeon_crtc
->crtc_offset
, 0);
1275 WREG32(AVIVO_D1GRPH_X_END
+ radeon_crtc
->crtc_offset
, target_fb
->width
);
1276 WREG32(AVIVO_D1GRPH_Y_END
+ radeon_crtc
->crtc_offset
, target_fb
->height
);
1278 fb_pitch_pixels
= target_fb
->pitch
/ (target_fb
->bits_per_pixel
/ 8);
1279 WREG32(AVIVO_D1GRPH_PITCH
+ radeon_crtc
->crtc_offset
, fb_pitch_pixels
);
1280 WREG32(AVIVO_D1GRPH_ENABLE
+ radeon_crtc
->crtc_offset
, 1);
1282 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT
+ radeon_crtc
->crtc_offset
,
1283 crtc
->mode
.vdisplay
);
1286 WREG32(AVIVO_D1MODE_VIEWPORT_START
+ radeon_crtc
->crtc_offset
,
1288 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE
+ radeon_crtc
->crtc_offset
,
1289 (crtc
->mode
.hdisplay
<< 16) | crtc
->mode
.vdisplay
);
1291 if (!atomic
&& fb
&& fb
!= crtc
->fb
) {
1292 radeon_fb
= to_radeon_framebuffer(fb
);
1293 rbo
= radeon_fb
->obj
->driver_private
;
1294 r
= radeon_bo_reserve(rbo
, false);
1295 if (unlikely(r
!= 0))
1297 radeon_bo_unpin(rbo
);
1298 radeon_bo_unreserve(rbo
);
1301 /* Bytes per pixel may have changed */
1302 radeon_bandwidth_update(rdev
);
1307 int atombios_crtc_set_base(struct drm_crtc
*crtc
, int x
, int y
,
1308 struct drm_framebuffer
*old_fb
)
1310 struct drm_device
*dev
= crtc
->dev
;
1311 struct radeon_device
*rdev
= dev
->dev_private
;
1313 if (ASIC_IS_DCE4(rdev
))
1314 return dce4_crtc_do_set_base(crtc
, old_fb
, x
, y
, 0);
1315 else if (ASIC_IS_AVIVO(rdev
))
1316 return avivo_crtc_do_set_base(crtc
, old_fb
, x
, y
, 0);
1318 return radeon_crtc_do_set_base(crtc
, old_fb
, x
, y
, 0);
1321 int atombios_crtc_set_base_atomic(struct drm_crtc
*crtc
,
1322 struct drm_framebuffer
*fb
,
1323 int x
, int y
, enum mode_set_atomic state
)
1325 struct drm_device
*dev
= crtc
->dev
;
1326 struct radeon_device
*rdev
= dev
->dev_private
;
1328 if (ASIC_IS_DCE4(rdev
))
1329 return dce4_crtc_do_set_base(crtc
, fb
, x
, y
, 1);
1330 else if (ASIC_IS_AVIVO(rdev
))
1331 return avivo_crtc_do_set_base(crtc
, fb
, x
, y
, 1);
1333 return radeon_crtc_do_set_base(crtc
, fb
, x
, y
, 1);
1336 /* properly set additional regs when using atombios */
1337 static void radeon_legacy_atom_fixup(struct drm_crtc
*crtc
)
1339 struct drm_device
*dev
= crtc
->dev
;
1340 struct radeon_device
*rdev
= dev
->dev_private
;
1341 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
1342 u32 disp_merge_cntl
;
1344 switch (radeon_crtc
->crtc_id
) {
1346 disp_merge_cntl
= RREG32(RADEON_DISP_MERGE_CNTL
);
1347 disp_merge_cntl
&= ~RADEON_DISP_RGB_OFFSET_EN
;
1348 WREG32(RADEON_DISP_MERGE_CNTL
, disp_merge_cntl
);
1351 disp_merge_cntl
= RREG32(RADEON_DISP2_MERGE_CNTL
);
1352 disp_merge_cntl
&= ~RADEON_DISP2_RGB_OFFSET_EN
;
1353 WREG32(RADEON_DISP2_MERGE_CNTL
, disp_merge_cntl
);
1354 WREG32(RADEON_FP_H2_SYNC_STRT_WID
, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID
));
1355 WREG32(RADEON_FP_V2_SYNC_STRT_WID
, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID
));
1360 static int radeon_atom_pick_pll(struct drm_crtc
*crtc
)
1362 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
1363 struct drm_device
*dev
= crtc
->dev
;
1364 struct radeon_device
*rdev
= dev
->dev_private
;
1365 struct drm_encoder
*test_encoder
;
1366 struct drm_crtc
*test_crtc
;
1367 uint32_t pll_in_use
= 0;
1369 if (ASIC_IS_DCE4(rdev
)) {
1370 /* if crtc is driving DP and we have an ext clock, use that */
1371 list_for_each_entry(test_encoder
, &dev
->mode_config
.encoder_list
, head
) {
1372 if (test_encoder
->crtc
&& (test_encoder
->crtc
== crtc
)) {
1373 if (atombios_get_encoder_mode(test_encoder
) == ATOM_ENCODER_MODE_DP
) {
1374 if (rdev
->clock
.dp_extclk
)
1375 return ATOM_PPLL_INVALID
;
1380 /* otherwise, pick one of the plls */
1381 list_for_each_entry(test_crtc
, &dev
->mode_config
.crtc_list
, head
) {
1382 struct radeon_crtc
*radeon_test_crtc
;
1384 if (crtc
== test_crtc
)
1387 radeon_test_crtc
= to_radeon_crtc(test_crtc
);
1388 if ((radeon_test_crtc
->pll_id
>= ATOM_PPLL1
) &&
1389 (radeon_test_crtc
->pll_id
<= ATOM_PPLL2
))
1390 pll_in_use
|= (1 << radeon_test_crtc
->pll_id
);
1392 if (!(pll_in_use
& 1))
1396 return radeon_crtc
->crtc_id
;
1400 int atombios_crtc_mode_set(struct drm_crtc
*crtc
,
1401 struct drm_display_mode
*mode
,
1402 struct drm_display_mode
*adjusted_mode
,
1403 int x
, int y
, struct drm_framebuffer
*old_fb
)
1405 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
1406 struct drm_device
*dev
= crtc
->dev
;
1407 struct radeon_device
*rdev
= dev
->dev_private
;
1408 struct drm_encoder
*encoder
;
1409 bool is_tvcv
= false;
1411 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
1413 if (encoder
->crtc
== crtc
) {
1414 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1415 if (radeon_encoder
->active_device
&
1416 (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
))
1421 /* always set DCPLL */
1422 if (ASIC_IS_DCE4(rdev
)) {
1423 struct radeon_atom_ss ss
;
1424 bool ss_enabled
= radeon_atombios_get_asic_ss_info(rdev
, &ss
,
1425 ASIC_INTERNAL_SS_ON_DCPLL
,
1426 rdev
->clock
.default_dispclk
);
1428 atombios_crtc_program_ss(crtc
, ATOM_DISABLE
, ATOM_DCPLL
, &ss
);
1429 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1430 atombios_crtc_set_dcpll(crtc
, rdev
->clock
.default_dispclk
);
1432 atombios_crtc_program_ss(crtc
, ATOM_ENABLE
, ATOM_DCPLL
, &ss
);
1434 atombios_crtc_set_pll(crtc
, adjusted_mode
);
1436 if (ASIC_IS_DCE4(rdev
))
1437 atombios_set_crtc_dtd_timing(crtc
, adjusted_mode
);
1438 else if (ASIC_IS_AVIVO(rdev
)) {
1440 atombios_crtc_set_timing(crtc
, adjusted_mode
);
1442 atombios_set_crtc_dtd_timing(crtc
, adjusted_mode
);
1444 atombios_crtc_set_timing(crtc
, adjusted_mode
);
1445 if (radeon_crtc
->crtc_id
== 0)
1446 atombios_set_crtc_dtd_timing(crtc
, adjusted_mode
);
1447 radeon_legacy_atom_fixup(crtc
);
1449 atombios_crtc_set_base(crtc
, x
, y
, old_fb
);
1450 atombios_overscan_setup(crtc
, mode
, adjusted_mode
);
1451 atombios_scaler_setup(crtc
);
1455 static bool atombios_crtc_mode_fixup(struct drm_crtc
*crtc
,
1456 struct drm_display_mode
*mode
,
1457 struct drm_display_mode
*adjusted_mode
)
1459 struct drm_device
*dev
= crtc
->dev
;
1460 struct radeon_device
*rdev
= dev
->dev_private
;
1462 /* adjust pm to upcoming mode change */
1463 radeon_pm_compute_clocks(rdev
);
1465 if (!radeon_crtc_scaling_mode_fixup(crtc
, mode
, adjusted_mode
))
1470 static void atombios_crtc_prepare(struct drm_crtc
*crtc
)
1472 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
1475 radeon_crtc
->pll_id
= radeon_atom_pick_pll(crtc
);
1477 atombios_lock_crtc(crtc
, ATOM_ENABLE
);
1478 atombios_crtc_dpms(crtc
, DRM_MODE_DPMS_OFF
);
1481 static void atombios_crtc_commit(struct drm_crtc
*crtc
)
1483 atombios_crtc_dpms(crtc
, DRM_MODE_DPMS_ON
);
1484 atombios_lock_crtc(crtc
, ATOM_DISABLE
);
1487 static void atombios_crtc_disable(struct drm_crtc
*crtc
)
1489 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
1490 atombios_crtc_dpms(crtc
, DRM_MODE_DPMS_OFF
);
1492 switch (radeon_crtc
->pll_id
) {
1495 /* disable the ppll */
1496 atombios_crtc_program_pll(crtc
, radeon_crtc
->crtc_id
, radeon_crtc
->pll_id
,
1497 0, 0, ATOM_DISABLE
, 0, 0, 0, 0);
1502 radeon_crtc
->pll_id
= -1;
1505 static const struct drm_crtc_helper_funcs atombios_helper_funcs
= {
1506 .dpms
= atombios_crtc_dpms
,
1507 .mode_fixup
= atombios_crtc_mode_fixup
,
1508 .mode_set
= atombios_crtc_mode_set
,
1509 .mode_set_base
= atombios_crtc_set_base
,
1510 .mode_set_base_atomic
= atombios_crtc_set_base_atomic
,
1511 .prepare
= atombios_crtc_prepare
,
1512 .commit
= atombios_crtc_commit
,
1513 .load_lut
= radeon_crtc_load_lut
,
1514 .disable
= atombios_crtc_disable
,
1517 void radeon_atombios_init_crtc(struct drm_device
*dev
,
1518 struct radeon_crtc
*radeon_crtc
)
1520 struct radeon_device
*rdev
= dev
->dev_private
;
1522 if (ASIC_IS_DCE4(rdev
)) {
1523 switch (radeon_crtc
->crtc_id
) {
1526 radeon_crtc
->crtc_offset
= EVERGREEN_CRTC0_REGISTER_OFFSET
;
1529 radeon_crtc
->crtc_offset
= EVERGREEN_CRTC1_REGISTER_OFFSET
;
1532 radeon_crtc
->crtc_offset
= EVERGREEN_CRTC2_REGISTER_OFFSET
;
1535 radeon_crtc
->crtc_offset
= EVERGREEN_CRTC3_REGISTER_OFFSET
;
1538 radeon_crtc
->crtc_offset
= EVERGREEN_CRTC4_REGISTER_OFFSET
;
1541 radeon_crtc
->crtc_offset
= EVERGREEN_CRTC5_REGISTER_OFFSET
;
1545 if (radeon_crtc
->crtc_id
== 1)
1546 radeon_crtc
->crtc_offset
=
1547 AVIVO_D2CRTC_H_TOTAL
- AVIVO_D1CRTC_H_TOTAL
;
1549 radeon_crtc
->crtc_offset
= 0;
1551 radeon_crtc
->pll_id
= -1;
1552 drm_crtc_helper_add(&radeon_crtc
->base
, &atombios_helper_funcs
);