projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/i915: Fix for ringbuf space wait in LRC mode
[deliverable/linux.git] / drivers / gpu / drm / radeon / atombios_crtc.c
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include <drm/drm_fixed.h>
30 #include "radeon.h"
31 #include "atom.h"
32 #include "atom-bits.h"
33
34 static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
37 {
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
43 int a1, a2;
44
45 memset(&args, 0, sizeof(args));
46
47 args.ucCRTC = radeon_crtc->crtc_id;
48
49 switch (radeon_crtc->rmx_type) {
50 case RMX_CENTER:
51 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
52 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
53 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
54 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
55 break;
56 case RMX_ASPECT:
57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
59
60 if (a1 > a2) {
61 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
62 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
63 } else if (a2 > a1) {
64 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
65 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
66 }
67 break;
68 case RMX_FULL:
69 default:
70 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
71 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
72 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
73 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
74 break;
75 }
76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
77 }
78
79 static void atombios_scaler_setup(struct drm_crtc *crtc)
80 {
81 struct drm_device *dev = crtc->dev;
82 struct radeon_device *rdev = dev->dev_private;
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
84 ENABLE_SCALER_PS_ALLOCATION args;
85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
86 struct radeon_encoder *radeon_encoder =
87 to_radeon_encoder(radeon_crtc->encoder);
88 /* fixme - fill in enc_priv for atom dac */
89 enum radeon_tv_std tv_std = TV_STD_NTSC;
90 bool is_tv = false, is_cv = false;
91
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
93 return;
94
95 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
96 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
97 tv_std = tv_dac->tv_std;
98 is_tv = true;
99 }
100
101 memset(&args, 0, sizeof(args));
102
103 args.ucScaler = radeon_crtc->crtc_id;
104
105 if (is_tv) {
106 switch (tv_std) {
107 case TV_STD_NTSC:
108 default:
109 args.ucTVStandard = ATOM_TV_NTSC;
110 break;
111 case TV_STD_PAL:
112 args.ucTVStandard = ATOM_TV_PAL;
113 break;
114 case TV_STD_PAL_M:
115 args.ucTVStandard = ATOM_TV_PALM;
116 break;
117 case TV_STD_PAL_60:
118 args.ucTVStandard = ATOM_TV_PAL60;
119 break;
120 case TV_STD_NTSC_J:
121 args.ucTVStandard = ATOM_TV_NTSCJ;
122 break;
123 case TV_STD_SCART_PAL:
124 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
125 break;
126 case TV_STD_SECAM:
127 args.ucTVStandard = ATOM_TV_SECAM;
128 break;
129 case TV_STD_PAL_CN:
130 args.ucTVStandard = ATOM_TV_PALCN;
131 break;
132 }
133 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
134 } else if (is_cv) {
135 args.ucTVStandard = ATOM_TV_CV;
136 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
137 } else {
138 switch (radeon_crtc->rmx_type) {
139 case RMX_FULL:
140 args.ucEnable = ATOM_SCALER_EXPANSION;
141 break;
142 case RMX_CENTER:
143 args.ucEnable = ATOM_SCALER_CENTER;
144 break;
145 case RMX_ASPECT:
146 args.ucEnable = ATOM_SCALER_EXPANSION;
147 break;
148 default:
149 if (ASIC_IS_AVIVO(rdev))
150 args.ucEnable = ATOM_SCALER_DISABLE;
151 else
152 args.ucEnable = ATOM_SCALER_CENTER;
153 break;
154 }
155 }
156 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
157 if ((is_tv || is_cv)
158 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
159 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
160 }
161 }
162
163 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
164 {
165 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
166 struct drm_device *dev = crtc->dev;
167 struct radeon_device *rdev = dev->dev_private;
168 int index =
169 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
170 ENABLE_CRTC_PS_ALLOCATION args;
171
172 memset(&args, 0, sizeof(args));
173
174 args.ucCRTC = radeon_crtc->crtc_id;
175 args.ucEnable = lock;
176
177 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
178 }
179
180 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
181 {
182 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
183 struct drm_device *dev = crtc->dev;
184 struct radeon_device *rdev = dev->dev_private;
185 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
186 ENABLE_CRTC_PS_ALLOCATION args;
187
188 memset(&args, 0, sizeof(args));
189
190 args.ucCRTC = radeon_crtc->crtc_id;
191 args.ucEnable = state;
192
193 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
194 }
195
196 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
197 {
198 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
199 struct drm_device *dev = crtc->dev;
200 struct radeon_device *rdev = dev->dev_private;
201 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
202 ENABLE_CRTC_PS_ALLOCATION args;
203
204 memset(&args, 0, sizeof(args));
205
206 args.ucCRTC = radeon_crtc->crtc_id;
207 args.ucEnable = state;
208
209 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
210 }
211
212 static const u32 vga_control_regs[6] =
213 {
214 AVIVO_D1VGA_CONTROL,
215 AVIVO_D2VGA_CONTROL,
216 EVERGREEN_D3VGA_CONTROL,
217 EVERGREEN_D4VGA_CONTROL,
218 EVERGREEN_D5VGA_CONTROL,
219 EVERGREEN_D6VGA_CONTROL,
220 };
221
222 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
223 {
224 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
225 struct drm_device *dev = crtc->dev;
226 struct radeon_device *rdev = dev->dev_private;
227 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
228 BLANK_CRTC_PS_ALLOCATION args;
229 u32 vga_control = 0;
230
231 memset(&args, 0, sizeof(args));
232
233 if (ASIC_IS_DCE8(rdev)) {
234 vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);
235 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);
236 }
237
238 args.ucCRTC = radeon_crtc->crtc_id;
239 args.ucBlanking = state;
240
241 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
242
243 if (ASIC_IS_DCE8(rdev)) {
244 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);
245 }
246 }
247
248 static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
249 {
250 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
251 struct drm_device *dev = crtc->dev;
252 struct radeon_device *rdev = dev->dev_private;
253 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
254 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
255
256 memset(&args, 0, sizeof(args));
257
258 args.ucDispPipeId = radeon_crtc->crtc_id;
259 args.ucEnable = state;
260
261 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
262 }
263
264 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
265 {
266 struct drm_device *dev = crtc->dev;
267 struct radeon_device *rdev = dev->dev_private;
268 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
269
270 switch (mode) {
271 case DRM_MODE_DPMS_ON:
272 radeon_crtc->enabled = true;
273 atombios_enable_crtc(crtc, ATOM_ENABLE);
274 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
275 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
276 atombios_blank_crtc(crtc, ATOM_DISABLE);
277 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
278 radeon_crtc_load_lut(crtc);
279 break;
280 case DRM_MODE_DPMS_STANDBY:
281 case DRM_MODE_DPMS_SUSPEND:
282 case DRM_MODE_DPMS_OFF:
283 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
284 if (radeon_crtc->enabled)
285 atombios_blank_crtc(crtc, ATOM_ENABLE);
286 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
287 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
288 atombios_enable_crtc(crtc, ATOM_DISABLE);
289 radeon_crtc->enabled = false;
290 break;
291 }
292 /* adjust pm to dpms */
293 radeon_pm_compute_clocks(rdev);
294 }
295
296 static void
297 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
298 struct drm_display_mode *mode)
299 {
300 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
301 struct drm_device *dev = crtc->dev;
302 struct radeon_device *rdev = dev->dev_private;
303 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
304 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
305 u16 misc = 0;
306
307 memset(&args, 0, sizeof(args));
308 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
309 args.usH_Blanking_Time =
310 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
311 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
312 args.usV_Blanking_Time =
313 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
314 args.usH_SyncOffset =
315 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
316 args.usH_SyncWidth =
317 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
318 args.usV_SyncOffset =
319 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
320 args.usV_SyncWidth =
321 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
322 args.ucH_Border = radeon_crtc->h_border;
323 args.ucV_Border = radeon_crtc->v_border;
324
325 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
326 misc |= ATOM_VSYNC_POLARITY;
327 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
328 misc |= ATOM_HSYNC_POLARITY;
329 if (mode->flags & DRM_MODE_FLAG_CSYNC)
330 misc |= ATOM_COMPOSITESYNC;
331 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
332 misc |= ATOM_INTERLACE;
333 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
334 misc |= ATOM_DOUBLE_CLOCK_MODE;
335
336 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
337 args.ucCRTC = radeon_crtc->crtc_id;
338
339 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
340 }
341
342 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
343 struct drm_display_mode *mode)
344 {
345 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
346 struct drm_device *dev = crtc->dev;
347 struct radeon_device *rdev = dev->dev_private;
348 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
349 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
350 u16 misc = 0;
351
352 memset(&args, 0, sizeof(args));
353 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
354 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
355 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
356 args.usH_SyncWidth =
357 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
358 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
359 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
360 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
361 args.usV_SyncWidth =
362 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
363
364 args.ucOverscanRight = radeon_crtc->h_border;
365 args.ucOverscanLeft = radeon_crtc->h_border;
366 args.ucOverscanBottom = radeon_crtc->v_border;
367 args.ucOverscanTop = radeon_crtc->v_border;
368
369 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
370 misc |= ATOM_VSYNC_POLARITY;
371 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
372 misc |= ATOM_HSYNC_POLARITY;
373 if (mode->flags & DRM_MODE_FLAG_CSYNC)
374 misc |= ATOM_COMPOSITESYNC;
375 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
376 misc |= ATOM_INTERLACE;
377 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
378 misc |= ATOM_DOUBLE_CLOCK_MODE;
379
380 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
381 args.ucCRTC = radeon_crtc->crtc_id;
382
383 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
384 }
385
386 static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
387 {
388 u32 ss_cntl;
389
390 if (ASIC_IS_DCE4(rdev)) {
391 switch (pll_id) {
392 case ATOM_PPLL1:
393 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
394 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
395 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
396 break;
397 case ATOM_PPLL2:
398 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
399 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
400 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
401 break;
402 case ATOM_DCPLL:
403 case ATOM_PPLL_INVALID:
404 return;
405 }
406 } else if (ASIC_IS_AVIVO(rdev)) {
407 switch (pll_id) {
408 case ATOM_PPLL1:
409 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
410 ss_cntl &= ~1;
411 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
412 break;
413 case ATOM_PPLL2:
414 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
415 ss_cntl &= ~1;
416 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
417 break;
418 case ATOM_DCPLL:
419 case ATOM_PPLL_INVALID:
420 return;
421 }
422 }
423 }
424
425
426 union atom_enable_ss {
427 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
428 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
429 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
430 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
431 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
432 };
433
434 static void atombios_crtc_program_ss(struct radeon_device *rdev,
435 int enable,
436 int pll_id,
437 int crtc_id,
438 struct radeon_atom_ss *ss)
439 {
440 unsigned i;
441 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
442 union atom_enable_ss args;
443
444 if (enable) {
445 /* Don't mess with SS if percentage is 0 or external ss.
446 * SS is already disabled previously, and disabling it
447 * again can cause display problems if the pll is already
448 * programmed.
449 */
450 if (ss->percentage == 0)
451 return;
452 if (ss->type & ATOM_EXTERNAL_SS_MASK)
453 return;
454 } else {
455 for (i = 0; i < rdev->num_crtc; i++) {
456 if (rdev->mode_info.crtcs[i] &&
457 rdev->mode_info.crtcs[i]->enabled &&
458 i != crtc_id &&
459 pll_id == rdev->mode_info.crtcs[i]->pll_id) {
460 /* one other crtc is using this pll don't turn
461 * off spread spectrum as it might turn off
462 * display on active crtc
463 */
464 return;
465 }
466 }
467 }
468
469 memset(&args, 0, sizeof(args));
470
471 if (ASIC_IS_DCE5(rdev)) {
472 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
473 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
474 switch (pll_id) {
475 case ATOM_PPLL1:
476 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
477 break;
478 case ATOM_PPLL2:
479 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
480 break;
481 case ATOM_DCPLL:
482 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
483 break;
484 case ATOM_PPLL_INVALID:
485 return;
486 }
487 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
488 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
489 args.v3.ucEnable = enable;
490 } else if (ASIC_IS_DCE4(rdev)) {
491 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
492 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
493 switch (pll_id) {
494 case ATOM_PPLL1:
495 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
496 break;
497 case ATOM_PPLL2:
498 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
499 break;
500 case ATOM_DCPLL:
501 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
502 break;
503 case ATOM_PPLL_INVALID:
504 return;
505 }
506 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
507 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
508 args.v2.ucEnable = enable;
509 } else if (ASIC_IS_DCE3(rdev)) {
510 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
511 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
512 args.v1.ucSpreadSpectrumStep = ss->step;
513 args.v1.ucSpreadSpectrumDelay = ss->delay;
514 args.v1.ucSpreadSpectrumRange = ss->range;
515 args.v1.ucPpll = pll_id;
516 args.v1.ucEnable = enable;
517 } else if (ASIC_IS_AVIVO(rdev)) {
518 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
519 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
520 atombios_disable_ss(rdev, pll_id);
521 return;
522 }
523 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
524 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
525 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
526 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
527 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
528 args.lvds_ss_2.ucEnable = enable;
529 } else {
530 if (enable == ATOM_DISABLE) {
531 atombios_disable_ss(rdev, pll_id);
532 return;
533 }
534 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
535 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
536 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
537 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
538 args.lvds_ss.ucEnable = enable;
539 }
540 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
541 }
542
543 union adjust_pixel_clock {
544 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
545 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
546 };
547
548 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
549 struct drm_display_mode *mode)
550 {
551 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
552 struct drm_device *dev = crtc->dev;
553 struct radeon_device *rdev = dev->dev_private;
554 struct drm_encoder *encoder = radeon_crtc->encoder;
555 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
556 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
557 u32 adjusted_clock = mode->clock;
558 int encoder_mode = atombios_get_encoder_mode(encoder);
559 u32 dp_clock = mode->clock;
560 u32 clock = mode->clock;
561 int bpc = radeon_crtc->bpc;
562 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
563
564 /* reset the pll flags */
565 radeon_crtc->pll_flags = 0;
566
567 if (ASIC_IS_AVIVO(rdev)) {
568 if ((rdev->family == CHIP_RS600) ||
569 (rdev->family == CHIP_RS690) ||
570 (rdev->family == CHIP_RS740))
571 radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
572 RADEON_PLL_PREFER_CLOSEST_LOWER);
573
574 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
575 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
576 else
577 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
578
579 if (rdev->family < CHIP_RV770)
580 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
581 /* use frac fb div on APUs */
582 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
583 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
584 /* use frac fb div on RS780/RS880 */
585 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
586 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
587 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
588 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
589 } else {
590 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;
591
592 if (mode->clock > 200000) /* range limits??? */
593 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
594 else
595 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
596 }
597
598 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
599 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
600 if (connector) {
601 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
602 struct radeon_connector_atom_dig *dig_connector =
603 radeon_connector->con_priv;
604
605 dp_clock = dig_connector->dp_clock;
606 }
607 }
608
609 /* use recommended ref_div for ss */
610 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
611 if (radeon_crtc->ss_enabled) {
612 if (radeon_crtc->ss.refdiv) {
613 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
614 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
615 if (ASIC_IS_AVIVO(rdev))
616 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
617 }
618 }
619 }
620
621 if (ASIC_IS_AVIVO(rdev)) {
622 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
623 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
624 adjusted_clock = mode->clock * 2;
625 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
626 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
627 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
628 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;
629 } else {
630 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
631 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
632 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
633 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
634 }
635
636 /* adjust pll for deep color modes */
637 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
638 switch (bpc) {
639 case 8:
640 default:
641 break;
642 case 10:
643 clock = (clock * 5) / 4;
644 break;
645 case 12:
646 clock = (clock * 3) / 2;
647 break;
648 case 16:
649 clock = clock * 2;
650 break;
651 }
652 }
653
654 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
655 * accordingly based on the encoder/transmitter to work around
656 * special hw requirements.
657 */
658 if (ASIC_IS_DCE3(rdev)) {
659 union adjust_pixel_clock args;
660 u8 frev, crev;
661 int index;
662
663 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
664 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
665 &crev))
666 return adjusted_clock;
667
668 memset(&args, 0, sizeof(args));
669
670 switch (frev) {
671 case 1:
672 switch (crev) {
673 case 1:
674 case 2:
675 args.v1.usPixelClock = cpu_to_le16(clock / 10);
676 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
677 args.v1.ucEncodeMode = encoder_mode;
678 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
679 args.v1.ucConfig |=
680 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
681
682 atom_execute_table(rdev->mode_info.atom_context,
683 index, (uint32_t *)&args);
684 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
685 break;
686 case 3:
687 args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);
688 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
689 args.v3.sInput.ucEncodeMode = encoder_mode;
690 args.v3.sInput.ucDispPllConfig = 0;
691 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
692 args.v3.sInput.ucDispPllConfig |=
693 DISPPLL_CONFIG_SS_ENABLE;
694 if (ENCODER_MODE_IS_DP(encoder_mode)) {
695 args.v3.sInput.ucDispPllConfig |=
696 DISPPLL_CONFIG_COHERENT_MODE;
697 /* 16200 or 27000 */
698 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
699 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
700 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
701 if (dig->coherent_mode)
702 args.v3.sInput.ucDispPllConfig |=
703 DISPPLL_CONFIG_COHERENT_MODE;
704 if (is_duallink)
705 args.v3.sInput.ucDispPllConfig |=
706 DISPPLL_CONFIG_DUAL_LINK;
707 }
708 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
709 ENCODER_OBJECT_ID_NONE)
710 args.v3.sInput.ucExtTransmitterID =
711 radeon_encoder_get_dp_bridge_encoder_id(encoder);
712 else
713 args.v3.sInput.ucExtTransmitterID = 0;
714
715 atom_execute_table(rdev->mode_info.atom_context,
716 index, (uint32_t *)&args);
717 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
718 if (args.v3.sOutput.ucRefDiv) {
719 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
720 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
721 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
722 }
723 if (args.v3.sOutput.ucPostDiv) {
724 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
725 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;
726 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
727 }
728 break;
729 default:
730 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
731 return adjusted_clock;
732 }
733 break;
734 default:
735 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
736 return adjusted_clock;
737 }
738 }
739 return adjusted_clock;
740 }
741
742 union set_pixel_clock {
743 SET_PIXEL_CLOCK_PS_ALLOCATION base;
744 PIXEL_CLOCK_PARAMETERS v1;
745 PIXEL_CLOCK_PARAMETERS_V2 v2;
746 PIXEL_CLOCK_PARAMETERS_V3 v3;
747 PIXEL_CLOCK_PARAMETERS_V5 v5;
748 PIXEL_CLOCK_PARAMETERS_V6 v6;
749 };
750
751 /* on DCE5, make sure the voltage is high enough to support the
752 * required disp clk.
753 */
754 static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
755 u32 dispclk)
756 {
757 u8 frev, crev;
758 int index;
759 union set_pixel_clock args;
760
761 memset(&args, 0, sizeof(args));
762
763 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
764 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
765 &crev))
766 return;
767
768 switch (frev) {
769 case 1:
770 switch (crev) {
771 case 5:
772 /* if the default dcpll clock is specified,
773 * SetPixelClock provides the dividers
774 */
775 args.v5.ucCRTC = ATOM_CRTC_INVALID;
776 args.v5.usPixelClock = cpu_to_le16(dispclk);
777 args.v5.ucPpll = ATOM_DCPLL;
778 break;
779 case 6:
780 /* if the default dcpll clock is specified,
781 * SetPixelClock provides the dividers
782 */
783 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
784 if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
785 args.v6.ucPpll = ATOM_EXT_PLL1;
786 else if (ASIC_IS_DCE6(rdev))
787 args.v6.ucPpll = ATOM_PPLL0;
788 else
789 args.v6.ucPpll = ATOM_DCPLL;
790 break;
791 default:
792 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
793 return;
794 }
795 break;
796 default:
797 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
798 return;
799 }
800 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
801 }
802
803 static void atombios_crtc_program_pll(struct drm_crtc *crtc,
804 u32 crtc_id,
805 int pll_id,
806 u32 encoder_mode,
807 u32 encoder_id,
808 u32 clock,
809 u32 ref_div,
810 u32 fb_div,
811 u32 frac_fb_div,
812 u32 post_div,
813 int bpc,
814 bool ss_enabled,
815 struct radeon_atom_ss *ss)
816 {
817 struct drm_device *dev = crtc->dev;
818 struct radeon_device *rdev = dev->dev_private;
819 u8 frev, crev;
820 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
821 union set_pixel_clock args;
822
823 memset(&args, 0, sizeof(args));
824
825 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
826 &crev))
827 return;
828
829 switch (frev) {
830 case 1:
831 switch (crev) {
832 case 1:
833 if (clock == ATOM_DISABLE)
834 return;
835 args.v1.usPixelClock = cpu_to_le16(clock / 10);
836 args.v1.usRefDiv = cpu_to_le16(ref_div);
837 args.v1.usFbDiv = cpu_to_le16(fb_div);
838 args.v1.ucFracFbDiv = frac_fb_div;
839 args.v1.ucPostDiv = post_div;
840 args.v1.ucPpll = pll_id;
841 args.v1.ucCRTC = crtc_id;
842 args.v1.ucRefDivSrc = 1;
843 break;
844 case 2:
845 args.v2.usPixelClock = cpu_to_le16(clock / 10);
846 args.v2.usRefDiv = cpu_to_le16(ref_div);
847 args.v2.usFbDiv = cpu_to_le16(fb_div);
848 args.v2.ucFracFbDiv = frac_fb_div;
849 args.v2.ucPostDiv = post_div;
850 args.v2.ucPpll = pll_id;
851 args.v2.ucCRTC = crtc_id;
852 args.v2.ucRefDivSrc = 1;
853 break;
854 case 3:
855 args.v3.usPixelClock = cpu_to_le16(clock / 10);
856 args.v3.usRefDiv = cpu_to_le16(ref_div);
857 args.v3.usFbDiv = cpu_to_le16(fb_div);
858 args.v3.ucFracFbDiv = frac_fb_div;
859 args.v3.ucPostDiv = post_div;
860 args.v3.ucPpll = pll_id;
861 if (crtc_id == ATOM_CRTC2)
862 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
863 else
864 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
865 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
866 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
867 args.v3.ucTransmitterId = encoder_id;
868 args.v3.ucEncoderMode = encoder_mode;
869 break;
870 case 5:
871 args.v5.ucCRTC = crtc_id;
872 args.v5.usPixelClock = cpu_to_le16(clock / 10);
873 args.v5.ucRefDiv = ref_div;
874 args.v5.usFbDiv = cpu_to_le16(fb_div);
875 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
876 args.v5.ucPostDiv = post_div;
877 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
878 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
879 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
880 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
881 switch (bpc) {
882 case 8:
883 default:
884 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
885 break;
886 case 10:
887 /* yes this is correct, the atom define is wrong */
888 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP;
889 break;
890 case 12:
891 /* yes this is correct, the atom define is wrong */
892 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
893 break;
894 }
895 }
896 args.v5.ucTransmitterID = encoder_id;
897 args.v5.ucEncoderMode = encoder_mode;
898 args.v5.ucPpll = pll_id;
899 break;
900 case 6:
901 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
902 args.v6.ucRefDiv = ref_div;
903 args.v6.usFbDiv = cpu_to_le16(fb_div);
904 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
905 args.v6.ucPostDiv = post_div;
906 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
907 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
908 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
909 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
910 switch (bpc) {
911 case 8:
912 default:
913 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
914 break;
915 case 10:
916 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6;
917 break;
918 case 12:
919 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6;
920 break;
921 case 16:
922 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
923 break;
924 }
925 }
926 args.v6.ucTransmitterID = encoder_id;
927 args.v6.ucEncoderMode = encoder_mode;
928 args.v6.ucPpll = pll_id;
929 break;
930 default:
931 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
932 return;
933 }
934 break;
935 default:
936 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
937 return;
938 }
939
940 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
941 }
942
943 static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
944 {
945 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
946 struct drm_device *dev = crtc->dev;
947 struct radeon_device *rdev = dev->dev_private;
948 struct radeon_encoder *radeon_encoder =
949 to_radeon_encoder(radeon_crtc->encoder);
950 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
951
952 radeon_crtc->bpc = 8;
953 radeon_crtc->ss_enabled = false;
954
955 if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
956 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
957 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
958 struct drm_connector *connector =
959 radeon_get_connector_for_encoder(radeon_crtc->encoder);
960 struct radeon_connector *radeon_connector =
961 to_radeon_connector(connector);
962 struct radeon_connector_atom_dig *dig_connector =
963 radeon_connector->con_priv;
964 int dp_clock;
965
966 /* Assign mode clock for hdmi deep color max clock limit check */
967 radeon_connector->pixelclock_for_modeset = mode->clock;
968 radeon_crtc->bpc = radeon_get_monitor_bpc(connector);
969
970 switch (encoder_mode) {
971 case ATOM_ENCODER_MODE_DP_MST:
972 case ATOM_ENCODER_MODE_DP:
973 /* DP/eDP */
974 dp_clock = dig_connector->dp_clock / 10;
975 if (ASIC_IS_DCE4(rdev))
976 radeon_crtc->ss_enabled =
977 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
978 ASIC_INTERNAL_SS_ON_DP,
979 dp_clock);
980 else {
981 if (dp_clock == 16200) {
982 radeon_crtc->ss_enabled =
983 radeon_atombios_get_ppll_ss_info(rdev,
984 &radeon_crtc->ss,
985 ATOM_DP_SS_ID2);
986 if (!radeon_crtc->ss_enabled)
987 radeon_crtc->ss_enabled =
988 radeon_atombios_get_ppll_ss_info(rdev,
989 &radeon_crtc->ss,
990 ATOM_DP_SS_ID1);
991 } else {
992 radeon_crtc->ss_enabled =
993 radeon_atombios_get_ppll_ss_info(rdev,
994 &radeon_crtc->ss,
995 ATOM_DP_SS_ID1);
996 }
997 /* disable spread spectrum on DCE3 DP */
998 radeon_crtc->ss_enabled = false;
999 }
1000 break;
1001 case ATOM_ENCODER_MODE_LVDS:
1002 if (ASIC_IS_DCE4(rdev))
1003 radeon_crtc->ss_enabled =
1004 radeon_atombios_get_asic_ss_info(rdev,
1005 &radeon_crtc->ss,
1006 dig->lcd_ss_id,
1007 mode->clock / 10);
1008 else
1009 radeon_crtc->ss_enabled =
1010 radeon_atombios_get_ppll_ss_info(rdev,
1011 &radeon_crtc->ss,
1012 dig->lcd_ss_id);
1013 break;
1014 case ATOM_ENCODER_MODE_DVI:
1015 if (ASIC_IS_DCE4(rdev))
1016 radeon_crtc->ss_enabled =
1017 radeon_atombios_get_asic_ss_info(rdev,
1018 &radeon_crtc->ss,
1019 ASIC_INTERNAL_SS_ON_TMDS,
1020 mode->clock / 10);
1021 break;
1022 case ATOM_ENCODER_MODE_HDMI:
1023 if (ASIC_IS_DCE4(rdev))
1024 radeon_crtc->ss_enabled =
1025 radeon_atombios_get_asic_ss_info(rdev,
1026 &radeon_crtc->ss,
1027 ASIC_INTERNAL_SS_ON_HDMI,
1028 mode->clock / 10);
1029 break;
1030 default:
1031 break;
1032 }
1033 }
1034
1035 /* adjust pixel clock as needed */
1036 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);
1037
1038 return true;
1039 }
1040
1041 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
1042 {
1043 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1044 struct drm_device *dev = crtc->dev;
1045 struct radeon_device *rdev = dev->dev_private;
1046 struct radeon_encoder *radeon_encoder =
1047 to_radeon_encoder(radeon_crtc->encoder);
1048 u32 pll_clock = mode->clock;
1049 u32 clock = mode->clock;
1050 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
1051 struct radeon_pll *pll;
1052 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
1053
1054 /* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */
1055 if (ASIC_IS_DCE5(rdev) &&
1056 (encoder_mode == ATOM_ENCODER_MODE_HDMI) &&
1057 (radeon_crtc->bpc > 8))
1058 clock = radeon_crtc->adjusted_clock;
1059
1060 switch (radeon_crtc->pll_id) {
1061 case ATOM_PPLL1:
1062 pll = &rdev->clock.p1pll;
1063 break;
1064 case ATOM_PPLL2:
1065 pll = &rdev->clock.p2pll;
1066 break;
1067 case ATOM_DCPLL:
1068 case ATOM_PPLL_INVALID:
1069 default:
1070 pll = &rdev->clock.dcpll;
1071 break;
1072 }
1073
1074 /* update pll params */
1075 pll->flags = radeon_crtc->pll_flags;
1076 pll->reference_div = radeon_crtc->pll_reference_div;
1077 pll->post_div = radeon_crtc->pll_post_div;
1078
1079 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1080 /* TV seems to prefer the legacy algo on some boards */
1081 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1082 &fb_div, &frac_fb_div, &ref_div, &post_div);
1083 else if (ASIC_IS_AVIVO(rdev))
1084 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,
1085 &fb_div, &frac_fb_div, &ref_div, &post_div);
1086 else
1087 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1088 &fb_div, &frac_fb_div, &ref_div, &post_div);
1089
1090 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,
1091 radeon_crtc->crtc_id, &radeon_crtc->ss);
1092
1093 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1094 encoder_mode, radeon_encoder->encoder_id, clock,
1095 ref_div, fb_div, frac_fb_div, post_div,
1096 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);
1097
1098 if (radeon_crtc->ss_enabled) {
1099 /* calculate ss amount and step size */
1100 if (ASIC_IS_DCE4(rdev)) {
1101 u32 step_size;
1102 u32 amount = (((fb_div * 10) + frac_fb_div) *
1103 (u32)radeon_crtc->ss.percentage) /
1104 (100 * (u32)radeon_crtc->ss.percentage_divider);
1105 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1106 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1107 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1108 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1109 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1110 (125 * 25 * pll->reference_freq / 100);
1111 else
1112 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1113 (125 * 25 * pll->reference_freq / 100);
1114 radeon_crtc->ss.step = step_size;
1115 }
1116
1117 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,
1118 radeon_crtc->crtc_id, &radeon_crtc->ss);
1119 }
1120 }
1121
1122 static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1123 struct drm_framebuffer *fb,
1124 int x, int y, int atomic)
1125 {
1126 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1127 struct drm_device *dev = crtc->dev;
1128 struct radeon_device *rdev = dev->dev_private;
1129 struct radeon_framebuffer *radeon_fb;
1130 struct drm_framebuffer *target_fb;
1131 struct drm_gem_object *obj;
1132 struct radeon_bo *rbo;
1133 uint64_t fb_location;
1134 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1135 unsigned bankw, bankh, mtaspect, tile_split;
1136 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1137 u32 tmp, viewport_w, viewport_h;
1138 int r;
1139 bool bypass_lut = false;
1140
1141 /* no fb bound */
1142 if (!atomic && !crtc->primary->fb) {
1143 DRM_DEBUG_KMS("No FB bound\n");
1144 return 0;
1145 }
1146
1147 if (atomic) {
1148 radeon_fb = to_radeon_framebuffer(fb);
1149 target_fb = fb;
1150 }
1151 else {
1152 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1153 target_fb = crtc->primary->fb;
1154 }
1155
1156 /* If atomic, assume fb object is pinned & idle & fenced and
1157 * just update base pointers
1158 */
1159 obj = radeon_fb->obj;
1160 rbo = gem_to_radeon_bo(obj);
1161 r = radeon_bo_reserve(rbo, false);
1162 if (unlikely(r != 0))
1163 return r;
1164
1165 if (atomic)
1166 fb_location = radeon_bo_gpu_offset(rbo);
1167 else {
1168 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1169 if (unlikely(r != 0)) {
1170 radeon_bo_unreserve(rbo);
1171 return -EINVAL;
1172 }
1173 }
1174
1175 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1176 radeon_bo_unreserve(rbo);
1177
1178 switch (target_fb->pixel_format) {
1179 case DRM_FORMAT_C8:
1180 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1181 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1182 break;
1183 case DRM_FORMAT_XRGB4444:
1184 case DRM_FORMAT_ARGB4444:
1185 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1186 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444));
1187 #ifdef __BIG_ENDIAN
1188 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1189 #endif
1190 break;
1191 case DRM_FORMAT_XRGB1555:
1192 case DRM_FORMAT_ARGB1555:
1193 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1194 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1195 #ifdef __BIG_ENDIAN
1196 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1197 #endif
1198 break;
1199 case DRM_FORMAT_BGRX5551:
1200 case DRM_FORMAT_BGRA5551:
1201 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1202 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551));
1203 #ifdef __BIG_ENDIAN
1204 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1205 #endif
1206 break;
1207 case DRM_FORMAT_RGB565:
1208 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1209 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1210 #ifdef __BIG_ENDIAN
1211 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1212 #endif
1213 break;
1214 case DRM_FORMAT_XRGB8888:
1215 case DRM_FORMAT_ARGB8888:
1216 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1217 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1218 #ifdef __BIG_ENDIAN
1219 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1220 #endif
1221 break;
1222 case DRM_FORMAT_XRGB2101010:
1223 case DRM_FORMAT_ARGB2101010:
1224 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1225 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010));
1226 #ifdef __BIG_ENDIAN
1227 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1228 #endif
1229 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1230 bypass_lut = true;
1231 break;
1232 case DRM_FORMAT_BGRX1010102:
1233 case DRM_FORMAT_BGRA1010102:
1234 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1235 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102));
1236 #ifdef __BIG_ENDIAN
1237 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1238 #endif
1239 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1240 bypass_lut = true;
1241 break;
1242 default:
1243 DRM_ERROR("Unsupported screen format %s\n",
1244 drm_get_format_name(target_fb->pixel_format));
1245 return -EINVAL;
1246 }
1247
1248 if (tiling_flags & RADEON_TILING_MACRO) {
1249 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1250
1251 /* Set NUM_BANKS. */
1252 if (rdev->family >= CHIP_TAHITI) {
1253 unsigned index, num_banks;
1254
1255 if (rdev->family >= CHIP_BONAIRE) {
1256 unsigned tileb, tile_split_bytes;
1257
1258 /* Calculate the macrotile mode index. */
1259 tile_split_bytes = 64 << tile_split;
1260 tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
1261 tileb = min(tile_split_bytes, tileb);
1262
1263 for (index = 0; tileb > 64; index++)
1264 tileb >>= 1;
1265
1266 if (index >= 16) {
1267 DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
1268 target_fb->bits_per_pixel, tile_split);
1269 return -EINVAL;
1270 }
1271
1272 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
1273 } else {
1274 switch (target_fb->bits_per_pixel) {
1275 case 8:
1276 index = 10;
1277 break;
1278 case 16:
1279 index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
1280 break;
1281 default:
1282 case 32:
1283 index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
1284 break;
1285 }
1286
1287 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
1288 }
1289
1290 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
1291 } else {
1292 /* NI and older. */
1293 if (rdev->family >= CHIP_CAYMAN)
1294 tmp = rdev->config.cayman.tile_config;
1295 else
1296 tmp = rdev->config.evergreen.tile_config;
1297
1298 switch ((tmp & 0xf0) >> 4) {
1299 case 0: /* 4 banks */
1300 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1301 break;
1302 case 1: /* 8 banks */
1303 default:
1304 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1305 break;
1306 case 2: /* 16 banks */
1307 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1308 break;
1309 }
1310 }
1311
1312 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1313 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1314 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1315 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1316 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1317 if (rdev->family >= CHIP_BONAIRE) {
1318 /* XXX need to know more about the surface tiling mode */
1319 fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING);
1320 }
1321 } else if (tiling_flags & RADEON_TILING_MICRO)
1322 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1323
1324 if (rdev->family >= CHIP_BONAIRE) {
1325 /* Read the pipe config from the 2D TILED SCANOUT mode.
1326 * It should be the same for the other modes too, but not all
1327 * modes set the pipe config field. */
1328 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;
1329
1330 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config);
1331 } else if ((rdev->family == CHIP_TAHITI) ||
1332 (rdev->family == CHIP_PITCAIRN))
1333 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
1334 else if ((rdev->family == CHIP_VERDE) ||
1335 (rdev->family == CHIP_OLAND) ||
1336 (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */
1337 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1338
1339 switch (radeon_crtc->crtc_id) {
1340 case 0:
1341 WREG32(AVIVO_D1VGA_CONTROL, 0);
1342 break;
1343 case 1:
1344 WREG32(AVIVO_D2VGA_CONTROL, 0);
1345 break;
1346 case 2:
1347 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1348 break;
1349 case 3:
1350 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1351 break;
1352 case 4:
1353 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1354 break;
1355 case 5:
1356 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1357 break;
1358 default:
1359 break;
1360 }
1361
1362 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1363 upper_32_bits(fb_location));
1364 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1365 upper_32_bits(fb_location));
1366 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1367 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1368 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1369 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1370 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1371 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1372
1373 /*
1374 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1375 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1376 * retain the full precision throughout the pipeline.
1377 */
1378 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset,
1379 (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0),
1380 ~EVERGREEN_LUT_10BIT_BYPASS_EN);
1381
1382 if (bypass_lut)
1383 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1384
1385 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1386 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1387 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1388 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1389 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1390 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1391
1392 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1393 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1394 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1395
1396 if (rdev->family >= CHIP_BONAIRE)
1397 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1398 target_fb->height);
1399 else
1400 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1401 target_fb->height);
1402 x &= ~3;
1403 y &= ~1;
1404 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1405 (x << 16) | y);
1406 viewport_w = crtc->mode.hdisplay;
1407 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1408 if ((rdev->family >= CHIP_BONAIRE) &&
1409 (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE))
1410 viewport_h *= 2;
1411 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1412 (viewport_w << 16) | viewport_h);
1413
1414 /* pageflip setup */
1415 /* make sure flip is at vb rather than hb */
1416 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1417 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1418 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1419
1420 /* set pageflip to happen only at start of vblank interval (front porch) */
1421 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);
1422
1423 if (!atomic && fb && fb != crtc->primary->fb) {
1424 radeon_fb = to_radeon_framebuffer(fb);
1425 rbo = gem_to_radeon_bo(radeon_fb->obj);
1426 r = radeon_bo_reserve(rbo, false);
1427 if (unlikely(r != 0))
1428 return r;
1429 radeon_bo_unpin(rbo);
1430 radeon_bo_unreserve(rbo);
1431 }
1432
1433 /* Bytes per pixel may have changed */
1434 radeon_bandwidth_update(rdev);
1435
1436 return 0;
1437 }
1438
1439 static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1440 struct drm_framebuffer *fb,
1441 int x, int y, int atomic)
1442 {
1443 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1444 struct drm_device *dev = crtc->dev;
1445 struct radeon_device *rdev = dev->dev_private;
1446 struct radeon_framebuffer *radeon_fb;
1447 struct drm_gem_object *obj;
1448 struct radeon_bo *rbo;
1449 struct drm_framebuffer *target_fb;
1450 uint64_t fb_location;
1451 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1452 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1453 u32 tmp, viewport_w, viewport_h;
1454 int r;
1455 bool bypass_lut = false;
1456
1457 /* no fb bound */
1458 if (!atomic && !crtc->primary->fb) {
1459 DRM_DEBUG_KMS("No FB bound\n");
1460 return 0;
1461 }
1462
1463 if (atomic) {
1464 radeon_fb = to_radeon_framebuffer(fb);
1465 target_fb = fb;
1466 }
1467 else {
1468 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1469 target_fb = crtc->primary->fb;
1470 }
1471
1472 obj = radeon_fb->obj;
1473 rbo = gem_to_radeon_bo(obj);
1474 r = radeon_bo_reserve(rbo, false);
1475 if (unlikely(r != 0))
1476 return r;
1477
1478 /* If atomic, assume fb object is pinned & idle & fenced and
1479 * just update base pointers
1480 */
1481 if (atomic)
1482 fb_location = radeon_bo_gpu_offset(rbo);
1483 else {
1484 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1485 if (unlikely(r != 0)) {
1486 radeon_bo_unreserve(rbo);
1487 return -EINVAL;
1488 }
1489 }
1490 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1491 radeon_bo_unreserve(rbo);
1492
1493 switch (target_fb->pixel_format) {
1494 case DRM_FORMAT_C8:
1495 fb_format =
1496 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1497 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1498 break;
1499 case DRM_FORMAT_XRGB4444:
1500 case DRM_FORMAT_ARGB4444:
1501 fb_format =
1502 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1503 AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444;
1504 #ifdef __BIG_ENDIAN
1505 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1506 #endif
1507 break;
1508 case DRM_FORMAT_XRGB1555:
1509 fb_format =
1510 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1511 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1512 #ifdef __BIG_ENDIAN
1513 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1514 #endif
1515 break;
1516 case DRM_FORMAT_RGB565:
1517 fb_format =
1518 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1519 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1520 #ifdef __BIG_ENDIAN
1521 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1522 #endif
1523 break;
1524 case DRM_FORMAT_XRGB8888:
1525 case DRM_FORMAT_ARGB8888:
1526 fb_format =
1527 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1528 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1529 #ifdef __BIG_ENDIAN
1530 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1531 #endif
1532 break;
1533 case DRM_FORMAT_XRGB2101010:
1534 case DRM_FORMAT_ARGB2101010:
1535 fb_format =
1536 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1537 AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010;
1538 #ifdef __BIG_ENDIAN
1539 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1540 #endif
1541 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1542 bypass_lut = true;
1543 break;
1544 default:
1545 DRM_ERROR("Unsupported screen format %s\n",
1546 drm_get_format_name(target_fb->pixel_format));
1547 return -EINVAL;
1548 }
1549
1550 if (rdev->family >= CHIP_R600) {
1551 if (tiling_flags & RADEON_TILING_MACRO)
1552 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1553 else if (tiling_flags & RADEON_TILING_MICRO)
1554 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1555 } else {
1556 if (tiling_flags & RADEON_TILING_MACRO)
1557 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1558
1559 if (tiling_flags & RADEON_TILING_MICRO)
1560 fb_format |= AVIVO_D1GRPH_TILED;
1561 }
1562
1563 if (radeon_crtc->crtc_id == 0)
1564 WREG32(AVIVO_D1VGA_CONTROL, 0);
1565 else
1566 WREG32(AVIVO_D2VGA_CONTROL, 0);
1567
1568 if (rdev->family >= CHIP_RV770) {
1569 if (radeon_crtc->crtc_id) {
1570 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1571 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1572 } else {
1573 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1574 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1575 }
1576 }
1577 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1578 (u32) fb_location);
1579 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1580 radeon_crtc->crtc_offset, (u32) fb_location);
1581 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1582 if (rdev->family >= CHIP_R600)
1583 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1584
1585 /* LUT only has 256 slots for 8 bpc fb. Bypass for > 8 bpc scanout for precision */
1586 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset,
1587 (bypass_lut ? AVIVO_LUT_10BIT_BYPASS_EN : 0), ~AVIVO_LUT_10BIT_BYPASS_EN);
1588
1589 if (bypass_lut)
1590 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1591
1592 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1593 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1594 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1595 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1596 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1597 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1598
1599 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1600 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1601 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1602
1603 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1604 target_fb->height);
1605 x &= ~3;
1606 y &= ~1;
1607 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1608 (x << 16) | y);
1609 viewport_w = crtc->mode.hdisplay;
1610 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1611 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1612 (viewport_w << 16) | viewport_h);
1613
1614 /* pageflip setup */
1615 /* make sure flip is at vb rather than hb */
1616 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1617 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1618 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1619
1620 /* set pageflip to happen only at start of vblank interval (front porch) */
1621 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);
1622
1623 if (!atomic && fb && fb != crtc->primary->fb) {
1624 radeon_fb = to_radeon_framebuffer(fb);
1625 rbo = gem_to_radeon_bo(radeon_fb->obj);
1626 r = radeon_bo_reserve(rbo, false);
1627 if (unlikely(r != 0))
1628 return r;
1629 radeon_bo_unpin(rbo);
1630 radeon_bo_unreserve(rbo);
1631 }
1632
1633 /* Bytes per pixel may have changed */
1634 radeon_bandwidth_update(rdev);
1635
1636 return 0;
1637 }
1638
1639 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1640 struct drm_framebuffer *old_fb)
1641 {
1642 struct drm_device *dev = crtc->dev;
1643 struct radeon_device *rdev = dev->dev_private;
1644
1645 if (ASIC_IS_DCE4(rdev))
1646 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1647 else if (ASIC_IS_AVIVO(rdev))
1648 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1649 else
1650 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1651 }
1652
1653 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1654 struct drm_framebuffer *fb,
1655 int x, int y, enum mode_set_atomic state)
1656 {
1657 struct drm_device *dev = crtc->dev;
1658 struct radeon_device *rdev = dev->dev_private;
1659
1660 if (ASIC_IS_DCE4(rdev))
1661 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1662 else if (ASIC_IS_AVIVO(rdev))
1663 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1664 else
1665 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1666 }
1667
1668 /* properly set additional regs when using atombios */
1669 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1670 {
1671 struct drm_device *dev = crtc->dev;
1672 struct radeon_device *rdev = dev->dev_private;
1673 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1674 u32 disp_merge_cntl;
1675
1676 switch (radeon_crtc->crtc_id) {
1677 case 0:
1678 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1679 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1680 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1681 break;
1682 case 1:
1683 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1684 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1685 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1686 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1687 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1688 break;
1689 }
1690 }
1691
1692 /**
1693 * radeon_get_pll_use_mask - look up a mask of which pplls are in use
1694 *
1695 * @crtc: drm crtc
1696 *
1697 * Returns the mask of which PPLLs (Pixel PLLs) are in use.
1698 */
1699 static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
1700 {
1701 struct drm_device *dev = crtc->dev;
1702 struct drm_crtc *test_crtc;
1703 struct radeon_crtc *test_radeon_crtc;
1704 u32 pll_in_use = 0;
1705
1706 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1707 if (crtc == test_crtc)
1708 continue;
1709
1710 test_radeon_crtc = to_radeon_crtc(test_crtc);
1711 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1712 pll_in_use |= (1 << test_radeon_crtc->pll_id);
1713 }
1714 return pll_in_use;
1715 }
1716
1717 /**
1718 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1719 *
1720 * @crtc: drm crtc
1721 *
1722 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1723 * also in DP mode. For DP, a single PPLL can be used for all DP
1724 * crtcs/encoders.
1725 */
1726 static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
1727 {
1728 struct drm_device *dev = crtc->dev;
1729 struct drm_crtc *test_crtc;
1730 struct radeon_crtc *test_radeon_crtc;
1731
1732 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1733 if (crtc == test_crtc)
1734 continue;
1735 test_radeon_crtc = to_radeon_crtc(test_crtc);
1736 if (test_radeon_crtc->encoder &&
1737 ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1738 /* for DP use the same PLL for all */
1739 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1740 return test_radeon_crtc->pll_id;
1741 }
1742 }
1743 return ATOM_PPLL_INVALID;
1744 }
1745
1746 /**
1747 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1748 *
1749 * @crtc: drm crtc
1750 * @encoder: drm encoder
1751 *
1752 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1753 * be shared (i.e., same clock).
1754 */
1755 static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
1756 {
1757 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1758 struct drm_device *dev = crtc->dev;
1759 struct drm_crtc *test_crtc;
1760 struct radeon_crtc *test_radeon_crtc;
1761 u32 adjusted_clock, test_adjusted_clock;
1762
1763 adjusted_clock = radeon_crtc->adjusted_clock;
1764
1765 if (adjusted_clock == 0)
1766 return ATOM_PPLL_INVALID;
1767
1768 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1769 if (crtc == test_crtc)
1770 continue;
1771 test_radeon_crtc = to_radeon_crtc(test_crtc);
1772 if (test_radeon_crtc->encoder &&
1773 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1774 /* check if we are already driving this connector with another crtc */
1775 if (test_radeon_crtc->connector == radeon_crtc->connector) {
1776 /* if we are, return that pll */
1777 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1778 return test_radeon_crtc->pll_id;
1779 }
1780 /* for non-DP check the clock */
1781 test_adjusted_clock = test_radeon_crtc->adjusted_clock;
1782 if ((crtc->mode.clock == test_crtc->mode.clock) &&
1783 (adjusted_clock == test_adjusted_clock) &&
1784 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&
1785 (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID))
1786 return test_radeon_crtc->pll_id;
1787 }
1788 }
1789 return ATOM_PPLL_INVALID;
1790 }
1791
1792 /**
1793 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1794 *
1795 * @crtc: drm crtc
1796 *
1797 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
1798 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1799 * monitors a dedicated PPLL must be used. If a particular board has
1800 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1801 * as there is no need to program the PLL itself. If we are not able to
1802 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
1803 * avoid messing up an existing monitor.
1804 *
1805 * Asic specific PLL information
1806 *
1807 * DCE 8.x
1808 * KB/KV
1809 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
1810 * CI
1811 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1812 *
1813 * DCE 6.1
1814 * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
1815 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
1816 *
1817 * DCE 6.0
1818 * - PPLL0 is available to all UNIPHY (DP only)
1819 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1820 *
1821 * DCE 5.0
1822 * - DCPLL is available to all UNIPHY (DP only)
1823 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1824 *
1825 * DCE 3.0/4.0/4.1
1826 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1827 *
1828 */
1829 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1830 {
1831 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1832 struct drm_device *dev = crtc->dev;
1833 struct radeon_device *rdev = dev->dev_private;
1834 struct radeon_encoder *radeon_encoder =
1835 to_radeon_encoder(radeon_crtc->encoder);
1836 u32 pll_in_use;
1837 int pll;
1838
1839 if (ASIC_IS_DCE8(rdev)) {
1840 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1841 if (rdev->clock.dp_extclk)
1842 /* skip PPLL programming if using ext clock */
1843 return ATOM_PPLL_INVALID;
1844 else {
1845 /* use the same PPLL for all DP monitors */
1846 pll = radeon_get_shared_dp_ppll(crtc);
1847 if (pll != ATOM_PPLL_INVALID)
1848 return pll;
1849 }
1850 } else {
1851 /* use the same PPLL for all monitors with the same clock */
1852 pll = radeon_get_shared_nondp_ppll(crtc);
1853 if (pll != ATOM_PPLL_INVALID)
1854 return pll;
1855 }
1856 /* otherwise, pick one of the plls */
1857 if ((rdev->family == CHIP_KABINI) ||
1858 (rdev->family == CHIP_MULLINS)) {
1859 /* KB/ML has PPLL1 and PPLL2 */
1860 pll_in_use = radeon_get_pll_use_mask(crtc);
1861 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1862 return ATOM_PPLL2;
1863 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1864 return ATOM_PPLL1;
1865 DRM_ERROR("unable to allocate a PPLL\n");
1866 return ATOM_PPLL_INVALID;
1867 } else {
1868 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
1869 pll_in_use = radeon_get_pll_use_mask(crtc);
1870 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1871 return ATOM_PPLL2;
1872 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1873 return ATOM_PPLL1;
1874 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1875 return ATOM_PPLL0;
1876 DRM_ERROR("unable to allocate a PPLL\n");
1877 return ATOM_PPLL_INVALID;
1878 }
1879 } else if (ASIC_IS_DCE61(rdev)) {
1880 struct radeon_encoder_atom_dig *dig =
1881 radeon_encoder->enc_priv;
1882
1883 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1884 (dig->linkb == false))
1885 /* UNIPHY A uses PPLL2 */
1886 return ATOM_PPLL2;
1887 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1888 /* UNIPHY B/C/D/E/F */
1889 if (rdev->clock.dp_extclk)
1890 /* skip PPLL programming if using ext clock */
1891 return ATOM_PPLL_INVALID;
1892 else {
1893 /* use the same PPLL for all DP monitors */
1894 pll = radeon_get_shared_dp_ppll(crtc);
1895 if (pll != ATOM_PPLL_INVALID)
1896 return pll;
1897 }
1898 } else {
1899 /* use the same PPLL for all monitors with the same clock */
1900 pll = radeon_get_shared_nondp_ppll(crtc);
1901 if (pll != ATOM_PPLL_INVALID)
1902 return pll;
1903 }
1904 /* UNIPHY B/C/D/E/F */
1905 pll_in_use = radeon_get_pll_use_mask(crtc);
1906 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1907 return ATOM_PPLL0;
1908 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1909 return ATOM_PPLL1;
1910 DRM_ERROR("unable to allocate a PPLL\n");
1911 return ATOM_PPLL_INVALID;
1912 } else if (ASIC_IS_DCE41(rdev)) {
1913 /* Don't share PLLs on DCE4.1 chips */
1914 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1915 if (rdev->clock.dp_extclk)
1916 /* skip PPLL programming if using ext clock */
1917 return ATOM_PPLL_INVALID;
1918 }
1919 pll_in_use = radeon_get_pll_use_mask(crtc);
1920 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1921 return ATOM_PPLL1;
1922 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1923 return ATOM_PPLL2;
1924 DRM_ERROR("unable to allocate a PPLL\n");
1925 return ATOM_PPLL_INVALID;
1926 } else if (ASIC_IS_DCE4(rdev)) {
1927 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1928 * depending on the asic:
1929 * DCE4: PPLL or ext clock
1930 * DCE5: PPLL, DCPLL, or ext clock
1931 * DCE6: PPLL, PPLL0, or ext clock
1932 *
1933 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1934 * PPLL/DCPLL programming and only program the DP DTO for the
1935 * crtc virtual pixel clock.
1936 */
1937 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1938 if (rdev->clock.dp_extclk)
1939 /* skip PPLL programming if using ext clock */
1940 return ATOM_PPLL_INVALID;
1941 else if (ASIC_IS_DCE6(rdev))
1942 /* use PPLL0 for all DP */
1943 return ATOM_PPLL0;
1944 else if (ASIC_IS_DCE5(rdev))
1945 /* use DCPLL for all DP */
1946 return ATOM_DCPLL;
1947 else {
1948 /* use the same PPLL for all DP monitors */
1949 pll = radeon_get_shared_dp_ppll(crtc);
1950 if (pll != ATOM_PPLL_INVALID)
1951 return pll;
1952 }
1953 } else {
1954 /* use the same PPLL for all monitors with the same clock */
1955 pll = radeon_get_shared_nondp_ppll(crtc);
1956 if (pll != ATOM_PPLL_INVALID)
1957 return pll;
1958 }
1959 /* all other cases */
1960 pll_in_use = radeon_get_pll_use_mask(crtc);
1961 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1962 return ATOM_PPLL1;
1963 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1964 return ATOM_PPLL2;
1965 DRM_ERROR("unable to allocate a PPLL\n");
1966 return ATOM_PPLL_INVALID;
1967 } else {
1968 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
1969 /* some atombios (observed in some DCE2/DCE3) code have a bug,
1970 * the matching btw pll and crtc is done through
1971 * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the
1972 * pll (1 or 2) to select which register to write. ie if using
1973 * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2
1974 * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to
1975 * choose which value to write. Which is reverse order from
1976 * register logic. So only case that works is when pllid is
1977 * same as crtcid or when both pll and crtc are enabled and
1978 * both use same clock.
1979 *
1980 * So just return crtc id as if crtc and pll were hard linked
1981 * together even if they aren't
1982 */
1983 return radeon_crtc->crtc_id;
1984 }
1985 }
1986
1987 void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
1988 {
1989 /* always set DCPLL */
1990 if (ASIC_IS_DCE6(rdev))
1991 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1992 else if (ASIC_IS_DCE4(rdev)) {
1993 struct radeon_atom_ss ss;
1994 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1995 ASIC_INTERNAL_SS_ON_DCPLL,
1996 rdev->clock.default_dispclk);
1997 if (ss_enabled)
1998 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
1999 /* XXX: DCE5, make sure voltage, dispclk is high enough */
2000 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
2001 if (ss_enabled)
2002 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
2003 }
2004
2005 }
2006
2007 int atombios_crtc_mode_set(struct drm_crtc *crtc,
2008 struct drm_display_mode *mode,
2009 struct drm_display_mode *adjusted_mode,
2010 int x, int y, struct drm_framebuffer *old_fb)
2011 {
2012 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2013 struct drm_device *dev = crtc->dev;
2014 struct radeon_device *rdev = dev->dev_private;
2015 struct radeon_encoder *radeon_encoder =
2016 to_radeon_encoder(radeon_crtc->encoder);
2017 bool is_tvcv = false;
2018
2019 if (radeon_encoder->active_device &
2020 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2021 is_tvcv = true;
2022
2023 if (!radeon_crtc->adjusted_clock)
2024 return -EINVAL;
2025
2026 atombios_crtc_set_pll(crtc, adjusted_mode);
2027
2028 if (ASIC_IS_DCE4(rdev))
2029 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2030 else if (ASIC_IS_AVIVO(rdev)) {
2031 if (is_tvcv)
2032 atombios_crtc_set_timing(crtc, adjusted_mode);
2033 else
2034 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2035 } else {
2036 atombios_crtc_set_timing(crtc, adjusted_mode);
2037 if (radeon_crtc->crtc_id == 0)
2038 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2039 radeon_legacy_atom_fixup(crtc);
2040 }
2041 atombios_crtc_set_base(crtc, x, y, old_fb);
2042 atombios_overscan_setup(crtc, mode, adjusted_mode);
2043 atombios_scaler_setup(crtc);
2044 radeon_cursor_reset(crtc);
2045 /* update the hw version fpr dpm */
2046 radeon_crtc->hw_mode = *adjusted_mode;
2047
2048 return 0;
2049 }
2050
2051 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
2052 const struct drm_display_mode *mode,
2053 struct drm_display_mode *adjusted_mode)
2054 {
2055 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2056 struct drm_device *dev = crtc->dev;
2057 struct drm_encoder *encoder;
2058
2059 /* assign the encoder to the radeon crtc to avoid repeated lookups later */
2060 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2061 if (encoder->crtc == crtc) {
2062 radeon_crtc->encoder = encoder;
2063 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);
2064 break;
2065 }
2066 }
2067 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) {
2068 radeon_crtc->encoder = NULL;
2069 radeon_crtc->connector = NULL;
2070 return false;
2071 }
2072 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2073 return false;
2074 if (!atombios_crtc_prepare_pll(crtc, adjusted_mode))
2075 return false;
2076 /* pick pll */
2077 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
2078 /* if we can't get a PPLL for a non-DP encoder, fail */
2079 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&
2080 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))
2081 return false;
2082
2083 return true;
2084 }
2085
2086 static void atombios_crtc_prepare(struct drm_crtc *crtc)
2087 {
2088 struct drm_device *dev = crtc->dev;
2089 struct radeon_device *rdev = dev->dev_private;
2090
2091 /* disable crtc pair power gating before programming */
2092 if (ASIC_IS_DCE6(rdev))
2093 atombios_powergate_crtc(crtc, ATOM_DISABLE);
2094
2095 atombios_lock_crtc(crtc, ATOM_ENABLE);
2096 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2097 }
2098
2099 static void atombios_crtc_commit(struct drm_crtc *crtc)
2100 {
2101 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2102 atombios_lock_crtc(crtc, ATOM_DISABLE);
2103 }
2104
2105 static void atombios_crtc_disable(struct drm_crtc *crtc)
2106 {
2107 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2108 struct drm_device *dev = crtc->dev;
2109 struct radeon_device *rdev = dev->dev_private;
2110 struct radeon_atom_ss ss;
2111 int i;
2112
2113 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2114 if (crtc->primary->fb) {
2115 int r;
2116 struct radeon_framebuffer *radeon_fb;
2117 struct radeon_bo *rbo;
2118
2119 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
2120 rbo = gem_to_radeon_bo(radeon_fb->obj);
2121 r = radeon_bo_reserve(rbo, false);
2122 if (unlikely(r))
2123 DRM_ERROR("failed to reserve rbo before unpin\n");
2124 else {
2125 radeon_bo_unpin(rbo);
2126 radeon_bo_unreserve(rbo);
2127 }
2128 }
2129 /* disable the GRPH */
2130 if (ASIC_IS_DCE4(rdev))
2131 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2132 else if (ASIC_IS_AVIVO(rdev))
2133 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2134
2135 if (ASIC_IS_DCE6(rdev))
2136 atombios_powergate_crtc(crtc, ATOM_ENABLE);
2137
2138 for (i = 0; i < rdev->num_crtc; i++) {
2139 if (rdev->mode_info.crtcs[i] &&
2140 rdev->mode_info.crtcs[i]->enabled &&
2141 i != radeon_crtc->crtc_id &&
2142 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
2143 /* one other crtc is using this pll don't turn
2144 * off the pll
2145 */
2146 goto done;
2147 }
2148 }
2149
2150 switch (radeon_crtc->pll_id) {
2151 case ATOM_PPLL1:
2152 case ATOM_PPLL2:
2153 /* disable the ppll */
2154 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2155 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2156 break;
2157 case ATOM_PPLL0:
2158 /* disable the ppll */
2159 if ((rdev->family == CHIP_ARUBA) ||
2160 (rdev->family == CHIP_KAVERI) ||
2161 (rdev->family == CHIP_BONAIRE) ||
2162 (rdev->family == CHIP_HAWAII))
2163 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2164 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2165 break;
2166 default:
2167 break;
2168 }
2169 done:
2170 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2171 radeon_crtc->adjusted_clock = 0;
2172 radeon_crtc->encoder = NULL;
2173 radeon_crtc->connector = NULL;
2174 }
2175
2176 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
2177 .dpms = atombios_crtc_dpms,
2178 .mode_fixup = atombios_crtc_mode_fixup,
2179 .mode_set = atombios_crtc_mode_set,
2180 .mode_set_base = atombios_crtc_set_base,
2181 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
2182 .prepare = atombios_crtc_prepare,
2183 .commit = atombios_crtc_commit,
2184 .load_lut = radeon_crtc_load_lut,
2185 .disable = atombios_crtc_disable,
2186 };
2187
2188 void radeon_atombios_init_crtc(struct drm_device *dev,
2189 struct radeon_crtc *radeon_crtc)
2190 {
2191 struct radeon_device *rdev = dev->dev_private;
2192
2193 if (ASIC_IS_DCE4(rdev)) {
2194 switch (radeon_crtc->crtc_id) {
2195 case 0:
2196 default:
2197 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
2198 break;
2199 case 1:
2200 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
2201 break;
2202 case 2:
2203 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
2204 break;
2205 case 3:
2206 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
2207 break;
2208 case 4:
2209 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
2210 break;
2211 case 5:
2212 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
2213 break;
2214 }
2215 } else {
2216 if (radeon_crtc->crtc_id == 1)
2217 radeon_crtc->crtc_offset =
2218 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
2219 else
2220 radeon_crtc->crtc_offset = 0;
2221 }
2222 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2223 radeon_crtc->adjusted_clock = 0;
2224 radeon_crtc->encoder = NULL;
2225 radeon_crtc->connector = NULL;
2226 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
2227 }
Linux kernel - Deliverables
This page took 0.119453 seconds and 5 git commands to generate.