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drm/i915: Record the RING_MODE register for post-mortem debugging
[deliverable/linux.git] / drivers / gpu / drm / radeon / atombios_crtc.c
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/drm_fb_helper.h>
29 #include <drm/radeon_drm.h>
30 #include <drm/drm_fixed.h>
31 #include "radeon.h"
32 #include "atom.h"
33 #include "atom-bits.h"
34
35 static void atombios_overscan_setup(struct drm_crtc *crtc,
36 struct drm_display_mode *mode,
37 struct drm_display_mode *adjusted_mode)
38 {
39 struct drm_device *dev = crtc->dev;
40 struct radeon_device *rdev = dev->dev_private;
41 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
42 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
43 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
44 int a1, a2;
45
46 memset(&args, 0, sizeof(args));
47
48 args.ucCRTC = radeon_crtc->crtc_id;
49
50 switch (radeon_crtc->rmx_type) {
51 case RMX_CENTER:
52 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
53 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
54 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
55 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
56 break;
57 case RMX_ASPECT:
58 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
59 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
60
61 if (a1 > a2) {
62 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
63 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
64 } else if (a2 > a1) {
65 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
66 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
67 }
68 break;
69 case RMX_FULL:
70 default:
71 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
72 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
73 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
74 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
75 break;
76 }
77 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
78 }
79
80 static void atombios_scaler_setup(struct drm_crtc *crtc)
81 {
82 struct drm_device *dev = crtc->dev;
83 struct radeon_device *rdev = dev->dev_private;
84 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
85 ENABLE_SCALER_PS_ALLOCATION args;
86 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
87 struct radeon_encoder *radeon_encoder =
88 to_radeon_encoder(radeon_crtc->encoder);
89 /* fixme - fill in enc_priv for atom dac */
90 enum radeon_tv_std tv_std = TV_STD_NTSC;
91 bool is_tv = false, is_cv = false;
92
93 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
94 return;
95
96 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
97 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
98 tv_std = tv_dac->tv_std;
99 is_tv = true;
100 }
101
102 memset(&args, 0, sizeof(args));
103
104 args.ucScaler = radeon_crtc->crtc_id;
105
106 if (is_tv) {
107 switch (tv_std) {
108 case TV_STD_NTSC:
109 default:
110 args.ucTVStandard = ATOM_TV_NTSC;
111 break;
112 case TV_STD_PAL:
113 args.ucTVStandard = ATOM_TV_PAL;
114 break;
115 case TV_STD_PAL_M:
116 args.ucTVStandard = ATOM_TV_PALM;
117 break;
118 case TV_STD_PAL_60:
119 args.ucTVStandard = ATOM_TV_PAL60;
120 break;
121 case TV_STD_NTSC_J:
122 args.ucTVStandard = ATOM_TV_NTSCJ;
123 break;
124 case TV_STD_SCART_PAL:
125 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
126 break;
127 case TV_STD_SECAM:
128 args.ucTVStandard = ATOM_TV_SECAM;
129 break;
130 case TV_STD_PAL_CN:
131 args.ucTVStandard = ATOM_TV_PALCN;
132 break;
133 }
134 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
135 } else if (is_cv) {
136 args.ucTVStandard = ATOM_TV_CV;
137 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
138 } else {
139 switch (radeon_crtc->rmx_type) {
140 case RMX_FULL:
141 args.ucEnable = ATOM_SCALER_EXPANSION;
142 break;
143 case RMX_CENTER:
144 args.ucEnable = ATOM_SCALER_CENTER;
145 break;
146 case RMX_ASPECT:
147 args.ucEnable = ATOM_SCALER_EXPANSION;
148 break;
149 default:
150 if (ASIC_IS_AVIVO(rdev))
151 args.ucEnable = ATOM_SCALER_DISABLE;
152 else
153 args.ucEnable = ATOM_SCALER_CENTER;
154 break;
155 }
156 }
157 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
158 if ((is_tv || is_cv)
159 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
160 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
161 }
162 }
163
164 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
165 {
166 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
167 struct drm_device *dev = crtc->dev;
168 struct radeon_device *rdev = dev->dev_private;
169 int index =
170 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
171 ENABLE_CRTC_PS_ALLOCATION args;
172
173 memset(&args, 0, sizeof(args));
174
175 args.ucCRTC = radeon_crtc->crtc_id;
176 args.ucEnable = lock;
177
178 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
179 }
180
181 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
182 {
183 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
184 struct drm_device *dev = crtc->dev;
185 struct radeon_device *rdev = dev->dev_private;
186 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
187 ENABLE_CRTC_PS_ALLOCATION args;
188
189 memset(&args, 0, sizeof(args));
190
191 args.ucCRTC = radeon_crtc->crtc_id;
192 args.ucEnable = state;
193
194 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
195 }
196
197 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
198 {
199 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
200 struct drm_device *dev = crtc->dev;
201 struct radeon_device *rdev = dev->dev_private;
202 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
203 ENABLE_CRTC_PS_ALLOCATION args;
204
205 memset(&args, 0, sizeof(args));
206
207 args.ucCRTC = radeon_crtc->crtc_id;
208 args.ucEnable = state;
209
210 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
211 }
212
213 static const u32 vga_control_regs[6] =
214 {
215 AVIVO_D1VGA_CONTROL,
216 AVIVO_D2VGA_CONTROL,
217 EVERGREEN_D3VGA_CONTROL,
218 EVERGREEN_D4VGA_CONTROL,
219 EVERGREEN_D5VGA_CONTROL,
220 EVERGREEN_D6VGA_CONTROL,
221 };
222
223 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
224 {
225 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
226 struct drm_device *dev = crtc->dev;
227 struct radeon_device *rdev = dev->dev_private;
228 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
229 BLANK_CRTC_PS_ALLOCATION args;
230 u32 vga_control = 0;
231
232 memset(&args, 0, sizeof(args));
233
234 if (ASIC_IS_DCE8(rdev)) {
235 vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);
236 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);
237 }
238
239 args.ucCRTC = radeon_crtc->crtc_id;
240 args.ucBlanking = state;
241
242 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
243
244 if (ASIC_IS_DCE8(rdev)) {
245 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);
246 }
247 }
248
249 static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
250 {
251 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
252 struct drm_device *dev = crtc->dev;
253 struct radeon_device *rdev = dev->dev_private;
254 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
255 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
256
257 memset(&args, 0, sizeof(args));
258
259 args.ucDispPipeId = radeon_crtc->crtc_id;
260 args.ucEnable = state;
261
262 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
263 }
264
265 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
266 {
267 struct drm_device *dev = crtc->dev;
268 struct radeon_device *rdev = dev->dev_private;
269 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
270
271 switch (mode) {
272 case DRM_MODE_DPMS_ON:
273 radeon_crtc->enabled = true;
274 atombios_enable_crtc(crtc, ATOM_ENABLE);
275 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
276 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
277 atombios_blank_crtc(crtc, ATOM_DISABLE);
278 if (dev->num_crtcs > radeon_crtc->crtc_id)
279 drm_crtc_vblank_on(crtc);
280 radeon_crtc_load_lut(crtc);
281 break;
282 case DRM_MODE_DPMS_STANDBY:
283 case DRM_MODE_DPMS_SUSPEND:
284 case DRM_MODE_DPMS_OFF:
285 if (dev->num_crtcs > radeon_crtc->crtc_id)
286 drm_crtc_vblank_off(crtc);
287 if (radeon_crtc->enabled)
288 atombios_blank_crtc(crtc, ATOM_ENABLE);
289 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
290 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
291 atombios_enable_crtc(crtc, ATOM_DISABLE);
292 radeon_crtc->enabled = false;
293 break;
294 }
295 /* adjust pm to dpms */
296 radeon_pm_compute_clocks(rdev);
297 }
298
299 static void
300 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
301 struct drm_display_mode *mode)
302 {
303 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
304 struct drm_device *dev = crtc->dev;
305 struct radeon_device *rdev = dev->dev_private;
306 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
307 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
308 u16 misc = 0;
309
310 memset(&args, 0, sizeof(args));
311 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
312 args.usH_Blanking_Time =
313 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
314 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
315 args.usV_Blanking_Time =
316 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
317 args.usH_SyncOffset =
318 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
319 args.usH_SyncWidth =
320 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
321 args.usV_SyncOffset =
322 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
323 args.usV_SyncWidth =
324 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
325 args.ucH_Border = radeon_crtc->h_border;
326 args.ucV_Border = radeon_crtc->v_border;
327
328 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
329 misc |= ATOM_VSYNC_POLARITY;
330 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
331 misc |= ATOM_HSYNC_POLARITY;
332 if (mode->flags & DRM_MODE_FLAG_CSYNC)
333 misc |= ATOM_COMPOSITESYNC;
334 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
335 misc |= ATOM_INTERLACE;
336 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
337 misc |= ATOM_DOUBLE_CLOCK_MODE;
338 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
339 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2;
340
341 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
342 args.ucCRTC = radeon_crtc->crtc_id;
343
344 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
345 }
346
347 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
348 struct drm_display_mode *mode)
349 {
350 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
351 struct drm_device *dev = crtc->dev;
352 struct radeon_device *rdev = dev->dev_private;
353 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
354 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
355 u16 misc = 0;
356
357 memset(&args, 0, sizeof(args));
358 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
359 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
360 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
361 args.usH_SyncWidth =
362 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
363 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
364 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
365 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
366 args.usV_SyncWidth =
367 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
368
369 args.ucOverscanRight = radeon_crtc->h_border;
370 args.ucOverscanLeft = radeon_crtc->h_border;
371 args.ucOverscanBottom = radeon_crtc->v_border;
372 args.ucOverscanTop = radeon_crtc->v_border;
373
374 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
375 misc |= ATOM_VSYNC_POLARITY;
376 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
377 misc |= ATOM_HSYNC_POLARITY;
378 if (mode->flags & DRM_MODE_FLAG_CSYNC)
379 misc |= ATOM_COMPOSITESYNC;
380 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
381 misc |= ATOM_INTERLACE;
382 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
383 misc |= ATOM_DOUBLE_CLOCK_MODE;
384 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
385 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2;
386
387 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
388 args.ucCRTC = radeon_crtc->crtc_id;
389
390 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
391 }
392
393 static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
394 {
395 u32 ss_cntl;
396
397 if (ASIC_IS_DCE4(rdev)) {
398 switch (pll_id) {
399 case ATOM_PPLL1:
400 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
401 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
402 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
403 break;
404 case ATOM_PPLL2:
405 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
406 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
407 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
408 break;
409 case ATOM_DCPLL:
410 case ATOM_PPLL_INVALID:
411 return;
412 }
413 } else if (ASIC_IS_AVIVO(rdev)) {
414 switch (pll_id) {
415 case ATOM_PPLL1:
416 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
417 ss_cntl &= ~1;
418 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
419 break;
420 case ATOM_PPLL2:
421 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
422 ss_cntl &= ~1;
423 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
424 break;
425 case ATOM_DCPLL:
426 case ATOM_PPLL_INVALID:
427 return;
428 }
429 }
430 }
431
432
433 union atom_enable_ss {
434 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
435 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
436 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
437 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
438 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
439 };
440
441 static void atombios_crtc_program_ss(struct radeon_device *rdev,
442 int enable,
443 int pll_id,
444 int crtc_id,
445 struct radeon_atom_ss *ss)
446 {
447 unsigned i;
448 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
449 union atom_enable_ss args;
450
451 if (enable) {
452 /* Don't mess with SS if percentage is 0 or external ss.
453 * SS is already disabled previously, and disabling it
454 * again can cause display problems if the pll is already
455 * programmed.
456 */
457 if (ss->percentage == 0)
458 return;
459 if (ss->type & ATOM_EXTERNAL_SS_MASK)
460 return;
461 } else {
462 for (i = 0; i < rdev->num_crtc; i++) {
463 if (rdev->mode_info.crtcs[i] &&
464 rdev->mode_info.crtcs[i]->enabled &&
465 i != crtc_id &&
466 pll_id == rdev->mode_info.crtcs[i]->pll_id) {
467 /* one other crtc is using this pll don't turn
468 * off spread spectrum as it might turn off
469 * display on active crtc
470 */
471 return;
472 }
473 }
474 }
475
476 memset(&args, 0, sizeof(args));
477
478 if (ASIC_IS_DCE5(rdev)) {
479 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
480 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
481 switch (pll_id) {
482 case ATOM_PPLL1:
483 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
484 break;
485 case ATOM_PPLL2:
486 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
487 break;
488 case ATOM_DCPLL:
489 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
490 break;
491 case ATOM_PPLL_INVALID:
492 return;
493 }
494 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
495 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
496 args.v3.ucEnable = enable;
497 } else if (ASIC_IS_DCE4(rdev)) {
498 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
499 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
500 switch (pll_id) {
501 case ATOM_PPLL1:
502 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
503 break;
504 case ATOM_PPLL2:
505 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
506 break;
507 case ATOM_DCPLL:
508 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
509 break;
510 case ATOM_PPLL_INVALID:
511 return;
512 }
513 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
514 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
515 args.v2.ucEnable = enable;
516 } else if (ASIC_IS_DCE3(rdev)) {
517 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
518 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
519 args.v1.ucSpreadSpectrumStep = ss->step;
520 args.v1.ucSpreadSpectrumDelay = ss->delay;
521 args.v1.ucSpreadSpectrumRange = ss->range;
522 args.v1.ucPpll = pll_id;
523 args.v1.ucEnable = enable;
524 } else if (ASIC_IS_AVIVO(rdev)) {
525 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
526 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
527 atombios_disable_ss(rdev, pll_id);
528 return;
529 }
530 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
531 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
532 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
533 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
534 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
535 args.lvds_ss_2.ucEnable = enable;
536 } else {
537 if (enable == ATOM_DISABLE) {
538 atombios_disable_ss(rdev, pll_id);
539 return;
540 }
541 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
542 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
543 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
544 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
545 args.lvds_ss.ucEnable = enable;
546 }
547 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
548 }
549
550 union adjust_pixel_clock {
551 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
552 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
553 };
554
555 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
556 struct drm_display_mode *mode)
557 {
558 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
559 struct drm_device *dev = crtc->dev;
560 struct radeon_device *rdev = dev->dev_private;
561 struct drm_encoder *encoder = radeon_crtc->encoder;
562 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
563 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
564 u32 adjusted_clock = mode->clock;
565 int encoder_mode = atombios_get_encoder_mode(encoder);
566 u32 dp_clock = mode->clock;
567 u32 clock = mode->clock;
568 int bpc = radeon_crtc->bpc;
569 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
570
571 /* reset the pll flags */
572 radeon_crtc->pll_flags = 0;
573
574 if (ASIC_IS_AVIVO(rdev)) {
575 if ((rdev->family == CHIP_RS600) ||
576 (rdev->family == CHIP_RS690) ||
577 (rdev->family == CHIP_RS740))
578 radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
579 RADEON_PLL_PREFER_CLOSEST_LOWER);
580
581 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
582 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
583 else
584 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
585
586 if (rdev->family < CHIP_RV770)
587 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
588 /* use frac fb div on APUs */
589 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
590 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
591 /* use frac fb div on RS780/RS880 */
592 if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
593 && !radeon_crtc->ss_enabled)
594 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
595 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
596 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
597 } else {
598 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;
599
600 if (mode->clock > 200000) /* range limits??? */
601 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
602 else
603 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
604 }
605
606 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
607 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
608 if (connector) {
609 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
610 struct radeon_connector_atom_dig *dig_connector =
611 radeon_connector->con_priv;
612
613 dp_clock = dig_connector->dp_clock;
614 }
615 }
616
617 if (radeon_encoder->is_mst_encoder) {
618 struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv;
619 struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv;
620
621 dp_clock = dig_connector->dp_clock;
622 }
623
624 /* use recommended ref_div for ss */
625 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
626 if (radeon_crtc->ss_enabled) {
627 if (radeon_crtc->ss.refdiv) {
628 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
629 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
630 if (rdev->family >= CHIP_RV770)
631 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
632 }
633 }
634 }
635
636 if (ASIC_IS_AVIVO(rdev)) {
637 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
638 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
639 adjusted_clock = mode->clock * 2;
640 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
641 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
642 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
643 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;
644 } else {
645 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
646 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
647 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
648 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
649 }
650
651 /* adjust pll for deep color modes */
652 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
653 switch (bpc) {
654 case 8:
655 default:
656 break;
657 case 10:
658 clock = (clock * 5) / 4;
659 break;
660 case 12:
661 clock = (clock * 3) / 2;
662 break;
663 case 16:
664 clock = clock * 2;
665 break;
666 }
667 }
668
669 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
670 * accordingly based on the encoder/transmitter to work around
671 * special hw requirements.
672 */
673 if (ASIC_IS_DCE3(rdev)) {
674 union adjust_pixel_clock args;
675 u8 frev, crev;
676 int index;
677
678 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
679 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
680 &crev))
681 return adjusted_clock;
682
683 memset(&args, 0, sizeof(args));
684
685 switch (frev) {
686 case 1:
687 switch (crev) {
688 case 1:
689 case 2:
690 args.v1.usPixelClock = cpu_to_le16(clock / 10);
691 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
692 args.v1.ucEncodeMode = encoder_mode;
693 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
694 args.v1.ucConfig |=
695 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
696
697 atom_execute_table(rdev->mode_info.atom_context,
698 index, (uint32_t *)&args);
699 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
700 break;
701 case 3:
702 args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);
703 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
704 args.v3.sInput.ucEncodeMode = encoder_mode;
705 args.v3.sInput.ucDispPllConfig = 0;
706 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
707 args.v3.sInput.ucDispPllConfig |=
708 DISPPLL_CONFIG_SS_ENABLE;
709 if (ENCODER_MODE_IS_DP(encoder_mode)) {
710 args.v3.sInput.ucDispPllConfig |=
711 DISPPLL_CONFIG_COHERENT_MODE;
712 /* 16200 or 27000 */
713 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
714 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
715 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
716 if (dig->coherent_mode)
717 args.v3.sInput.ucDispPllConfig |=
718 DISPPLL_CONFIG_COHERENT_MODE;
719 if (is_duallink)
720 args.v3.sInput.ucDispPllConfig |=
721 DISPPLL_CONFIG_DUAL_LINK;
722 }
723 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
724 ENCODER_OBJECT_ID_NONE)
725 args.v3.sInput.ucExtTransmitterID =
726 radeon_encoder_get_dp_bridge_encoder_id(encoder);
727 else
728 args.v3.sInput.ucExtTransmitterID = 0;
729
730 atom_execute_table(rdev->mode_info.atom_context,
731 index, (uint32_t *)&args);
732 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
733 if (args.v3.sOutput.ucRefDiv) {
734 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
735 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
736 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
737 }
738 if (args.v3.sOutput.ucPostDiv) {
739 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
740 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;
741 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
742 }
743 break;
744 default:
745 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
746 return adjusted_clock;
747 }
748 break;
749 default:
750 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
751 return adjusted_clock;
752 }
753 }
754 return adjusted_clock;
755 }
756
757 union set_pixel_clock {
758 SET_PIXEL_CLOCK_PS_ALLOCATION base;
759 PIXEL_CLOCK_PARAMETERS v1;
760 PIXEL_CLOCK_PARAMETERS_V2 v2;
761 PIXEL_CLOCK_PARAMETERS_V3 v3;
762 PIXEL_CLOCK_PARAMETERS_V5 v5;
763 PIXEL_CLOCK_PARAMETERS_V6 v6;
764 };
765
766 /* on DCE5, make sure the voltage is high enough to support the
767 * required disp clk.
768 */
769 static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
770 u32 dispclk)
771 {
772 u8 frev, crev;
773 int index;
774 union set_pixel_clock args;
775
776 memset(&args, 0, sizeof(args));
777
778 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
779 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
780 &crev))
781 return;
782
783 switch (frev) {
784 case 1:
785 switch (crev) {
786 case 5:
787 /* if the default dcpll clock is specified,
788 * SetPixelClock provides the dividers
789 */
790 args.v5.ucCRTC = ATOM_CRTC_INVALID;
791 args.v5.usPixelClock = cpu_to_le16(dispclk);
792 args.v5.ucPpll = ATOM_DCPLL;
793 break;
794 case 6:
795 /* if the default dcpll clock is specified,
796 * SetPixelClock provides the dividers
797 */
798 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
799 if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
800 args.v6.ucPpll = ATOM_EXT_PLL1;
801 else if (ASIC_IS_DCE6(rdev))
802 args.v6.ucPpll = ATOM_PPLL0;
803 else
804 args.v6.ucPpll = ATOM_DCPLL;
805 break;
806 default:
807 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
808 return;
809 }
810 break;
811 default:
812 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
813 return;
814 }
815 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
816 }
817
818 static void atombios_crtc_program_pll(struct drm_crtc *crtc,
819 u32 crtc_id,
820 int pll_id,
821 u32 encoder_mode,
822 u32 encoder_id,
823 u32 clock,
824 u32 ref_div,
825 u32 fb_div,
826 u32 frac_fb_div,
827 u32 post_div,
828 int bpc,
829 bool ss_enabled,
830 struct radeon_atom_ss *ss)
831 {
832 struct drm_device *dev = crtc->dev;
833 struct radeon_device *rdev = dev->dev_private;
834 u8 frev, crev;
835 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
836 union set_pixel_clock args;
837
838 memset(&args, 0, sizeof(args));
839
840 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
841 &crev))
842 return;
843
844 switch (frev) {
845 case 1:
846 switch (crev) {
847 case 1:
848 if (clock == ATOM_DISABLE)
849 return;
850 args.v1.usPixelClock = cpu_to_le16(clock / 10);
851 args.v1.usRefDiv = cpu_to_le16(ref_div);
852 args.v1.usFbDiv = cpu_to_le16(fb_div);
853 args.v1.ucFracFbDiv = frac_fb_div;
854 args.v1.ucPostDiv = post_div;
855 args.v1.ucPpll = pll_id;
856 args.v1.ucCRTC = crtc_id;
857 args.v1.ucRefDivSrc = 1;
858 break;
859 case 2:
860 args.v2.usPixelClock = cpu_to_le16(clock / 10);
861 args.v2.usRefDiv = cpu_to_le16(ref_div);
862 args.v2.usFbDiv = cpu_to_le16(fb_div);
863 args.v2.ucFracFbDiv = frac_fb_div;
864 args.v2.ucPostDiv = post_div;
865 args.v2.ucPpll = pll_id;
866 args.v2.ucCRTC = crtc_id;
867 args.v2.ucRefDivSrc = 1;
868 break;
869 case 3:
870 args.v3.usPixelClock = cpu_to_le16(clock / 10);
871 args.v3.usRefDiv = cpu_to_le16(ref_div);
872 args.v3.usFbDiv = cpu_to_le16(fb_div);
873 args.v3.ucFracFbDiv = frac_fb_div;
874 args.v3.ucPostDiv = post_div;
875 args.v3.ucPpll = pll_id;
876 if (crtc_id == ATOM_CRTC2)
877 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
878 else
879 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
880 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
881 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
882 args.v3.ucTransmitterId = encoder_id;
883 args.v3.ucEncoderMode = encoder_mode;
884 break;
885 case 5:
886 args.v5.ucCRTC = crtc_id;
887 args.v5.usPixelClock = cpu_to_le16(clock / 10);
888 args.v5.ucRefDiv = ref_div;
889 args.v5.usFbDiv = cpu_to_le16(fb_div);
890 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
891 args.v5.ucPostDiv = post_div;
892 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
893 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
894 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
895 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
896 switch (bpc) {
897 case 8:
898 default:
899 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
900 break;
901 case 10:
902 /* yes this is correct, the atom define is wrong */
903 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP;
904 break;
905 case 12:
906 /* yes this is correct, the atom define is wrong */
907 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
908 break;
909 }
910 }
911 args.v5.ucTransmitterID = encoder_id;
912 args.v5.ucEncoderMode = encoder_mode;
913 args.v5.ucPpll = pll_id;
914 break;
915 case 6:
916 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
917 args.v6.ucRefDiv = ref_div;
918 args.v6.usFbDiv = cpu_to_le16(fb_div);
919 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
920 args.v6.ucPostDiv = post_div;
921 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
922 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
923 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
924 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
925 switch (bpc) {
926 case 8:
927 default:
928 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
929 break;
930 case 10:
931 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6;
932 break;
933 case 12:
934 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6;
935 break;
936 case 16:
937 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
938 break;
939 }
940 }
941 args.v6.ucTransmitterID = encoder_id;
942 args.v6.ucEncoderMode = encoder_mode;
943 args.v6.ucPpll = pll_id;
944 break;
945 default:
946 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
947 return;
948 }
949 break;
950 default:
951 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
952 return;
953 }
954
955 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
956 }
957
958 static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
959 {
960 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
961 struct drm_device *dev = crtc->dev;
962 struct radeon_device *rdev = dev->dev_private;
963 struct radeon_encoder *radeon_encoder =
964 to_radeon_encoder(radeon_crtc->encoder);
965 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
966
967 radeon_crtc->bpc = 8;
968 radeon_crtc->ss_enabled = false;
969
970 if (radeon_encoder->is_mst_encoder) {
971 radeon_dp_mst_prepare_pll(crtc, mode);
972 } else if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
973 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
974 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
975 struct drm_connector *connector =
976 radeon_get_connector_for_encoder(radeon_crtc->encoder);
977 struct radeon_connector *radeon_connector =
978 to_radeon_connector(connector);
979 struct radeon_connector_atom_dig *dig_connector =
980 radeon_connector->con_priv;
981 int dp_clock;
982
983 /* Assign mode clock for hdmi deep color max clock limit check */
984 radeon_connector->pixelclock_for_modeset = mode->clock;
985 radeon_crtc->bpc = radeon_get_monitor_bpc(connector);
986
987 switch (encoder_mode) {
988 case ATOM_ENCODER_MODE_DP_MST:
989 case ATOM_ENCODER_MODE_DP:
990 /* DP/eDP */
991 dp_clock = dig_connector->dp_clock / 10;
992 if (ASIC_IS_DCE4(rdev))
993 radeon_crtc->ss_enabled =
994 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
995 ASIC_INTERNAL_SS_ON_DP,
996 dp_clock);
997 else {
998 if (dp_clock == 16200) {
999 radeon_crtc->ss_enabled =
1000 radeon_atombios_get_ppll_ss_info(rdev,
1001 &radeon_crtc->ss,
1002 ATOM_DP_SS_ID2);
1003 if (!radeon_crtc->ss_enabled)
1004 radeon_crtc->ss_enabled =
1005 radeon_atombios_get_ppll_ss_info(rdev,
1006 &radeon_crtc->ss,
1007 ATOM_DP_SS_ID1);
1008 } else {
1009 radeon_crtc->ss_enabled =
1010 radeon_atombios_get_ppll_ss_info(rdev,
1011 &radeon_crtc->ss,
1012 ATOM_DP_SS_ID1);
1013 }
1014 /* disable spread spectrum on DCE3 DP */
1015 radeon_crtc->ss_enabled = false;
1016 }
1017 break;
1018 case ATOM_ENCODER_MODE_LVDS:
1019 if (ASIC_IS_DCE4(rdev))
1020 radeon_crtc->ss_enabled =
1021 radeon_atombios_get_asic_ss_info(rdev,
1022 &radeon_crtc->ss,
1023 dig->lcd_ss_id,
1024 mode->clock / 10);
1025 else
1026 radeon_crtc->ss_enabled =
1027 radeon_atombios_get_ppll_ss_info(rdev,
1028 &radeon_crtc->ss,
1029 dig->lcd_ss_id);
1030 break;
1031 case ATOM_ENCODER_MODE_DVI:
1032 if (ASIC_IS_DCE4(rdev))
1033 radeon_crtc->ss_enabled =
1034 radeon_atombios_get_asic_ss_info(rdev,
1035 &radeon_crtc->ss,
1036 ASIC_INTERNAL_SS_ON_TMDS,
1037 mode->clock / 10);
1038 break;
1039 case ATOM_ENCODER_MODE_HDMI:
1040 if (ASIC_IS_DCE4(rdev))
1041 radeon_crtc->ss_enabled =
1042 radeon_atombios_get_asic_ss_info(rdev,
1043 &radeon_crtc->ss,
1044 ASIC_INTERNAL_SS_ON_HDMI,
1045 mode->clock / 10);
1046 break;
1047 default:
1048 break;
1049 }
1050 }
1051
1052 /* adjust pixel clock as needed */
1053 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);
1054
1055 return true;
1056 }
1057
1058 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
1059 {
1060 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1061 struct drm_device *dev = crtc->dev;
1062 struct radeon_device *rdev = dev->dev_private;
1063 struct radeon_encoder *radeon_encoder =
1064 to_radeon_encoder(radeon_crtc->encoder);
1065 u32 pll_clock = mode->clock;
1066 u32 clock = mode->clock;
1067 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
1068 struct radeon_pll *pll;
1069 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
1070
1071 /* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */
1072 if (ASIC_IS_DCE5(rdev) &&
1073 (encoder_mode == ATOM_ENCODER_MODE_HDMI) &&
1074 (radeon_crtc->bpc > 8))
1075 clock = radeon_crtc->adjusted_clock;
1076
1077 switch (radeon_crtc->pll_id) {
1078 case ATOM_PPLL1:
1079 pll = &rdev->clock.p1pll;
1080 break;
1081 case ATOM_PPLL2:
1082 pll = &rdev->clock.p2pll;
1083 break;
1084 case ATOM_DCPLL:
1085 case ATOM_PPLL_INVALID:
1086 default:
1087 pll = &rdev->clock.dcpll;
1088 break;
1089 }
1090
1091 /* update pll params */
1092 pll->flags = radeon_crtc->pll_flags;
1093 pll->reference_div = radeon_crtc->pll_reference_div;
1094 pll->post_div = radeon_crtc->pll_post_div;
1095
1096 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1097 /* TV seems to prefer the legacy algo on some boards */
1098 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1099 &fb_div, &frac_fb_div, &ref_div, &post_div);
1100 else if (ASIC_IS_AVIVO(rdev))
1101 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,
1102 &fb_div, &frac_fb_div, &ref_div, &post_div);
1103 else
1104 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1105 &fb_div, &frac_fb_div, &ref_div, &post_div);
1106
1107 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,
1108 radeon_crtc->crtc_id, &radeon_crtc->ss);
1109
1110 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1111 encoder_mode, radeon_encoder->encoder_id, clock,
1112 ref_div, fb_div, frac_fb_div, post_div,
1113 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);
1114
1115 if (radeon_crtc->ss_enabled) {
1116 /* calculate ss amount and step size */
1117 if (ASIC_IS_DCE4(rdev)) {
1118 u32 step_size;
1119 u32 amount = (((fb_div * 10) + frac_fb_div) *
1120 (u32)radeon_crtc->ss.percentage) /
1121 (100 * (u32)radeon_crtc->ss.percentage_divider);
1122 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1123 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1124 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1125 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1126 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1127 (125 * 25 * pll->reference_freq / 100);
1128 else
1129 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1130 (125 * 25 * pll->reference_freq / 100);
1131 radeon_crtc->ss.step = step_size;
1132 }
1133
1134 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,
1135 radeon_crtc->crtc_id, &radeon_crtc->ss);
1136 }
1137 }
1138
1139 static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1140 struct drm_framebuffer *fb,
1141 int x, int y, int atomic)
1142 {
1143 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1144 struct drm_device *dev = crtc->dev;
1145 struct radeon_device *rdev = dev->dev_private;
1146 struct radeon_framebuffer *radeon_fb;
1147 struct drm_framebuffer *target_fb;
1148 struct drm_gem_object *obj;
1149 struct radeon_bo *rbo;
1150 uint64_t fb_location;
1151 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1152 unsigned bankw, bankh, mtaspect, tile_split;
1153 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1154 u32 tmp, viewport_w, viewport_h;
1155 int r;
1156 bool bypass_lut = false;
1157
1158 /* no fb bound */
1159 if (!atomic && !crtc->primary->fb) {
1160 DRM_DEBUG_KMS("No FB bound\n");
1161 return 0;
1162 }
1163
1164 if (atomic) {
1165 radeon_fb = to_radeon_framebuffer(fb);
1166 target_fb = fb;
1167 }
1168 else {
1169 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1170 target_fb = crtc->primary->fb;
1171 }
1172
1173 /* If atomic, assume fb object is pinned & idle & fenced and
1174 * just update base pointers
1175 */
1176 obj = radeon_fb->obj;
1177 rbo = gem_to_radeon_bo(obj);
1178 r = radeon_bo_reserve(rbo, false);
1179 if (unlikely(r != 0))
1180 return r;
1181
1182 if (atomic)
1183 fb_location = radeon_bo_gpu_offset(rbo);
1184 else {
1185 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1186 if (unlikely(r != 0)) {
1187 radeon_bo_unreserve(rbo);
1188 return -EINVAL;
1189 }
1190 }
1191
1192 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1193 radeon_bo_unreserve(rbo);
1194
1195 switch (target_fb->pixel_format) {
1196 case DRM_FORMAT_C8:
1197 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1198 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1199 break;
1200 case DRM_FORMAT_XRGB4444:
1201 case DRM_FORMAT_ARGB4444:
1202 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1203 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444));
1204 #ifdef __BIG_ENDIAN
1205 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1206 #endif
1207 break;
1208 case DRM_FORMAT_XRGB1555:
1209 case DRM_FORMAT_ARGB1555:
1210 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1211 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1212 #ifdef __BIG_ENDIAN
1213 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1214 #endif
1215 break;
1216 case DRM_FORMAT_BGRX5551:
1217 case DRM_FORMAT_BGRA5551:
1218 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1219 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551));
1220 #ifdef __BIG_ENDIAN
1221 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1222 #endif
1223 break;
1224 case DRM_FORMAT_RGB565:
1225 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1226 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1227 #ifdef __BIG_ENDIAN
1228 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1229 #endif
1230 break;
1231 case DRM_FORMAT_XRGB8888:
1232 case DRM_FORMAT_ARGB8888:
1233 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1234 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1235 #ifdef __BIG_ENDIAN
1236 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1237 #endif
1238 break;
1239 case DRM_FORMAT_XRGB2101010:
1240 case DRM_FORMAT_ARGB2101010:
1241 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1242 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010));
1243 #ifdef __BIG_ENDIAN
1244 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1245 #endif
1246 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1247 bypass_lut = true;
1248 break;
1249 case DRM_FORMAT_BGRX1010102:
1250 case DRM_FORMAT_BGRA1010102:
1251 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1252 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102));
1253 #ifdef __BIG_ENDIAN
1254 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1255 #endif
1256 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1257 bypass_lut = true;
1258 break;
1259 default:
1260 DRM_ERROR("Unsupported screen format %s\n",
1261 drm_get_format_name(target_fb->pixel_format));
1262 return -EINVAL;
1263 }
1264
1265 if (tiling_flags & RADEON_TILING_MACRO) {
1266 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1267
1268 /* Set NUM_BANKS. */
1269 if (rdev->family >= CHIP_TAHITI) {
1270 unsigned index, num_banks;
1271
1272 if (rdev->family >= CHIP_BONAIRE) {
1273 unsigned tileb, tile_split_bytes;
1274
1275 /* Calculate the macrotile mode index. */
1276 tile_split_bytes = 64 << tile_split;
1277 tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
1278 tileb = min(tile_split_bytes, tileb);
1279
1280 for (index = 0; tileb > 64; index++)
1281 tileb >>= 1;
1282
1283 if (index >= 16) {
1284 DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
1285 target_fb->bits_per_pixel, tile_split);
1286 return -EINVAL;
1287 }
1288
1289 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
1290 } else {
1291 switch (target_fb->bits_per_pixel) {
1292 case 8:
1293 index = 10;
1294 break;
1295 case 16:
1296 index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
1297 break;
1298 default:
1299 case 32:
1300 index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
1301 break;
1302 }
1303
1304 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
1305 }
1306
1307 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
1308 } else {
1309 /* NI and older. */
1310 if (rdev->family >= CHIP_CAYMAN)
1311 tmp = rdev->config.cayman.tile_config;
1312 else
1313 tmp = rdev->config.evergreen.tile_config;
1314
1315 switch ((tmp & 0xf0) >> 4) {
1316 case 0: /* 4 banks */
1317 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1318 break;
1319 case 1: /* 8 banks */
1320 default:
1321 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1322 break;
1323 case 2: /* 16 banks */
1324 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1325 break;
1326 }
1327 }
1328
1329 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1330 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1331 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1332 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1333 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1334 if (rdev->family >= CHIP_BONAIRE) {
1335 /* XXX need to know more about the surface tiling mode */
1336 fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING);
1337 }
1338 } else if (tiling_flags & RADEON_TILING_MICRO)
1339 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1340
1341 if (rdev->family >= CHIP_BONAIRE) {
1342 /* Read the pipe config from the 2D TILED SCANOUT mode.
1343 * It should be the same for the other modes too, but not all
1344 * modes set the pipe config field. */
1345 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;
1346
1347 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config);
1348 } else if ((rdev->family == CHIP_TAHITI) ||
1349 (rdev->family == CHIP_PITCAIRN))
1350 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
1351 else if ((rdev->family == CHIP_VERDE) ||
1352 (rdev->family == CHIP_OLAND) ||
1353 (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */
1354 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1355
1356 switch (radeon_crtc->crtc_id) {
1357 case 0:
1358 WREG32(AVIVO_D1VGA_CONTROL, 0);
1359 break;
1360 case 1:
1361 WREG32(AVIVO_D2VGA_CONTROL, 0);
1362 break;
1363 case 2:
1364 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1365 break;
1366 case 3:
1367 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1368 break;
1369 case 4:
1370 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1371 break;
1372 case 5:
1373 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1374 break;
1375 default:
1376 break;
1377 }
1378
1379 /* Make sure surface address is updated at vertical blank rather than
1380 * horizontal blank
1381 */
1382 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);
1383
1384 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1385 upper_32_bits(fb_location));
1386 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1387 upper_32_bits(fb_location));
1388 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1389 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1390 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1391 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1392 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1393 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1394
1395 /*
1396 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1397 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1398 * retain the full precision throughout the pipeline.
1399 */
1400 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset,
1401 (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0),
1402 ~EVERGREEN_LUT_10BIT_BYPASS_EN);
1403
1404 if (bypass_lut)
1405 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1406
1407 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1408 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1409 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1410 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1411 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1412 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1413
1414 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1415 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1416 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1417
1418 if (rdev->family >= CHIP_BONAIRE)
1419 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1420 target_fb->height);
1421 else
1422 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1423 target_fb->height);
1424 x &= ~3;
1425 y &= ~1;
1426 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1427 (x << 16) | y);
1428 viewport_w = crtc->mode.hdisplay;
1429 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1430 if ((rdev->family >= CHIP_BONAIRE) &&
1431 (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE))
1432 viewport_h *= 2;
1433 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1434 (viewport_w << 16) | viewport_h);
1435
1436 /* set pageflip to happen only at start of vblank interval (front porch) */
1437 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);
1438
1439 if (!atomic && fb && fb != crtc->primary->fb) {
1440 radeon_fb = to_radeon_framebuffer(fb);
1441 rbo = gem_to_radeon_bo(radeon_fb->obj);
1442 r = radeon_bo_reserve(rbo, false);
1443 if (unlikely(r != 0))
1444 return r;
1445 radeon_bo_unpin(rbo);
1446 radeon_bo_unreserve(rbo);
1447 }
1448
1449 /* Bytes per pixel may have changed */
1450 radeon_bandwidth_update(rdev);
1451
1452 return 0;
1453 }
1454
1455 static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1456 struct drm_framebuffer *fb,
1457 int x, int y, int atomic)
1458 {
1459 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1460 struct drm_device *dev = crtc->dev;
1461 struct radeon_device *rdev = dev->dev_private;
1462 struct radeon_framebuffer *radeon_fb;
1463 struct drm_gem_object *obj;
1464 struct radeon_bo *rbo;
1465 struct drm_framebuffer *target_fb;
1466 uint64_t fb_location;
1467 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1468 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1469 u32 viewport_w, viewport_h;
1470 int r;
1471 bool bypass_lut = false;
1472
1473 /* no fb bound */
1474 if (!atomic && !crtc->primary->fb) {
1475 DRM_DEBUG_KMS("No FB bound\n");
1476 return 0;
1477 }
1478
1479 if (atomic) {
1480 radeon_fb = to_radeon_framebuffer(fb);
1481 target_fb = fb;
1482 }
1483 else {
1484 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1485 target_fb = crtc->primary->fb;
1486 }
1487
1488 obj = radeon_fb->obj;
1489 rbo = gem_to_radeon_bo(obj);
1490 r = radeon_bo_reserve(rbo, false);
1491 if (unlikely(r != 0))
1492 return r;
1493
1494 /* If atomic, assume fb object is pinned & idle & fenced and
1495 * just update base pointers
1496 */
1497 if (atomic)
1498 fb_location = radeon_bo_gpu_offset(rbo);
1499 else {
1500 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1501 if (unlikely(r != 0)) {
1502 radeon_bo_unreserve(rbo);
1503 return -EINVAL;
1504 }
1505 }
1506 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1507 radeon_bo_unreserve(rbo);
1508
1509 switch (target_fb->pixel_format) {
1510 case DRM_FORMAT_C8:
1511 fb_format =
1512 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1513 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1514 break;
1515 case DRM_FORMAT_XRGB4444:
1516 case DRM_FORMAT_ARGB4444:
1517 fb_format =
1518 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1519 AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444;
1520 #ifdef __BIG_ENDIAN
1521 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1522 #endif
1523 break;
1524 case DRM_FORMAT_XRGB1555:
1525 fb_format =
1526 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1527 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1528 #ifdef __BIG_ENDIAN
1529 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1530 #endif
1531 break;
1532 case DRM_FORMAT_RGB565:
1533 fb_format =
1534 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1535 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1536 #ifdef __BIG_ENDIAN
1537 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1538 #endif
1539 break;
1540 case DRM_FORMAT_XRGB8888:
1541 case DRM_FORMAT_ARGB8888:
1542 fb_format =
1543 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1544 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1545 #ifdef __BIG_ENDIAN
1546 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1547 #endif
1548 break;
1549 case DRM_FORMAT_XRGB2101010:
1550 case DRM_FORMAT_ARGB2101010:
1551 fb_format =
1552 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1553 AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010;
1554 #ifdef __BIG_ENDIAN
1555 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1556 #endif
1557 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1558 bypass_lut = true;
1559 break;
1560 default:
1561 DRM_ERROR("Unsupported screen format %s\n",
1562 drm_get_format_name(target_fb->pixel_format));
1563 return -EINVAL;
1564 }
1565
1566 if (rdev->family >= CHIP_R600) {
1567 if (tiling_flags & RADEON_TILING_MACRO)
1568 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1569 else if (tiling_flags & RADEON_TILING_MICRO)
1570 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1571 } else {
1572 if (tiling_flags & RADEON_TILING_MACRO)
1573 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1574
1575 if (tiling_flags & RADEON_TILING_MICRO)
1576 fb_format |= AVIVO_D1GRPH_TILED;
1577 }
1578
1579 if (radeon_crtc->crtc_id == 0)
1580 WREG32(AVIVO_D1VGA_CONTROL, 0);
1581 else
1582 WREG32(AVIVO_D2VGA_CONTROL, 0);
1583
1584 /* Make sure surface address is update at vertical blank rather than
1585 * horizontal blank
1586 */
1587 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);
1588
1589 if (rdev->family >= CHIP_RV770) {
1590 if (radeon_crtc->crtc_id) {
1591 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1592 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1593 } else {
1594 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1595 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1596 }
1597 }
1598 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1599 (u32) fb_location);
1600 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1601 radeon_crtc->crtc_offset, (u32) fb_location);
1602 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1603 if (rdev->family >= CHIP_R600)
1604 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1605
1606 /* LUT only has 256 slots for 8 bpc fb. Bypass for > 8 bpc scanout for precision */
1607 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset,
1608 (bypass_lut ? AVIVO_LUT_10BIT_BYPASS_EN : 0), ~AVIVO_LUT_10BIT_BYPASS_EN);
1609
1610 if (bypass_lut)
1611 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1612
1613 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1614 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1615 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1616 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1617 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1618 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1619
1620 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1621 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1622 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1623
1624 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1625 target_fb->height);
1626 x &= ~3;
1627 y &= ~1;
1628 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1629 (x << 16) | y);
1630 viewport_w = crtc->mode.hdisplay;
1631 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1632 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1633 (viewport_w << 16) | viewport_h);
1634
1635 /* set pageflip to happen only at start of vblank interval (front porch) */
1636 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);
1637
1638 if (!atomic && fb && fb != crtc->primary->fb) {
1639 radeon_fb = to_radeon_framebuffer(fb);
1640 rbo = gem_to_radeon_bo(radeon_fb->obj);
1641 r = radeon_bo_reserve(rbo, false);
1642 if (unlikely(r != 0))
1643 return r;
1644 radeon_bo_unpin(rbo);
1645 radeon_bo_unreserve(rbo);
1646 }
1647
1648 /* Bytes per pixel may have changed */
1649 radeon_bandwidth_update(rdev);
1650
1651 return 0;
1652 }
1653
1654 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1655 struct drm_framebuffer *old_fb)
1656 {
1657 struct drm_device *dev = crtc->dev;
1658 struct radeon_device *rdev = dev->dev_private;
1659
1660 if (ASIC_IS_DCE4(rdev))
1661 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1662 else if (ASIC_IS_AVIVO(rdev))
1663 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1664 else
1665 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1666 }
1667
1668 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1669 struct drm_framebuffer *fb,
1670 int x, int y, enum mode_set_atomic state)
1671 {
1672 struct drm_device *dev = crtc->dev;
1673 struct radeon_device *rdev = dev->dev_private;
1674
1675 if (ASIC_IS_DCE4(rdev))
1676 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1677 else if (ASIC_IS_AVIVO(rdev))
1678 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1679 else
1680 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1681 }
1682
1683 /* properly set additional regs when using atombios */
1684 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1685 {
1686 struct drm_device *dev = crtc->dev;
1687 struct radeon_device *rdev = dev->dev_private;
1688 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1689 u32 disp_merge_cntl;
1690
1691 switch (radeon_crtc->crtc_id) {
1692 case 0:
1693 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1694 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1695 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1696 break;
1697 case 1:
1698 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1699 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1700 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1701 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1702 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1703 break;
1704 }
1705 }
1706
1707 /**
1708 * radeon_get_pll_use_mask - look up a mask of which pplls are in use
1709 *
1710 * @crtc: drm crtc
1711 *
1712 * Returns the mask of which PPLLs (Pixel PLLs) are in use.
1713 */
1714 static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
1715 {
1716 struct drm_device *dev = crtc->dev;
1717 struct drm_crtc *test_crtc;
1718 struct radeon_crtc *test_radeon_crtc;
1719 u32 pll_in_use = 0;
1720
1721 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1722 if (crtc == test_crtc)
1723 continue;
1724
1725 test_radeon_crtc = to_radeon_crtc(test_crtc);
1726 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1727 pll_in_use |= (1 << test_radeon_crtc->pll_id);
1728 }
1729 return pll_in_use;
1730 }
1731
1732 /**
1733 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1734 *
1735 * @crtc: drm crtc
1736 *
1737 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1738 * also in DP mode. For DP, a single PPLL can be used for all DP
1739 * crtcs/encoders.
1740 */
1741 static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
1742 {
1743 struct drm_device *dev = crtc->dev;
1744 struct radeon_device *rdev = dev->dev_private;
1745 struct drm_crtc *test_crtc;
1746 struct radeon_crtc *test_radeon_crtc;
1747
1748 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1749 if (crtc == test_crtc)
1750 continue;
1751 test_radeon_crtc = to_radeon_crtc(test_crtc);
1752 if (test_radeon_crtc->encoder &&
1753 ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1754 /* PPLL2 is exclusive to UNIPHYA on DCE61 */
1755 if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
1756 test_radeon_crtc->pll_id == ATOM_PPLL2)
1757 continue;
1758 /* for DP use the same PLL for all */
1759 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1760 return test_radeon_crtc->pll_id;
1761 }
1762 }
1763 return ATOM_PPLL_INVALID;
1764 }
1765
1766 /**
1767 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1768 *
1769 * @crtc: drm crtc
1770 * @encoder: drm encoder
1771 *
1772 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1773 * be shared (i.e., same clock).
1774 */
1775 static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
1776 {
1777 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1778 struct drm_device *dev = crtc->dev;
1779 struct radeon_device *rdev = dev->dev_private;
1780 struct drm_crtc *test_crtc;
1781 struct radeon_crtc *test_radeon_crtc;
1782 u32 adjusted_clock, test_adjusted_clock;
1783
1784 adjusted_clock = radeon_crtc->adjusted_clock;
1785
1786 if (adjusted_clock == 0)
1787 return ATOM_PPLL_INVALID;
1788
1789 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1790 if (crtc == test_crtc)
1791 continue;
1792 test_radeon_crtc = to_radeon_crtc(test_crtc);
1793 if (test_radeon_crtc->encoder &&
1794 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1795 /* PPLL2 is exclusive to UNIPHYA on DCE61 */
1796 if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
1797 test_radeon_crtc->pll_id == ATOM_PPLL2)
1798 continue;
1799 /* check if we are already driving this connector with another crtc */
1800 if (test_radeon_crtc->connector == radeon_crtc->connector) {
1801 /* if we are, return that pll */
1802 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1803 return test_radeon_crtc->pll_id;
1804 }
1805 /* for non-DP check the clock */
1806 test_adjusted_clock = test_radeon_crtc->adjusted_clock;
1807 if ((crtc->mode.clock == test_crtc->mode.clock) &&
1808 (adjusted_clock == test_adjusted_clock) &&
1809 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&
1810 (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID))
1811 return test_radeon_crtc->pll_id;
1812 }
1813 }
1814 return ATOM_PPLL_INVALID;
1815 }
1816
1817 /**
1818 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1819 *
1820 * @crtc: drm crtc
1821 *
1822 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
1823 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1824 * monitors a dedicated PPLL must be used. If a particular board has
1825 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1826 * as there is no need to program the PLL itself. If we are not able to
1827 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
1828 * avoid messing up an existing monitor.
1829 *
1830 * Asic specific PLL information
1831 *
1832 * DCE 8.x
1833 * KB/KV
1834 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
1835 * CI
1836 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1837 *
1838 * DCE 6.1
1839 * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
1840 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
1841 *
1842 * DCE 6.0
1843 * - PPLL0 is available to all UNIPHY (DP only)
1844 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1845 *
1846 * DCE 5.0
1847 * - DCPLL is available to all UNIPHY (DP only)
1848 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1849 *
1850 * DCE 3.0/4.0/4.1
1851 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1852 *
1853 */
1854 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1855 {
1856 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1857 struct drm_device *dev = crtc->dev;
1858 struct radeon_device *rdev = dev->dev_private;
1859 struct radeon_encoder *radeon_encoder =
1860 to_radeon_encoder(radeon_crtc->encoder);
1861 u32 pll_in_use;
1862 int pll;
1863
1864 if (ASIC_IS_DCE8(rdev)) {
1865 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1866 if (rdev->clock.dp_extclk)
1867 /* skip PPLL programming if using ext clock */
1868 return ATOM_PPLL_INVALID;
1869 else {
1870 /* use the same PPLL for all DP monitors */
1871 pll = radeon_get_shared_dp_ppll(crtc);
1872 if (pll != ATOM_PPLL_INVALID)
1873 return pll;
1874 }
1875 } else {
1876 /* use the same PPLL for all monitors with the same clock */
1877 pll = radeon_get_shared_nondp_ppll(crtc);
1878 if (pll != ATOM_PPLL_INVALID)
1879 return pll;
1880 }
1881 /* otherwise, pick one of the plls */
1882 if ((rdev->family == CHIP_KABINI) ||
1883 (rdev->family == CHIP_MULLINS)) {
1884 /* KB/ML has PPLL1 and PPLL2 */
1885 pll_in_use = radeon_get_pll_use_mask(crtc);
1886 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1887 return ATOM_PPLL2;
1888 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1889 return ATOM_PPLL1;
1890 DRM_ERROR("unable to allocate a PPLL\n");
1891 return ATOM_PPLL_INVALID;
1892 } else {
1893 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
1894 pll_in_use = radeon_get_pll_use_mask(crtc);
1895 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1896 return ATOM_PPLL2;
1897 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1898 return ATOM_PPLL1;
1899 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1900 return ATOM_PPLL0;
1901 DRM_ERROR("unable to allocate a PPLL\n");
1902 return ATOM_PPLL_INVALID;
1903 }
1904 } else if (ASIC_IS_DCE61(rdev)) {
1905 struct radeon_encoder_atom_dig *dig =
1906 radeon_encoder->enc_priv;
1907
1908 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1909 (dig->linkb == false))
1910 /* UNIPHY A uses PPLL2 */
1911 return ATOM_PPLL2;
1912 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1913 /* UNIPHY B/C/D/E/F */
1914 if (rdev->clock.dp_extclk)
1915 /* skip PPLL programming if using ext clock */
1916 return ATOM_PPLL_INVALID;
1917 else {
1918 /* use the same PPLL for all DP monitors */
1919 pll = radeon_get_shared_dp_ppll(crtc);
1920 if (pll != ATOM_PPLL_INVALID)
1921 return pll;
1922 }
1923 } else {
1924 /* use the same PPLL for all monitors with the same clock */
1925 pll = radeon_get_shared_nondp_ppll(crtc);
1926 if (pll != ATOM_PPLL_INVALID)
1927 return pll;
1928 }
1929 /* UNIPHY B/C/D/E/F */
1930 pll_in_use = radeon_get_pll_use_mask(crtc);
1931 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1932 return ATOM_PPLL0;
1933 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1934 return ATOM_PPLL1;
1935 DRM_ERROR("unable to allocate a PPLL\n");
1936 return ATOM_PPLL_INVALID;
1937 } else if (ASIC_IS_DCE41(rdev)) {
1938 /* Don't share PLLs on DCE4.1 chips */
1939 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1940 if (rdev->clock.dp_extclk)
1941 /* skip PPLL programming if using ext clock */
1942 return ATOM_PPLL_INVALID;
1943 }
1944 pll_in_use = radeon_get_pll_use_mask(crtc);
1945 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1946 return ATOM_PPLL1;
1947 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1948 return ATOM_PPLL2;
1949 DRM_ERROR("unable to allocate a PPLL\n");
1950 return ATOM_PPLL_INVALID;
1951 } else if (ASIC_IS_DCE4(rdev)) {
1952 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1953 * depending on the asic:
1954 * DCE4: PPLL or ext clock
1955 * DCE5: PPLL, DCPLL, or ext clock
1956 * DCE6: PPLL, PPLL0, or ext clock
1957 *
1958 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1959 * PPLL/DCPLL programming and only program the DP DTO for the
1960 * crtc virtual pixel clock.
1961 */
1962 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1963 if (rdev->clock.dp_extclk)
1964 /* skip PPLL programming if using ext clock */
1965 return ATOM_PPLL_INVALID;
1966 else if (ASIC_IS_DCE6(rdev))
1967 /* use PPLL0 for all DP */
1968 return ATOM_PPLL0;
1969 else if (ASIC_IS_DCE5(rdev))
1970 /* use DCPLL for all DP */
1971 return ATOM_DCPLL;
1972 else {
1973 /* use the same PPLL for all DP monitors */
1974 pll = radeon_get_shared_dp_ppll(crtc);
1975 if (pll != ATOM_PPLL_INVALID)
1976 return pll;
1977 }
1978 } else {
1979 /* use the same PPLL for all monitors with the same clock */
1980 pll = radeon_get_shared_nondp_ppll(crtc);
1981 if (pll != ATOM_PPLL_INVALID)
1982 return pll;
1983 }
1984 /* all other cases */
1985 pll_in_use = radeon_get_pll_use_mask(crtc);
1986 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1987 return ATOM_PPLL1;
1988 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1989 return ATOM_PPLL2;
1990 DRM_ERROR("unable to allocate a PPLL\n");
1991 return ATOM_PPLL_INVALID;
1992 } else {
1993 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
1994 /* some atombios (observed in some DCE2/DCE3) code have a bug,
1995 * the matching btw pll and crtc is done through
1996 * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the
1997 * pll (1 or 2) to select which register to write. ie if using
1998 * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2
1999 * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to
2000 * choose which value to write. Which is reverse order from
2001 * register logic. So only case that works is when pllid is
2002 * same as crtcid or when both pll and crtc are enabled and
2003 * both use same clock.
2004 *
2005 * So just return crtc id as if crtc and pll were hard linked
2006 * together even if they aren't
2007 */
2008 return radeon_crtc->crtc_id;
2009 }
2010 }
2011
2012 void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
2013 {
2014 /* always set DCPLL */
2015 if (ASIC_IS_DCE6(rdev))
2016 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
2017 else if (ASIC_IS_DCE4(rdev)) {
2018 struct radeon_atom_ss ss;
2019 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
2020 ASIC_INTERNAL_SS_ON_DCPLL,
2021 rdev->clock.default_dispclk);
2022 if (ss_enabled)
2023 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
2024 /* XXX: DCE5, make sure voltage, dispclk is high enough */
2025 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
2026 if (ss_enabled)
2027 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
2028 }
2029
2030 }
2031
2032 int atombios_crtc_mode_set(struct drm_crtc *crtc,
2033 struct drm_display_mode *mode,
2034 struct drm_display_mode *adjusted_mode,
2035 int x, int y, struct drm_framebuffer *old_fb)
2036 {
2037 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2038 struct drm_device *dev = crtc->dev;
2039 struct radeon_device *rdev = dev->dev_private;
2040 struct radeon_encoder *radeon_encoder =
2041 to_radeon_encoder(radeon_crtc->encoder);
2042 bool is_tvcv = false;
2043
2044 if (radeon_encoder->active_device &
2045 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2046 is_tvcv = true;
2047
2048 if (!radeon_crtc->adjusted_clock)
2049 return -EINVAL;
2050
2051 atombios_crtc_set_pll(crtc, adjusted_mode);
2052
2053 if (ASIC_IS_DCE4(rdev))
2054 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2055 else if (ASIC_IS_AVIVO(rdev)) {
2056 if (is_tvcv)
2057 atombios_crtc_set_timing(crtc, adjusted_mode);
2058 else
2059 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2060 } else {
2061 atombios_crtc_set_timing(crtc, adjusted_mode);
2062 if (radeon_crtc->crtc_id == 0)
2063 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2064 radeon_legacy_atom_fixup(crtc);
2065 }
2066 atombios_crtc_set_base(crtc, x, y, old_fb);
2067 atombios_overscan_setup(crtc, mode, adjusted_mode);
2068 atombios_scaler_setup(crtc);
2069 radeon_cursor_reset(crtc);
2070 /* update the hw version fpr dpm */
2071 radeon_crtc->hw_mode = *adjusted_mode;
2072
2073 return 0;
2074 }
2075
2076 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
2077 const struct drm_display_mode *mode,
2078 struct drm_display_mode *adjusted_mode)
2079 {
2080 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2081 struct drm_device *dev = crtc->dev;
2082 struct drm_encoder *encoder;
2083
2084 /* assign the encoder to the radeon crtc to avoid repeated lookups later */
2085 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2086 if (encoder->crtc == crtc) {
2087 radeon_crtc->encoder = encoder;
2088 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);
2089 break;
2090 }
2091 }
2092 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) {
2093 radeon_crtc->encoder = NULL;
2094 radeon_crtc->connector = NULL;
2095 return false;
2096 }
2097 if (radeon_crtc->encoder) {
2098 struct radeon_encoder *radeon_encoder =
2099 to_radeon_encoder(radeon_crtc->encoder);
2100
2101 radeon_crtc->output_csc = radeon_encoder->output_csc;
2102 }
2103 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2104 return false;
2105 if (!atombios_crtc_prepare_pll(crtc, adjusted_mode))
2106 return false;
2107 /* pick pll */
2108 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
2109 /* if we can't get a PPLL for a non-DP encoder, fail */
2110 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&
2111 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))
2112 return false;
2113
2114 return true;
2115 }
2116
2117 static void atombios_crtc_prepare(struct drm_crtc *crtc)
2118 {
2119 struct drm_device *dev = crtc->dev;
2120 struct radeon_device *rdev = dev->dev_private;
2121
2122 /* disable crtc pair power gating before programming */
2123 if (ASIC_IS_DCE6(rdev))
2124 atombios_powergate_crtc(crtc, ATOM_DISABLE);
2125
2126 atombios_lock_crtc(crtc, ATOM_ENABLE);
2127 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2128 }
2129
2130 static void atombios_crtc_commit(struct drm_crtc *crtc)
2131 {
2132 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2133 atombios_lock_crtc(crtc, ATOM_DISABLE);
2134 }
2135
2136 static void atombios_crtc_disable(struct drm_crtc *crtc)
2137 {
2138 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2139 struct drm_device *dev = crtc->dev;
2140 struct radeon_device *rdev = dev->dev_private;
2141 struct radeon_atom_ss ss;
2142 int i;
2143
2144 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2145 if (crtc->primary->fb) {
2146 int r;
2147 struct radeon_framebuffer *radeon_fb;
2148 struct radeon_bo *rbo;
2149
2150 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
2151 rbo = gem_to_radeon_bo(radeon_fb->obj);
2152 r = radeon_bo_reserve(rbo, false);
2153 if (unlikely(r))
2154 DRM_ERROR("failed to reserve rbo before unpin\n");
2155 else {
2156 radeon_bo_unpin(rbo);
2157 radeon_bo_unreserve(rbo);
2158 }
2159 }
2160 /* disable the GRPH */
2161 if (ASIC_IS_DCE4(rdev))
2162 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2163 else if (ASIC_IS_AVIVO(rdev))
2164 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2165
2166 if (ASIC_IS_DCE6(rdev))
2167 atombios_powergate_crtc(crtc, ATOM_ENABLE);
2168
2169 for (i = 0; i < rdev->num_crtc; i++) {
2170 if (rdev->mode_info.crtcs[i] &&
2171 rdev->mode_info.crtcs[i]->enabled &&
2172 i != radeon_crtc->crtc_id &&
2173 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
2174 /* one other crtc is using this pll don't turn
2175 * off the pll
2176 */
2177 goto done;
2178 }
2179 }
2180
2181 switch (radeon_crtc->pll_id) {
2182 case ATOM_PPLL1:
2183 case ATOM_PPLL2:
2184 /* disable the ppll */
2185 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2186 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2187 break;
2188 case ATOM_PPLL0:
2189 /* disable the ppll */
2190 if ((rdev->family == CHIP_ARUBA) ||
2191 (rdev->family == CHIP_KAVERI) ||
2192 (rdev->family == CHIP_BONAIRE) ||
2193 (rdev->family == CHIP_HAWAII))
2194 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2195 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2196 break;
2197 default:
2198 break;
2199 }
2200 done:
2201 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2202 radeon_crtc->adjusted_clock = 0;
2203 radeon_crtc->encoder = NULL;
2204 radeon_crtc->connector = NULL;
2205 }
2206
2207 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
2208 .dpms = atombios_crtc_dpms,
2209 .mode_fixup = atombios_crtc_mode_fixup,
2210 .mode_set = atombios_crtc_mode_set,
2211 .mode_set_base = atombios_crtc_set_base,
2212 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
2213 .prepare = atombios_crtc_prepare,
2214 .commit = atombios_crtc_commit,
2215 .load_lut = radeon_crtc_load_lut,
2216 .disable = atombios_crtc_disable,
2217 };
2218
2219 void radeon_atombios_init_crtc(struct drm_device *dev,
2220 struct radeon_crtc *radeon_crtc)
2221 {
2222 struct radeon_device *rdev = dev->dev_private;
2223
2224 if (ASIC_IS_DCE4(rdev)) {
2225 switch (radeon_crtc->crtc_id) {
2226 case 0:
2227 default:
2228 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
2229 break;
2230 case 1:
2231 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
2232 break;
2233 case 2:
2234 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
2235 break;
2236 case 3:
2237 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
2238 break;
2239 case 4:
2240 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
2241 break;
2242 case 5:
2243 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
2244 break;
2245 }
2246 } else {
2247 if (radeon_crtc->crtc_id == 1)
2248 radeon_crtc->crtc_offset =
2249 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
2250 else
2251 radeon_crtc->crtc_offset = 0;
2252 }
2253 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2254 radeon_crtc->adjusted_clock = 0;
2255 radeon_crtc->encoder = NULL;
2256 radeon_crtc->connector = NULL;
2257 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
2258 }
Linux kernel - Deliverables
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