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drm: extract dp link bw helpers
[deliverable/linux.git] / drivers / gpu / drm / radeon / atombios_dp.c
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 * Jerome Glisse
26 */
27 #include <drm/drmP.h>
28 #include <drm/radeon_drm.h>
29 #include "radeon.h"
30
31 #include "atom.h"
32 #include "atom-bits.h"
33 #include <drm/drm_dp_helper.h>
34
35 /* move these to drm_dp_helper.c/h */
36 #define DP_LINK_CONFIGURATION_SIZE 9
37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
38
39 static char *voltage_names[] = {
40 "0.4V", "0.6V", "0.8V", "1.2V"
41 };
42 static char *pre_emph_names[] = {
43 "0dB", "3.5dB", "6dB", "9.5dB"
44 };
45
46 /***** radeon AUX functions *****/
47 union aux_channel_transaction {
48 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
49 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
50 };
51
52 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
53 u8 *send, int send_bytes,
54 u8 *recv, int recv_size,
55 u8 delay, u8 *ack)
56 {
57 struct drm_device *dev = chan->dev;
58 struct radeon_device *rdev = dev->dev_private;
59 union aux_channel_transaction args;
60 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
61 unsigned char *base;
62 int recv_bytes;
63
64 memset(&args, 0, sizeof(args));
65
66 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
67
68 memcpy(base, send, send_bytes);
69
70 args.v1.lpAuxRequest = 0 + 4;
71 args.v1.lpDataOut = 16 + 4;
72 args.v1.ucDataOutLen = 0;
73 args.v1.ucChannelID = chan->rec.i2c_id;
74 args.v1.ucDelay = delay / 10;
75 if (ASIC_IS_DCE4(rdev))
76 args.v2.ucHPD_ID = chan->rec.hpd;
77
78 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
79
80 *ack = args.v1.ucReplyStatus;
81
82 /* timeout */
83 if (args.v1.ucReplyStatus == 1) {
84 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
85 return -ETIMEDOUT;
86 }
87
88 /* flags not zero */
89 if (args.v1.ucReplyStatus == 2) {
90 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
91 return -EBUSY;
92 }
93
94 /* error */
95 if (args.v1.ucReplyStatus == 3) {
96 DRM_DEBUG_KMS("dp_aux_ch error\n");
97 return -EIO;
98 }
99
100 recv_bytes = args.v1.ucDataOutLen;
101 if (recv_bytes > recv_size)
102 recv_bytes = recv_size;
103
104 if (recv && recv_size)
105 memcpy(recv, base + 16, recv_bytes);
106
107 return recv_bytes;
108 }
109
110 static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
111 u16 address, u8 *send, u8 send_bytes, u8 delay)
112 {
113 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
114 int ret;
115 u8 msg[20];
116 int msg_bytes = send_bytes + 4;
117 u8 ack;
118 unsigned retry;
119
120 if (send_bytes > 16)
121 return -1;
122
123 msg[0] = address;
124 msg[1] = address >> 8;
125 msg[2] = AUX_NATIVE_WRITE << 4;
126 msg[3] = (msg_bytes << 4) | (send_bytes - 1);
127 memcpy(&msg[4], send, send_bytes);
128
129 for (retry = 0; retry < 4; retry++) {
130 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
131 msg, msg_bytes, NULL, 0, delay, &ack);
132 if (ret == -EBUSY)
133 continue;
134 else if (ret < 0)
135 return ret;
136 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
137 return send_bytes;
138 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
139 udelay(400);
140 else
141 return -EIO;
142 }
143
144 return -EIO;
145 }
146
147 static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
148 u16 address, u8 *recv, int recv_bytes, u8 delay)
149 {
150 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
151 u8 msg[4];
152 int msg_bytes = 4;
153 u8 ack;
154 int ret;
155 unsigned retry;
156
157 msg[0] = address;
158 msg[1] = address >> 8;
159 msg[2] = AUX_NATIVE_READ << 4;
160 msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
161
162 for (retry = 0; retry < 4; retry++) {
163 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
164 msg, msg_bytes, recv, recv_bytes, delay, &ack);
165 if (ret == -EBUSY)
166 continue;
167 else if (ret < 0)
168 return ret;
169 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
170 return ret;
171 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
172 udelay(400);
173 else if (ret == 0)
174 return -EPROTO;
175 else
176 return -EIO;
177 }
178
179 return -EIO;
180 }
181
182 static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,
183 u16 reg, u8 val)
184 {
185 radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0);
186 }
187
188 static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector,
189 u16 reg)
190 {
191 u8 val = 0;
192
193 radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0);
194
195 return val;
196 }
197
198 int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
199 u8 write_byte, u8 *read_byte)
200 {
201 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
202 struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter;
203 u16 address = algo_data->address;
204 u8 msg[5];
205 u8 reply[2];
206 unsigned retry;
207 int msg_bytes;
208 int reply_bytes = 1;
209 int ret;
210 u8 ack;
211
212 /* Set up the command byte */
213 if (mode & MODE_I2C_READ)
214 msg[2] = AUX_I2C_READ << 4;
215 else
216 msg[2] = AUX_I2C_WRITE << 4;
217
218 if (!(mode & MODE_I2C_STOP))
219 msg[2] |= AUX_I2C_MOT << 4;
220
221 msg[0] = address;
222 msg[1] = address >> 8;
223
224 switch (mode) {
225 case MODE_I2C_WRITE:
226 msg_bytes = 5;
227 msg[3] = msg_bytes << 4;
228 msg[4] = write_byte;
229 break;
230 case MODE_I2C_READ:
231 msg_bytes = 4;
232 msg[3] = msg_bytes << 4;
233 break;
234 default:
235 msg_bytes = 4;
236 msg[3] = 3 << 4;
237 break;
238 }
239
240 for (retry = 0; retry < 4; retry++) {
241 ret = radeon_process_aux_ch(auxch,
242 msg, msg_bytes, reply, reply_bytes, 0, &ack);
243 if (ret == -EBUSY)
244 continue;
245 else if (ret < 0) {
246 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
247 return ret;
248 }
249
250 switch (ack & AUX_NATIVE_REPLY_MASK) {
251 case AUX_NATIVE_REPLY_ACK:
252 /* I2C-over-AUX Reply field is only valid
253 * when paired with AUX ACK.
254 */
255 break;
256 case AUX_NATIVE_REPLY_NACK:
257 DRM_DEBUG_KMS("aux_ch native nack\n");
258 return -EREMOTEIO;
259 case AUX_NATIVE_REPLY_DEFER:
260 DRM_DEBUG_KMS("aux_ch native defer\n");
261 udelay(400);
262 continue;
263 default:
264 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack);
265 return -EREMOTEIO;
266 }
267
268 switch (ack & AUX_I2C_REPLY_MASK) {
269 case AUX_I2C_REPLY_ACK:
270 if (mode == MODE_I2C_READ)
271 *read_byte = reply[0];
272 return ret;
273 case AUX_I2C_REPLY_NACK:
274 DRM_DEBUG_KMS("aux_i2c nack\n");
275 return -EREMOTEIO;
276 case AUX_I2C_REPLY_DEFER:
277 DRM_DEBUG_KMS("aux_i2c defer\n");
278 udelay(400);
279 break;
280 default:
281 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack);
282 return -EREMOTEIO;
283 }
284 }
285
286 DRM_DEBUG_KMS("aux i2c too many retries, giving up\n");
287 return -EREMOTEIO;
288 }
289
290 /***** general DP utility functions *****/
291
292 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
293 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5
294
295 static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
296 int lane_count,
297 u8 train_set[4])
298 {
299 u8 v = 0;
300 u8 p = 0;
301 int lane;
302
303 for (lane = 0; lane < lane_count; lane++) {
304 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
305 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
306
307 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
308 lane,
309 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
310 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
311
312 if (this_v > v)
313 v = this_v;
314 if (this_p > p)
315 p = this_p;
316 }
317
318 if (v >= DP_VOLTAGE_MAX)
319 v |= DP_TRAIN_MAX_SWING_REACHED;
320
321 if (p >= DP_PRE_EMPHASIS_MAX)
322 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
323
324 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
325 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
326 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
327
328 for (lane = 0; lane < 4; lane++)
329 train_set[lane] = v | p;
330 }
331
332 /* convert bits per color to bits per pixel */
333 /* get bpc from the EDID */
334 static int convert_bpc_to_bpp(int bpc)
335 {
336 if (bpc == 0)
337 return 24;
338 else
339 return bpc * 3;
340 }
341
342 /* get the max pix clock supported by the link rate and lane num */
343 static int dp_get_max_dp_pix_clock(int link_rate,
344 int lane_num,
345 int bpp)
346 {
347 return (link_rate * lane_num * 8) / bpp;
348 }
349
350 static u8 dp_get_max_lane_number(u8 dpcd[DP_DPCD_SIZE])
351 {
352 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
353 }
354
355 /***** radeon specific DP functions *****/
356
357 /* First get the min lane# when low rate is used according to pixel clock
358 * (prefer low rate), second check max lane# supported by DP panel,
359 * if the max lane# < low rate lane# then use max lane# instead.
360 */
361 static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
362 u8 dpcd[DP_DPCD_SIZE],
363 int pix_clock)
364 {
365 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
366 int max_link_rate = drm_dp_max_link_rate(dpcd);
367 int max_lane_num = dp_get_max_lane_number(dpcd);
368 int lane_num;
369 int max_dp_pix_clock;
370
371 for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
372 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
373 if (pix_clock <= max_dp_pix_clock)
374 break;
375 }
376
377 return lane_num;
378 }
379
380 static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
381 u8 dpcd[DP_DPCD_SIZE],
382 int pix_clock)
383 {
384 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
385 int lane_num, max_pix_clock;
386
387 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
388 ENCODER_OBJECT_ID_NUTMEG)
389 return 270000;
390
391 lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
392 max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
393 if (pix_clock <= max_pix_clock)
394 return 162000;
395 max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
396 if (pix_clock <= max_pix_clock)
397 return 270000;
398 if (radeon_connector_is_dp12_capable(connector)) {
399 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
400 if (pix_clock <= max_pix_clock)
401 return 540000;
402 }
403
404 return drm_dp_max_link_rate(dpcd);
405 }
406
407 static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
408 int action, int dp_clock,
409 u8 ucconfig, u8 lane_num)
410 {
411 DP_ENCODER_SERVICE_PARAMETERS args;
412 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
413
414 memset(&args, 0, sizeof(args));
415 args.ucLinkClock = dp_clock / 10;
416 args.ucConfig = ucconfig;
417 args.ucAction = action;
418 args.ucLaneNum = lane_num;
419 args.ucStatus = 0;
420
421 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
422 return args.ucStatus;
423 }
424
425 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
426 {
427 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
428 struct drm_device *dev = radeon_connector->base.dev;
429 struct radeon_device *rdev = dev->dev_private;
430
431 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
432 dig_connector->dp_i2c_bus->rec.i2c_id, 0);
433 }
434
435 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
436 {
437 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
438 u8 buf[3];
439
440 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
441 return;
442
443 if (radeon_dp_aux_native_read(radeon_connector, DP_SINK_OUI, buf, 3, 0))
444 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
445 buf[0], buf[1], buf[2]);
446
447 if (radeon_dp_aux_native_read(radeon_connector, DP_BRANCH_OUI, buf, 3, 0))
448 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
449 buf[0], buf[1], buf[2]);
450 }
451
452 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
453 {
454 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
455 u8 msg[DP_DPCD_SIZE];
456 int ret, i;
457
458 ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg,
459 DP_DPCD_SIZE, 0);
460 if (ret > 0) {
461 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
462 DRM_DEBUG_KMS("DPCD: ");
463 for (i = 0; i < DP_DPCD_SIZE; i++)
464 DRM_DEBUG_KMS("%02x ", msg[i]);
465 DRM_DEBUG_KMS("\n");
466
467 radeon_dp_probe_oui(radeon_connector);
468
469 return true;
470 }
471 dig_connector->dpcd[0] = 0;
472 return false;
473 }
474
475 int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
476 struct drm_connector *connector)
477 {
478 struct drm_device *dev = encoder->dev;
479 struct radeon_device *rdev = dev->dev_private;
480 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
481 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
482 u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
483 u8 tmp;
484
485 if (!ASIC_IS_DCE4(rdev))
486 return panel_mode;
487
488 if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
489 /* DP bridge chips */
490 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
491 if (tmp & 1)
492 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
493 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
494 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
495 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
496 else
497 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
498 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
499 /* eDP */
500 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
501 if (tmp & 1)
502 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
503 }
504
505 return panel_mode;
506 }
507
508 void radeon_dp_set_link_config(struct drm_connector *connector,
509 const struct drm_display_mode *mode)
510 {
511 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
512 struct radeon_connector_atom_dig *dig_connector;
513
514 if (!radeon_connector->con_priv)
515 return;
516 dig_connector = radeon_connector->con_priv;
517
518 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
519 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
520 dig_connector->dp_clock =
521 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
522 dig_connector->dp_lane_count =
523 radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
524 }
525 }
526
527 int radeon_dp_mode_valid_helper(struct drm_connector *connector,
528 struct drm_display_mode *mode)
529 {
530 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
531 struct radeon_connector_atom_dig *dig_connector;
532 int dp_clock;
533
534 if (!radeon_connector->con_priv)
535 return MODE_CLOCK_HIGH;
536 dig_connector = radeon_connector->con_priv;
537
538 dp_clock =
539 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
540
541 if ((dp_clock == 540000) &&
542 (!radeon_connector_is_dp12_capable(connector)))
543 return MODE_CLOCK_HIGH;
544
545 return MODE_OK;
546 }
547
548 static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector,
549 u8 link_status[DP_LINK_STATUS_SIZE])
550 {
551 int ret;
552 ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS,
553 link_status, DP_LINK_STATUS_SIZE, 100);
554 if (ret <= 0) {
555 return false;
556 }
557
558 DRM_DEBUG_KMS("link status %*ph\n", 6, link_status);
559 return true;
560 }
561
562 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
563 {
564 u8 link_status[DP_LINK_STATUS_SIZE];
565 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
566
567 if (!radeon_dp_get_link_status(radeon_connector, link_status))
568 return false;
569 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
570 return false;
571 return true;
572 }
573
574 struct radeon_dp_link_train_info {
575 struct radeon_device *rdev;
576 struct drm_encoder *encoder;
577 struct drm_connector *connector;
578 struct radeon_connector *radeon_connector;
579 int enc_id;
580 int dp_clock;
581 int dp_lane_count;
582 bool tp3_supported;
583 u8 dpcd[DP_RECEIVER_CAP_SIZE];
584 u8 train_set[4];
585 u8 link_status[DP_LINK_STATUS_SIZE];
586 u8 tries;
587 bool use_dpencoder;
588 };
589
590 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
591 {
592 /* set the initial vs/emph on the source */
593 atombios_dig_transmitter_setup(dp_info->encoder,
594 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
595 0, dp_info->train_set[0]); /* sets all lanes at once */
596
597 /* set the vs/emph on the sink */
598 radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET,
599 dp_info->train_set, dp_info->dp_lane_count, 0);
600 }
601
602 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
603 {
604 int rtp = 0;
605
606 /* set training pattern on the source */
607 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
608 switch (tp) {
609 case DP_TRAINING_PATTERN_1:
610 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
611 break;
612 case DP_TRAINING_PATTERN_2:
613 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
614 break;
615 case DP_TRAINING_PATTERN_3:
616 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
617 break;
618 }
619 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
620 } else {
621 switch (tp) {
622 case DP_TRAINING_PATTERN_1:
623 rtp = 0;
624 break;
625 case DP_TRAINING_PATTERN_2:
626 rtp = 1;
627 break;
628 }
629 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
630 dp_info->dp_clock, dp_info->enc_id, rtp);
631 }
632
633 /* enable training pattern on the sink */
634 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp);
635 }
636
637 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
638 {
639 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
640 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
641 u8 tmp;
642
643 /* power up the sink */
644 if (dp_info->dpcd[0] >= 0x11)
645 radeon_write_dpcd_reg(dp_info->radeon_connector,
646 DP_SET_POWER, DP_SET_POWER_D0);
647
648 /* possibly enable downspread on the sink */
649 if (dp_info->dpcd[3] & 0x1)
650 radeon_write_dpcd_reg(dp_info->radeon_connector,
651 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
652 else
653 radeon_write_dpcd_reg(dp_info->radeon_connector,
654 DP_DOWNSPREAD_CTRL, 0);
655
656 if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
657 (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
658 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1);
659 }
660
661 /* set the lane count on the sink */
662 tmp = dp_info->dp_lane_count;
663 if (dp_info->dpcd[DP_DPCD_REV] >= 0x11 &&
664 dp_info->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)
665 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
666 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp);
667
668 /* set the link rate on the sink */
669 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
670 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp);
671
672 /* start training on the source */
673 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
674 atombios_dig_encoder_setup(dp_info->encoder,
675 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
676 else
677 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
678 dp_info->dp_clock, dp_info->enc_id, 0);
679
680 /* disable the training pattern on the sink */
681 radeon_write_dpcd_reg(dp_info->radeon_connector,
682 DP_TRAINING_PATTERN_SET,
683 DP_TRAINING_PATTERN_DISABLE);
684
685 return 0;
686 }
687
688 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
689 {
690 udelay(400);
691
692 /* disable the training pattern on the sink */
693 radeon_write_dpcd_reg(dp_info->radeon_connector,
694 DP_TRAINING_PATTERN_SET,
695 DP_TRAINING_PATTERN_DISABLE);
696
697 /* disable the training pattern on the source */
698 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
699 atombios_dig_encoder_setup(dp_info->encoder,
700 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
701 else
702 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
703 dp_info->dp_clock, dp_info->enc_id, 0);
704
705 return 0;
706 }
707
708 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
709 {
710 bool clock_recovery;
711 u8 voltage;
712 int i;
713
714 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
715 memset(dp_info->train_set, 0, 4);
716 radeon_dp_update_vs_emph(dp_info);
717
718 udelay(400);
719
720 /* clock recovery loop */
721 clock_recovery = false;
722 dp_info->tries = 0;
723 voltage = 0xff;
724 while (1) {
725 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
726
727 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) {
728 DRM_ERROR("displayport link status failed\n");
729 break;
730 }
731
732 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
733 clock_recovery = true;
734 break;
735 }
736
737 for (i = 0; i < dp_info->dp_lane_count; i++) {
738 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
739 break;
740 }
741 if (i == dp_info->dp_lane_count) {
742 DRM_ERROR("clock recovery reached max voltage\n");
743 break;
744 }
745
746 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
747 ++dp_info->tries;
748 if (dp_info->tries == 5) {
749 DRM_ERROR("clock recovery tried 5 times\n");
750 break;
751 }
752 } else
753 dp_info->tries = 0;
754
755 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
756
757 /* Compute new train_set as requested by sink */
758 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
759
760 radeon_dp_update_vs_emph(dp_info);
761 }
762 if (!clock_recovery) {
763 DRM_ERROR("clock recovery failed\n");
764 return -1;
765 } else {
766 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
767 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
768 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
769 DP_TRAIN_PRE_EMPHASIS_SHIFT);
770 return 0;
771 }
772 }
773
774 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
775 {
776 bool channel_eq;
777
778 if (dp_info->tp3_supported)
779 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
780 else
781 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
782
783 /* channel equalization loop */
784 dp_info->tries = 0;
785 channel_eq = false;
786 while (1) {
787 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
788
789 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) {
790 DRM_ERROR("displayport link status failed\n");
791 break;
792 }
793
794 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
795 channel_eq = true;
796 break;
797 }
798
799 /* Try 5 times */
800 if (dp_info->tries > 5) {
801 DRM_ERROR("channel eq failed: 5 tries\n");
802 break;
803 }
804
805 /* Compute new train_set as requested by sink */
806 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
807
808 radeon_dp_update_vs_emph(dp_info);
809 dp_info->tries++;
810 }
811
812 if (!channel_eq) {
813 DRM_ERROR("channel eq failed\n");
814 return -1;
815 } else {
816 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
817 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
818 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
819 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
820 return 0;
821 }
822 }
823
824 void radeon_dp_link_train(struct drm_encoder *encoder,
825 struct drm_connector *connector)
826 {
827 struct drm_device *dev = encoder->dev;
828 struct radeon_device *rdev = dev->dev_private;
829 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
830 struct radeon_encoder_atom_dig *dig;
831 struct radeon_connector *radeon_connector;
832 struct radeon_connector_atom_dig *dig_connector;
833 struct radeon_dp_link_train_info dp_info;
834 int index;
835 u8 tmp, frev, crev;
836
837 if (!radeon_encoder->enc_priv)
838 return;
839 dig = radeon_encoder->enc_priv;
840
841 radeon_connector = to_radeon_connector(connector);
842 if (!radeon_connector->con_priv)
843 return;
844 dig_connector = radeon_connector->con_priv;
845
846 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
847 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
848 return;
849
850 /* DPEncoderService newer than 1.1 can't program properly the
851 * training pattern. When facing such version use the
852 * DIGXEncoderControl (X== 1 | 2)
853 */
854 dp_info.use_dpencoder = true;
855 index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
856 if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
857 if (crev > 1) {
858 dp_info.use_dpencoder = false;
859 }
860 }
861
862 dp_info.enc_id = 0;
863 if (dig->dig_encoder)
864 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
865 else
866 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
867 if (dig->linkb)
868 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
869 else
870 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
871
872 tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT);
873 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
874 dp_info.tp3_supported = true;
875 else
876 dp_info.tp3_supported = false;
877
878 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
879 dp_info.rdev = rdev;
880 dp_info.encoder = encoder;
881 dp_info.connector = connector;
882 dp_info.radeon_connector = radeon_connector;
883 dp_info.dp_lane_count = dig_connector->dp_lane_count;
884 dp_info.dp_clock = dig_connector->dp_clock;
885
886 if (radeon_dp_link_train_init(&dp_info))
887 goto done;
888 if (radeon_dp_link_train_cr(&dp_info))
889 goto done;
890 if (radeon_dp_link_train_ce(&dp_info))
891 goto done;
892 done:
893 if (radeon_dp_link_train_finish(&dp_info))
894 return;
895 }
Linux kernel - Deliverables
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