2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
28 #include <drm/radeon_drm.h>
32 #include "atom-bits.h"
33 #include <drm/drm_dp_helper.h>
35 /* move these to drm_dp_helper.c/h */
36 #define DP_LINK_CONFIGURATION_SIZE 9
37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
39 static char *voltage_names
[] = {
40 "0.4V", "0.6V", "0.8V", "1.2V"
42 static char *pre_emph_names
[] = {
43 "0dB", "3.5dB", "6dB", "9.5dB"
46 /***** radeon AUX functions *****/
48 /* Atom needs data in little endian format
49 * so swap as appropriate when copying data to
50 * or from atom. Note that atom operates on
53 void radeon_atom_copy_swap(u8
*dst
, u8
*src
, u8 num_bytes
, bool to_le
)
56 u8 src_tmp
[20], dst_tmp
[20]; /* used for byteswapping */
60 memcpy(src_tmp
, src
, num_bytes
);
61 src32
= (u32
*)src_tmp
;
62 dst32
= (u32
*)dst_tmp
;
64 for (i
= 0; i
< ((num_bytes
+ 3) / 4); i
++)
65 dst32
[i
] = cpu_to_le32(src32
[i
]);
66 memcpy(dst
, dst_tmp
, num_bytes
);
68 u8 dws
= num_bytes
& ~3;
69 for (i
= 0; i
< ((num_bytes
+ 3) / 4); i
++)
70 dst32
[i
] = le32_to_cpu(src32
[i
]);
71 memcpy(dst
, dst_tmp
, dws
);
73 for (i
= 0; i
< (num_bytes
% 4); i
++)
74 dst
[dws
+i
] = dst_tmp
[dws
+i
];
78 memcpy(dst
, src
, num_bytes
);
82 union aux_channel_transaction
{
83 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1
;
84 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2
;
87 static int radeon_process_aux_ch(struct radeon_i2c_chan
*chan
,
88 u8
*send
, int send_bytes
,
89 u8
*recv
, int recv_size
,
92 struct drm_device
*dev
= chan
->dev
;
93 struct radeon_device
*rdev
= dev
->dev_private
;
94 union aux_channel_transaction args
;
95 int index
= GetIndexIntoMasterTable(COMMAND
, ProcessAuxChannelTransaction
);
99 memset(&args
, 0, sizeof(args
));
101 base
= (unsigned char *)(rdev
->mode_info
.atom_context
->scratch
+ 1);
103 radeon_atom_copy_swap(base
, send
, send_bytes
, true);
105 args
.v1
.lpAuxRequest
= cpu_to_le16((u16
)(0 + 4));
106 args
.v1
.lpDataOut
= cpu_to_le16((u16
)(16 + 4));
107 args
.v1
.ucDataOutLen
= 0;
108 args
.v1
.ucChannelID
= chan
->rec
.i2c_id
;
109 args
.v1
.ucDelay
= delay
/ 10;
110 if (ASIC_IS_DCE4(rdev
))
111 args
.v2
.ucHPD_ID
= chan
->rec
.hpd
;
113 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
115 *ack
= args
.v1
.ucReplyStatus
;
118 if (args
.v1
.ucReplyStatus
== 1) {
119 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
124 if (args
.v1
.ucReplyStatus
== 2) {
125 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
130 if (args
.v1
.ucReplyStatus
== 3) {
131 DRM_DEBUG_KMS("dp_aux_ch error\n");
135 recv_bytes
= args
.v1
.ucDataOutLen
;
136 if (recv_bytes
> recv_size
)
137 recv_bytes
= recv_size
;
139 if (recv
&& recv_size
)
140 radeon_atom_copy_swap(recv
, base
+ 16, recv_bytes
, false);
145 static int radeon_dp_aux_native_write(struct radeon_connector
*radeon_connector
,
146 u16 address
, u8
*send
, u8 send_bytes
, u8 delay
)
148 struct radeon_connector_atom_dig
*dig_connector
= radeon_connector
->con_priv
;
151 int msg_bytes
= send_bytes
+ 4;
159 msg
[1] = address
>> 8;
160 msg
[2] = DP_AUX_NATIVE_WRITE
<< 4;
161 msg
[3] = (msg_bytes
<< 4) | (send_bytes
- 1);
162 memcpy(&msg
[4], send
, send_bytes
);
164 for (retry
= 0; retry
< 7; retry
++) {
165 ret
= radeon_process_aux_ch(dig_connector
->dp_i2c_bus
,
166 msg
, msg_bytes
, NULL
, 0, delay
, &ack
);
172 if ((ack
& DP_AUX_NATIVE_REPLY_MASK
) == DP_AUX_NATIVE_REPLY_ACK
)
174 else if ((ack
& DP_AUX_NATIVE_REPLY_MASK
) == DP_AUX_NATIVE_REPLY_DEFER
)
183 static int radeon_dp_aux_native_read(struct radeon_connector
*radeon_connector
,
184 u16 address
, u8
*recv
, int recv_bytes
, u8 delay
)
186 struct radeon_connector_atom_dig
*dig_connector
= radeon_connector
->con_priv
;
194 msg
[1] = address
>> 8;
195 msg
[2] = DP_AUX_NATIVE_READ
<< 4;
196 msg
[3] = (msg_bytes
<< 4) | (recv_bytes
- 1);
198 for (retry
= 0; retry
< 7; retry
++) {
199 ret
= radeon_process_aux_ch(dig_connector
->dp_i2c_bus
,
200 msg
, msg_bytes
, recv
, recv_bytes
, delay
, &ack
);
206 if ((ack
& DP_AUX_NATIVE_REPLY_MASK
) == DP_AUX_NATIVE_REPLY_ACK
)
208 else if ((ack
& DP_AUX_NATIVE_REPLY_MASK
) == DP_AUX_NATIVE_REPLY_DEFER
)
219 static void radeon_write_dpcd_reg(struct radeon_connector
*radeon_connector
,
222 radeon_dp_aux_native_write(radeon_connector
, reg
, &val
, 1, 0);
225 static u8
radeon_read_dpcd_reg(struct radeon_connector
*radeon_connector
,
230 radeon_dp_aux_native_read(radeon_connector
, reg
, &val
, 1, 0);
235 int radeon_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
236 u8 write_byte
, u8
*read_byte
)
238 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
239 struct radeon_i2c_chan
*auxch
= (struct radeon_i2c_chan
*)adapter
;
240 u16 address
= algo_data
->address
;
249 /* Set up the command byte */
250 if (mode
& MODE_I2C_READ
)
251 msg
[2] = DP_AUX_I2C_READ
<< 4;
253 msg
[2] = DP_AUX_I2C_WRITE
<< 4;
255 if (!(mode
& MODE_I2C_STOP
))
256 msg
[2] |= DP_AUX_I2C_MOT
<< 4;
259 msg
[1] = address
>> 8;
264 msg
[3] = msg_bytes
<< 4;
269 msg
[3] = msg_bytes
<< 4;
277 for (retry
= 0; retry
< 7; retry
++) {
278 ret
= radeon_process_aux_ch(auxch
,
279 msg
, msg_bytes
, reply
, reply_bytes
, 0, &ack
);
283 DRM_DEBUG_KMS("aux_ch failed %d\n", ret
);
287 switch ((ack
>> 4) & DP_AUX_NATIVE_REPLY_MASK
) {
288 case DP_AUX_NATIVE_REPLY_ACK
:
289 /* I2C-over-AUX Reply field is only valid
290 * when paired with AUX ACK.
293 case DP_AUX_NATIVE_REPLY_NACK
:
294 DRM_DEBUG_KMS("aux_ch native nack\n");
296 case DP_AUX_NATIVE_REPLY_DEFER
:
297 DRM_DEBUG_KMS("aux_ch native defer\n");
301 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack
);
305 switch ((ack
>> 4) & DP_AUX_I2C_REPLY_MASK
) {
306 case DP_AUX_I2C_REPLY_ACK
:
307 if (mode
== MODE_I2C_READ
)
308 *read_byte
= reply
[0];
310 case DP_AUX_I2C_REPLY_NACK
:
311 DRM_DEBUG_KMS("aux_i2c nack\n");
313 case DP_AUX_I2C_REPLY_DEFER
:
314 DRM_DEBUG_KMS("aux_i2c defer\n");
318 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack
);
323 DRM_DEBUG_KMS("aux i2c too many retries, giving up\n");
327 /***** general DP utility functions *****/
329 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
330 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5
332 static void dp_get_adjust_train(u8 link_status
[DP_LINK_STATUS_SIZE
],
340 for (lane
= 0; lane
< lane_count
; lane
++) {
341 u8 this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
342 u8 this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
344 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
346 voltage_names
[this_v
>> DP_TRAIN_VOLTAGE_SWING_SHIFT
],
347 pre_emph_names
[this_p
>> DP_TRAIN_PRE_EMPHASIS_SHIFT
]);
355 if (v
>= DP_VOLTAGE_MAX
)
356 v
|= DP_TRAIN_MAX_SWING_REACHED
;
358 if (p
>= DP_PRE_EMPHASIS_MAX
)
359 p
|= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
361 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
362 voltage_names
[(v
& DP_TRAIN_VOLTAGE_SWING_MASK
) >> DP_TRAIN_VOLTAGE_SWING_SHIFT
],
363 pre_emph_names
[(p
& DP_TRAIN_PRE_EMPHASIS_MASK
) >> DP_TRAIN_PRE_EMPHASIS_SHIFT
]);
365 for (lane
= 0; lane
< 4; lane
++)
366 train_set
[lane
] = v
| p
;
369 /* convert bits per color to bits per pixel */
370 /* get bpc from the EDID */
371 static int convert_bpc_to_bpp(int bpc
)
379 /* get the max pix clock supported by the link rate and lane num */
380 static int dp_get_max_dp_pix_clock(int link_rate
,
384 return (link_rate
* lane_num
* 8) / bpp
;
387 /***** radeon specific DP functions *****/
389 /* First get the min lane# when low rate is used according to pixel clock
390 * (prefer low rate), second check max lane# supported by DP panel,
391 * if the max lane# < low rate lane# then use max lane# instead.
393 static int radeon_dp_get_dp_lane_number(struct drm_connector
*connector
,
394 u8 dpcd
[DP_DPCD_SIZE
],
397 int bpp
= convert_bpc_to_bpp(radeon_get_monitor_bpc(connector
));
398 int max_link_rate
= drm_dp_max_link_rate(dpcd
);
399 int max_lane_num
= drm_dp_max_lane_count(dpcd
);
401 int max_dp_pix_clock
;
403 for (lane_num
= 1; lane_num
< max_lane_num
; lane_num
<<= 1) {
404 max_dp_pix_clock
= dp_get_max_dp_pix_clock(max_link_rate
, lane_num
, bpp
);
405 if (pix_clock
<= max_dp_pix_clock
)
412 static int radeon_dp_get_dp_link_clock(struct drm_connector
*connector
,
413 u8 dpcd
[DP_DPCD_SIZE
],
416 int bpp
= convert_bpc_to_bpp(radeon_get_monitor_bpc(connector
));
417 int lane_num
, max_pix_clock
;
419 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector
) ==
420 ENCODER_OBJECT_ID_NUTMEG
)
423 lane_num
= radeon_dp_get_dp_lane_number(connector
, dpcd
, pix_clock
);
424 max_pix_clock
= dp_get_max_dp_pix_clock(162000, lane_num
, bpp
);
425 if (pix_clock
<= max_pix_clock
)
427 max_pix_clock
= dp_get_max_dp_pix_clock(270000, lane_num
, bpp
);
428 if (pix_clock
<= max_pix_clock
)
430 if (radeon_connector_is_dp12_capable(connector
)) {
431 max_pix_clock
= dp_get_max_dp_pix_clock(540000, lane_num
, bpp
);
432 if (pix_clock
<= max_pix_clock
)
436 return drm_dp_max_link_rate(dpcd
);
439 static u8
radeon_dp_encoder_service(struct radeon_device
*rdev
,
440 int action
, int dp_clock
,
441 u8 ucconfig
, u8 lane_num
)
443 DP_ENCODER_SERVICE_PARAMETERS args
;
444 int index
= GetIndexIntoMasterTable(COMMAND
, DPEncoderService
);
446 memset(&args
, 0, sizeof(args
));
447 args
.ucLinkClock
= dp_clock
/ 10;
448 args
.ucConfig
= ucconfig
;
449 args
.ucAction
= action
;
450 args
.ucLaneNum
= lane_num
;
453 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
454 return args
.ucStatus
;
457 u8
radeon_dp_getsinktype(struct radeon_connector
*radeon_connector
)
459 struct radeon_connector_atom_dig
*dig_connector
= radeon_connector
->con_priv
;
460 struct drm_device
*dev
= radeon_connector
->base
.dev
;
461 struct radeon_device
*rdev
= dev
->dev_private
;
463 return radeon_dp_encoder_service(rdev
, ATOM_DP_ACTION_GET_SINK_TYPE
, 0,
464 dig_connector
->dp_i2c_bus
->rec
.i2c_id
, 0);
467 static void radeon_dp_probe_oui(struct radeon_connector
*radeon_connector
)
469 struct radeon_connector_atom_dig
*dig_connector
= radeon_connector
->con_priv
;
472 if (!(dig_connector
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
475 if (radeon_dp_aux_native_read(radeon_connector
, DP_SINK_OUI
, buf
, 3, 0))
476 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
477 buf
[0], buf
[1], buf
[2]);
479 if (radeon_dp_aux_native_read(radeon_connector
, DP_BRANCH_OUI
, buf
, 3, 0))
480 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
481 buf
[0], buf
[1], buf
[2]);
484 bool radeon_dp_getdpcd(struct radeon_connector
*radeon_connector
)
486 struct radeon_connector_atom_dig
*dig_connector
= radeon_connector
->con_priv
;
487 u8 msg
[DP_DPCD_SIZE
];
490 ret
= radeon_dp_aux_native_read(radeon_connector
, DP_DPCD_REV
, msg
,
493 memcpy(dig_connector
->dpcd
, msg
, DP_DPCD_SIZE
);
494 DRM_DEBUG_KMS("DPCD: ");
495 for (i
= 0; i
< DP_DPCD_SIZE
; i
++)
496 DRM_DEBUG_KMS("%02x ", msg
[i
]);
499 radeon_dp_probe_oui(radeon_connector
);
503 dig_connector
->dpcd
[0] = 0;
507 int radeon_dp_get_panel_mode(struct drm_encoder
*encoder
,
508 struct drm_connector
*connector
)
510 struct drm_device
*dev
= encoder
->dev
;
511 struct radeon_device
*rdev
= dev
->dev_private
;
512 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
513 int panel_mode
= DP_PANEL_MODE_EXTERNAL_DP_MODE
;
514 u16 dp_bridge
= radeon_connector_encoder_get_dp_bridge_encoder_id(connector
);
517 if (!ASIC_IS_DCE4(rdev
))
520 if (dp_bridge
!= ENCODER_OBJECT_ID_NONE
) {
521 /* DP bridge chips */
522 tmp
= radeon_read_dpcd_reg(radeon_connector
, DP_EDP_CONFIGURATION_CAP
);
524 panel_mode
= DP_PANEL_MODE_INTERNAL_DP2_MODE
;
525 else if ((dp_bridge
== ENCODER_OBJECT_ID_NUTMEG
) ||
526 (dp_bridge
== ENCODER_OBJECT_ID_TRAVIS
))
527 panel_mode
= DP_PANEL_MODE_INTERNAL_DP1_MODE
;
529 panel_mode
= DP_PANEL_MODE_EXTERNAL_DP_MODE
;
530 } else if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
) {
532 tmp
= radeon_read_dpcd_reg(radeon_connector
, DP_EDP_CONFIGURATION_CAP
);
534 panel_mode
= DP_PANEL_MODE_INTERNAL_DP2_MODE
;
540 void radeon_dp_set_link_config(struct drm_connector
*connector
,
541 const struct drm_display_mode
*mode
)
543 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
544 struct radeon_connector_atom_dig
*dig_connector
;
546 if (!radeon_connector
->con_priv
)
548 dig_connector
= radeon_connector
->con_priv
;
550 if ((dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_DISPLAYPORT
) ||
551 (dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_eDP
)) {
552 dig_connector
->dp_clock
=
553 radeon_dp_get_dp_link_clock(connector
, dig_connector
->dpcd
, mode
->clock
);
554 dig_connector
->dp_lane_count
=
555 radeon_dp_get_dp_lane_number(connector
, dig_connector
->dpcd
, mode
->clock
);
559 int radeon_dp_mode_valid_helper(struct drm_connector
*connector
,
560 struct drm_display_mode
*mode
)
562 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
563 struct radeon_connector_atom_dig
*dig_connector
;
566 if (!radeon_connector
->con_priv
)
567 return MODE_CLOCK_HIGH
;
568 dig_connector
= radeon_connector
->con_priv
;
571 radeon_dp_get_dp_link_clock(connector
, dig_connector
->dpcd
, mode
->clock
);
573 if ((dp_clock
== 540000) &&
574 (!radeon_connector_is_dp12_capable(connector
)))
575 return MODE_CLOCK_HIGH
;
580 static bool radeon_dp_get_link_status(struct radeon_connector
*radeon_connector
,
581 u8 link_status
[DP_LINK_STATUS_SIZE
])
584 ret
= radeon_dp_aux_native_read(radeon_connector
, DP_LANE0_1_STATUS
,
585 link_status
, DP_LINK_STATUS_SIZE
, 100);
590 DRM_DEBUG_KMS("link status %6ph\n", link_status
);
594 bool radeon_dp_needs_link_train(struct radeon_connector
*radeon_connector
)
596 u8 link_status
[DP_LINK_STATUS_SIZE
];
597 struct radeon_connector_atom_dig
*dig
= radeon_connector
->con_priv
;
599 if (!radeon_dp_get_link_status(radeon_connector
, link_status
))
601 if (drm_dp_channel_eq_ok(link_status
, dig
->dp_lane_count
))
606 struct radeon_dp_link_train_info
{
607 struct radeon_device
*rdev
;
608 struct drm_encoder
*encoder
;
609 struct drm_connector
*connector
;
610 struct radeon_connector
*radeon_connector
;
615 u8 dpcd
[DP_RECEIVER_CAP_SIZE
];
617 u8 link_status
[DP_LINK_STATUS_SIZE
];
622 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info
*dp_info
)
624 /* set the initial vs/emph on the source */
625 atombios_dig_transmitter_setup(dp_info
->encoder
,
626 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
,
627 0, dp_info
->train_set
[0]); /* sets all lanes at once */
629 /* set the vs/emph on the sink */
630 radeon_dp_aux_native_write(dp_info
->radeon_connector
, DP_TRAINING_LANE0_SET
,
631 dp_info
->train_set
, dp_info
->dp_lane_count
, 0);
634 static void radeon_dp_set_tp(struct radeon_dp_link_train_info
*dp_info
, int tp
)
638 /* set training pattern on the source */
639 if (ASIC_IS_DCE4(dp_info
->rdev
) || !dp_info
->use_dpencoder
) {
641 case DP_TRAINING_PATTERN_1
:
642 rtp
= ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1
;
644 case DP_TRAINING_PATTERN_2
:
645 rtp
= ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2
;
647 case DP_TRAINING_PATTERN_3
:
648 rtp
= ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3
;
651 atombios_dig_encoder_setup(dp_info
->encoder
, rtp
, 0);
654 case DP_TRAINING_PATTERN_1
:
657 case DP_TRAINING_PATTERN_2
:
661 radeon_dp_encoder_service(dp_info
->rdev
, ATOM_DP_ACTION_TRAINING_PATTERN_SEL
,
662 dp_info
->dp_clock
, dp_info
->enc_id
, rtp
);
665 /* enable training pattern on the sink */
666 radeon_write_dpcd_reg(dp_info
->radeon_connector
, DP_TRAINING_PATTERN_SET
, tp
);
669 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info
*dp_info
)
671 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(dp_info
->encoder
);
672 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
675 /* power up the sink */
676 if (dp_info
->dpcd
[0] >= 0x11)
677 radeon_write_dpcd_reg(dp_info
->radeon_connector
,
678 DP_SET_POWER
, DP_SET_POWER_D0
);
680 /* possibly enable downspread on the sink */
681 if (dp_info
->dpcd
[3] & 0x1)
682 radeon_write_dpcd_reg(dp_info
->radeon_connector
,
683 DP_DOWNSPREAD_CTRL
, DP_SPREAD_AMP_0_5
);
685 radeon_write_dpcd_reg(dp_info
->radeon_connector
,
686 DP_DOWNSPREAD_CTRL
, 0);
688 if ((dp_info
->connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
) &&
689 (dig
->panel_mode
== DP_PANEL_MODE_INTERNAL_DP2_MODE
)) {
690 radeon_write_dpcd_reg(dp_info
->radeon_connector
, DP_EDP_CONFIGURATION_SET
, 1);
693 /* set the lane count on the sink */
694 tmp
= dp_info
->dp_lane_count
;
695 if (drm_dp_enhanced_frame_cap(dp_info
->dpcd
))
696 tmp
|= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
697 radeon_write_dpcd_reg(dp_info
->radeon_connector
, DP_LANE_COUNT_SET
, tmp
);
699 /* set the link rate on the sink */
700 tmp
= drm_dp_link_rate_to_bw_code(dp_info
->dp_clock
);
701 radeon_write_dpcd_reg(dp_info
->radeon_connector
, DP_LINK_BW_SET
, tmp
);
703 /* start training on the source */
704 if (ASIC_IS_DCE4(dp_info
->rdev
) || !dp_info
->use_dpencoder
)
705 atombios_dig_encoder_setup(dp_info
->encoder
,
706 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START
, 0);
708 radeon_dp_encoder_service(dp_info
->rdev
, ATOM_DP_ACTION_TRAINING_START
,
709 dp_info
->dp_clock
, dp_info
->enc_id
, 0);
711 /* disable the training pattern on the sink */
712 radeon_write_dpcd_reg(dp_info
->radeon_connector
,
713 DP_TRAINING_PATTERN_SET
,
714 DP_TRAINING_PATTERN_DISABLE
);
719 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info
*dp_info
)
723 /* disable the training pattern on the sink */
724 radeon_write_dpcd_reg(dp_info
->radeon_connector
,
725 DP_TRAINING_PATTERN_SET
,
726 DP_TRAINING_PATTERN_DISABLE
);
728 /* disable the training pattern on the source */
729 if (ASIC_IS_DCE4(dp_info
->rdev
) || !dp_info
->use_dpencoder
)
730 atombios_dig_encoder_setup(dp_info
->encoder
,
731 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE
, 0);
733 radeon_dp_encoder_service(dp_info
->rdev
, ATOM_DP_ACTION_TRAINING_COMPLETE
,
734 dp_info
->dp_clock
, dp_info
->enc_id
, 0);
739 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info
*dp_info
)
745 radeon_dp_set_tp(dp_info
, DP_TRAINING_PATTERN_1
);
746 memset(dp_info
->train_set
, 0, 4);
747 radeon_dp_update_vs_emph(dp_info
);
751 /* clock recovery loop */
752 clock_recovery
= false;
756 drm_dp_link_train_clock_recovery_delay(dp_info
->dpcd
);
758 if (!radeon_dp_get_link_status(dp_info
->radeon_connector
, dp_info
->link_status
)) {
759 DRM_ERROR("displayport link status failed\n");
763 if (drm_dp_clock_recovery_ok(dp_info
->link_status
, dp_info
->dp_lane_count
)) {
764 clock_recovery
= true;
768 for (i
= 0; i
< dp_info
->dp_lane_count
; i
++) {
769 if ((dp_info
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
772 if (i
== dp_info
->dp_lane_count
) {
773 DRM_ERROR("clock recovery reached max voltage\n");
777 if ((dp_info
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
779 if (dp_info
->tries
== 5) {
780 DRM_ERROR("clock recovery tried 5 times\n");
786 voltage
= dp_info
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
788 /* Compute new train_set as requested by sink */
789 dp_get_adjust_train(dp_info
->link_status
, dp_info
->dp_lane_count
, dp_info
->train_set
);
791 radeon_dp_update_vs_emph(dp_info
);
793 if (!clock_recovery
) {
794 DRM_ERROR("clock recovery failed\n");
797 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
798 dp_info
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
,
799 (dp_info
->train_set
[0] & DP_TRAIN_PRE_EMPHASIS_MASK
) >>
800 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
805 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info
*dp_info
)
809 if (dp_info
->tp3_supported
)
810 radeon_dp_set_tp(dp_info
, DP_TRAINING_PATTERN_3
);
812 radeon_dp_set_tp(dp_info
, DP_TRAINING_PATTERN_2
);
814 /* channel equalization loop */
818 drm_dp_link_train_channel_eq_delay(dp_info
->dpcd
);
820 if (!radeon_dp_get_link_status(dp_info
->radeon_connector
, dp_info
->link_status
)) {
821 DRM_ERROR("displayport link status failed\n");
825 if (drm_dp_channel_eq_ok(dp_info
->link_status
, dp_info
->dp_lane_count
)) {
831 if (dp_info
->tries
> 5) {
832 DRM_ERROR("channel eq failed: 5 tries\n");
836 /* Compute new train_set as requested by sink */
837 dp_get_adjust_train(dp_info
->link_status
, dp_info
->dp_lane_count
, dp_info
->train_set
);
839 radeon_dp_update_vs_emph(dp_info
);
844 DRM_ERROR("channel eq failed\n");
847 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
848 dp_info
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
,
849 (dp_info
->train_set
[0] & DP_TRAIN_PRE_EMPHASIS_MASK
)
850 >> DP_TRAIN_PRE_EMPHASIS_SHIFT
);
855 void radeon_dp_link_train(struct drm_encoder
*encoder
,
856 struct drm_connector
*connector
)
858 struct drm_device
*dev
= encoder
->dev
;
859 struct radeon_device
*rdev
= dev
->dev_private
;
860 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
861 struct radeon_encoder_atom_dig
*dig
;
862 struct radeon_connector
*radeon_connector
;
863 struct radeon_connector_atom_dig
*dig_connector
;
864 struct radeon_dp_link_train_info dp_info
;
868 if (!radeon_encoder
->enc_priv
)
870 dig
= radeon_encoder
->enc_priv
;
872 radeon_connector
= to_radeon_connector(connector
);
873 if (!radeon_connector
->con_priv
)
875 dig_connector
= radeon_connector
->con_priv
;
877 if ((dig_connector
->dp_sink_type
!= CONNECTOR_OBJECT_ID_DISPLAYPORT
) &&
878 (dig_connector
->dp_sink_type
!= CONNECTOR_OBJECT_ID_eDP
))
881 /* DPEncoderService newer than 1.1 can't program properly the
882 * training pattern. When facing such version use the
883 * DIGXEncoderControl (X== 1 | 2)
885 dp_info
.use_dpencoder
= true;
886 index
= GetIndexIntoMasterTable(COMMAND
, DPEncoderService
);
887 if (atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
)) {
889 dp_info
.use_dpencoder
= false;
894 if (dig
->dig_encoder
)
895 dp_info
.enc_id
|= ATOM_DP_CONFIG_DIG2_ENCODER
;
897 dp_info
.enc_id
|= ATOM_DP_CONFIG_DIG1_ENCODER
;
899 dp_info
.enc_id
|= ATOM_DP_CONFIG_LINK_B
;
901 dp_info
.enc_id
|= ATOM_DP_CONFIG_LINK_A
;
903 tmp
= radeon_read_dpcd_reg(radeon_connector
, DP_MAX_LANE_COUNT
);
904 if (ASIC_IS_DCE5(rdev
) && (tmp
& DP_TPS3_SUPPORTED
))
905 dp_info
.tp3_supported
= true;
907 dp_info
.tp3_supported
= false;
909 memcpy(dp_info
.dpcd
, dig_connector
->dpcd
, DP_RECEIVER_CAP_SIZE
);
911 dp_info
.encoder
= encoder
;
912 dp_info
.connector
= connector
;
913 dp_info
.radeon_connector
= radeon_connector
;
914 dp_info
.dp_lane_count
= dig_connector
->dp_lane_count
;
915 dp_info
.dp_clock
= dig_connector
->dp_clock
;
917 if (radeon_dp_link_train_init(&dp_info
))
919 if (radeon_dp_link_train_cr(&dp_info
))
921 if (radeon_dp_link_train_ce(&dp_info
))
924 if (radeon_dp_link_train_finish(&dp_info
))