2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include "atom-bits.h"
32 #include "drm_dp_helper.h"
34 /* move these to drm_dp_helper.c/h */
35 #define DP_LINK_CONFIGURATION_SIZE 9
36 #define DP_LINK_STATUS_SIZE 6
37 #define DP_DPCD_SIZE 8
39 static char *voltage_names
[] = {
40 "0.4V", "0.6V", "0.8V", "1.2V"
42 static char *pre_emph_names
[] = {
43 "0dB", "3.5dB", "6dB", "9.5dB"
46 static const int dp_clocks
[] = {
47 54000, /* 1 lane, 1.62 Ghz */
48 90000, /* 1 lane, 2.70 Ghz */
49 108000, /* 2 lane, 1.62 Ghz */
50 180000, /* 2 lane, 2.70 Ghz */
51 216000, /* 4 lane, 1.62 Ghz */
52 360000, /* 4 lane, 2.70 Ghz */
55 static const int num_dp_clocks
= sizeof(dp_clocks
) / sizeof(int);
57 /* common helper functions */
58 static int dp_lanes_for_mode_clock(u8 dpcd
[DP_DPCD_SIZE
], int mode_clock
)
67 max_link_bw
= dpcd
[DP_MAX_LINK_RATE
];
68 max_lane_count
= dpcd
[DP_MAX_LANE_COUNT
] & DP_MAX_LANE_COUNT_MASK
;
70 switch (max_link_bw
) {
73 for (i
= 0; i
< num_dp_clocks
; i
++) {
76 switch (max_lane_count
) {
89 if (dp_clocks
[i
] > mode_clock
) {
100 for (i
= 0; i
< num_dp_clocks
; i
++) {
101 switch (max_lane_count
) {
114 if (dp_clocks
[i
] > mode_clock
) {
129 static int dp_link_clock_for_mode_clock(u8 dpcd
[DP_DPCD_SIZE
], int mode_clock
)
138 max_link_bw
= dpcd
[DP_MAX_LINK_RATE
];
139 max_lane_count
= dpcd
[DP_MAX_LANE_COUNT
] & DP_MAX_LANE_COUNT_MASK
;
141 switch (max_link_bw
) {
142 case DP_LINK_BW_1_62
:
144 for (i
= 0; i
< num_dp_clocks
; i
++) {
147 switch (max_lane_count
) {
160 if (dp_clocks
[i
] > mode_clock
)
165 for (i
= 0; i
< num_dp_clocks
; i
++) {
166 switch (max_lane_count
) {
179 if (dp_clocks
[i
] > mode_clock
)
180 return (i
% 2) ? 270000 : 162000;
187 int dp_mode_valid(u8 dpcd
[DP_DPCD_SIZE
], int mode_clock
)
189 int lanes
= dp_lanes_for_mode_clock(dpcd
, mode_clock
);
190 int bw
= dp_lanes_for_mode_clock(dpcd
, mode_clock
);
192 if ((lanes
== 0) || (bw
== 0))
193 return MODE_CLOCK_HIGH
;
198 static u8
dp_link_status(u8 link_status
[DP_LINK_STATUS_SIZE
], int r
)
200 return link_status
[r
- DP_LANE0_1_STATUS
];
203 static u8
dp_get_lane_status(u8 link_status
[DP_LINK_STATUS_SIZE
],
206 int i
= DP_LANE0_1_STATUS
+ (lane
>> 1);
207 int s
= (lane
& 1) * 4;
208 u8 l
= dp_link_status(link_status
, i
);
209 return (l
>> s
) & 0xf;
212 static bool dp_clock_recovery_ok(u8 link_status
[DP_LINK_STATUS_SIZE
],
218 for (lane
= 0; lane
< lane_count
; lane
++) {
219 lane_status
= dp_get_lane_status(link_status
, lane
);
220 if ((lane_status
& DP_LANE_CR_DONE
) == 0)
226 static bool dp_channel_eq_ok(u8 link_status
[DP_LINK_STATUS_SIZE
],
233 lane_align
= dp_link_status(link_status
,
234 DP_LANE_ALIGN_STATUS_UPDATED
);
235 if ((lane_align
& DP_INTERLANE_ALIGN_DONE
) == 0)
237 for (lane
= 0; lane
< lane_count
; lane
++) {
238 lane_status
= dp_get_lane_status(link_status
, lane
);
239 if ((lane_status
& DP_CHANNEL_EQ_BITS
) != DP_CHANNEL_EQ_BITS
)
245 static u8
dp_get_adjust_request_voltage(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
249 int i
= DP_ADJUST_REQUEST_LANE0_1
+ (lane
>> 1);
250 int s
= ((lane
& 1) ?
251 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT
:
252 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT
);
253 u8 l
= dp_link_status(link_status
, i
);
255 return ((l
>> s
) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT
;
258 static u8
dp_get_adjust_request_pre_emphasis(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
261 int i
= DP_ADJUST_REQUEST_LANE0_1
+ (lane
>> 1);
262 int s
= ((lane
& 1) ?
263 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT
:
264 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT
);
265 u8 l
= dp_link_status(link_status
, i
);
267 return ((l
>> s
) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT
;
270 /* XXX fix me -- chip specific */
271 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
272 static u8
dp_pre_emphasis_max(u8 voltage_swing
)
274 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
275 case DP_TRAIN_VOLTAGE_SWING_400
:
276 return DP_TRAIN_PRE_EMPHASIS_6
;
277 case DP_TRAIN_VOLTAGE_SWING_600
:
278 return DP_TRAIN_PRE_EMPHASIS_6
;
279 case DP_TRAIN_VOLTAGE_SWING_800
:
280 return DP_TRAIN_PRE_EMPHASIS_3_5
;
281 case DP_TRAIN_VOLTAGE_SWING_1200
:
283 return DP_TRAIN_PRE_EMPHASIS_0
;
287 static void dp_get_adjust_train(u8 link_status
[DP_LINK_STATUS_SIZE
],
295 for (lane
= 0; lane
< lane_count
; lane
++) {
296 u8 this_v
= dp_get_adjust_request_voltage(link_status
, lane
);
297 u8 this_p
= dp_get_adjust_request_pre_emphasis(link_status
, lane
);
299 DRM_DEBUG("requested signal parameters: lane %d voltage %s pre_emph %s\n",
301 voltage_names
[this_v
>> DP_TRAIN_VOLTAGE_SWING_SHIFT
],
302 pre_emph_names
[this_p
>> DP_TRAIN_PRE_EMPHASIS_SHIFT
]);
310 if (v
>= DP_VOLTAGE_MAX
)
311 v
= DP_VOLTAGE_MAX
| DP_TRAIN_MAX_SWING_REACHED
;
313 if (p
>= dp_pre_emphasis_max(v
))
314 p
= dp_pre_emphasis_max(v
) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
316 DRM_DEBUG("using signal parameters: voltage %s pre_emph %s\n",
317 voltage_names
[(v
& DP_TRAIN_VOLTAGE_SWING_MASK
) >> DP_TRAIN_VOLTAGE_SWING_SHIFT
],
318 pre_emph_names
[(p
& DP_TRAIN_PRE_EMPHASIS_MASK
) >> DP_TRAIN_PRE_EMPHASIS_SHIFT
]);
320 for (lane
= 0; lane
< 4; lane
++)
321 train_set
[lane
] = v
| p
;
325 /* radeon aux chan functions */
326 bool radeon_process_aux_ch(struct radeon_i2c_chan
*chan
, u8
*req_bytes
,
327 int num_bytes
, u8
*read_byte
,
328 u8 read_buf_len
, u8 delay
)
330 struct drm_device
*dev
= chan
->dev
;
331 struct radeon_device
*rdev
= dev
->dev_private
;
332 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION args
;
333 int index
= GetIndexIntoMasterTable(COMMAND
, ProcessAuxChannelTransaction
);
336 memset(&args
, 0, sizeof(args
));
338 base
= (unsigned char *)rdev
->mode_info
.atom_context
->scratch
;
340 memcpy(base
, req_bytes
, num_bytes
);
342 args
.lpAuxRequest
= 0;
344 args
.ucDataOutLen
= 0;
345 args
.ucChannelID
= chan
->rec
.i2c_id
;
346 args
.ucDelay
= delay
/ 10;
348 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
350 if (args
.ucReplyStatus
) {
351 DRM_DEBUG("failed to get auxch %02x%02x %02x %02x 0x%02x %02x\n",
352 req_bytes
[1], req_bytes
[0], req_bytes
[2], req_bytes
[3],
353 chan
->rec
.i2c_id
, args
.ucReplyStatus
);
357 if (args
.ucDataOutLen
&& read_byte
&& read_buf_len
) {
358 if (read_buf_len
< args
.ucDataOutLen
) {
359 DRM_ERROR("Buffer to small for return answer %d %d\n",
360 read_buf_len
, args
.ucDataOutLen
);
364 int len
= min(read_buf_len
, args
.ucDataOutLen
);
365 memcpy(read_byte
, base
+ 16, len
);
371 bool radeon_dp_aux_native_write(struct radeon_connector
*radeon_connector
, uint16_t address
,
372 uint8_t send_bytes
, uint8_t *send
)
374 struct radeon_connector_atom_dig
*dig_connector
= radeon_connector
->con_priv
;
376 u8 msg_len
, dp_msg_len
;
381 msg
[1] = address
>> 8;
382 msg
[2] = AUX_NATIVE_WRITE
<< 4;
383 dp_msg_len
+= send_bytes
;
384 msg
[3] = (dp_msg_len
<< 4) | (send_bytes
- 1);
389 memcpy(&msg
[4], send
, send_bytes
);
390 msg_len
= 4 + send_bytes
;
391 ret
= radeon_process_aux_ch(dig_connector
->dp_i2c_bus
, msg
, msg_len
, NULL
, 0, 0);
395 bool radeon_dp_aux_native_read(struct radeon_connector
*radeon_connector
, uint16_t address
,
396 uint8_t delay
, uint8_t expected_bytes
,
399 struct radeon_connector_atom_dig
*dig_connector
= radeon_connector
->con_priv
;
401 u8 msg_len
, dp_msg_len
;
406 msg
[1] = address
>> 8;
407 msg
[2] = AUX_NATIVE_READ
<< 4;
408 msg
[3] = (dp_msg_len
) << 4;
409 msg
[3] |= expected_bytes
- 1;
411 ret
= radeon_process_aux_ch(dig_connector
->dp_i2c_bus
, msg
, msg_len
, read_p
, expected_bytes
, delay
);
415 /* radeon dp functions */
416 static u8
radeon_dp_encoder_service(struct radeon_device
*rdev
, int action
, int dp_clock
,
417 uint8_t ucconfig
, uint8_t lane_num
)
419 DP_ENCODER_SERVICE_PARAMETERS args
;
420 int index
= GetIndexIntoMasterTable(COMMAND
, DPEncoderService
);
422 memset(&args
, 0, sizeof(args
));
423 args
.ucLinkClock
= dp_clock
/ 10;
424 args
.ucConfig
= ucconfig
;
425 args
.ucAction
= action
;
426 args
.ucLaneNum
= lane_num
;
429 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
430 return args
.ucStatus
;
433 u8
radeon_dp_getsinktype(struct radeon_connector
*radeon_connector
)
435 struct radeon_connector_atom_dig
*dig_connector
= radeon_connector
->con_priv
;
436 struct drm_device
*dev
= radeon_connector
->base
.dev
;
437 struct radeon_device
*rdev
= dev
->dev_private
;
439 return radeon_dp_encoder_service(rdev
, ATOM_DP_ACTION_GET_SINK_TYPE
, 0,
440 dig_connector
->dp_i2c_bus
->rec
.i2c_id
, 0);
443 bool radeon_dp_getdpcd(struct radeon_connector
*radeon_connector
)
445 struct radeon_connector_atom_dig
*dig_connector
= radeon_connector
->con_priv
;
449 ret
= radeon_dp_aux_native_read(radeon_connector
, DP_DPCD_REV
, 0, 8, msg
);
451 memcpy(dig_connector
->dpcd
, msg
, 8);
455 for (i
= 0; i
< 8; i
++)
456 DRM_DEBUG("%02x ", msg
[i
]);
461 dig_connector
->dpcd
[0] = 0;
465 void radeon_dp_set_link_config(struct drm_connector
*connector
,
466 struct drm_display_mode
*mode
)
468 struct radeon_connector
*radeon_connector
;
469 struct radeon_connector_atom_dig
*dig_connector
;
471 if ((connector
->connector_type
!= DRM_MODE_CONNECTOR_DisplayPort
) ||
472 (connector
->connector_type
!= DRM_MODE_CONNECTOR_eDP
))
475 radeon_connector
= to_radeon_connector(connector
);
476 if (!radeon_connector
->con_priv
)
478 dig_connector
= radeon_connector
->con_priv
;
480 dig_connector
->dp_clock
=
481 dp_link_clock_for_mode_clock(dig_connector
->dpcd
, mode
->clock
);
482 dig_connector
->dp_lane_count
=
483 dp_lanes_for_mode_clock(dig_connector
->dpcd
, mode
->clock
);
486 int radeon_dp_mode_valid_helper(struct radeon_connector
*radeon_connector
,
487 struct drm_display_mode
*mode
)
489 struct radeon_connector_atom_dig
*dig_connector
= radeon_connector
->con_priv
;
491 return dp_mode_valid(dig_connector
->dpcd
, mode
->clock
);
494 static bool atom_dp_get_link_status(struct radeon_connector
*radeon_connector
,
495 u8 link_status
[DP_LINK_STATUS_SIZE
])
498 ret
= radeon_dp_aux_native_read(radeon_connector
, DP_LANE0_1_STATUS
, 100,
499 DP_LINK_STATUS_SIZE
, link_status
);
501 DRM_ERROR("displayport link status failed\n");
505 DRM_DEBUG("link status %02x %02x %02x %02x %02x %02x\n",
506 link_status
[0], link_status
[1], link_status
[2],
507 link_status
[3], link_status
[4], link_status
[5]);
511 bool radeon_dp_needs_link_train(struct radeon_connector
*radeon_connector
)
513 struct radeon_connector_atom_dig
*dig_connector
= radeon_connector
->con_priv
;
514 u8 link_status
[DP_LINK_STATUS_SIZE
];
516 if (!atom_dp_get_link_status(radeon_connector
, link_status
))
518 if (dp_channel_eq_ok(link_status
, dig_connector
->dp_lane_count
))
523 static void dp_set_power(struct radeon_connector
*radeon_connector
, u8 power_state
)
525 struct radeon_connector_atom_dig
*dig_connector
= radeon_connector
->con_priv
;
527 if (dig_connector
->dpcd
[0] >= 0x11) {
528 radeon_dp_aux_native_write(radeon_connector
, DP_SET_POWER
, 1,
533 static void dp_set_downspread(struct radeon_connector
*radeon_connector
, u8 downspread
)
535 radeon_dp_aux_native_write(radeon_connector
, DP_DOWNSPREAD_CTRL
, 1,
539 static void dp_set_link_bw_lanes(struct radeon_connector
*radeon_connector
,
540 u8 link_configuration
[DP_LINK_CONFIGURATION_SIZE
])
542 radeon_dp_aux_native_write(radeon_connector
, DP_LINK_BW_SET
, 2,
546 static void dp_update_dpvs_emph(struct radeon_connector
*radeon_connector
,
547 struct drm_encoder
*encoder
,
550 struct radeon_connector_atom_dig
*dig_connector
= radeon_connector
->con_priv
;
553 for (i
= 0; i
< dig_connector
->dp_lane_count
; i
++)
554 atombios_dig_transmitter_setup(encoder
,
555 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
,
558 radeon_dp_aux_native_write(radeon_connector
, DP_TRAINING_LANE0_SET
,
559 dig_connector
->dp_lane_count
, train_set
);
562 static void dp_set_training(struct radeon_connector
*radeon_connector
,
565 radeon_dp_aux_native_write(radeon_connector
, DP_TRAINING_PATTERN_SET
,
569 void dp_link_train(struct drm_encoder
*encoder
,
570 struct drm_connector
*connector
)
572 struct drm_device
*dev
= encoder
->dev
;
573 struct radeon_device
*rdev
= dev
->dev_private
;
574 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
575 struct radeon_encoder_atom_dig
*dig
;
576 struct radeon_connector
*radeon_connector
;
577 struct radeon_connector_atom_dig
*dig_connector
;
579 bool clock_recovery
, channel_eq
;
580 u8 link_status
[DP_LINK_STATUS_SIZE
];
581 u8 link_configuration
[DP_LINK_CONFIGURATION_SIZE
];
586 if ((connector
->connector_type
!= DRM_MODE_CONNECTOR_DisplayPort
) ||
587 (connector
->connector_type
!= DRM_MODE_CONNECTOR_eDP
))
590 if (!radeon_encoder
->enc_priv
)
592 dig
= radeon_encoder
->enc_priv
;
594 radeon_connector
= to_radeon_connector(connector
);
595 if (!radeon_connector
->con_priv
)
597 dig_connector
= radeon_connector
->con_priv
;
599 if (ASIC_IS_DCE32(rdev
)) {
601 enc_id
|= ATOM_DP_CONFIG_DIG2_ENCODER
;
603 enc_id
|= ATOM_DP_CONFIG_DIG1_ENCODER
;
604 if (dig_connector
->linkb
)
605 enc_id
|= ATOM_DP_CONFIG_LINK_B
;
607 enc_id
|= ATOM_DP_CONFIG_LINK_A
;
609 if (dig_connector
->linkb
)
610 enc_id
|= ATOM_DP_CONFIG_DIG2_ENCODER
| ATOM_DP_CONFIG_LINK_B
;
612 enc_id
|= ATOM_DP_CONFIG_DIG1_ENCODER
| ATOM_DP_CONFIG_LINK_A
;
615 memset(link_configuration
, 0, DP_LINK_CONFIGURATION_SIZE
);
616 if (dig_connector
->dp_clock
== 270000)
617 link_configuration
[0] = DP_LINK_BW_2_7
;
619 link_configuration
[0] = DP_LINK_BW_1_62
;
620 link_configuration
[1] = dig_connector
->dp_lane_count
;
621 if (dig_connector
->dpcd
[0] >= 0x11)
622 link_configuration
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
624 /* power up the sink */
625 dp_set_power(radeon_connector
, DP_SET_POWER_D0
);
626 /* disable the training pattern on the sink */
627 dp_set_training(radeon_connector
, DP_TRAINING_PATTERN_DISABLE
);
628 /* set link bw and lanes on the sink */
629 dp_set_link_bw_lanes(radeon_connector
, link_configuration
);
630 /* disable downspread on the sink */
631 dp_set_downspread(radeon_connector
, 0);
632 /* start training on the source */
633 radeon_dp_encoder_service(rdev
, ATOM_DP_ACTION_TRAINING_START
,
634 dig_connector
->dp_clock
, enc_id
, 0);
635 /* set training pattern 1 on the source */
636 radeon_dp_encoder_service(rdev
, ATOM_DP_ACTION_TRAINING_PATTERN_SEL
,
637 dig_connector
->dp_clock
, enc_id
, 0);
639 /* set initial vs/emph */
640 memset(train_set
, 0, 4);
642 /* set training pattern 1 on the sink */
643 dp_set_training(radeon_connector
, DP_TRAINING_PATTERN_1
);
645 dp_update_dpvs_emph(radeon_connector
, encoder
, train_set
);
647 /* clock recovery loop */
648 clock_recovery
= false;
653 if (!atom_dp_get_link_status(radeon_connector
, link_status
))
656 if (dp_clock_recovery_ok(link_status
, dig_connector
->dp_lane_count
)) {
657 clock_recovery
= true;
661 for (i
= 0; i
< dig_connector
->dp_lane_count
; i
++) {
662 if ((train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
665 if (i
== dig_connector
->dp_lane_count
) {
666 DRM_ERROR("clock recovery reached max voltage\n");
670 if ((train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
673 DRM_ERROR("clock recovery tried 5 times\n");
679 voltage
= train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
681 /* Compute new train_set as requested by sink */
682 dp_get_adjust_train(link_status
, dig_connector
->dp_lane_count
, train_set
);
683 dp_update_dpvs_emph(radeon_connector
, encoder
, train_set
);
686 DRM_ERROR("clock recovery failed\n");
688 DRM_DEBUG("clock recovery at voltage %d pre-emphasis %d\n",
689 train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
,
690 (train_set
[0] & DP_TRAIN_PRE_EMPHASIS_MASK
) >>
691 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
694 /* set training pattern 2 on the sink */
695 dp_set_training(radeon_connector
, DP_TRAINING_PATTERN_2
);
696 /* set training pattern 2 on the source */
697 radeon_dp_encoder_service(rdev
, ATOM_DP_ACTION_TRAINING_PATTERN_SEL
,
698 dig_connector
->dp_clock
, enc_id
, 1);
700 /* channel equalization loop */
705 if (!atom_dp_get_link_status(radeon_connector
, link_status
))
708 if (dp_channel_eq_ok(link_status
, dig_connector
->dp_lane_count
)) {
715 DRM_ERROR("channel eq failed: 5 tries\n");
719 /* Compute new train_set as requested by sink */
720 dp_get_adjust_train(link_status
, dig_connector
->dp_lane_count
, train_set
);
721 dp_update_dpvs_emph(radeon_connector
, encoder
, train_set
);
727 DRM_ERROR("channel eq failed\n");
729 DRM_DEBUG("channel eq at voltage %d pre-emphasis %d\n",
730 train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
,
731 (train_set
[0] & DP_TRAIN_PRE_EMPHASIS_MASK
)
732 >> DP_TRAIN_PRE_EMPHASIS_SHIFT
);
734 /* disable the training pattern on the sink */
735 dp_set_training(radeon_connector
, DP_TRAINING_PATTERN_DISABLE
);
737 radeon_dp_encoder_service(rdev
, ATOM_DP_ACTION_TRAINING_COMPLETE
,
738 dig_connector
->dp_clock
, enc_id
, 0);
741 int radeon_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
742 uint8_t write_byte
, uint8_t *read_byte
)
744 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
745 struct radeon_i2c_chan
*auxch
= (struct radeon_i2c_chan
*)adapter
;
747 uint16_t address
= algo_data
->address
;
750 int msg_len
, dp_msg_len
;
753 /* Set up the command byte */
754 if (mode
& MODE_I2C_READ
)
755 msg
[2] = AUX_I2C_READ
<< 4;
757 msg
[2] = AUX_I2C_WRITE
<< 4;
759 if (!(mode
& MODE_I2C_STOP
))
760 msg
[2] |= AUX_I2C_MOT
<< 4;
763 msg
[1] = address
>> 8;
782 msg
[3] = (dp_msg_len
) << 4;
783 ret
= radeon_process_aux_ch(auxch
, msg
, msg_len
, reply
, reply_bytes
, 0);
787 *read_byte
= reply
[0];