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3f46bb1bb9875e75edaaf38a5638d8348772988a
[deliverable/linux.git] / drivers / gpu / drm / radeon / atombios_dp.c
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 * Jerome Glisse
26 */
27 #include <drm/drmP.h>
28 #include <drm/radeon_drm.h>
29 #include "radeon.h"
30
31 #include "atom.h"
32 #include "atom-bits.h"
33 #include <drm/drm_dp_helper.h>
34
35 /* move these to drm_dp_helper.c/h */
36 #define DP_LINK_CONFIGURATION_SIZE 9
37 #define DP_DPCD_SIZE 8
38
39 static char *voltage_names[] = {
40 "0.4V", "0.6V", "0.8V", "1.2V"
41 };
42 static char *pre_emph_names[] = {
43 "0dB", "3.5dB", "6dB", "9.5dB"
44 };
45
46 /***** radeon AUX functions *****/
47 union aux_channel_transaction {
48 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
49 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
50 };
51
52 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
53 u8 *send, int send_bytes,
54 u8 *recv, int recv_size,
55 u8 delay, u8 *ack)
56 {
57 struct drm_device *dev = chan->dev;
58 struct radeon_device *rdev = dev->dev_private;
59 union aux_channel_transaction args;
60 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
61 unsigned char *base;
62 int recv_bytes;
63
64 memset(&args, 0, sizeof(args));
65
66 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
67
68 memcpy(base, send, send_bytes);
69
70 args.v1.lpAuxRequest = 0 + 4;
71 args.v1.lpDataOut = 16 + 4;
72 args.v1.ucDataOutLen = 0;
73 args.v1.ucChannelID = chan->rec.i2c_id;
74 args.v1.ucDelay = delay / 10;
75 if (ASIC_IS_DCE4(rdev))
76 args.v2.ucHPD_ID = chan->rec.hpd;
77
78 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
79
80 *ack = args.v1.ucReplyStatus;
81
82 /* timeout */
83 if (args.v1.ucReplyStatus == 1) {
84 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
85 return -ETIMEDOUT;
86 }
87
88 /* flags not zero */
89 if (args.v1.ucReplyStatus == 2) {
90 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
91 return -EBUSY;
92 }
93
94 /* error */
95 if (args.v1.ucReplyStatus == 3) {
96 DRM_DEBUG_KMS("dp_aux_ch error\n");
97 return -EIO;
98 }
99
100 recv_bytes = args.v1.ucDataOutLen;
101 if (recv_bytes > recv_size)
102 recv_bytes = recv_size;
103
104 if (recv && recv_size)
105 memcpy(recv, base + 16, recv_bytes);
106
107 return recv_bytes;
108 }
109
110 static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
111 u16 address, u8 *send, u8 send_bytes, u8 delay)
112 {
113 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
114 int ret;
115 u8 msg[20];
116 int msg_bytes = send_bytes + 4;
117 u8 ack;
118 unsigned retry;
119
120 if (send_bytes > 16)
121 return -1;
122
123 msg[0] = address;
124 msg[1] = address >> 8;
125 msg[2] = AUX_NATIVE_WRITE << 4;
126 msg[3] = (msg_bytes << 4) | (send_bytes - 1);
127 memcpy(&msg[4], send, send_bytes);
128
129 for (retry = 0; retry < 4; retry++) {
130 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
131 msg, msg_bytes, NULL, 0, delay, &ack);
132 if (ret == -EBUSY)
133 continue;
134 else if (ret < 0)
135 return ret;
136 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
137 return send_bytes;
138 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
139 udelay(400);
140 else
141 return -EIO;
142 }
143
144 return -EIO;
145 }
146
147 static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
148 u16 address, u8 *recv, int recv_bytes, u8 delay)
149 {
150 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
151 u8 msg[4];
152 int msg_bytes = 4;
153 u8 ack;
154 int ret;
155 unsigned retry;
156
157 msg[0] = address;
158 msg[1] = address >> 8;
159 msg[2] = AUX_NATIVE_READ << 4;
160 msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
161
162 for (retry = 0; retry < 4; retry++) {
163 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
164 msg, msg_bytes, recv, recv_bytes, delay, &ack);
165 if (ret == -EBUSY)
166 continue;
167 else if (ret < 0)
168 return ret;
169 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
170 return ret;
171 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
172 udelay(400);
173 else if (ret == 0)
174 return -EPROTO;
175 else
176 return -EIO;
177 }
178
179 return -EIO;
180 }
181
182 static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,
183 u16 reg, u8 val)
184 {
185 radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0);
186 }
187
188 static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector,
189 u16 reg)
190 {
191 u8 val = 0;
192
193 radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0);
194
195 return val;
196 }
197
198 int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
199 u8 write_byte, u8 *read_byte)
200 {
201 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
202 struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter;
203 u16 address = algo_data->address;
204 u8 msg[5];
205 u8 reply[2];
206 unsigned retry;
207 int msg_bytes;
208 int reply_bytes = 1;
209 int ret;
210 u8 ack;
211
212 /* Set up the command byte */
213 if (mode & MODE_I2C_READ)
214 msg[2] = AUX_I2C_READ << 4;
215 else
216 msg[2] = AUX_I2C_WRITE << 4;
217
218 if (!(mode & MODE_I2C_STOP))
219 msg[2] |= AUX_I2C_MOT << 4;
220
221 msg[0] = address;
222 msg[1] = address >> 8;
223
224 switch (mode) {
225 case MODE_I2C_WRITE:
226 msg_bytes = 5;
227 msg[3] = msg_bytes << 4;
228 msg[4] = write_byte;
229 break;
230 case MODE_I2C_READ:
231 msg_bytes = 4;
232 msg[3] = msg_bytes << 4;
233 break;
234 default:
235 msg_bytes = 4;
236 msg[3] = 3 << 4;
237 break;
238 }
239
240 for (retry = 0; retry < 4; retry++) {
241 ret = radeon_process_aux_ch(auxch,
242 msg, msg_bytes, reply, reply_bytes, 0, &ack);
243 if (ret == -EBUSY)
244 continue;
245 else if (ret < 0) {
246 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
247 return ret;
248 }
249
250 switch (ack & AUX_NATIVE_REPLY_MASK) {
251 case AUX_NATIVE_REPLY_ACK:
252 /* I2C-over-AUX Reply field is only valid
253 * when paired with AUX ACK.
254 */
255 break;
256 case AUX_NATIVE_REPLY_NACK:
257 DRM_DEBUG_KMS("aux_ch native nack\n");
258 return -EREMOTEIO;
259 case AUX_NATIVE_REPLY_DEFER:
260 DRM_DEBUG_KMS("aux_ch native defer\n");
261 udelay(400);
262 continue;
263 default:
264 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack);
265 return -EREMOTEIO;
266 }
267
268 switch (ack & AUX_I2C_REPLY_MASK) {
269 case AUX_I2C_REPLY_ACK:
270 if (mode == MODE_I2C_READ)
271 *read_byte = reply[0];
272 return ret;
273 case AUX_I2C_REPLY_NACK:
274 DRM_DEBUG_KMS("aux_i2c nack\n");
275 return -EREMOTEIO;
276 case AUX_I2C_REPLY_DEFER:
277 DRM_DEBUG_KMS("aux_i2c defer\n");
278 udelay(400);
279 break;
280 default:
281 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack);
282 return -EREMOTEIO;
283 }
284 }
285
286 DRM_DEBUG_KMS("aux i2c too many retries, giving up\n");
287 return -EREMOTEIO;
288 }
289
290 /***** general DP utility functions *****/
291
292 static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
293 {
294 return link_status[r - DP_LANE0_1_STATUS];
295 }
296
297 static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
298 int lane)
299 {
300 int i = DP_LANE0_1_STATUS + (lane >> 1);
301 int s = (lane & 1) * 4;
302 u8 l = dp_link_status(link_status, i);
303 return (l >> s) & 0xf;
304 }
305
306 static bool dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
307 int lane_count)
308 {
309 int lane;
310 u8 lane_status;
311
312 for (lane = 0; lane < lane_count; lane++) {
313 lane_status = dp_get_lane_status(link_status, lane);
314 if ((lane_status & DP_LANE_CR_DONE) == 0)
315 return false;
316 }
317 return true;
318 }
319
320 static u8 dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
321 int lane)
322
323 {
324 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
325 int s = ((lane & 1) ?
326 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
327 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
328 u8 l = dp_link_status(link_status, i);
329
330 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
331 }
332
333 static u8 dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
334 int lane)
335 {
336 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
337 int s = ((lane & 1) ?
338 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
339 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
340 u8 l = dp_link_status(link_status, i);
341
342 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
343 }
344
345 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
346 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5
347
348 static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
349 int lane_count,
350 u8 train_set[4])
351 {
352 u8 v = 0;
353 u8 p = 0;
354 int lane;
355
356 for (lane = 0; lane < lane_count; lane++) {
357 u8 this_v = dp_get_adjust_request_voltage(link_status, lane);
358 u8 this_p = dp_get_adjust_request_pre_emphasis(link_status, lane);
359
360 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
361 lane,
362 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
363 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
364
365 if (this_v > v)
366 v = this_v;
367 if (this_p > p)
368 p = this_p;
369 }
370
371 if (v >= DP_VOLTAGE_MAX)
372 v |= DP_TRAIN_MAX_SWING_REACHED;
373
374 if (p >= DP_PRE_EMPHASIS_MAX)
375 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
376
377 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
378 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
379 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
380
381 for (lane = 0; lane < 4; lane++)
382 train_set[lane] = v | p;
383 }
384
385 /* convert bits per color to bits per pixel */
386 /* get bpc from the EDID */
387 static int convert_bpc_to_bpp(int bpc)
388 {
389 if (bpc == 0)
390 return 24;
391 else
392 return bpc * 3;
393 }
394
395 /* get the max pix clock supported by the link rate and lane num */
396 static int dp_get_max_dp_pix_clock(int link_rate,
397 int lane_num,
398 int bpp)
399 {
400 return (link_rate * lane_num * 8) / bpp;
401 }
402
403 static int dp_get_max_link_rate(u8 dpcd[DP_DPCD_SIZE])
404 {
405 switch (dpcd[DP_MAX_LINK_RATE]) {
406 case DP_LINK_BW_1_62:
407 default:
408 return 162000;
409 case DP_LINK_BW_2_7:
410 return 270000;
411 case DP_LINK_BW_5_4:
412 return 540000;
413 }
414 }
415
416 static u8 dp_get_max_lane_number(u8 dpcd[DP_DPCD_SIZE])
417 {
418 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
419 }
420
421 static u8 dp_get_dp_link_rate_coded(int link_rate)
422 {
423 switch (link_rate) {
424 case 162000:
425 default:
426 return DP_LINK_BW_1_62;
427 case 270000:
428 return DP_LINK_BW_2_7;
429 case 540000:
430 return DP_LINK_BW_5_4;
431 }
432 }
433
434 /***** radeon specific DP functions *****/
435
436 /* First get the min lane# when low rate is used according to pixel clock
437 * (prefer low rate), second check max lane# supported by DP panel,
438 * if the max lane# < low rate lane# then use max lane# instead.
439 */
440 static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
441 u8 dpcd[DP_DPCD_SIZE],
442 int pix_clock)
443 {
444 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
445 int max_link_rate = dp_get_max_link_rate(dpcd);
446 int max_lane_num = dp_get_max_lane_number(dpcd);
447 int lane_num;
448 int max_dp_pix_clock;
449
450 for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
451 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
452 if (pix_clock <= max_dp_pix_clock)
453 break;
454 }
455
456 return lane_num;
457 }
458
459 static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
460 u8 dpcd[DP_DPCD_SIZE],
461 int pix_clock)
462 {
463 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
464 int lane_num, max_pix_clock;
465
466 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
467 ENCODER_OBJECT_ID_NUTMEG)
468 return 270000;
469
470 lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
471 max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
472 if (pix_clock <= max_pix_clock)
473 return 162000;
474 max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
475 if (pix_clock <= max_pix_clock)
476 return 270000;
477 if (radeon_connector_is_dp12_capable(connector)) {
478 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
479 if (pix_clock <= max_pix_clock)
480 return 540000;
481 }
482
483 return dp_get_max_link_rate(dpcd);
484 }
485
486 static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
487 int action, int dp_clock,
488 u8 ucconfig, u8 lane_num)
489 {
490 DP_ENCODER_SERVICE_PARAMETERS args;
491 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
492
493 memset(&args, 0, sizeof(args));
494 args.ucLinkClock = dp_clock / 10;
495 args.ucConfig = ucconfig;
496 args.ucAction = action;
497 args.ucLaneNum = lane_num;
498 args.ucStatus = 0;
499
500 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
501 return args.ucStatus;
502 }
503
504 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
505 {
506 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
507 struct drm_device *dev = radeon_connector->base.dev;
508 struct radeon_device *rdev = dev->dev_private;
509
510 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
511 dig_connector->dp_i2c_bus->rec.i2c_id, 0);
512 }
513
514 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
515 {
516 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
517 u8 buf[3];
518
519 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
520 return;
521
522 if (radeon_dp_aux_native_read(radeon_connector, DP_SINK_OUI, buf, 3, 0))
523 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
524 buf[0], buf[1], buf[2]);
525
526 if (radeon_dp_aux_native_read(radeon_connector, DP_BRANCH_OUI, buf, 3, 0))
527 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
528 buf[0], buf[1], buf[2]);
529 }
530
531 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
532 {
533 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
534 u8 msg[25];
535 int ret, i;
536
537 ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg, 8, 0);
538 if (ret > 0) {
539 memcpy(dig_connector->dpcd, msg, 8);
540 DRM_DEBUG_KMS("DPCD: ");
541 for (i = 0; i < 8; i++)
542 DRM_DEBUG_KMS("%02x ", msg[i]);
543 DRM_DEBUG_KMS("\n");
544
545 radeon_dp_probe_oui(radeon_connector);
546
547 return true;
548 }
549 dig_connector->dpcd[0] = 0;
550 return false;
551 }
552
553 int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
554 struct drm_connector *connector)
555 {
556 struct drm_device *dev = encoder->dev;
557 struct radeon_device *rdev = dev->dev_private;
558 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
559 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
560 u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
561 u8 tmp;
562
563 if (!ASIC_IS_DCE4(rdev))
564 return panel_mode;
565
566 if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
567 /* DP bridge chips */
568 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
569 if (tmp & 1)
570 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
571 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
572 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
573 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
574 else
575 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
576 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
577 /* eDP */
578 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
579 if (tmp & 1)
580 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
581 }
582
583 return panel_mode;
584 }
585
586 void radeon_dp_set_link_config(struct drm_connector *connector,
587 const struct drm_display_mode *mode)
588 {
589 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
590 struct radeon_connector_atom_dig *dig_connector;
591
592 if (!radeon_connector->con_priv)
593 return;
594 dig_connector = radeon_connector->con_priv;
595
596 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
597 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
598 dig_connector->dp_clock =
599 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
600 dig_connector->dp_lane_count =
601 radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
602 }
603 }
604
605 int radeon_dp_mode_valid_helper(struct drm_connector *connector,
606 struct drm_display_mode *mode)
607 {
608 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
609 struct radeon_connector_atom_dig *dig_connector;
610 int dp_clock;
611
612 if (!radeon_connector->con_priv)
613 return MODE_CLOCK_HIGH;
614 dig_connector = radeon_connector->con_priv;
615
616 dp_clock =
617 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
618
619 if ((dp_clock == 540000) &&
620 (!radeon_connector_is_dp12_capable(connector)))
621 return MODE_CLOCK_HIGH;
622
623 return MODE_OK;
624 }
625
626 static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector,
627 u8 link_status[DP_LINK_STATUS_SIZE])
628 {
629 int ret;
630 ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS,
631 link_status, DP_LINK_STATUS_SIZE, 100);
632 if (ret <= 0) {
633 return false;
634 }
635
636 DRM_DEBUG_KMS("link status %*ph\n", 6, link_status);
637 return true;
638 }
639
640 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
641 {
642 u8 link_status[DP_LINK_STATUS_SIZE];
643 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
644
645 if (!radeon_dp_get_link_status(radeon_connector, link_status))
646 return false;
647 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
648 return false;
649 return true;
650 }
651
652 struct radeon_dp_link_train_info {
653 struct radeon_device *rdev;
654 struct drm_encoder *encoder;
655 struct drm_connector *connector;
656 struct radeon_connector *radeon_connector;
657 int enc_id;
658 int dp_clock;
659 int dp_lane_count;
660 int rd_interval;
661 bool tp3_supported;
662 u8 dpcd[8];
663 u8 train_set[4];
664 u8 link_status[DP_LINK_STATUS_SIZE];
665 u8 tries;
666 bool use_dpencoder;
667 };
668
669 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
670 {
671 /* set the initial vs/emph on the source */
672 atombios_dig_transmitter_setup(dp_info->encoder,
673 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
674 0, dp_info->train_set[0]); /* sets all lanes at once */
675
676 /* set the vs/emph on the sink */
677 radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET,
678 dp_info->train_set, dp_info->dp_lane_count, 0);
679 }
680
681 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
682 {
683 int rtp = 0;
684
685 /* set training pattern on the source */
686 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
687 switch (tp) {
688 case DP_TRAINING_PATTERN_1:
689 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
690 break;
691 case DP_TRAINING_PATTERN_2:
692 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
693 break;
694 case DP_TRAINING_PATTERN_3:
695 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
696 break;
697 }
698 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
699 } else {
700 switch (tp) {
701 case DP_TRAINING_PATTERN_1:
702 rtp = 0;
703 break;
704 case DP_TRAINING_PATTERN_2:
705 rtp = 1;
706 break;
707 }
708 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
709 dp_info->dp_clock, dp_info->enc_id, rtp);
710 }
711
712 /* enable training pattern on the sink */
713 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp);
714 }
715
716 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
717 {
718 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
719 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
720 u8 tmp;
721
722 /* power up the sink */
723 if (dp_info->dpcd[0] >= 0x11)
724 radeon_write_dpcd_reg(dp_info->radeon_connector,
725 DP_SET_POWER, DP_SET_POWER_D0);
726
727 /* possibly enable downspread on the sink */
728 if (dp_info->dpcd[3] & 0x1)
729 radeon_write_dpcd_reg(dp_info->radeon_connector,
730 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
731 else
732 radeon_write_dpcd_reg(dp_info->radeon_connector,
733 DP_DOWNSPREAD_CTRL, 0);
734
735 if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
736 (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
737 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1);
738 }
739
740 /* set the lane count on the sink */
741 tmp = dp_info->dp_lane_count;
742 if (dp_info->dpcd[DP_DPCD_REV] >= 0x11 &&
743 dp_info->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)
744 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
745 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp);
746
747 /* set the link rate on the sink */
748 tmp = dp_get_dp_link_rate_coded(dp_info->dp_clock);
749 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp);
750
751 /* start training on the source */
752 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
753 atombios_dig_encoder_setup(dp_info->encoder,
754 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
755 else
756 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
757 dp_info->dp_clock, dp_info->enc_id, 0);
758
759 /* disable the training pattern on the sink */
760 radeon_write_dpcd_reg(dp_info->radeon_connector,
761 DP_TRAINING_PATTERN_SET,
762 DP_TRAINING_PATTERN_DISABLE);
763
764 return 0;
765 }
766
767 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
768 {
769 udelay(400);
770
771 /* disable the training pattern on the sink */
772 radeon_write_dpcd_reg(dp_info->radeon_connector,
773 DP_TRAINING_PATTERN_SET,
774 DP_TRAINING_PATTERN_DISABLE);
775
776 /* disable the training pattern on the source */
777 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
778 atombios_dig_encoder_setup(dp_info->encoder,
779 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
780 else
781 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
782 dp_info->dp_clock, dp_info->enc_id, 0);
783
784 return 0;
785 }
786
787 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
788 {
789 bool clock_recovery;
790 u8 voltage;
791 int i;
792
793 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
794 memset(dp_info->train_set, 0, 4);
795 radeon_dp_update_vs_emph(dp_info);
796
797 udelay(400);
798
799 /* clock recovery loop */
800 clock_recovery = false;
801 dp_info->tries = 0;
802 voltage = 0xff;
803 while (1) {
804 if (dp_info->rd_interval == 0)
805 udelay(100);
806 else
807 mdelay(dp_info->rd_interval * 4);
808
809 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) {
810 DRM_ERROR("displayport link status failed\n");
811 break;
812 }
813
814 if (dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
815 clock_recovery = true;
816 break;
817 }
818
819 for (i = 0; i < dp_info->dp_lane_count; i++) {
820 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
821 break;
822 }
823 if (i == dp_info->dp_lane_count) {
824 DRM_ERROR("clock recovery reached max voltage\n");
825 break;
826 }
827
828 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
829 ++dp_info->tries;
830 if (dp_info->tries == 5) {
831 DRM_ERROR("clock recovery tried 5 times\n");
832 break;
833 }
834 } else
835 dp_info->tries = 0;
836
837 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
838
839 /* Compute new train_set as requested by sink */
840 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
841
842 radeon_dp_update_vs_emph(dp_info);
843 }
844 if (!clock_recovery) {
845 DRM_ERROR("clock recovery failed\n");
846 return -1;
847 } else {
848 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
849 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
850 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
851 DP_TRAIN_PRE_EMPHASIS_SHIFT);
852 return 0;
853 }
854 }
855
856 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
857 {
858 bool channel_eq;
859
860 if (dp_info->tp3_supported)
861 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
862 else
863 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
864
865 /* channel equalization loop */
866 dp_info->tries = 0;
867 channel_eq = false;
868 while (1) {
869 if (dp_info->rd_interval == 0)
870 udelay(400);
871 else
872 mdelay(dp_info->rd_interval * 4);
873
874 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) {
875 DRM_ERROR("displayport link status failed\n");
876 break;
877 }
878
879 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
880 channel_eq = true;
881 break;
882 }
883
884 /* Try 5 times */
885 if (dp_info->tries > 5) {
886 DRM_ERROR("channel eq failed: 5 tries\n");
887 break;
888 }
889
890 /* Compute new train_set as requested by sink */
891 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
892
893 radeon_dp_update_vs_emph(dp_info);
894 dp_info->tries++;
895 }
896
897 if (!channel_eq) {
898 DRM_ERROR("channel eq failed\n");
899 return -1;
900 } else {
901 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
902 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
903 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
904 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
905 return 0;
906 }
907 }
908
909 void radeon_dp_link_train(struct drm_encoder *encoder,
910 struct drm_connector *connector)
911 {
912 struct drm_device *dev = encoder->dev;
913 struct radeon_device *rdev = dev->dev_private;
914 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
915 struct radeon_encoder_atom_dig *dig;
916 struct radeon_connector *radeon_connector;
917 struct radeon_connector_atom_dig *dig_connector;
918 struct radeon_dp_link_train_info dp_info;
919 int index;
920 u8 tmp, frev, crev;
921
922 if (!radeon_encoder->enc_priv)
923 return;
924 dig = radeon_encoder->enc_priv;
925
926 radeon_connector = to_radeon_connector(connector);
927 if (!radeon_connector->con_priv)
928 return;
929 dig_connector = radeon_connector->con_priv;
930
931 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
932 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
933 return;
934
935 /* DPEncoderService newer than 1.1 can't program properly the
936 * training pattern. When facing such version use the
937 * DIGXEncoderControl (X== 1 | 2)
938 */
939 dp_info.use_dpencoder = true;
940 index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
941 if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
942 if (crev > 1) {
943 dp_info.use_dpencoder = false;
944 }
945 }
946
947 dp_info.enc_id = 0;
948 if (dig->dig_encoder)
949 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
950 else
951 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
952 if (dig->linkb)
953 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
954 else
955 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
956
957 dp_info.rd_interval = radeon_read_dpcd_reg(radeon_connector, DP_TRAINING_AUX_RD_INTERVAL);
958 tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT);
959 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
960 dp_info.tp3_supported = true;
961 else
962 dp_info.tp3_supported = false;
963
964 memcpy(dp_info.dpcd, dig_connector->dpcd, 8);
965 dp_info.rdev = rdev;
966 dp_info.encoder = encoder;
967 dp_info.connector = connector;
968 dp_info.radeon_connector = radeon_connector;
969 dp_info.dp_lane_count = dig_connector->dp_lane_count;
970 dp_info.dp_clock = dig_connector->dp_clock;
971
972 if (radeon_dp_link_train_init(&dp_info))
973 goto done;
974 if (radeon_dp_link_train_cr(&dp_info))
975 goto done;
976 if (radeon_dp_link_train_ce(&dp_info))
977 goto done;
978 done:
979 if (radeon_dp_link_train_finish(&dp_info))
980 return;
981 }
Linux kernel - Deliverables
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