2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
28 #include <drm/radeon_drm.h>
32 #include "atom-bits.h"
33 #include <drm/drm_dp_helper.h>
35 /* move these to drm_dp_helper.c/h */
36 #define DP_LINK_CONFIGURATION_SIZE 9
37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
39 static char *voltage_names
[] = {
40 "0.4V", "0.6V", "0.8V", "1.2V"
42 static char *pre_emph_names
[] = {
43 "0dB", "3.5dB", "6dB", "9.5dB"
46 /***** radeon AUX functions *****/
48 /* Atom needs data in little endian format
49 * so swap as appropriate when copying data to
50 * or from atom. Note that atom operates on
53 void radeon_atom_copy_swap(u8
*dst
, u8
*src
, u8 num_bytes
, bool to_le
)
56 u8 src_tmp
[20], dst_tmp
[20]; /* used for byteswapping */
60 memcpy(src_tmp
, src
, num_bytes
);
61 src32
= (u32
*)src_tmp
;
62 dst32
= (u32
*)dst_tmp
;
64 for (i
= 0; i
< ((num_bytes
+ 3) / 4); i
++)
65 dst32
[i
] = cpu_to_le32(src32
[i
]);
66 memcpy(dst
, dst_tmp
, num_bytes
);
68 u8 dws
= num_bytes
& ~3;
69 for (i
= 0; i
< ((num_bytes
+ 3) / 4); i
++)
70 dst32
[i
] = le32_to_cpu(src32
[i
]);
71 memcpy(dst
, dst_tmp
, dws
);
73 for (i
= 0; i
< (num_bytes
% 4); i
++)
74 dst
[dws
+i
] = dst_tmp
[dws
+i
];
78 memcpy(dst
, src
, num_bytes
);
82 union aux_channel_transaction
{
83 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1
;
84 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2
;
87 static int radeon_process_aux_ch(struct radeon_i2c_chan
*chan
,
88 u8
*send
, int send_bytes
,
89 u8
*recv
, int recv_size
,
92 struct drm_device
*dev
= chan
->dev
;
93 struct radeon_device
*rdev
= dev
->dev_private
;
94 union aux_channel_transaction args
;
95 int index
= GetIndexIntoMasterTable(COMMAND
, ProcessAuxChannelTransaction
);
100 memset(&args
, 0, sizeof(args
));
102 mutex_lock(&chan
->mutex
);
103 mutex_lock(&rdev
->mode_info
.atom_context
->scratch_mutex
);
105 base
= (unsigned char *)(rdev
->mode_info
.atom_context
->scratch
+ 1);
107 radeon_atom_copy_swap(base
, send
, send_bytes
, true);
109 args
.v1
.lpAuxRequest
= cpu_to_le16((u16
)(0 + 4));
110 args
.v1
.lpDataOut
= cpu_to_le16((u16
)(16 + 4));
111 args
.v1
.ucDataOutLen
= 0;
112 args
.v1
.ucChannelID
= chan
->rec
.i2c_id
;
113 args
.v1
.ucDelay
= delay
/ 10;
114 if (ASIC_IS_DCE4(rdev
))
115 args
.v2
.ucHPD_ID
= chan
->rec
.hpd
;
117 atom_execute_table_scratch_unlocked(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
119 *ack
= args
.v1
.ucReplyStatus
;
122 if (args
.v1
.ucReplyStatus
== 1) {
123 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
129 if (args
.v1
.ucReplyStatus
== 2) {
130 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
136 if (args
.v1
.ucReplyStatus
== 3) {
137 DRM_DEBUG_KMS("dp_aux_ch error\n");
142 recv_bytes
= args
.v1
.ucDataOutLen
;
143 if (recv_bytes
> recv_size
)
144 recv_bytes
= recv_size
;
146 if (recv
&& recv_size
)
147 radeon_atom_copy_swap(recv
, base
+ 16, recv_bytes
, false);
151 mutex_unlock(&rdev
->mode_info
.atom_context
->scratch_mutex
);
152 mutex_unlock(&chan
->mutex
);
157 #define BARE_ADDRESS_SIZE 3
158 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
161 radeon_dp_aux_transfer_atom(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
163 struct radeon_i2c_chan
*chan
=
164 container_of(aux
, struct radeon_i2c_chan
, aux
);
170 if (WARN_ON(msg
->size
> 16))
173 tx_buf
[0] = msg
->address
& 0xff;
174 tx_buf
[1] = (msg
->address
>> 8) & 0xff;
175 tx_buf
[2] = (msg
->request
<< 4) |
176 ((msg
->address
>> 16) & 0xf);
177 tx_buf
[3] = msg
->size
? (msg
->size
- 1) : 0;
179 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
180 case DP_AUX_NATIVE_WRITE
:
181 case DP_AUX_I2C_WRITE
:
182 case DP_AUX_I2C_WRITE_STATUS_UPDATE
:
183 /* The atom implementation only supports writes with a max payload of
184 * 12 bytes since it uses 4 bits for the total count (header + payload)
185 * in the parameter space. The atom interface supports 16 byte
186 * payloads for reads. The hw itself supports up to 16 bytes of payload.
188 if (WARN_ON_ONCE(msg
->size
> 12))
190 /* tx_size needs to be 4 even for bare address packets since the atom
191 * table needs the info in tx_buf[3].
193 tx_size
= HEADER_SIZE
+ msg
->size
;
195 tx_buf
[3] |= BARE_ADDRESS_SIZE
<< 4;
197 tx_buf
[3] |= tx_size
<< 4;
198 memcpy(tx_buf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
199 ret
= radeon_process_aux_ch(chan
,
200 tx_buf
, tx_size
, NULL
, 0, delay
, &ack
);
202 /* Return payload size. */
205 case DP_AUX_NATIVE_READ
:
206 case DP_AUX_I2C_READ
:
207 /* tx_size needs to be 4 even for bare address packets since the atom
208 * table needs the info in tx_buf[3].
210 tx_size
= HEADER_SIZE
;
212 tx_buf
[3] |= BARE_ADDRESS_SIZE
<< 4;
214 tx_buf
[3] |= tx_size
<< 4;
215 ret
= radeon_process_aux_ch(chan
,
216 tx_buf
, tx_size
, msg
->buffer
, msg
->size
, delay
, &ack
);
224 msg
->reply
= ack
>> 4;
229 void radeon_dp_aux_init(struct radeon_connector
*radeon_connector
)
231 struct drm_device
*dev
= radeon_connector
->base
.dev
;
232 struct radeon_device
*rdev
= dev
->dev_private
;
235 radeon_connector
->ddc_bus
->rec
.hpd
= radeon_connector
->hpd
.hpd
;
236 radeon_connector
->ddc_bus
->aux
.dev
= radeon_connector
->base
.kdev
;
237 if (ASIC_IS_DCE5(rdev
)) {
239 radeon_connector
->ddc_bus
->aux
.transfer
= radeon_dp_aux_transfer_native
;
241 radeon_connector
->ddc_bus
->aux
.transfer
= radeon_dp_aux_transfer_atom
;
243 radeon_connector
->ddc_bus
->aux
.transfer
= radeon_dp_aux_transfer_atom
;
246 ret
= drm_dp_aux_register(&radeon_connector
->ddc_bus
->aux
);
248 radeon_connector
->ddc_bus
->has_aux
= true;
250 WARN(ret
, "drm_dp_aux_register() failed with error %d\n", ret
);
253 /***** general DP utility functions *****/
255 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3
256 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3
258 static void dp_get_adjust_train(const u8 link_status
[DP_LINK_STATUS_SIZE
],
266 for (lane
= 0; lane
< lane_count
; lane
++) {
267 u8 this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
268 u8 this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
270 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
272 voltage_names
[this_v
>> DP_TRAIN_VOLTAGE_SWING_SHIFT
],
273 pre_emph_names
[this_p
>> DP_TRAIN_PRE_EMPHASIS_SHIFT
]);
281 if (v
>= DP_VOLTAGE_MAX
)
282 v
|= DP_TRAIN_MAX_SWING_REACHED
;
284 if (p
>= DP_PRE_EMPHASIS_MAX
)
285 p
|= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
287 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
288 voltage_names
[(v
& DP_TRAIN_VOLTAGE_SWING_MASK
) >> DP_TRAIN_VOLTAGE_SWING_SHIFT
],
289 pre_emph_names
[(p
& DP_TRAIN_PRE_EMPHASIS_MASK
) >> DP_TRAIN_PRE_EMPHASIS_SHIFT
]);
291 for (lane
= 0; lane
< 4; lane
++)
292 train_set
[lane
] = v
| p
;
295 /* convert bits per color to bits per pixel */
296 /* get bpc from the EDID */
297 static int convert_bpc_to_bpp(int bpc
)
305 /***** radeon specific DP functions *****/
307 int radeon_dp_get_dp_link_config(struct drm_connector
*connector
,
308 const u8 dpcd
[DP_DPCD_SIZE
],
310 unsigned *dp_lanes
, unsigned *dp_rate
)
312 int bpp
= convert_bpc_to_bpp(radeon_get_monitor_bpc(connector
));
313 static const unsigned link_rates
[3] = { 162000, 270000, 540000 };
314 unsigned max_link_rate
= drm_dp_max_link_rate(dpcd
);
315 unsigned max_lane_num
= drm_dp_max_lane_count(dpcd
);
316 unsigned lane_num
, i
, max_pix_clock
;
318 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector
) ==
319 ENCODER_OBJECT_ID_NUTMEG
) {
320 for (lane_num
= 1; lane_num
<= max_lane_num
; lane_num
<<= 1) {
321 max_pix_clock
= (lane_num
* 270000 * 8) / bpp
;
322 if (max_pix_clock
>= pix_clock
) {
323 *dp_lanes
= lane_num
;
329 for (i
= 0; i
< ARRAY_SIZE(link_rates
) && link_rates
[i
] <= max_link_rate
; i
++) {
330 for (lane_num
= 1; lane_num
<= max_lane_num
; lane_num
<<= 1) {
331 max_pix_clock
= (lane_num
* link_rates
[i
] * 8) / bpp
;
332 if (max_pix_clock
>= pix_clock
) {
333 *dp_lanes
= lane_num
;
334 *dp_rate
= link_rates
[i
];
344 static u8
radeon_dp_encoder_service(struct radeon_device
*rdev
,
345 int action
, int dp_clock
,
346 u8 ucconfig
, u8 lane_num
)
348 DP_ENCODER_SERVICE_PARAMETERS args
;
349 int index
= GetIndexIntoMasterTable(COMMAND
, DPEncoderService
);
351 memset(&args
, 0, sizeof(args
));
352 args
.ucLinkClock
= dp_clock
/ 10;
353 args
.ucConfig
= ucconfig
;
354 args
.ucAction
= action
;
355 args
.ucLaneNum
= lane_num
;
358 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
359 return args
.ucStatus
;
362 u8
radeon_dp_getsinktype(struct radeon_connector
*radeon_connector
)
364 struct drm_device
*dev
= radeon_connector
->base
.dev
;
365 struct radeon_device
*rdev
= dev
->dev_private
;
367 return radeon_dp_encoder_service(rdev
, ATOM_DP_ACTION_GET_SINK_TYPE
, 0,
368 radeon_connector
->ddc_bus
->rec
.i2c_id
, 0);
371 static void radeon_dp_probe_oui(struct radeon_connector
*radeon_connector
)
373 struct radeon_connector_atom_dig
*dig_connector
= radeon_connector
->con_priv
;
376 if (!(dig_connector
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
379 if (drm_dp_dpcd_read(&radeon_connector
->ddc_bus
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
380 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
381 buf
[0], buf
[1], buf
[2]);
383 if (drm_dp_dpcd_read(&radeon_connector
->ddc_bus
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
384 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
385 buf
[0], buf
[1], buf
[2]);
388 bool radeon_dp_getdpcd(struct radeon_connector
*radeon_connector
)
390 struct radeon_connector_atom_dig
*dig_connector
= radeon_connector
->con_priv
;
391 u8 msg
[DP_DPCD_SIZE
];
394 ret
= drm_dp_dpcd_read(&radeon_connector
->ddc_bus
->aux
, DP_DPCD_REV
, msg
,
396 if (ret
== DP_DPCD_SIZE
) {
397 memcpy(dig_connector
->dpcd
, msg
, DP_DPCD_SIZE
);
399 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector
->dpcd
),
400 dig_connector
->dpcd
);
402 radeon_dp_probe_oui(radeon_connector
);
407 dig_connector
->dpcd
[0] = 0;
411 int radeon_dp_get_panel_mode(struct drm_encoder
*encoder
,
412 struct drm_connector
*connector
)
414 struct drm_device
*dev
= encoder
->dev
;
415 struct radeon_device
*rdev
= dev
->dev_private
;
416 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
417 struct radeon_connector_atom_dig
*dig_connector
;
418 int panel_mode
= DP_PANEL_MODE_EXTERNAL_DP_MODE
;
419 u16 dp_bridge
= radeon_connector_encoder_get_dp_bridge_encoder_id(connector
);
422 if (!ASIC_IS_DCE4(rdev
))
425 if (!radeon_connector
->con_priv
)
428 dig_connector
= radeon_connector
->con_priv
;
430 if (dp_bridge
!= ENCODER_OBJECT_ID_NONE
) {
431 /* DP bridge chips */
432 if (drm_dp_dpcd_readb(&radeon_connector
->ddc_bus
->aux
,
433 DP_EDP_CONFIGURATION_CAP
, &tmp
) == 1) {
435 panel_mode
= DP_PANEL_MODE_INTERNAL_DP2_MODE
;
436 else if ((dp_bridge
== ENCODER_OBJECT_ID_NUTMEG
) ||
437 (dp_bridge
== ENCODER_OBJECT_ID_TRAVIS
))
438 panel_mode
= DP_PANEL_MODE_INTERNAL_DP1_MODE
;
440 panel_mode
= DP_PANEL_MODE_EXTERNAL_DP_MODE
;
442 } else if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
) {
444 if (drm_dp_dpcd_readb(&radeon_connector
->ddc_bus
->aux
,
445 DP_EDP_CONFIGURATION_CAP
, &tmp
) == 1) {
447 panel_mode
= DP_PANEL_MODE_INTERNAL_DP2_MODE
;
454 void radeon_dp_set_link_config(struct drm_connector
*connector
,
455 const struct drm_display_mode
*mode
)
457 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
458 struct radeon_connector_atom_dig
*dig_connector
;
461 if (!radeon_connector
->con_priv
)
463 dig_connector
= radeon_connector
->con_priv
;
465 if ((dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_DISPLAYPORT
) ||
466 (dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_eDP
)) {
467 ret
= radeon_dp_get_dp_link_config(connector
, dig_connector
->dpcd
,
469 &dig_connector
->dp_lane_count
,
470 &dig_connector
->dp_clock
);
472 dig_connector
->dp_clock
= 0;
473 dig_connector
->dp_lane_count
= 0;
478 int radeon_dp_mode_valid_helper(struct drm_connector
*connector
,
479 struct drm_display_mode
*mode
)
481 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
482 struct radeon_connector_atom_dig
*dig_connector
;
483 unsigned dp_clock
, dp_lanes
;
486 if ((mode
->clock
> 340000) &&
487 (!radeon_connector_is_dp12_capable(connector
)))
488 return MODE_CLOCK_HIGH
;
490 if (!radeon_connector
->con_priv
)
491 return MODE_CLOCK_HIGH
;
492 dig_connector
= radeon_connector
->con_priv
;
494 ret
= radeon_dp_get_dp_link_config(connector
, dig_connector
->dpcd
,
499 return MODE_CLOCK_HIGH
;
501 if ((dp_clock
== 540000) &&
502 (!radeon_connector_is_dp12_capable(connector
)))
503 return MODE_CLOCK_HIGH
;
508 bool radeon_dp_needs_link_train(struct radeon_connector
*radeon_connector
)
510 u8 link_status
[DP_LINK_STATUS_SIZE
];
511 struct radeon_connector_atom_dig
*dig
= radeon_connector
->con_priv
;
513 if (drm_dp_dpcd_read_link_status(&radeon_connector
->ddc_bus
->aux
, link_status
)
516 if (drm_dp_channel_eq_ok(link_status
, dig
->dp_lane_count
))
521 void radeon_dp_set_rx_power_state(struct drm_connector
*connector
,
524 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
525 struct radeon_connector_atom_dig
*dig_connector
;
527 if (!radeon_connector
->con_priv
)
530 dig_connector
= radeon_connector
->con_priv
;
532 /* power up/down the sink */
533 if (dig_connector
->dpcd
[0] >= 0x11) {
534 drm_dp_dpcd_writeb(&radeon_connector
->ddc_bus
->aux
,
535 DP_SET_POWER
, power_state
);
536 usleep_range(1000, 2000);
541 struct radeon_dp_link_train_info
{
542 struct radeon_device
*rdev
;
543 struct drm_encoder
*encoder
;
544 struct drm_connector
*connector
;
549 u8 dpcd
[DP_RECEIVER_CAP_SIZE
];
551 u8 link_status
[DP_LINK_STATUS_SIZE
];
554 struct drm_dp_aux
*aux
;
557 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info
*dp_info
)
559 /* set the initial vs/emph on the source */
560 atombios_dig_transmitter_setup(dp_info
->encoder
,
561 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
,
562 0, dp_info
->train_set
[0]); /* sets all lanes at once */
564 /* set the vs/emph on the sink */
565 drm_dp_dpcd_write(dp_info
->aux
, DP_TRAINING_LANE0_SET
,
566 dp_info
->train_set
, dp_info
->dp_lane_count
);
569 static void radeon_dp_set_tp(struct radeon_dp_link_train_info
*dp_info
, int tp
)
573 /* set training pattern on the source */
574 if (ASIC_IS_DCE4(dp_info
->rdev
) || !dp_info
->use_dpencoder
) {
576 case DP_TRAINING_PATTERN_1
:
577 rtp
= ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1
;
579 case DP_TRAINING_PATTERN_2
:
580 rtp
= ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2
;
582 case DP_TRAINING_PATTERN_3
:
583 rtp
= ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3
;
586 atombios_dig_encoder_setup(dp_info
->encoder
, rtp
, 0);
589 case DP_TRAINING_PATTERN_1
:
592 case DP_TRAINING_PATTERN_2
:
596 radeon_dp_encoder_service(dp_info
->rdev
, ATOM_DP_ACTION_TRAINING_PATTERN_SEL
,
597 dp_info
->dp_clock
, dp_info
->enc_id
, rtp
);
600 /* enable training pattern on the sink */
601 drm_dp_dpcd_writeb(dp_info
->aux
, DP_TRAINING_PATTERN_SET
, tp
);
604 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info
*dp_info
)
606 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(dp_info
->encoder
);
607 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
610 /* power up the sink */
611 radeon_dp_set_rx_power_state(dp_info
->connector
, DP_SET_POWER_D0
);
613 /* possibly enable downspread on the sink */
614 if (dp_info
->dpcd
[3] & 0x1)
615 drm_dp_dpcd_writeb(dp_info
->aux
,
616 DP_DOWNSPREAD_CTRL
, DP_SPREAD_AMP_0_5
);
618 drm_dp_dpcd_writeb(dp_info
->aux
,
619 DP_DOWNSPREAD_CTRL
, 0);
621 if (dig
->panel_mode
== DP_PANEL_MODE_INTERNAL_DP2_MODE
)
622 drm_dp_dpcd_writeb(dp_info
->aux
, DP_EDP_CONFIGURATION_SET
, 1);
624 /* set the lane count on the sink */
625 tmp
= dp_info
->dp_lane_count
;
626 if (drm_dp_enhanced_frame_cap(dp_info
->dpcd
))
627 tmp
|= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
628 drm_dp_dpcd_writeb(dp_info
->aux
, DP_LANE_COUNT_SET
, tmp
);
630 /* set the link rate on the sink */
631 tmp
= drm_dp_link_rate_to_bw_code(dp_info
->dp_clock
);
632 drm_dp_dpcd_writeb(dp_info
->aux
, DP_LINK_BW_SET
, tmp
);
634 /* start training on the source */
635 if (ASIC_IS_DCE4(dp_info
->rdev
) || !dp_info
->use_dpencoder
)
636 atombios_dig_encoder_setup(dp_info
->encoder
,
637 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START
, 0);
639 radeon_dp_encoder_service(dp_info
->rdev
, ATOM_DP_ACTION_TRAINING_START
,
640 dp_info
->dp_clock
, dp_info
->enc_id
, 0);
642 /* disable the training pattern on the sink */
643 drm_dp_dpcd_writeb(dp_info
->aux
,
644 DP_TRAINING_PATTERN_SET
,
645 DP_TRAINING_PATTERN_DISABLE
);
650 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info
*dp_info
)
654 /* disable the training pattern on the sink */
655 drm_dp_dpcd_writeb(dp_info
->aux
,
656 DP_TRAINING_PATTERN_SET
,
657 DP_TRAINING_PATTERN_DISABLE
);
659 /* disable the training pattern on the source */
660 if (ASIC_IS_DCE4(dp_info
->rdev
) || !dp_info
->use_dpencoder
)
661 atombios_dig_encoder_setup(dp_info
->encoder
,
662 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE
, 0);
664 radeon_dp_encoder_service(dp_info
->rdev
, ATOM_DP_ACTION_TRAINING_COMPLETE
,
665 dp_info
->dp_clock
, dp_info
->enc_id
, 0);
670 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info
*dp_info
)
676 radeon_dp_set_tp(dp_info
, DP_TRAINING_PATTERN_1
);
677 memset(dp_info
->train_set
, 0, 4);
678 radeon_dp_update_vs_emph(dp_info
);
682 /* clock recovery loop */
683 clock_recovery
= false;
687 drm_dp_link_train_clock_recovery_delay(dp_info
->dpcd
);
689 if (drm_dp_dpcd_read_link_status(dp_info
->aux
,
690 dp_info
->link_status
) <= 0) {
691 DRM_ERROR("displayport link status failed\n");
695 if (drm_dp_clock_recovery_ok(dp_info
->link_status
, dp_info
->dp_lane_count
)) {
696 clock_recovery
= true;
700 for (i
= 0; i
< dp_info
->dp_lane_count
; i
++) {
701 if ((dp_info
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
704 if (i
== dp_info
->dp_lane_count
) {
705 DRM_ERROR("clock recovery reached max voltage\n");
709 if ((dp_info
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
711 if (dp_info
->tries
== 5) {
712 DRM_ERROR("clock recovery tried 5 times\n");
718 voltage
= dp_info
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
720 /* Compute new train_set as requested by sink */
721 dp_get_adjust_train(dp_info
->link_status
, dp_info
->dp_lane_count
, dp_info
->train_set
);
723 radeon_dp_update_vs_emph(dp_info
);
725 if (!clock_recovery
) {
726 DRM_ERROR("clock recovery failed\n");
729 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
730 dp_info
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
,
731 (dp_info
->train_set
[0] & DP_TRAIN_PRE_EMPHASIS_MASK
) >>
732 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
737 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info
*dp_info
)
741 if (dp_info
->tp3_supported
)
742 radeon_dp_set_tp(dp_info
, DP_TRAINING_PATTERN_3
);
744 radeon_dp_set_tp(dp_info
, DP_TRAINING_PATTERN_2
);
746 /* channel equalization loop */
750 drm_dp_link_train_channel_eq_delay(dp_info
->dpcd
);
752 if (drm_dp_dpcd_read_link_status(dp_info
->aux
,
753 dp_info
->link_status
) <= 0) {
754 DRM_ERROR("displayport link status failed\n");
758 if (drm_dp_channel_eq_ok(dp_info
->link_status
, dp_info
->dp_lane_count
)) {
764 if (dp_info
->tries
> 5) {
765 DRM_ERROR("channel eq failed: 5 tries\n");
769 /* Compute new train_set as requested by sink */
770 dp_get_adjust_train(dp_info
->link_status
, dp_info
->dp_lane_count
, dp_info
->train_set
);
772 radeon_dp_update_vs_emph(dp_info
);
777 DRM_ERROR("channel eq failed\n");
780 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
781 dp_info
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
,
782 (dp_info
->train_set
[0] & DP_TRAIN_PRE_EMPHASIS_MASK
)
783 >> DP_TRAIN_PRE_EMPHASIS_SHIFT
);
788 void radeon_dp_link_train(struct drm_encoder
*encoder
,
789 struct drm_connector
*connector
)
791 struct drm_device
*dev
= encoder
->dev
;
792 struct radeon_device
*rdev
= dev
->dev_private
;
793 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
794 struct radeon_encoder_atom_dig
*dig
;
795 struct radeon_connector
*radeon_connector
;
796 struct radeon_connector_atom_dig
*dig_connector
;
797 struct radeon_dp_link_train_info dp_info
;
801 if (!radeon_encoder
->enc_priv
)
803 dig
= radeon_encoder
->enc_priv
;
805 radeon_connector
= to_radeon_connector(connector
);
806 if (!radeon_connector
->con_priv
)
808 dig_connector
= radeon_connector
->con_priv
;
810 if ((dig_connector
->dp_sink_type
!= CONNECTOR_OBJECT_ID_DISPLAYPORT
) &&
811 (dig_connector
->dp_sink_type
!= CONNECTOR_OBJECT_ID_eDP
))
814 /* DPEncoderService newer than 1.1 can't program properly the
815 * training pattern. When facing such version use the
816 * DIGXEncoderControl (X== 1 | 2)
818 dp_info
.use_dpencoder
= true;
819 index
= GetIndexIntoMasterTable(COMMAND
, DPEncoderService
);
820 if (atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
)) {
822 dp_info
.use_dpencoder
= false;
827 if (dig
->dig_encoder
)
828 dp_info
.enc_id
|= ATOM_DP_CONFIG_DIG2_ENCODER
;
830 dp_info
.enc_id
|= ATOM_DP_CONFIG_DIG1_ENCODER
;
832 dp_info
.enc_id
|= ATOM_DP_CONFIG_LINK_B
;
834 dp_info
.enc_id
|= ATOM_DP_CONFIG_LINK_A
;
836 if (drm_dp_dpcd_readb(&radeon_connector
->ddc_bus
->aux
, DP_MAX_LANE_COUNT
, &tmp
)
838 if (ASIC_IS_DCE5(rdev
) && (tmp
& DP_TPS3_SUPPORTED
))
839 dp_info
.tp3_supported
= true;
841 dp_info
.tp3_supported
= false;
843 dp_info
.tp3_supported
= false;
846 memcpy(dp_info
.dpcd
, dig_connector
->dpcd
, DP_RECEIVER_CAP_SIZE
);
848 dp_info
.encoder
= encoder
;
849 dp_info
.connector
= connector
;
850 dp_info
.dp_lane_count
= dig_connector
->dp_lane_count
;
851 dp_info
.dp_clock
= dig_connector
->dp_clock
;
852 dp_info
.aux
= &radeon_connector
->ddc_bus
->aux
;
854 if (radeon_dp_link_train_init(&dp_info
))
856 if (radeon_dp_link_train_cr(&dp_info
))
858 if (radeon_dp_link_train_ce(&dp_info
))
861 if (radeon_dp_link_train_finish(&dp_info
))