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[deliverable/linux.git] / drivers / gpu / drm / radeon / atombios_dp.c
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 * Jerome Glisse
26 */
27 #include <drm/drmP.h>
28 #include <drm/radeon_drm.h>
29 #include "radeon.h"
30
31 #include "atom.h"
32 #include "atom-bits.h"
33 #include <drm/drm_dp_helper.h>
34
35 /* move these to drm_dp_helper.c/h */
36 #define DP_LINK_CONFIGURATION_SIZE 9
37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
38
39 static char *voltage_names[] = {
40 "0.4V", "0.6V", "0.8V", "1.2V"
41 };
42 static char *pre_emph_names[] = {
43 "0dB", "3.5dB", "6dB", "9.5dB"
44 };
45
46 /***** radeon AUX functions *****/
47
48 /* Atom needs data in little endian format
49 * so swap as appropriate when copying data to
50 * or from atom. Note that atom operates on
51 * dw units.
52 */
53 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
54 {
55 #ifdef __BIG_ENDIAN
56 u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
57 u32 *dst32, *src32;
58 int i;
59
60 memcpy(src_tmp, src, num_bytes);
61 src32 = (u32 *)src_tmp;
62 dst32 = (u32 *)dst_tmp;
63 if (to_le) {
64 for (i = 0; i < ((num_bytes + 3) / 4); i++)
65 dst32[i] = cpu_to_le32(src32[i]);
66 memcpy(dst, dst_tmp, num_bytes);
67 } else {
68 u8 dws = num_bytes & ~3;
69 for (i = 0; i < ((num_bytes + 3) / 4); i++)
70 dst32[i] = le32_to_cpu(src32[i]);
71 memcpy(dst, dst_tmp, dws);
72 if (num_bytes % 4) {
73 for (i = 0; i < (num_bytes % 4); i++)
74 dst[dws+i] = dst_tmp[dws+i];
75 }
76 }
77 #else
78 memcpy(dst, src, num_bytes);
79 #endif
80 }
81
82 union aux_channel_transaction {
83 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
84 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
85 };
86
87 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
88 u8 *send, int send_bytes,
89 u8 *recv, int recv_size,
90 u8 delay, u8 *ack)
91 {
92 struct drm_device *dev = chan->dev;
93 struct radeon_device *rdev = dev->dev_private;
94 union aux_channel_transaction args;
95 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
96 unsigned char *base;
97 int recv_bytes;
98
99 memset(&args, 0, sizeof(args));
100
101 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
102
103 radeon_atom_copy_swap(base, send, send_bytes, true);
104
105 args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
106 args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4));
107 args.v1.ucDataOutLen = 0;
108 args.v1.ucChannelID = chan->rec.i2c_id;
109 args.v1.ucDelay = delay / 10;
110 if (ASIC_IS_DCE4(rdev))
111 args.v2.ucHPD_ID = chan->rec.hpd;
112
113 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
114
115 *ack = args.v1.ucReplyStatus;
116
117 /* timeout */
118 if (args.v1.ucReplyStatus == 1) {
119 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
120 return -ETIMEDOUT;
121 }
122
123 /* flags not zero */
124 if (args.v1.ucReplyStatus == 2) {
125 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
126 return -EBUSY;
127 }
128
129 /* error */
130 if (args.v1.ucReplyStatus == 3) {
131 DRM_DEBUG_KMS("dp_aux_ch error\n");
132 return -EIO;
133 }
134
135 recv_bytes = args.v1.ucDataOutLen;
136 if (recv_bytes > recv_size)
137 recv_bytes = recv_size;
138
139 if (recv && recv_size)
140 radeon_atom_copy_swap(recv, base + 16, recv_bytes, false);
141
142 return recv_bytes;
143 }
144
145 static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
146 u16 address, u8 *send, u8 send_bytes, u8 delay)
147 {
148 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
149 int ret;
150 u8 msg[20];
151 int msg_bytes = send_bytes + 4;
152 u8 ack;
153 unsigned retry;
154
155 if (send_bytes > 16)
156 return -1;
157
158 msg[0] = address;
159 msg[1] = address >> 8;
160 msg[2] = DP_AUX_NATIVE_WRITE << 4;
161 msg[3] = (msg_bytes << 4) | (send_bytes - 1);
162 memcpy(&msg[4], send, send_bytes);
163
164 for (retry = 0; retry < 7; retry++) {
165 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
166 msg, msg_bytes, NULL, 0, delay, &ack);
167 if (ret == -EBUSY)
168 continue;
169 else if (ret < 0)
170 return ret;
171 ack >>= 4;
172 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
173 return send_bytes;
174 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
175 usleep_range(400, 500);
176 else
177 return -EIO;
178 }
179
180 return -EIO;
181 }
182
183 static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
184 u16 address, u8 *recv, int recv_bytes, u8 delay)
185 {
186 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
187 u8 msg[4];
188 int msg_bytes = 4;
189 u8 ack;
190 int ret;
191 unsigned retry;
192
193 msg[0] = address;
194 msg[1] = address >> 8;
195 msg[2] = DP_AUX_NATIVE_READ << 4;
196 msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
197
198 for (retry = 0; retry < 7; retry++) {
199 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
200 msg, msg_bytes, recv, recv_bytes, delay, &ack);
201 if (ret == -EBUSY)
202 continue;
203 else if (ret < 0)
204 return ret;
205 ack >>= 4;
206 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
207 return ret;
208 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
209 usleep_range(400, 500);
210 else if (ret == 0)
211 return -EPROTO;
212 else
213 return -EIO;
214 }
215
216 return -EIO;
217 }
218
219 static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,
220 u16 reg, u8 val)
221 {
222 radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0);
223 }
224
225 static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector,
226 u16 reg)
227 {
228 u8 val = 0;
229
230 radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0);
231
232 return val;
233 }
234
235 int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
236 u8 write_byte, u8 *read_byte)
237 {
238 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
239 struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter;
240 u16 address = algo_data->address;
241 u8 msg[5];
242 u8 reply[2];
243 unsigned retry;
244 int msg_bytes;
245 int reply_bytes = 1;
246 int ret;
247 u8 ack;
248
249 /* Set up the command byte */
250 if (mode & MODE_I2C_READ)
251 msg[2] = DP_AUX_I2C_READ << 4;
252 else
253 msg[2] = DP_AUX_I2C_WRITE << 4;
254
255 if (!(mode & MODE_I2C_STOP))
256 msg[2] |= DP_AUX_I2C_MOT << 4;
257
258 msg[0] = address;
259 msg[1] = address >> 8;
260
261 switch (mode) {
262 case MODE_I2C_WRITE:
263 msg_bytes = 5;
264 msg[3] = msg_bytes << 4;
265 msg[4] = write_byte;
266 break;
267 case MODE_I2C_READ:
268 msg_bytes = 4;
269 msg[3] = msg_bytes << 4;
270 break;
271 default:
272 msg_bytes = 4;
273 msg[3] = 3 << 4;
274 break;
275 }
276
277 for (retry = 0; retry < 7; retry++) {
278 ret = radeon_process_aux_ch(auxch,
279 msg, msg_bytes, reply, reply_bytes, 0, &ack);
280 if (ret == -EBUSY)
281 continue;
282 else if (ret < 0) {
283 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
284 return ret;
285 }
286
287 switch ((ack >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
288 case DP_AUX_NATIVE_REPLY_ACK:
289 /* I2C-over-AUX Reply field is only valid
290 * when paired with AUX ACK.
291 */
292 break;
293 case DP_AUX_NATIVE_REPLY_NACK:
294 DRM_DEBUG_KMS("aux_ch native nack\n");
295 return -EREMOTEIO;
296 case DP_AUX_NATIVE_REPLY_DEFER:
297 DRM_DEBUG_KMS("aux_ch native defer\n");
298 usleep_range(500, 600);
299 continue;
300 default:
301 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack);
302 return -EREMOTEIO;
303 }
304
305 switch ((ack >> 4) & DP_AUX_I2C_REPLY_MASK) {
306 case DP_AUX_I2C_REPLY_ACK:
307 if (mode == MODE_I2C_READ)
308 *read_byte = reply[0];
309 return ret;
310 case DP_AUX_I2C_REPLY_NACK:
311 DRM_DEBUG_KMS("aux_i2c nack\n");
312 return -EREMOTEIO;
313 case DP_AUX_I2C_REPLY_DEFER:
314 DRM_DEBUG_KMS("aux_i2c defer\n");
315 usleep_range(400, 500);
316 break;
317 default:
318 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack);
319 return -EREMOTEIO;
320 }
321 }
322
323 DRM_DEBUG_KMS("aux i2c too many retries, giving up\n");
324 return -EREMOTEIO;
325 }
326
327 /***** general DP utility functions *****/
328
329 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
330 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5
331
332 static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
333 int lane_count,
334 u8 train_set[4])
335 {
336 u8 v = 0;
337 u8 p = 0;
338 int lane;
339
340 for (lane = 0; lane < lane_count; lane++) {
341 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
342 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
343
344 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
345 lane,
346 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
347 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
348
349 if (this_v > v)
350 v = this_v;
351 if (this_p > p)
352 p = this_p;
353 }
354
355 if (v >= DP_VOLTAGE_MAX)
356 v |= DP_TRAIN_MAX_SWING_REACHED;
357
358 if (p >= DP_PRE_EMPHASIS_MAX)
359 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
360
361 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
362 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
363 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
364
365 for (lane = 0; lane < 4; lane++)
366 train_set[lane] = v | p;
367 }
368
369 /* convert bits per color to bits per pixel */
370 /* get bpc from the EDID */
371 static int convert_bpc_to_bpp(int bpc)
372 {
373 if (bpc == 0)
374 return 24;
375 else
376 return bpc * 3;
377 }
378
379 /* get the max pix clock supported by the link rate and lane num */
380 static int dp_get_max_dp_pix_clock(int link_rate,
381 int lane_num,
382 int bpp)
383 {
384 return (link_rate * lane_num * 8) / bpp;
385 }
386
387 /***** radeon specific DP functions *****/
388
389 /* First get the min lane# when low rate is used according to pixel clock
390 * (prefer low rate), second check max lane# supported by DP panel,
391 * if the max lane# < low rate lane# then use max lane# instead.
392 */
393 static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
394 u8 dpcd[DP_DPCD_SIZE],
395 int pix_clock)
396 {
397 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
398 int max_link_rate = drm_dp_max_link_rate(dpcd);
399 int max_lane_num = drm_dp_max_lane_count(dpcd);
400 int lane_num;
401 int max_dp_pix_clock;
402
403 for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
404 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
405 if (pix_clock <= max_dp_pix_clock)
406 break;
407 }
408
409 return lane_num;
410 }
411
412 static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
413 u8 dpcd[DP_DPCD_SIZE],
414 int pix_clock)
415 {
416 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
417 int lane_num, max_pix_clock;
418
419 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
420 ENCODER_OBJECT_ID_NUTMEG)
421 return 270000;
422
423 lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
424 max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
425 if (pix_clock <= max_pix_clock)
426 return 162000;
427 max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
428 if (pix_clock <= max_pix_clock)
429 return 270000;
430 if (radeon_connector_is_dp12_capable(connector)) {
431 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
432 if (pix_clock <= max_pix_clock)
433 return 540000;
434 }
435
436 return drm_dp_max_link_rate(dpcd);
437 }
438
439 static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
440 int action, int dp_clock,
441 u8 ucconfig, u8 lane_num)
442 {
443 DP_ENCODER_SERVICE_PARAMETERS args;
444 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
445
446 memset(&args, 0, sizeof(args));
447 args.ucLinkClock = dp_clock / 10;
448 args.ucConfig = ucconfig;
449 args.ucAction = action;
450 args.ucLaneNum = lane_num;
451 args.ucStatus = 0;
452
453 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
454 return args.ucStatus;
455 }
456
457 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
458 {
459 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
460 struct drm_device *dev = radeon_connector->base.dev;
461 struct radeon_device *rdev = dev->dev_private;
462
463 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
464 dig_connector->dp_i2c_bus->rec.i2c_id, 0);
465 }
466
467 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
468 {
469 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
470 u8 buf[3];
471
472 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
473 return;
474
475 if (radeon_dp_aux_native_read(radeon_connector, DP_SINK_OUI, buf, 3, 0))
476 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
477 buf[0], buf[1], buf[2]);
478
479 if (radeon_dp_aux_native_read(radeon_connector, DP_BRANCH_OUI, buf, 3, 0))
480 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
481 buf[0], buf[1], buf[2]);
482 }
483
484 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
485 {
486 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
487 u8 msg[DP_DPCD_SIZE];
488 int ret, i;
489
490 ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg,
491 DP_DPCD_SIZE, 0);
492 if (ret > 0) {
493 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
494 DRM_DEBUG_KMS("DPCD: ");
495 for (i = 0; i < DP_DPCD_SIZE; i++)
496 DRM_DEBUG_KMS("%02x ", msg[i]);
497 DRM_DEBUG_KMS("\n");
498
499 radeon_dp_probe_oui(radeon_connector);
500
501 return true;
502 }
503 dig_connector->dpcd[0] = 0;
504 return false;
505 }
506
507 int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
508 struct drm_connector *connector)
509 {
510 struct drm_device *dev = encoder->dev;
511 struct radeon_device *rdev = dev->dev_private;
512 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
513 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
514 u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
515 u8 tmp;
516
517 if (!ASIC_IS_DCE4(rdev))
518 return panel_mode;
519
520 if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
521 /* DP bridge chips */
522 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
523 if (tmp & 1)
524 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
525 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
526 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
527 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
528 else
529 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
530 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
531 /* eDP */
532 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
533 if (tmp & 1)
534 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
535 }
536
537 return panel_mode;
538 }
539
540 void radeon_dp_set_link_config(struct drm_connector *connector,
541 const struct drm_display_mode *mode)
542 {
543 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
544 struct radeon_connector_atom_dig *dig_connector;
545
546 if (!radeon_connector->con_priv)
547 return;
548 dig_connector = radeon_connector->con_priv;
549
550 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
551 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
552 dig_connector->dp_clock =
553 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
554 dig_connector->dp_lane_count =
555 radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
556 }
557 }
558
559 int radeon_dp_mode_valid_helper(struct drm_connector *connector,
560 struct drm_display_mode *mode)
561 {
562 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
563 struct radeon_connector_atom_dig *dig_connector;
564 int dp_clock;
565
566 if (!radeon_connector->con_priv)
567 return MODE_CLOCK_HIGH;
568 dig_connector = radeon_connector->con_priv;
569
570 dp_clock =
571 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
572
573 if ((dp_clock == 540000) &&
574 (!radeon_connector_is_dp12_capable(connector)))
575 return MODE_CLOCK_HIGH;
576
577 return MODE_OK;
578 }
579
580 static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector,
581 u8 link_status[DP_LINK_STATUS_SIZE])
582 {
583 int ret;
584 ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS,
585 link_status, DP_LINK_STATUS_SIZE, 100);
586 if (ret <= 0) {
587 return false;
588 }
589
590 DRM_DEBUG_KMS("link status %6ph\n", link_status);
591 return true;
592 }
593
594 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
595 {
596 u8 link_status[DP_LINK_STATUS_SIZE];
597 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
598
599 if (!radeon_dp_get_link_status(radeon_connector, link_status))
600 return false;
601 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
602 return false;
603 return true;
604 }
605
606 struct radeon_dp_link_train_info {
607 struct radeon_device *rdev;
608 struct drm_encoder *encoder;
609 struct drm_connector *connector;
610 struct radeon_connector *radeon_connector;
611 int enc_id;
612 int dp_clock;
613 int dp_lane_count;
614 bool tp3_supported;
615 u8 dpcd[DP_RECEIVER_CAP_SIZE];
616 u8 train_set[4];
617 u8 link_status[DP_LINK_STATUS_SIZE];
618 u8 tries;
619 bool use_dpencoder;
620 };
621
622 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
623 {
624 /* set the initial vs/emph on the source */
625 atombios_dig_transmitter_setup(dp_info->encoder,
626 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
627 0, dp_info->train_set[0]); /* sets all lanes at once */
628
629 /* set the vs/emph on the sink */
630 radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET,
631 dp_info->train_set, dp_info->dp_lane_count, 0);
632 }
633
634 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
635 {
636 int rtp = 0;
637
638 /* set training pattern on the source */
639 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
640 switch (tp) {
641 case DP_TRAINING_PATTERN_1:
642 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
643 break;
644 case DP_TRAINING_PATTERN_2:
645 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
646 break;
647 case DP_TRAINING_PATTERN_3:
648 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
649 break;
650 }
651 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
652 } else {
653 switch (tp) {
654 case DP_TRAINING_PATTERN_1:
655 rtp = 0;
656 break;
657 case DP_TRAINING_PATTERN_2:
658 rtp = 1;
659 break;
660 }
661 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
662 dp_info->dp_clock, dp_info->enc_id, rtp);
663 }
664
665 /* enable training pattern on the sink */
666 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp);
667 }
668
669 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
670 {
671 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
672 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
673 u8 tmp;
674
675 /* power up the sink */
676 if (dp_info->dpcd[0] >= 0x11) {
677 radeon_write_dpcd_reg(dp_info->radeon_connector,
678 DP_SET_POWER, DP_SET_POWER_D0);
679 usleep_range(1000, 2000);
680 }
681
682 /* possibly enable downspread on the sink */
683 if (dp_info->dpcd[3] & 0x1)
684 radeon_write_dpcd_reg(dp_info->radeon_connector,
685 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
686 else
687 radeon_write_dpcd_reg(dp_info->radeon_connector,
688 DP_DOWNSPREAD_CTRL, 0);
689
690 if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
691 (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
692 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1);
693 }
694
695 /* set the lane count on the sink */
696 tmp = dp_info->dp_lane_count;
697 if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
698 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
699 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp);
700
701 /* set the link rate on the sink */
702 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
703 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp);
704
705 /* start training on the source */
706 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
707 atombios_dig_encoder_setup(dp_info->encoder,
708 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
709 else
710 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
711 dp_info->dp_clock, dp_info->enc_id, 0);
712
713 /* disable the training pattern on the sink */
714 radeon_write_dpcd_reg(dp_info->radeon_connector,
715 DP_TRAINING_PATTERN_SET,
716 DP_TRAINING_PATTERN_DISABLE);
717
718 return 0;
719 }
720
721 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
722 {
723 udelay(400);
724
725 /* disable the training pattern on the sink */
726 radeon_write_dpcd_reg(dp_info->radeon_connector,
727 DP_TRAINING_PATTERN_SET,
728 DP_TRAINING_PATTERN_DISABLE);
729
730 /* disable the training pattern on the source */
731 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
732 atombios_dig_encoder_setup(dp_info->encoder,
733 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
734 else
735 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
736 dp_info->dp_clock, dp_info->enc_id, 0);
737
738 return 0;
739 }
740
741 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
742 {
743 bool clock_recovery;
744 u8 voltage;
745 int i;
746
747 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
748 memset(dp_info->train_set, 0, 4);
749 radeon_dp_update_vs_emph(dp_info);
750
751 udelay(400);
752
753 /* clock recovery loop */
754 clock_recovery = false;
755 dp_info->tries = 0;
756 voltage = 0xff;
757 while (1) {
758 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
759
760 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) {
761 DRM_ERROR("displayport link status failed\n");
762 break;
763 }
764
765 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
766 clock_recovery = true;
767 break;
768 }
769
770 for (i = 0; i < dp_info->dp_lane_count; i++) {
771 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
772 break;
773 }
774 if (i == dp_info->dp_lane_count) {
775 DRM_ERROR("clock recovery reached max voltage\n");
776 break;
777 }
778
779 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
780 ++dp_info->tries;
781 if (dp_info->tries == 5) {
782 DRM_ERROR("clock recovery tried 5 times\n");
783 break;
784 }
785 } else
786 dp_info->tries = 0;
787
788 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
789
790 /* Compute new train_set as requested by sink */
791 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
792
793 radeon_dp_update_vs_emph(dp_info);
794 }
795 if (!clock_recovery) {
796 DRM_ERROR("clock recovery failed\n");
797 return -1;
798 } else {
799 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
800 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
801 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
802 DP_TRAIN_PRE_EMPHASIS_SHIFT);
803 return 0;
804 }
805 }
806
807 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
808 {
809 bool channel_eq;
810
811 if (dp_info->tp3_supported)
812 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
813 else
814 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
815
816 /* channel equalization loop */
817 dp_info->tries = 0;
818 channel_eq = false;
819 while (1) {
820 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
821
822 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) {
823 DRM_ERROR("displayport link status failed\n");
824 break;
825 }
826
827 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
828 channel_eq = true;
829 break;
830 }
831
832 /* Try 5 times */
833 if (dp_info->tries > 5) {
834 DRM_ERROR("channel eq failed: 5 tries\n");
835 break;
836 }
837
838 /* Compute new train_set as requested by sink */
839 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
840
841 radeon_dp_update_vs_emph(dp_info);
842 dp_info->tries++;
843 }
844
845 if (!channel_eq) {
846 DRM_ERROR("channel eq failed\n");
847 return -1;
848 } else {
849 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
850 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
851 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
852 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
853 return 0;
854 }
855 }
856
857 void radeon_dp_link_train(struct drm_encoder *encoder,
858 struct drm_connector *connector)
859 {
860 struct drm_device *dev = encoder->dev;
861 struct radeon_device *rdev = dev->dev_private;
862 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
863 struct radeon_encoder_atom_dig *dig;
864 struct radeon_connector *radeon_connector;
865 struct radeon_connector_atom_dig *dig_connector;
866 struct radeon_dp_link_train_info dp_info;
867 int index;
868 u8 tmp, frev, crev;
869
870 if (!radeon_encoder->enc_priv)
871 return;
872 dig = radeon_encoder->enc_priv;
873
874 radeon_connector = to_radeon_connector(connector);
875 if (!radeon_connector->con_priv)
876 return;
877 dig_connector = radeon_connector->con_priv;
878
879 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
880 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
881 return;
882
883 /* DPEncoderService newer than 1.1 can't program properly the
884 * training pattern. When facing such version use the
885 * DIGXEncoderControl (X== 1 | 2)
886 */
887 dp_info.use_dpencoder = true;
888 index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
889 if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
890 if (crev > 1) {
891 dp_info.use_dpencoder = false;
892 }
893 }
894
895 dp_info.enc_id = 0;
896 if (dig->dig_encoder)
897 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
898 else
899 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
900 if (dig->linkb)
901 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
902 else
903 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
904
905 tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT);
906 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
907 dp_info.tp3_supported = true;
908 else
909 dp_info.tp3_supported = false;
910
911 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
912 dp_info.rdev = rdev;
913 dp_info.encoder = encoder;
914 dp_info.connector = connector;
915 dp_info.radeon_connector = radeon_connector;
916 dp_info.dp_lane_count = dig_connector->dp_lane_count;
917 dp_info.dp_clock = dig_connector->dp_clock;
918
919 if (radeon_dp_link_train_init(&dp_info))
920 goto done;
921 if (radeon_dp_link_train_cr(&dp_info))
922 goto done;
923 if (radeon_dp_link_train_ce(&dp_info))
924 goto done;
925 done:
926 if (radeon_dp_link_train_finish(&dp_info))
927 return;
928 }
Linux kernel - Deliverables
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