drivers/gpu/drm/radeon/atombios_dp.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  *          Jerome Glisse
  26  */
  27 #include <drm/drmP.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon.h"
  30
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33 #include <drm/drm_dp_helper.h>
  34
  35 /* move these to drm_dp_helper.c/h */
  36 #define DP_LINK_CONFIGURATION_SIZE 9
  37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
  38
  39 static char *voltage_names[] = {
  40         "0.4V", "0.6V", "0.8V", "1.2V"
  41 };
  42 static char *pre_emph_names[] = {
  43         "0dB", "3.5dB", "6dB", "9.5dB"
  44 };
  45
  46 /***** radeon AUX functions *****/
  47
  48 /* Atom needs data in little endian format
  49  * so swap as appropriate when copying data to
  50  * or from atom. Note that atom operates on
  51  * dw units.
  52  */
  53 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
  54 {
  55 #ifdef __BIG_ENDIAN
  56         u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
  57         u32 *dst32, *src32;
  58         int i;
  59
  60         memcpy(src_tmp, src, num_bytes);
  61         src32 = (u32 *)src_tmp;
  62         dst32 = (u32 *)dst_tmp;
  63         if (to_le) {
  64                 for (i = 0; i < ((num_bytes + 3) / 4); i++)
  65                         dst32[i] = cpu_to_le32(src32[i]);
  66                 memcpy(dst, dst_tmp, num_bytes);
  67         } else {
  68                 u8 dws = num_bytes & ~3;
  69                 for (i = 0; i < ((num_bytes + 3) / 4); i++)
  70                         dst32[i] = le32_to_cpu(src32[i]);
  71                 memcpy(dst, dst_tmp, dws);
  72                 if (num_bytes % 4) {
  73                         for (i = 0; i < (num_bytes % 4); i++)
  74                                 dst[dws+i] = dst_tmp[dws+i];
  75                 }
  76         }
  77 #else
  78         memcpy(dst, src, num_bytes);
  79 #endif
  80 }
  81
  82 union aux_channel_transaction {
  83         PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
  84         PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
  85 };
  86
  87 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
  88                                  u8 *send, int send_bytes,
  89                                  u8 *recv, int recv_size,
  90                                  u8 delay, u8 *ack)
  91 {
  92         struct drm_device *dev = chan->dev;
  93         struct radeon_device *rdev = dev->dev_private;
  94         union aux_channel_transaction args;
  95         int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
  96         unsigned char *base;
  97         int recv_bytes;
  98         int r = 0;
  99
 100         memset(&args, 0, sizeof(args));
 101
 102         mutex_lock(&chan->mutex);
 103         mutex_lock(&rdev->mode_info.atom_context->scratch_mutex);
 104
 105         base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
 106
 107         radeon_atom_copy_swap(base, send, send_bytes, true);
 108
 109         args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
 110         args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4));
 111         args.v1.ucDataOutLen = 0;
 112         args.v1.ucChannelID = chan->rec.i2c_id;
 113         args.v1.ucDelay = delay / 10;
 114         if (ASIC_IS_DCE4(rdev))
 115                 args.v2.ucHPD_ID = chan->rec.hpd;
 116
 117         atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 118
 119         *ack = args.v1.ucReplyStatus;
 120
 121         /* timeout */
 122         if (args.v1.ucReplyStatus == 1) {
 123                 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
 124                 r = -ETIMEDOUT;
 125                 goto done;
 126         }
 127
 128         /* flags not zero */
 129         if (args.v1.ucReplyStatus == 2) {
 130                 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
 131                 r = -EIO;
 132                 goto done;
 133         }
 134
 135         /* error */
 136         if (args.v1.ucReplyStatus == 3) {
 137                 DRM_DEBUG_KMS("dp_aux_ch error\n");
 138                 r = -EIO;
 139                 goto done;
 140         }
 141
 142         recv_bytes = args.v1.ucDataOutLen;
 143         if (recv_bytes > recv_size)
 144                 recv_bytes = recv_size;
 145
 146         if (recv && recv_size)
 147                 radeon_atom_copy_swap(recv, base + 16, recv_bytes, false);
 148
 149         r = recv_bytes;
 150 done:
 151         mutex_unlock(&rdev->mode_info.atom_context->scratch_mutex);
 152         mutex_unlock(&chan->mutex);
 153
 154         return r;
 155 }
 156
 157 #define BARE_ADDRESS_SIZE 3
 158 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
 159
 160 static ssize_t
 161 radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 162 {
 163         struct radeon_i2c_chan *chan =
 164                 container_of(aux, struct radeon_i2c_chan, aux);
 165         int ret;
 166         u8 tx_buf[20];
 167         size_t tx_size;
 168         u8 ack, delay = 0;
 169
 170         if (WARN_ON(msg->size > 16))
 171                 return -E2BIG;
 172
 173         tx_buf[0] = msg->address & 0xff;
 174         tx_buf[1] = msg->address >> 8;
 175         tx_buf[2] = msg->request << 4;
 176         tx_buf[3] = msg->size ? (msg->size - 1) : 0;
 177
 178         switch (msg->request & ~DP_AUX_I2C_MOT) {
 179         case DP_AUX_NATIVE_WRITE:
 180         case DP_AUX_I2C_WRITE:
 181                 /* The atom implementation only supports writes with a max payload of
 182                  * 12 bytes since it uses 4 bits for the total count (header + payload)
 183                  * in the parameter space.  The atom interface supports 16 byte
 184                  * payloads for reads. The hw itself supports up to 16 bytes of payload.
 185                  */
 186                 if (WARN_ON_ONCE(msg->size > 12))
 187                         return -E2BIG;
 188                 /* tx_size needs to be 4 even for bare address packets since the atom
 189                  * table needs the info in tx_buf[3].
 190                  */
 191                 tx_size = HEADER_SIZE + msg->size;
 192                 if (msg->size == 0)
 193                         tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
 194                 else
 195                         tx_buf[3] |= tx_size << 4;
 196                 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
 197                 ret = radeon_process_aux_ch(chan,
 198                                             tx_buf, tx_size, NULL, 0, delay, &ack);
 199                 if (ret >= 0)
 200                         /* Return payload size. */
 201                         ret = msg->size;
 202                 break;
 203         case DP_AUX_NATIVE_READ:
 204         case DP_AUX_I2C_READ:
 205                 /* tx_size needs to be 4 even for bare address packets since the atom
 206                  * table needs the info in tx_buf[3].
 207                  */
 208                 tx_size = HEADER_SIZE;
 209                 if (msg->size == 0)
 210                         tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
 211                 else
 212                         tx_buf[3] |= tx_size << 4;
 213                 ret = radeon_process_aux_ch(chan,
 214                                             tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
 215                 break;
 216         default:
 217                 ret = -EINVAL;
 218                 break;
 219         }
 220
 221         if (ret >= 0)
 222                 msg->reply = ack >> 4;
 223
 224         return ret;
 225 }
 226
 227 void radeon_dp_aux_init(struct radeon_connector *radeon_connector)
 228 {
 229         int ret;
 230
 231         radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd;
 232         radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev;
 233         radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer;
 234
 235         ret = drm_dp_aux_register(&radeon_connector->ddc_bus->aux);
 236         if (!ret)
 237                 radeon_connector->ddc_bus->has_aux = true;
 238
 239         WARN(ret, "drm_dp_aux_register() failed with error %d\n", ret);
 240 }
 241
 242 /***** general DP utility functions *****/
 243
 244 #define DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_LEVEL_3
 245 #define DP_PRE_EMPHASIS_MAX    DP_TRAIN_PRE_EMPH_LEVEL_3
 246
 247 static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
 248                                 int lane_count,
 249                                 u8 train_set[4])
 250 {
 251         u8 v = 0;
 252         u8 p = 0;
 253         int lane;
 254
 255         for (lane = 0; lane < lane_count; lane++) {
 256                 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
 257                 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
 258
 259                 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
 260                           lane,
 261                           voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 262                           pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 263
 264                 if (this_v > v)
 265                         v = this_v;
 266                 if (this_p > p)
 267                         p = this_p;
 268         }
 269
 270         if (v >= DP_VOLTAGE_MAX)
 271                 v |= DP_TRAIN_MAX_SWING_REACHED;
 272
 273         if (p >= DP_PRE_EMPHASIS_MAX)
 274                 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 275
 276         DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
 277                   voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 278                   pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 279
 280         for (lane = 0; lane < 4; lane++)
 281                 train_set[lane] = v | p;
 282 }
 283
 284 /* convert bits per color to bits per pixel */
 285 /* get bpc from the EDID */
 286 static int convert_bpc_to_bpp(int bpc)
 287 {
 288         if (bpc == 0)
 289                 return 24;
 290         else
 291                 return bpc * 3;
 292 }
 293
 294 /* get the max pix clock supported by the link rate and lane num */
 295 static int dp_get_max_dp_pix_clock(int link_rate,
 296                                    int lane_num,
 297                                    int bpp)
 298 {
 299         return (link_rate * lane_num * 8) / bpp;
 300 }
 301
 302 /***** radeon specific DP functions *****/
 303
 304 static int radeon_dp_get_max_link_rate(struct drm_connector *connector,
 305                                        u8 dpcd[DP_DPCD_SIZE])
 306 {
 307         int max_link_rate;
 308
 309         if (radeon_connector_is_dp12_capable(connector))
 310                 max_link_rate = min(drm_dp_max_link_rate(dpcd), 540000);
 311         else
 312                 max_link_rate = min(drm_dp_max_link_rate(dpcd), 270000);
 313
 314         return max_link_rate;
 315 }
 316
 317 /* First get the min lane# when low rate is used according to pixel clock
 318  * (prefer low rate), second check max lane# supported by DP panel,
 319  * if the max lane# < low rate lane# then use max lane# instead.
 320  */
 321 static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
 322                                         u8 dpcd[DP_DPCD_SIZE],
 323                                         int pix_clock)
 324 {
 325         int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
 326         int max_link_rate = radeon_dp_get_max_link_rate(connector, dpcd);
 327         int max_lane_num = drm_dp_max_lane_count(dpcd);
 328         int lane_num;
 329         int max_dp_pix_clock;
 330
 331         for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
 332                 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
 333                 if (pix_clock <= max_dp_pix_clock)
 334                         break;
 335         }
 336
 337         return lane_num;
 338 }
 339
 340 static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
 341                                        u8 dpcd[DP_DPCD_SIZE],
 342                                        int pix_clock)
 343 {
 344         int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
 345         int lane_num, max_pix_clock;
 346
 347         if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
 348             ENCODER_OBJECT_ID_NUTMEG)
 349                 return 270000;
 350
 351         lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
 352         max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
 353         if (pix_clock <= max_pix_clock)
 354                 return 162000;
 355         max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
 356         if (pix_clock <= max_pix_clock)
 357                 return 270000;
 358         if (radeon_connector_is_dp12_capable(connector)) {
 359                 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
 360                 if (pix_clock <= max_pix_clock)
 361                         return 540000;
 362         }
 363
 364         return radeon_dp_get_max_link_rate(connector, dpcd);
 365 }
 366
 367 static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
 368                                     int action, int dp_clock,
 369                                     u8 ucconfig, u8 lane_num)
 370 {
 371         DP_ENCODER_SERVICE_PARAMETERS args;
 372         int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
 373
 374         memset(&args, 0, sizeof(args));
 375         args.ucLinkClock = dp_clock / 10;
 376         args.ucConfig = ucconfig;
 377         args.ucAction = action;
 378         args.ucLaneNum = lane_num;
 379         args.ucStatus = 0;
 380
 381         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 382         return args.ucStatus;
 383 }
 384
 385 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
 386 {
 387         struct drm_device *dev = radeon_connector->base.dev;
 388         struct radeon_device *rdev = dev->dev_private;
 389
 390         return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
 391                                          radeon_connector->ddc_bus->rec.i2c_id, 0);
 392 }
 393
 394 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
 395 {
 396         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 397         u8 buf[3];
 398
 399         if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
 400                 return;
 401
 402         if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
 403                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
 404                               buf[0], buf[1], buf[2]);
 405
 406         if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
 407                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
 408                               buf[0], buf[1], buf[2]);
 409 }
 410
 411 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
 412 {
 413         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 414         u8 msg[DP_DPCD_SIZE];
 415         int ret;
 416
 417         ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
 418                                DP_DPCD_SIZE);
 419         if (ret > 0) {
 420                 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
 421
 422                 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
 423                               dig_connector->dpcd);
 424
 425                 radeon_dp_probe_oui(radeon_connector);
 426
 427                 return true;
 428         }
 429         dig_connector->dpcd[0] = 0;
 430         return false;
 431 }
 432
 433 int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
 434                              struct drm_connector *connector)
 435 {
 436         struct drm_device *dev = encoder->dev;
 437         struct radeon_device *rdev = dev->dev_private;
 438         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 439         struct radeon_connector_atom_dig *dig_connector;
 440         int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 441         u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
 442         u8 tmp;
 443
 444         if (!ASIC_IS_DCE4(rdev))
 445                 return panel_mode;
 446
 447         if (!radeon_connector->con_priv)
 448                 return panel_mode;
 449
 450         dig_connector = radeon_connector->con_priv;
 451
 452         if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
 453                 /* DP bridge chips */
 454                 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
 455                                       DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
 456                         if (tmp & 1)
 457                                 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
 458                         else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
 459                                  (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
 460                                 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
 461                         else
 462                                 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 463                 }
 464         } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
 465                 /* eDP */
 466                 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
 467                                       DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
 468                         if (tmp & 1)
 469                                 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
 470                 }
 471         }
 472
 473         return panel_mode;
 474 }
 475
 476 void radeon_dp_set_link_config(struct drm_connector *connector,
 477                                const struct drm_display_mode *mode)
 478 {
 479         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 480         struct radeon_connector_atom_dig *dig_connector;
 481
 482         if (!radeon_connector->con_priv)
 483                 return;
 484         dig_connector = radeon_connector->con_priv;
 485
 486         if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 487             (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
 488                 dig_connector->dp_clock =
 489                         radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
 490                 dig_connector->dp_lane_count =
 491                         radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
 492         }
 493 }
 494
 495 int radeon_dp_mode_valid_helper(struct drm_connector *connector,
 496                                 struct drm_display_mode *mode)
 497 {
 498         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 499         struct radeon_connector_atom_dig *dig_connector;
 500         int dp_clock;
 501
 502         if ((mode->clock > 340000) &&
 503             (!radeon_connector_is_dp12_capable(connector)))
 504                 return MODE_CLOCK_HIGH;
 505
 506         if (!radeon_connector->con_priv)
 507                 return MODE_CLOCK_HIGH;
 508         dig_connector = radeon_connector->con_priv;
 509
 510         dp_clock =
 511                 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
 512
 513         if ((dp_clock == 540000) &&
 514             (!radeon_connector_is_dp12_capable(connector)))
 515                 return MODE_CLOCK_HIGH;
 516
 517         return MODE_OK;
 518 }
 519
 520 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
 521 {
 522         u8 link_status[DP_LINK_STATUS_SIZE];
 523         struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 524
 525         if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux, link_status)
 526             <= 0)
 527                 return false;
 528         if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
 529                 return false;
 530         return true;
 531 }
 532
 533 void radeon_dp_set_rx_power_state(struct drm_connector *connector,
 534                                   u8 power_state)
 535 {
 536         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 537         struct radeon_connector_atom_dig *dig_connector;
 538
 539         if (!radeon_connector->con_priv)
 540                 return;
 541
 542         dig_connector = radeon_connector->con_priv;
 543
 544         /* power up/down the sink */
 545         if (dig_connector->dpcd[0] >= 0x11) {
 546                 drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux,
 547                                    DP_SET_POWER, power_state);
 548                 usleep_range(1000, 2000);
 549         }
 550 }
 551
 552
 553 struct radeon_dp_link_train_info {
 554         struct radeon_device *rdev;
 555         struct drm_encoder *encoder;
 556         struct drm_connector *connector;
 557         int enc_id;
 558         int dp_clock;
 559         int dp_lane_count;
 560         bool tp3_supported;
 561         u8 dpcd[DP_RECEIVER_CAP_SIZE];
 562         u8 train_set[4];
 563         u8 link_status[DP_LINK_STATUS_SIZE];
 564         u8 tries;
 565         bool use_dpencoder;
 566         struct drm_dp_aux *aux;
 567 };
 568
 569 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
 570 {
 571         /* set the initial vs/emph on the source */
 572         atombios_dig_transmitter_setup(dp_info->encoder,
 573                                        ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
 574                                        0, dp_info->train_set[0]); /* sets all lanes at once */
 575
 576         /* set the vs/emph on the sink */
 577         drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
 578                           dp_info->train_set, dp_info->dp_lane_count);
 579 }
 580
 581 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
 582 {
 583         int rtp = 0;
 584
 585         /* set training pattern on the source */
 586         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
 587                 switch (tp) {
 588                 case DP_TRAINING_PATTERN_1:
 589                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
 590                         break;
 591                 case DP_TRAINING_PATTERN_2:
 592                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
 593                         break;
 594                 case DP_TRAINING_PATTERN_3:
 595                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
 596                         break;
 597                 }
 598                 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
 599         } else {
 600                 switch (tp) {
 601                 case DP_TRAINING_PATTERN_1:
 602                         rtp = 0;
 603                         break;
 604                 case DP_TRAINING_PATTERN_2:
 605                         rtp = 1;
 606                         break;
 607                 }
 608                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
 609                                           dp_info->dp_clock, dp_info->enc_id, rtp);
 610         }
 611
 612         /* enable training pattern on the sink */
 613         drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
 614 }
 615
 616 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
 617 {
 618         struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
 619         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 620         u8 tmp;
 621
 622         /* power up the sink */
 623         radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
 624
 625         /* possibly enable downspread on the sink */
 626         if (dp_info->dpcd[3] & 0x1)
 627                 drm_dp_dpcd_writeb(dp_info->aux,
 628                                    DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
 629         else
 630                 drm_dp_dpcd_writeb(dp_info->aux,
 631                                    DP_DOWNSPREAD_CTRL, 0);
 632
 633         if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)
 634                 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
 635
 636         /* set the lane count on the sink */
 637         tmp = dp_info->dp_lane_count;
 638         if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
 639                 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 640         drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
 641
 642         /* set the link rate on the sink */
 643         tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
 644         drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
 645
 646         /* start training on the source */
 647         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
 648                 atombios_dig_encoder_setup(dp_info->encoder,
 649                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
 650         else
 651                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
 652                                           dp_info->dp_clock, dp_info->enc_id, 0);
 653
 654         /* disable the training pattern on the sink */
 655         drm_dp_dpcd_writeb(dp_info->aux,
 656                            DP_TRAINING_PATTERN_SET,
 657                            DP_TRAINING_PATTERN_DISABLE);
 658
 659         return 0;
 660 }
 661
 662 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
 663 {
 664         udelay(400);
 665
 666         /* disable the training pattern on the sink */
 667         drm_dp_dpcd_writeb(dp_info->aux,
 668                            DP_TRAINING_PATTERN_SET,
 669                            DP_TRAINING_PATTERN_DISABLE);
 670
 671         /* disable the training pattern on the source */
 672         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
 673                 atombios_dig_encoder_setup(dp_info->encoder,
 674                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
 675         else
 676                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
 677                                           dp_info->dp_clock, dp_info->enc_id, 0);
 678
 679         return 0;
 680 }
 681
 682 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
 683 {
 684         bool clock_recovery;
 685         u8 voltage;
 686         int i;
 687
 688         radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
 689         memset(dp_info->train_set, 0, 4);
 690         radeon_dp_update_vs_emph(dp_info);
 691
 692         udelay(400);
 693
 694         /* clock recovery loop */
 695         clock_recovery = false;
 696         dp_info->tries = 0;
 697         voltage = 0xff;
 698         while (1) {
 699                 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
 700
 701                 if (drm_dp_dpcd_read_link_status(dp_info->aux,
 702                                                  dp_info->link_status) <= 0) {
 703                         DRM_ERROR("displayport link status failed\n");
 704                         break;
 705                 }
 706
 707                 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
 708                         clock_recovery = true;
 709                         break;
 710                 }
 711
 712                 for (i = 0; i < dp_info->dp_lane_count; i++) {
 713                         if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
 714                                 break;
 715                 }
 716                 if (i == dp_info->dp_lane_count) {
 717                         DRM_ERROR("clock recovery reached max voltage\n");
 718                         break;
 719                 }
 720
 721                 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
 722                         ++dp_info->tries;
 723                         if (dp_info->tries == 5) {
 724                                 DRM_ERROR("clock recovery tried 5 times\n");
 725                                 break;
 726                         }
 727                 } else
 728                         dp_info->tries = 0;
 729
 730                 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 731
 732                 /* Compute new train_set as requested by sink */
 733                 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
 734
 735                 radeon_dp_update_vs_emph(dp_info);
 736         }
 737         if (!clock_recovery) {
 738                 DRM_ERROR("clock recovery failed\n");
 739                 return -1;
 740         } else {
 741                 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
 742                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 743                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
 744                           DP_TRAIN_PRE_EMPHASIS_SHIFT);
 745                 return 0;
 746         }
 747 }
 748
 749 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
 750 {
 751         bool channel_eq;
 752
 753         if (dp_info->tp3_supported)
 754                 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
 755         else
 756                 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
 757
 758         /* channel equalization loop */
 759         dp_info->tries = 0;
 760         channel_eq = false;
 761         while (1) {
 762                 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
 763
 764                 if (drm_dp_dpcd_read_link_status(dp_info->aux,
 765                                                  dp_info->link_status) <= 0) {
 766                         DRM_ERROR("displayport link status failed\n");
 767                         break;
 768                 }
 769
 770                 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
 771                         channel_eq = true;
 772                         break;
 773                 }
 774
 775                 /* Try 5 times */
 776                 if (dp_info->tries > 5) {
 777                         DRM_ERROR("channel eq failed: 5 tries\n");
 778                         break;
 779                 }
 780
 781                 /* Compute new train_set as requested by sink */
 782                 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
 783
 784                 radeon_dp_update_vs_emph(dp_info);
 785                 dp_info->tries++;
 786         }
 787
 788         if (!channel_eq) {
 789                 DRM_ERROR("channel eq failed\n");
 790                 return -1;
 791         } else {
 792                 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
 793                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 794                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
 795                           >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
 796                 return 0;
 797         }
 798 }
 799
 800 void radeon_dp_link_train(struct drm_encoder *encoder,
 801                           struct drm_connector *connector)
 802 {
 803         struct drm_device *dev = encoder->dev;
 804         struct radeon_device *rdev = dev->dev_private;
 805         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 806         struct radeon_encoder_atom_dig *dig;
 807         struct radeon_connector *radeon_connector;
 808         struct radeon_connector_atom_dig *dig_connector;
 809         struct radeon_dp_link_train_info dp_info;
 810         int index;
 811         u8 tmp, frev, crev;
 812
 813         if (!radeon_encoder->enc_priv)
 814                 return;
 815         dig = radeon_encoder->enc_priv;
 816
 817         radeon_connector = to_radeon_connector(connector);
 818         if (!radeon_connector->con_priv)
 819                 return;
 820         dig_connector = radeon_connector->con_priv;
 821
 822         if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
 823             (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
 824                 return;
 825
 826         /* DPEncoderService newer than 1.1 can't program properly the
 827          * training pattern. When facing such version use the
 828          * DIGXEncoderControl (X== 1 | 2)
 829          */
 830         dp_info.use_dpencoder = true;
 831         index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
 832         if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
 833                 if (crev > 1) {
 834                         dp_info.use_dpencoder = false;
 835                 }
 836         }
 837
 838         dp_info.enc_id = 0;
 839         if (dig->dig_encoder)
 840                 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
 841         else
 842                 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
 843         if (dig->linkb)
 844                 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
 845         else
 846                 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
 847
 848         if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
 849             == 1) {
 850                 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
 851                         dp_info.tp3_supported = true;
 852                 else
 853                         dp_info.tp3_supported = false;
 854         } else {
 855                 dp_info.tp3_supported = false;
 856         }
 857
 858         memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
 859         dp_info.rdev = rdev;
 860         dp_info.encoder = encoder;
 861         dp_info.connector = connector;
 862         dp_info.dp_lane_count = dig_connector->dp_lane_count;
 863         dp_info.dp_clock = dig_connector->dp_clock;
 864         dp_info.aux = &radeon_connector->ddc_bus->aux;
 865
 866         if (radeon_dp_link_train_init(&dp_info))
 867                 goto done;
 868         if (radeon_dp_link_train_cr(&dp_info))
 869                 goto done;
 870         if (radeon_dp_link_train_ce(&dp_info))
 871                 goto done;
 872 done:
 873         if (radeon_dp_link_train_finish(&dp_info))
 874                 return;
 875 }