2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include "atom-bits.h"
32 #include "drm_dp_helper.h"
34 /* move these to drm_dp_helper.c/h */
35 #define DP_LINK_CONFIGURATION_SIZE 9
36 #define DP_LINK_STATUS_SIZE 6
37 #define DP_DPCD_SIZE 8
39 static char *voltage_names
[] = {
40 "0.4V", "0.6V", "0.8V", "1.2V"
42 static char *pre_emph_names
[] = {
43 "0dB", "3.5dB", "6dB", "9.5dB"
46 /***** radeon AUX functions *****/
47 union aux_channel_transaction
{
48 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1
;
49 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2
;
52 static int radeon_process_aux_ch(struct radeon_i2c_chan
*chan
,
53 u8
*send
, int send_bytes
,
54 u8
*recv
, int recv_size
,
57 struct drm_device
*dev
= chan
->dev
;
58 struct radeon_device
*rdev
= dev
->dev_private
;
59 union aux_channel_transaction args
;
60 int index
= GetIndexIntoMasterTable(COMMAND
, ProcessAuxChannelTransaction
);
64 memset(&args
, 0, sizeof(args
));
66 base
= (unsigned char *)rdev
->mode_info
.atom_context
->scratch
;
68 memcpy(base
, send
, send_bytes
);
70 args
.v1
.lpAuxRequest
= 0;
71 args
.v1
.lpDataOut
= 16;
72 args
.v1
.ucDataOutLen
= 0;
73 args
.v1
.ucChannelID
= chan
->rec
.i2c_id
;
74 args
.v1
.ucDelay
= delay
/ 10;
75 if (ASIC_IS_DCE4(rdev
))
76 args
.v2
.ucHPD_ID
= chan
->rec
.hpd
;
78 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
80 *ack
= args
.v1
.ucReplyStatus
;
83 if (args
.v1
.ucReplyStatus
== 1) {
84 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
89 if (args
.v1
.ucReplyStatus
== 2) {
90 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
95 if (args
.v1
.ucReplyStatus
== 3) {
96 DRM_DEBUG_KMS("dp_aux_ch error\n");
100 recv_bytes
= args
.v1
.ucDataOutLen
;
101 if (recv_bytes
> recv_size
)
102 recv_bytes
= recv_size
;
104 if (recv
&& recv_size
)
105 memcpy(recv
, base
+ 16, recv_bytes
);
110 static int radeon_dp_aux_native_write(struct radeon_connector
*radeon_connector
,
111 u16 address
, u8
*send
, u8 send_bytes
, u8 delay
)
113 struct radeon_connector_atom_dig
*dig_connector
= radeon_connector
->con_priv
;
116 int msg_bytes
= send_bytes
+ 4;
124 msg
[1] = address
>> 8;
125 msg
[2] = AUX_NATIVE_WRITE
<< 4;
126 msg
[3] = (msg_bytes
<< 4) | (send_bytes
- 1);
127 memcpy(&msg
[4], send
, send_bytes
);
129 for (retry
= 0; retry
< 4; retry
++) {
130 ret
= radeon_process_aux_ch(dig_connector
->dp_i2c_bus
,
131 msg
, msg_bytes
, NULL
, 0, delay
, &ack
);
134 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
)
136 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
145 static int radeon_dp_aux_native_read(struct radeon_connector
*radeon_connector
,
146 u16 address
, u8
*recv
, int recv_bytes
, u8 delay
)
148 struct radeon_connector_atom_dig
*dig_connector
= radeon_connector
->con_priv
;
156 msg
[1] = address
>> 8;
157 msg
[2] = AUX_NATIVE_READ
<< 4;
158 msg
[3] = (msg_bytes
<< 4) | (recv_bytes
- 1);
160 for (retry
= 0; retry
< 4; retry
++) {
161 ret
= radeon_process_aux_ch(dig_connector
->dp_i2c_bus
,
162 msg
, msg_bytes
, recv
, recv_bytes
, delay
, &ack
);
165 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
)
167 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
178 static void radeon_write_dpcd_reg(struct radeon_connector
*radeon_connector
,
181 radeon_dp_aux_native_write(radeon_connector
, reg
, &val
, 1, 0);
184 static u8
radeon_read_dpcd_reg(struct radeon_connector
*radeon_connector
,
189 radeon_dp_aux_native_read(radeon_connector
, reg
, &val
, 1, 0);
194 int radeon_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
195 u8 write_byte
, u8
*read_byte
)
197 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
198 struct radeon_i2c_chan
*auxch
= (struct radeon_i2c_chan
*)adapter
;
199 u16 address
= algo_data
->address
;
208 /* Set up the command byte */
209 if (mode
& MODE_I2C_READ
)
210 msg
[2] = AUX_I2C_READ
<< 4;
212 msg
[2] = AUX_I2C_WRITE
<< 4;
214 if (!(mode
& MODE_I2C_STOP
))
215 msg
[2] |= AUX_I2C_MOT
<< 4;
218 msg
[1] = address
>> 8;
223 msg
[3] = msg_bytes
<< 4;
228 msg
[3] = msg_bytes
<< 4;
236 for (retry
= 0; retry
< 4; retry
++) {
237 ret
= radeon_process_aux_ch(auxch
,
238 msg
, msg_bytes
, reply
, reply_bytes
, 0, &ack
);
240 DRM_DEBUG_KMS("aux_ch failed %d\n", ret
);
244 switch (ack
& AUX_NATIVE_REPLY_MASK
) {
245 case AUX_NATIVE_REPLY_ACK
:
246 /* I2C-over-AUX Reply field is only valid
247 * when paired with AUX ACK.
250 case AUX_NATIVE_REPLY_NACK
:
251 DRM_DEBUG_KMS("aux_ch native nack\n");
253 case AUX_NATIVE_REPLY_DEFER
:
254 DRM_DEBUG_KMS("aux_ch native defer\n");
258 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack
);
262 switch (ack
& AUX_I2C_REPLY_MASK
) {
263 case AUX_I2C_REPLY_ACK
:
264 if (mode
== MODE_I2C_READ
)
265 *read_byte
= reply
[0];
267 case AUX_I2C_REPLY_NACK
:
268 DRM_DEBUG_KMS("aux_i2c nack\n");
270 case AUX_I2C_REPLY_DEFER
:
271 DRM_DEBUG_KMS("aux_i2c defer\n");
275 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack
);
280 DRM_ERROR("aux i2c too many retries, giving up\n");
284 /***** general DP utility functions *****/
286 static u8
dp_link_status(u8 link_status
[DP_LINK_STATUS_SIZE
], int r
)
288 return link_status
[r
- DP_LANE0_1_STATUS
];
291 static u8
dp_get_lane_status(u8 link_status
[DP_LINK_STATUS_SIZE
],
294 int i
= DP_LANE0_1_STATUS
+ (lane
>> 1);
295 int s
= (lane
& 1) * 4;
296 u8 l
= dp_link_status(link_status
, i
);
297 return (l
>> s
) & 0xf;
300 static bool dp_clock_recovery_ok(u8 link_status
[DP_LINK_STATUS_SIZE
],
306 for (lane
= 0; lane
< lane_count
; lane
++) {
307 lane_status
= dp_get_lane_status(link_status
, lane
);
308 if ((lane_status
& DP_LANE_CR_DONE
) == 0)
314 static bool dp_channel_eq_ok(u8 link_status
[DP_LINK_STATUS_SIZE
],
321 lane_align
= dp_link_status(link_status
,
322 DP_LANE_ALIGN_STATUS_UPDATED
);
323 if ((lane_align
& DP_INTERLANE_ALIGN_DONE
) == 0)
325 for (lane
= 0; lane
< lane_count
; lane
++) {
326 lane_status
= dp_get_lane_status(link_status
, lane
);
327 if ((lane_status
& DP_CHANNEL_EQ_BITS
) != DP_CHANNEL_EQ_BITS
)
333 static u8
dp_get_adjust_request_voltage(u8 link_status
[DP_LINK_STATUS_SIZE
],
337 int i
= DP_ADJUST_REQUEST_LANE0_1
+ (lane
>> 1);
338 int s
= ((lane
& 1) ?
339 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT
:
340 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT
);
341 u8 l
= dp_link_status(link_status
, i
);
343 return ((l
>> s
) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT
;
346 static u8
dp_get_adjust_request_pre_emphasis(u8 link_status
[DP_LINK_STATUS_SIZE
],
349 int i
= DP_ADJUST_REQUEST_LANE0_1
+ (lane
>> 1);
350 int s
= ((lane
& 1) ?
351 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT
:
352 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT
);
353 u8 l
= dp_link_status(link_status
, i
);
355 return ((l
>> s
) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT
;
358 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
359 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5
361 static void dp_get_adjust_train(u8 link_status
[DP_LINK_STATUS_SIZE
],
369 for (lane
= 0; lane
< lane_count
; lane
++) {
370 u8 this_v
= dp_get_adjust_request_voltage(link_status
, lane
);
371 u8 this_p
= dp_get_adjust_request_pre_emphasis(link_status
, lane
);
373 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
375 voltage_names
[this_v
>> DP_TRAIN_VOLTAGE_SWING_SHIFT
],
376 pre_emph_names
[this_p
>> DP_TRAIN_PRE_EMPHASIS_SHIFT
]);
384 if (v
>= DP_VOLTAGE_MAX
)
385 v
|= DP_TRAIN_MAX_SWING_REACHED
;
387 if (p
>= DP_PRE_EMPHASIS_MAX
)
388 p
|= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
390 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
391 voltage_names
[(v
& DP_TRAIN_VOLTAGE_SWING_MASK
) >> DP_TRAIN_VOLTAGE_SWING_SHIFT
],
392 pre_emph_names
[(p
& DP_TRAIN_PRE_EMPHASIS_MASK
) >> DP_TRAIN_PRE_EMPHASIS_SHIFT
]);
394 for (lane
= 0; lane
< 4; lane
++)
395 train_set
[lane
] = v
| p
;
398 /* convert bits per color to bits per pixel */
399 /* get bpc from the EDID */
400 static int convert_bpc_to_bpp(int bpc
)
408 /* get the max pix clock supported by the link rate and lane num */
409 static int dp_get_max_dp_pix_clock(int link_rate
,
413 return (link_rate
* lane_num
* 8) / bpp
;
416 static int dp_get_max_link_rate(u8 dpcd
[DP_DPCD_SIZE
])
418 switch (dpcd
[DP_MAX_LINK_RATE
]) {
419 case DP_LINK_BW_1_62
:
429 static u8
dp_get_max_lane_number(u8 dpcd
[DP_DPCD_SIZE
])
431 return dpcd
[DP_MAX_LANE_COUNT
] & DP_MAX_LANE_COUNT_MASK
;
434 static u8
dp_get_dp_link_rate_coded(int link_rate
)
439 return DP_LINK_BW_1_62
;
441 return DP_LINK_BW_2_7
;
443 return DP_LINK_BW_5_4
;
447 /***** radeon specific DP functions *****/
449 /* First get the min lane# when low rate is used according to pixel clock
450 * (prefer low rate), second check max lane# supported by DP panel,
451 * if the max lane# < low rate lane# then use max lane# instead.
453 static int radeon_dp_get_dp_lane_number(struct drm_connector
*connector
,
454 u8 dpcd
[DP_DPCD_SIZE
],
457 int bpp
= convert_bpc_to_bpp(connector
->display_info
.bpc
);
458 int max_link_rate
= dp_get_max_link_rate(dpcd
);
459 int max_lane_num
= dp_get_max_lane_number(dpcd
);
461 int max_dp_pix_clock
;
463 for (lane_num
= 1; lane_num
< max_lane_num
; lane_num
<<= 1) {
464 max_dp_pix_clock
= dp_get_max_dp_pix_clock(max_link_rate
, lane_num
, bpp
);
465 if (pix_clock
<= max_dp_pix_clock
)
472 static int radeon_dp_get_dp_link_clock(struct drm_connector
*connector
,
473 u8 dpcd
[DP_DPCD_SIZE
],
476 int bpp
= convert_bpc_to_bpp(connector
->display_info
.bpc
);
477 int lane_num
, max_pix_clock
;
479 if (radeon_connector_encoder_is_dp_bridge(connector
))
482 lane_num
= radeon_dp_get_dp_lane_number(connector
, dpcd
, pix_clock
);
483 max_pix_clock
= dp_get_max_dp_pix_clock(162000, lane_num
, bpp
);
484 if (pix_clock
<= max_pix_clock
)
486 max_pix_clock
= dp_get_max_dp_pix_clock(270000, lane_num
, bpp
);
487 if (pix_clock
<= max_pix_clock
)
489 if (radeon_connector_is_dp12_capable(connector
)) {
490 max_pix_clock
= dp_get_max_dp_pix_clock(540000, lane_num
, bpp
);
491 if (pix_clock
<= max_pix_clock
)
495 return dp_get_max_link_rate(dpcd
);
498 static u8
radeon_dp_encoder_service(struct radeon_device
*rdev
,
499 int action
, int dp_clock
,
500 u8 ucconfig
, u8 lane_num
)
502 DP_ENCODER_SERVICE_PARAMETERS args
;
503 int index
= GetIndexIntoMasterTable(COMMAND
, DPEncoderService
);
505 memset(&args
, 0, sizeof(args
));
506 args
.ucLinkClock
= dp_clock
/ 10;
507 args
.ucConfig
= ucconfig
;
508 args
.ucAction
= action
;
509 args
.ucLaneNum
= lane_num
;
512 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
513 return args
.ucStatus
;
516 u8
radeon_dp_getsinktype(struct radeon_connector
*radeon_connector
)
518 struct radeon_connector_atom_dig
*dig_connector
= radeon_connector
->con_priv
;
519 struct drm_device
*dev
= radeon_connector
->base
.dev
;
520 struct radeon_device
*rdev
= dev
->dev_private
;
522 return radeon_dp_encoder_service(rdev
, ATOM_DP_ACTION_GET_SINK_TYPE
, 0,
523 dig_connector
->dp_i2c_bus
->rec
.i2c_id
, 0);
526 bool radeon_dp_getdpcd(struct radeon_connector
*radeon_connector
)
528 struct radeon_connector_atom_dig
*dig_connector
= radeon_connector
->con_priv
;
532 ret
= radeon_dp_aux_native_read(radeon_connector
, DP_DPCD_REV
, msg
, 8, 0);
534 memcpy(dig_connector
->dpcd
, msg
, 8);
535 DRM_DEBUG_KMS("DPCD: ");
536 for (i
= 0; i
< 8; i
++)
537 DRM_DEBUG_KMS("%02x ", msg
[i
]);
541 dig_connector
->dpcd
[0] = 0;
545 static void radeon_dp_set_panel_mode(struct drm_encoder
*encoder
,
546 struct drm_connector
*connector
)
548 struct drm_device
*dev
= encoder
->dev
;
549 struct radeon_device
*rdev
= dev
->dev_private
;
550 int panel_mode
= DP_PANEL_MODE_EXTERNAL_DP_MODE
;
552 if (!ASIC_IS_DCE4(rdev
))
555 if (radeon_connector_encoder_is_dp_bridge(connector
))
556 panel_mode
= DP_PANEL_MODE_INTERNAL_DP1_MODE
;
558 atombios_dig_encoder_setup(encoder
,
559 ATOM_ENCODER_CMD_SETUP_PANEL_MODE
,
563 void radeon_dp_set_link_config(struct drm_connector
*connector
,
564 struct drm_display_mode
*mode
)
566 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
567 struct radeon_connector_atom_dig
*dig_connector
;
569 if (!radeon_connector
->con_priv
)
571 dig_connector
= radeon_connector
->con_priv
;
573 if ((dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_DISPLAYPORT
) ||
574 (dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_eDP
)) {
575 dig_connector
->dp_clock
=
576 radeon_dp_get_dp_link_clock(connector
, dig_connector
->dpcd
, mode
->clock
);
577 dig_connector
->dp_lane_count
=
578 radeon_dp_get_dp_lane_number(connector
, dig_connector
->dpcd
, mode
->clock
);
582 int radeon_dp_mode_valid_helper(struct drm_connector
*connector
,
583 struct drm_display_mode
*mode
)
585 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
586 struct radeon_connector_atom_dig
*dig_connector
;
589 if (!radeon_connector
->con_priv
)
590 return MODE_CLOCK_HIGH
;
591 dig_connector
= radeon_connector
->con_priv
;
594 radeon_dp_get_dp_link_clock(connector
, dig_connector
->dpcd
, mode
->clock
);
596 if ((dp_clock
== 540000) &&
597 (!radeon_connector_is_dp12_capable(connector
)))
598 return MODE_CLOCK_HIGH
;
603 static bool radeon_dp_get_link_status(struct radeon_connector
*radeon_connector
,
604 u8 link_status
[DP_LINK_STATUS_SIZE
])
607 ret
= radeon_dp_aux_native_read(radeon_connector
, DP_LANE0_1_STATUS
,
608 link_status
, DP_LINK_STATUS_SIZE
, 100);
610 DRM_ERROR("displayport link status failed\n");
614 DRM_DEBUG_KMS("link status %02x %02x %02x %02x %02x %02x\n",
615 link_status
[0], link_status
[1], link_status
[2],
616 link_status
[3], link_status
[4], link_status
[5]);
620 bool radeon_dp_needs_link_train(struct radeon_connector
*radeon_connector
)
622 u8 link_status
[DP_LINK_STATUS_SIZE
];
623 struct radeon_connector_atom_dig
*dig
= radeon_connector
->con_priv
;
625 if (!radeon_dp_get_link_status(radeon_connector
, link_status
))
627 if (dp_channel_eq_ok(link_status
, dig
->dp_lane_count
))
632 struct radeon_dp_link_train_info
{
633 struct radeon_device
*rdev
;
634 struct drm_encoder
*encoder
;
635 struct drm_connector
*connector
;
636 struct radeon_connector
*radeon_connector
;
644 u8 link_status
[DP_LINK_STATUS_SIZE
];
649 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info
*dp_info
)
651 /* set the initial vs/emph on the source */
652 atombios_dig_transmitter_setup(dp_info
->encoder
,
653 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
,
654 0, dp_info
->train_set
[0]); /* sets all lanes at once */
656 /* set the vs/emph on the sink */
657 radeon_dp_aux_native_write(dp_info
->radeon_connector
, DP_TRAINING_LANE0_SET
,
658 dp_info
->train_set
, dp_info
->dp_lane_count
, 0);
661 static void radeon_dp_set_tp(struct radeon_dp_link_train_info
*dp_info
, int tp
)
665 /* set training pattern on the source */
666 if (ASIC_IS_DCE4(dp_info
->rdev
) || !dp_info
->use_dpencoder
) {
668 case DP_TRAINING_PATTERN_1
:
669 rtp
= ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1
;
671 case DP_TRAINING_PATTERN_2
:
672 rtp
= ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2
;
674 case DP_TRAINING_PATTERN_3
:
675 rtp
= ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3
;
678 atombios_dig_encoder_setup(dp_info
->encoder
, rtp
, 0);
681 case DP_TRAINING_PATTERN_1
:
684 case DP_TRAINING_PATTERN_2
:
688 radeon_dp_encoder_service(dp_info
->rdev
, ATOM_DP_ACTION_TRAINING_PATTERN_SEL
,
689 dp_info
->dp_clock
, dp_info
->enc_id
, rtp
);
692 /* enable training pattern on the sink */
693 radeon_write_dpcd_reg(dp_info
->radeon_connector
, DP_TRAINING_PATTERN_SET
, tp
);
696 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info
*dp_info
)
700 /* power up the sink */
701 if (dp_info
->dpcd
[0] >= 0x11)
702 radeon_write_dpcd_reg(dp_info
->radeon_connector
,
703 DP_SET_POWER
, DP_SET_POWER_D0
);
705 /* possibly enable downspread on the sink */
706 if (dp_info
->dpcd
[3] & 0x1)
707 radeon_write_dpcd_reg(dp_info
->radeon_connector
,
708 DP_DOWNSPREAD_CTRL
, DP_SPREAD_AMP_0_5
);
710 radeon_write_dpcd_reg(dp_info
->radeon_connector
,
711 DP_DOWNSPREAD_CTRL
, 0);
713 radeon_dp_set_panel_mode(dp_info
->encoder
, dp_info
->connector
);
715 /* set the lane count on the sink */
716 tmp
= dp_info
->dp_lane_count
;
717 if (dp_info
->dpcd
[0] >= 0x11)
718 tmp
|= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
719 radeon_write_dpcd_reg(dp_info
->radeon_connector
, DP_LANE_COUNT_SET
, tmp
);
721 /* set the link rate on the sink */
722 tmp
= dp_get_dp_link_rate_coded(dp_info
->dp_clock
);
723 radeon_write_dpcd_reg(dp_info
->radeon_connector
, DP_LINK_BW_SET
, tmp
);
725 /* start training on the source */
726 if (ASIC_IS_DCE4(dp_info
->rdev
) || !dp_info
->use_dpencoder
)
727 atombios_dig_encoder_setup(dp_info
->encoder
,
728 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START
, 0);
730 radeon_dp_encoder_service(dp_info
->rdev
, ATOM_DP_ACTION_TRAINING_START
,
731 dp_info
->dp_clock
, dp_info
->enc_id
, 0);
733 /* disable the training pattern on the sink */
734 radeon_write_dpcd_reg(dp_info
->radeon_connector
,
735 DP_TRAINING_PATTERN_SET
,
736 DP_TRAINING_PATTERN_DISABLE
);
741 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info
*dp_info
)
745 /* disable the training pattern on the sink */
746 radeon_write_dpcd_reg(dp_info
->radeon_connector
,
747 DP_TRAINING_PATTERN_SET
,
748 DP_TRAINING_PATTERN_DISABLE
);
750 /* disable the training pattern on the source */
751 if (ASIC_IS_DCE4(dp_info
->rdev
) || !dp_info
->use_dpencoder
)
752 atombios_dig_encoder_setup(dp_info
->encoder
,
753 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE
, 0);
755 radeon_dp_encoder_service(dp_info
->rdev
, ATOM_DP_ACTION_TRAINING_COMPLETE
,
756 dp_info
->dp_clock
, dp_info
->enc_id
, 0);
761 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info
*dp_info
)
767 radeon_dp_set_tp(dp_info
, DP_TRAINING_PATTERN_1
);
768 memset(dp_info
->train_set
, 0, 4);
769 radeon_dp_update_vs_emph(dp_info
);
773 /* clock recovery loop */
774 clock_recovery
= false;
778 if (dp_info
->rd_interval
== 0)
781 mdelay(dp_info
->rd_interval
* 4);
783 if (!radeon_dp_get_link_status(dp_info
->radeon_connector
, dp_info
->link_status
))
786 if (dp_clock_recovery_ok(dp_info
->link_status
, dp_info
->dp_lane_count
)) {
787 clock_recovery
= true;
791 for (i
= 0; i
< dp_info
->dp_lane_count
; i
++) {
792 if ((dp_info
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
795 if (i
== dp_info
->dp_lane_count
) {
796 DRM_ERROR("clock recovery reached max voltage\n");
800 if ((dp_info
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
802 if (dp_info
->tries
== 5) {
803 DRM_ERROR("clock recovery tried 5 times\n");
809 voltage
= dp_info
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
811 /* Compute new train_set as requested by sink */
812 dp_get_adjust_train(dp_info
->link_status
, dp_info
->dp_lane_count
, dp_info
->train_set
);
814 radeon_dp_update_vs_emph(dp_info
);
816 if (!clock_recovery
) {
817 DRM_ERROR("clock recovery failed\n");
820 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
821 dp_info
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
,
822 (dp_info
->train_set
[0] & DP_TRAIN_PRE_EMPHASIS_MASK
) >>
823 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
828 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info
*dp_info
)
832 if (dp_info
->tp3_supported
)
833 radeon_dp_set_tp(dp_info
, DP_TRAINING_PATTERN_3
);
835 radeon_dp_set_tp(dp_info
, DP_TRAINING_PATTERN_2
);
837 /* channel equalization loop */
841 if (dp_info
->rd_interval
== 0)
844 mdelay(dp_info
->rd_interval
* 4);
846 if (!radeon_dp_get_link_status(dp_info
->radeon_connector
, dp_info
->link_status
))
849 if (dp_channel_eq_ok(dp_info
->link_status
, dp_info
->dp_lane_count
)) {
855 if (dp_info
->tries
> 5) {
856 DRM_ERROR("channel eq failed: 5 tries\n");
860 /* Compute new train_set as requested by sink */
861 dp_get_adjust_train(dp_info
->link_status
, dp_info
->dp_lane_count
, dp_info
->train_set
);
863 radeon_dp_update_vs_emph(dp_info
);
868 DRM_ERROR("channel eq failed\n");
871 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
872 dp_info
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
,
873 (dp_info
->train_set
[0] & DP_TRAIN_PRE_EMPHASIS_MASK
)
874 >> DP_TRAIN_PRE_EMPHASIS_SHIFT
);
879 void radeon_dp_link_train(struct drm_encoder
*encoder
,
880 struct drm_connector
*connector
)
882 struct drm_device
*dev
= encoder
->dev
;
883 struct radeon_device
*rdev
= dev
->dev_private
;
884 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
885 struct radeon_encoder_atom_dig
*dig
;
886 struct radeon_connector
*radeon_connector
;
887 struct radeon_connector_atom_dig
*dig_connector
;
888 struct radeon_dp_link_train_info dp_info
;
892 if (!radeon_encoder
->enc_priv
)
894 dig
= radeon_encoder
->enc_priv
;
896 radeon_connector
= to_radeon_connector(connector
);
897 if (!radeon_connector
->con_priv
)
899 dig_connector
= radeon_connector
->con_priv
;
901 if ((dig_connector
->dp_sink_type
!= CONNECTOR_OBJECT_ID_DISPLAYPORT
) &&
902 (dig_connector
->dp_sink_type
!= CONNECTOR_OBJECT_ID_eDP
))
905 /* DPEncoderService newer than 1.1 can't program properly the
906 * training pattern. When facing such version use the
907 * DIGXEncoderControl (X== 1 | 2)
909 dp_info
.use_dpencoder
= true;
910 index
= GetIndexIntoMasterTable(COMMAND
, DPEncoderService
);
911 if (atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
)) {
913 dp_info
.use_dpencoder
= false;
918 if (dig
->dig_encoder
)
919 dp_info
.enc_id
|= ATOM_DP_CONFIG_DIG2_ENCODER
;
921 dp_info
.enc_id
|= ATOM_DP_CONFIG_DIG1_ENCODER
;
923 dp_info
.enc_id
|= ATOM_DP_CONFIG_LINK_B
;
925 dp_info
.enc_id
|= ATOM_DP_CONFIG_LINK_A
;
927 dp_info
.rd_interval
= radeon_read_dpcd_reg(radeon_connector
, DP_TRAINING_AUX_RD_INTERVAL
);
928 tmp
= radeon_read_dpcd_reg(radeon_connector
, DP_MAX_LANE_COUNT
);
929 if (ASIC_IS_DCE5(rdev
) && (tmp
& DP_TPS3_SUPPORTED
))
930 dp_info
.tp3_supported
= true;
932 dp_info
.tp3_supported
= false;
934 memcpy(dp_info
.dpcd
, dig_connector
->dpcd
, 8);
936 dp_info
.encoder
= encoder
;
937 dp_info
.connector
= connector
;
938 dp_info
.radeon_connector
= radeon_connector
;
939 dp_info
.dp_lane_count
= dig_connector
->dp_lane_count
;
940 dp_info
.dp_clock
= dig_connector
->dp_clock
;
942 if (radeon_dp_link_train_init(&dp_info
))
944 if (radeon_dp_link_train_cr(&dp_info
))
946 if (radeon_dp_link_train_ce(&dp_info
))
949 if (radeon_dp_link_train_finish(&dp_info
))