2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
31 #include <linux/backlight.h>
33 extern int atom_debug
;
36 radeon_atom_get_backlight_level_from_reg(struct radeon_device
*rdev
)
41 if (rdev
->family
>= CHIP_R600
)
42 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
44 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
46 backlight_level
= ((bios_2_scratch
& ATOM_S2_CURRENT_BL_LEVEL_MASK
) >>
47 ATOM_S2_CURRENT_BL_LEVEL_SHIFT
);
49 return backlight_level
;
53 radeon_atom_set_backlight_level_to_reg(struct radeon_device
*rdev
,
58 if (rdev
->family
>= CHIP_R600
)
59 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
61 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
63 bios_2_scratch
&= ~ATOM_S2_CURRENT_BL_LEVEL_MASK
;
64 bios_2_scratch
|= ((backlight_level
<< ATOM_S2_CURRENT_BL_LEVEL_SHIFT
) &
65 ATOM_S2_CURRENT_BL_LEVEL_MASK
);
67 if (rdev
->family
>= CHIP_R600
)
68 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
70 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);
74 atombios_get_backlight_level(struct radeon_encoder
*radeon_encoder
)
76 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
77 struct radeon_device
*rdev
= dev
->dev_private
;
79 if (!(rdev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
82 return radeon_atom_get_backlight_level_from_reg(rdev
);
86 atombios_set_backlight_level(struct radeon_encoder
*radeon_encoder
, u8 level
)
88 struct drm_encoder
*encoder
= &radeon_encoder
->base
;
89 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
90 struct radeon_device
*rdev
= dev
->dev_private
;
91 struct radeon_encoder_atom_dig
*dig
;
92 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args
;
95 if (!(rdev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
98 if ((radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) &&
99 radeon_encoder
->enc_priv
) {
100 dig
= radeon_encoder
->enc_priv
;
101 dig
->backlight_level
= level
;
102 radeon_atom_set_backlight_level_to_reg(rdev
, dig
->backlight_level
);
104 switch (radeon_encoder
->encoder_id
) {
105 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
106 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
107 index
= GetIndexIntoMasterTable(COMMAND
, LCD1OutputControl
);
108 if (dig
->backlight_level
== 0) {
109 args
.ucAction
= ATOM_LCD_BLOFF
;
110 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
112 args
.ucAction
= ATOM_LCD_BL_BRIGHTNESS_CONTROL
;
113 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
114 args
.ucAction
= ATOM_LCD_BLON
;
115 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
118 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
119 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
120 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
122 if (dig
->backlight_level
== 0)
123 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_LCD_BLOFF
, 0, 0);
125 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL
, 0, 0);
126 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_LCD_BLON
, 0, 0);
135 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
137 static u8
radeon_atom_bl_level(struct backlight_device
*bd
)
141 /* Convert brightness to hardware level */
142 if (bd
->props
.brightness
< 0)
144 else if (bd
->props
.brightness
> RADEON_MAX_BL_LEVEL
)
145 level
= RADEON_MAX_BL_LEVEL
;
147 level
= bd
->props
.brightness
;
152 static int radeon_atom_backlight_update_status(struct backlight_device
*bd
)
154 struct radeon_backlight_privdata
*pdata
= bl_get_data(bd
);
155 struct radeon_encoder
*radeon_encoder
= pdata
->encoder
;
157 atombios_set_backlight_level(radeon_encoder
, radeon_atom_bl_level(bd
));
162 static int radeon_atom_backlight_get_brightness(struct backlight_device
*bd
)
164 struct radeon_backlight_privdata
*pdata
= bl_get_data(bd
);
165 struct radeon_encoder
*radeon_encoder
= pdata
->encoder
;
166 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
167 struct radeon_device
*rdev
= dev
->dev_private
;
169 return radeon_atom_get_backlight_level_from_reg(rdev
);
172 static const struct backlight_ops radeon_atom_backlight_ops
= {
173 .get_brightness
= radeon_atom_backlight_get_brightness
,
174 .update_status
= radeon_atom_backlight_update_status
,
177 void radeon_atom_backlight_init(struct radeon_encoder
*radeon_encoder
,
178 struct drm_connector
*drm_connector
)
180 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
181 struct radeon_device
*rdev
= dev
->dev_private
;
182 struct backlight_device
*bd
;
183 struct backlight_properties props
;
184 struct radeon_backlight_privdata
*pdata
;
185 struct radeon_encoder_atom_dig
*dig
;
188 /* Mac laptops with multiple GPUs use the gmux driver for backlight
189 * so don't register a backlight device
191 if ((rdev
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_APPLE
) &&
192 (rdev
->pdev
->device
== 0x6741))
195 if (!radeon_encoder
->enc_priv
)
198 if (!rdev
->is_atom_bios
)
201 if (!(rdev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
204 pdata
= kmalloc(sizeof(struct radeon_backlight_privdata
), GFP_KERNEL
);
206 DRM_ERROR("Memory allocation failed\n");
210 memset(&props
, 0, sizeof(props
));
211 props
.max_brightness
= RADEON_MAX_BL_LEVEL
;
212 props
.type
= BACKLIGHT_RAW
;
213 snprintf(bl_name
, sizeof(bl_name
),
214 "radeon_bl%d", dev
->primary
->index
);
215 bd
= backlight_device_register(bl_name
, drm_connector
->kdev
,
216 pdata
, &radeon_atom_backlight_ops
, &props
);
218 DRM_ERROR("Backlight registration failed\n");
222 pdata
->encoder
= radeon_encoder
;
224 dig
= radeon_encoder
->enc_priv
;
227 bd
->props
.brightness
= radeon_atom_backlight_get_brightness(bd
);
228 /* Set a reasonable default here if the level is 0 otherwise
229 * fbdev will attempt to turn the backlight on after console
230 * unblanking and it will try and restore 0 which turns the backlight
233 if (bd
->props
.brightness
== 0)
234 bd
->props
.brightness
= RADEON_MAX_BL_LEVEL
;
235 bd
->props
.power
= FB_BLANK_UNBLANK
;
236 backlight_update_status(bd
);
238 DRM_INFO("radeon atom DIG backlight initialized\n");
247 static void radeon_atom_backlight_exit(struct radeon_encoder
*radeon_encoder
)
249 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
250 struct radeon_device
*rdev
= dev
->dev_private
;
251 struct backlight_device
*bd
= NULL
;
252 struct radeon_encoder_atom_dig
*dig
;
254 if (!radeon_encoder
->enc_priv
)
257 if (!rdev
->is_atom_bios
)
260 if (!(rdev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
263 dig
= radeon_encoder
->enc_priv
;
268 struct radeon_legacy_backlight_privdata
*pdata
;
270 pdata
= bl_get_data(bd
);
271 backlight_device_unregister(bd
);
274 DRM_INFO("radeon atom LVDS backlight unloaded\n");
278 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
280 void radeon_atom_backlight_init(struct radeon_encoder
*encoder
)
284 static void radeon_atom_backlight_exit(struct radeon_encoder
*encoder
)
290 /* evil but including atombios.h is much worse */
291 bool radeon_atom_get_tv_timings(struct radeon_device
*rdev
, int index
,
292 struct drm_display_mode
*mode
);
295 static inline bool radeon_encoder_is_digital(struct drm_encoder
*encoder
)
297 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
298 switch (radeon_encoder
->encoder_id
) {
299 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
300 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
301 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
302 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
303 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
304 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
305 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
306 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
307 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
308 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
309 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
310 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
317 static bool radeon_atom_mode_fixup(struct drm_encoder
*encoder
,
318 const struct drm_display_mode
*mode
,
319 struct drm_display_mode
*adjusted_mode
)
321 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
322 struct drm_device
*dev
= encoder
->dev
;
323 struct radeon_device
*rdev
= dev
->dev_private
;
325 /* set the active encoder to connector routing */
326 radeon_encoder_set_active_device(encoder
);
327 drm_mode_set_crtcinfo(adjusted_mode
, 0);
330 if ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
331 && (mode
->crtc_vsync_start
< (mode
->crtc_vdisplay
+ 2)))
332 adjusted_mode
->crtc_vsync_start
= adjusted_mode
->crtc_vdisplay
+ 2;
334 /* get the native mode for LVDS */
335 if (radeon_encoder
->active_device
& (ATOM_DEVICE_LCD_SUPPORT
))
336 radeon_panel_mode_fixup(encoder
, adjusted_mode
);
338 /* get the native mode for TV */
339 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
)) {
340 struct radeon_encoder_atom_dac
*tv_dac
= radeon_encoder
->enc_priv
;
342 if (tv_dac
->tv_std
== TV_STD_NTSC
||
343 tv_dac
->tv_std
== TV_STD_NTSC_J
||
344 tv_dac
->tv_std
== TV_STD_PAL_M
)
345 radeon_atom_get_tv_timings(rdev
, 0, adjusted_mode
);
347 radeon_atom_get_tv_timings(rdev
, 1, adjusted_mode
);
351 if (ASIC_IS_DCE3(rdev
) &&
352 ((radeon_encoder
->active_device
& (ATOM_DEVICE_DFP_SUPPORT
| ATOM_DEVICE_LCD_SUPPORT
)) ||
353 (radeon_encoder_get_dp_bridge_encoder_id(encoder
) != ENCODER_OBJECT_ID_NONE
))) {
354 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
355 radeon_dp_set_link_config(connector
, adjusted_mode
);
362 atombios_dac_setup(struct drm_encoder
*encoder
, int action
)
364 struct drm_device
*dev
= encoder
->dev
;
365 struct radeon_device
*rdev
= dev
->dev_private
;
366 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
367 DAC_ENCODER_CONTROL_PS_ALLOCATION args
;
369 struct radeon_encoder_atom_dac
*dac_info
= radeon_encoder
->enc_priv
;
371 memset(&args
, 0, sizeof(args
));
373 switch (radeon_encoder
->encoder_id
) {
374 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
375 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
376 index
= GetIndexIntoMasterTable(COMMAND
, DAC1EncoderControl
);
378 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
379 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
380 index
= GetIndexIntoMasterTable(COMMAND
, DAC2EncoderControl
);
384 args
.ucAction
= action
;
386 if (radeon_encoder
->active_device
& (ATOM_DEVICE_CRT_SUPPORT
))
387 args
.ucDacStandard
= ATOM_DAC1_PS2
;
388 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
389 args
.ucDacStandard
= ATOM_DAC1_CV
;
391 switch (dac_info
->tv_std
) {
394 case TV_STD_SCART_PAL
:
397 args
.ucDacStandard
= ATOM_DAC1_PAL
;
403 args
.ucDacStandard
= ATOM_DAC1_NTSC
;
407 args
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
409 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
414 atombios_tv_setup(struct drm_encoder
*encoder
, int action
)
416 struct drm_device
*dev
= encoder
->dev
;
417 struct radeon_device
*rdev
= dev
->dev_private
;
418 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
419 TV_ENCODER_CONTROL_PS_ALLOCATION args
;
421 struct radeon_encoder_atom_dac
*dac_info
= radeon_encoder
->enc_priv
;
423 memset(&args
, 0, sizeof(args
));
425 index
= GetIndexIntoMasterTable(COMMAND
, TVEncoderControl
);
427 args
.sTVEncoder
.ucAction
= action
;
429 if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
430 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_CV
;
432 switch (dac_info
->tv_std
) {
434 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_NTSC
;
437 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PAL
;
440 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PALM
;
443 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PAL60
;
446 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_NTSCJ
;
448 case TV_STD_SCART_PAL
:
449 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PAL
; /* ??? */
452 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_SECAM
;
455 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PALCN
;
458 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_NTSC
;
463 args
.sTVEncoder
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
465 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
469 static u8
radeon_atom_get_bpc(struct drm_encoder
*encoder
)
474 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
475 bpc
= radeon_crtc
->bpc
;
480 return PANEL_BPC_UNDEFINE
;
482 return PANEL_6BIT_PER_COLOR
;
485 return PANEL_8BIT_PER_COLOR
;
487 return PANEL_10BIT_PER_COLOR
;
489 return PANEL_12BIT_PER_COLOR
;
491 return PANEL_16BIT_PER_COLOR
;
495 union dvo_encoder_control
{
496 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds
;
497 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo
;
498 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3
;
499 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4
;
503 atombios_dvo_setup(struct drm_encoder
*encoder
, int action
)
505 struct drm_device
*dev
= encoder
->dev
;
506 struct radeon_device
*rdev
= dev
->dev_private
;
507 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
508 union dvo_encoder_control args
;
509 int index
= GetIndexIntoMasterTable(COMMAND
, DVOEncoderControl
);
512 memset(&args
, 0, sizeof(args
));
514 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
517 /* some R4xx chips have the wrong frev */
518 if (rdev
->family
<= CHIP_RV410
)
526 args
.ext_tmds
.sXTmdsEncoder
.ucEnable
= action
;
528 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
529 args
.ext_tmds
.sXTmdsEncoder
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
531 args
.ext_tmds
.sXTmdsEncoder
.ucMisc
|= ATOM_PANEL_MISC_888RGB
;
535 args
.dvo
.sDVOEncoder
.ucAction
= action
;
536 args
.dvo
.sDVOEncoder
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
537 /* DFP1, CRT1, TV1 depending on the type of port */
538 args
.dvo
.sDVOEncoder
.ucDeviceType
= ATOM_DEVICE_DFP1_INDEX
;
540 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
541 args
.dvo
.sDVOEncoder
.usDevAttr
.sDigAttrib
.ucAttribute
|= PANEL_ENCODER_MISC_DUAL
;
545 args
.dvo_v3
.ucAction
= action
;
546 args
.dvo_v3
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
547 args
.dvo_v3
.ucDVOConfig
= 0; /* XXX */
551 args
.dvo_v4
.ucAction
= action
;
552 args
.dvo_v4
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
553 args
.dvo_v4
.ucDVOConfig
= 0; /* XXX */
554 args
.dvo_v4
.ucBitPerColor
= radeon_atom_get_bpc(encoder
);
557 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
562 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
566 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
569 union lvds_encoder_control
{
570 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1
;
571 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2
;
575 atombios_digital_setup(struct drm_encoder
*encoder
, int action
)
577 struct drm_device
*dev
= encoder
->dev
;
578 struct radeon_device
*rdev
= dev
->dev_private
;
579 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
580 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
581 union lvds_encoder_control args
;
583 int hdmi_detected
= 0;
589 if (atombios_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
)
592 memset(&args
, 0, sizeof(args
));
594 switch (radeon_encoder
->encoder_id
) {
595 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
596 index
= GetIndexIntoMasterTable(COMMAND
, LVDSEncoderControl
);
598 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
599 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
600 index
= GetIndexIntoMasterTable(COMMAND
, TMDS1EncoderControl
);
602 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
603 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
604 index
= GetIndexIntoMasterTable(COMMAND
, LVDSEncoderControl
);
606 index
= GetIndexIntoMasterTable(COMMAND
, TMDS2EncoderControl
);
610 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
619 args
.v1
.ucAction
= action
;
621 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_HDMI_TYPE
;
622 args
.v1
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
623 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
624 if (dig
->lcd_misc
& ATOM_PANEL_MISC_DUAL
)
625 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
626 if (dig
->lcd_misc
& ATOM_PANEL_MISC_888RGB
)
627 args
.v1
.ucMisc
|= ATOM_PANEL_MISC_888RGB
;
630 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_TMDS_LINKB
;
631 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
632 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
633 /*if (pScrn->rgbBits == 8) */
634 args
.v1
.ucMisc
|= ATOM_PANEL_MISC_888RGB
;
640 args
.v2
.ucAction
= action
;
642 if (dig
->coherent_mode
)
643 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_COHERENT
;
646 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_HDMI_TYPE
;
647 args
.v2
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
648 args
.v2
.ucTruncate
= 0;
649 args
.v2
.ucSpatial
= 0;
650 args
.v2
.ucTemporal
= 0;
652 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
653 if (dig
->lcd_misc
& ATOM_PANEL_MISC_DUAL
)
654 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
655 if (dig
->lcd_misc
& ATOM_PANEL_MISC_SPATIAL
) {
656 args
.v2
.ucSpatial
= PANEL_ENCODER_SPATIAL_DITHER_EN
;
657 if (dig
->lcd_misc
& ATOM_PANEL_MISC_888RGB
)
658 args
.v2
.ucSpatial
|= PANEL_ENCODER_SPATIAL_DITHER_DEPTH
;
660 if (dig
->lcd_misc
& ATOM_PANEL_MISC_TEMPORAL
) {
661 args
.v2
.ucTemporal
= PANEL_ENCODER_TEMPORAL_DITHER_EN
;
662 if (dig
->lcd_misc
& ATOM_PANEL_MISC_888RGB
)
663 args
.v2
.ucTemporal
|= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH
;
664 if (((dig
->lcd_misc
>> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT
) & 0x3) == 2)
665 args
.v2
.ucTemporal
|= PANEL_ENCODER_TEMPORAL_LEVEL_4
;
669 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_TMDS_LINKB
;
670 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
671 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
675 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
680 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
684 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
688 atombios_get_encoder_mode(struct drm_encoder
*encoder
)
690 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
691 struct drm_connector
*connector
;
692 struct radeon_connector
*radeon_connector
;
693 struct radeon_connector_atom_dig
*dig_connector
;
695 /* dp bridges are always DP */
696 if (radeon_encoder_get_dp_bridge_encoder_id(encoder
) != ENCODER_OBJECT_ID_NONE
)
697 return ATOM_ENCODER_MODE_DP
;
699 /* DVO is always DVO */
700 if ((radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DVO1
) ||
701 (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
))
702 return ATOM_ENCODER_MODE_DVO
;
704 connector
= radeon_get_connector_for_encoder(encoder
);
705 /* if we don't have an active device yet, just use one of
706 * the connectors tied to the encoder.
709 connector
= radeon_get_connector_for_encoder_init(encoder
);
710 radeon_connector
= to_radeon_connector(connector
);
712 switch (connector
->connector_type
) {
713 case DRM_MODE_CONNECTOR_DVII
:
714 case DRM_MODE_CONNECTOR_HDMIB
: /* HDMI-B is basically DL-DVI; analog works fine */
715 if (radeon_audio
!= 0) {
716 if (radeon_connector
->use_digital
&&
717 (radeon_connector
->audio
== RADEON_AUDIO_ENABLE
))
718 return ATOM_ENCODER_MODE_HDMI
;
719 else if (drm_detect_hdmi_monitor(radeon_connector
->edid
) &&
720 (radeon_connector
->audio
== RADEON_AUDIO_AUTO
))
721 return ATOM_ENCODER_MODE_HDMI
;
722 else if (radeon_connector
->use_digital
)
723 return ATOM_ENCODER_MODE_DVI
;
725 return ATOM_ENCODER_MODE_CRT
;
726 } else if (radeon_connector
->use_digital
) {
727 return ATOM_ENCODER_MODE_DVI
;
729 return ATOM_ENCODER_MODE_CRT
;
732 case DRM_MODE_CONNECTOR_DVID
:
733 case DRM_MODE_CONNECTOR_HDMIA
:
735 if (radeon_audio
!= 0) {
736 if (radeon_connector
->audio
== RADEON_AUDIO_ENABLE
)
737 return ATOM_ENCODER_MODE_HDMI
;
738 else if (drm_detect_hdmi_monitor(radeon_connector
->edid
) &&
739 (radeon_connector
->audio
== RADEON_AUDIO_AUTO
))
740 return ATOM_ENCODER_MODE_HDMI
;
742 return ATOM_ENCODER_MODE_DVI
;
744 return ATOM_ENCODER_MODE_DVI
;
747 case DRM_MODE_CONNECTOR_LVDS
:
748 return ATOM_ENCODER_MODE_LVDS
;
750 case DRM_MODE_CONNECTOR_DisplayPort
:
751 dig_connector
= radeon_connector
->con_priv
;
752 if ((dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_DISPLAYPORT
) ||
753 (dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_eDP
)) {
754 return ATOM_ENCODER_MODE_DP
;
755 } else if (radeon_audio
!= 0) {
756 if (radeon_connector
->audio
== RADEON_AUDIO_ENABLE
)
757 return ATOM_ENCODER_MODE_HDMI
;
758 else if (drm_detect_hdmi_monitor(radeon_connector
->edid
) &&
759 (radeon_connector
->audio
== RADEON_AUDIO_AUTO
))
760 return ATOM_ENCODER_MODE_HDMI
;
762 return ATOM_ENCODER_MODE_DVI
;
764 return ATOM_ENCODER_MODE_DVI
;
767 case DRM_MODE_CONNECTOR_eDP
:
768 return ATOM_ENCODER_MODE_DP
;
769 case DRM_MODE_CONNECTOR_DVIA
:
770 case DRM_MODE_CONNECTOR_VGA
:
771 return ATOM_ENCODER_MODE_CRT
;
773 case DRM_MODE_CONNECTOR_Composite
:
774 case DRM_MODE_CONNECTOR_SVIDEO
:
775 case DRM_MODE_CONNECTOR_9PinDIN
:
777 return ATOM_ENCODER_MODE_TV
;
778 /*return ATOM_ENCODER_MODE_CV;*/
784 * DIG Encoder/Transmitter Setup
787 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
788 * Supports up to 3 digital outputs
789 * - 2 DIG encoder blocks.
790 * DIG1 can drive UNIPHY link A or link B
791 * DIG2 can drive UNIPHY link B or LVTMA
794 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
795 * Supports up to 5 digital outputs
796 * - 2 DIG encoder blocks.
797 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
800 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
801 * Supports up to 6 digital outputs
802 * - 6 DIG encoder blocks.
803 * - DIG to PHY mapping is hardcoded
804 * DIG1 drives UNIPHY0 link A, A+B
805 * DIG2 drives UNIPHY0 link B
806 * DIG3 drives UNIPHY1 link A, A+B
807 * DIG4 drives UNIPHY1 link B
808 * DIG5 drives UNIPHY2 link A, A+B
809 * DIG6 drives UNIPHY2 link B
812 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
813 * Supports up to 6 digital outputs
814 * - 2 DIG encoder blocks.
816 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
818 * DIG1 drives UNIPHY0/1/2 link A
819 * DIG2 drives UNIPHY0/1/2 link B
822 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
824 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
825 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
826 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
827 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
830 union dig_encoder_control
{
831 DIG_ENCODER_CONTROL_PS_ALLOCATION v1
;
832 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2
;
833 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3
;
834 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4
;
838 atombios_dig_encoder_setup(struct drm_encoder
*encoder
, int action
, int panel_mode
)
840 struct drm_device
*dev
= encoder
->dev
;
841 struct radeon_device
*rdev
= dev
->dev_private
;
842 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
843 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
844 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
845 union dig_encoder_control args
;
849 int dp_lane_count
= 0;
850 int hpd_id
= RADEON_HPD_NONE
;
853 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
854 struct radeon_connector_atom_dig
*dig_connector
=
855 radeon_connector
->con_priv
;
857 dp_clock
= dig_connector
->dp_clock
;
858 dp_lane_count
= dig_connector
->dp_lane_count
;
859 hpd_id
= radeon_connector
->hpd
.hpd
;
862 /* no dig encoder assigned */
863 if (dig
->dig_encoder
== -1)
866 memset(&args
, 0, sizeof(args
));
868 if (ASIC_IS_DCE4(rdev
))
869 index
= GetIndexIntoMasterTable(COMMAND
, DIGxEncoderControl
);
871 if (dig
->dig_encoder
)
872 index
= GetIndexIntoMasterTable(COMMAND
, DIG2EncoderControl
);
874 index
= GetIndexIntoMasterTable(COMMAND
, DIG1EncoderControl
);
877 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
884 args
.v1
.ucAction
= action
;
885 args
.v1
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
886 if (action
== ATOM_ENCODER_CMD_SETUP_PANEL_MODE
)
887 args
.v3
.ucPanelMode
= panel_mode
;
889 args
.v1
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
891 if (ENCODER_MODE_IS_DP(args
.v1
.ucEncoderMode
))
892 args
.v1
.ucLaneNum
= dp_lane_count
;
893 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
894 args
.v1
.ucLaneNum
= 8;
896 args
.v1
.ucLaneNum
= 4;
898 if (ENCODER_MODE_IS_DP(args
.v1
.ucEncoderMode
) && (dp_clock
== 270000))
899 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ
;
900 switch (radeon_encoder
->encoder_id
) {
901 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
902 args
.v1
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER1
;
904 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
905 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
906 args
.v1
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER2
;
908 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
909 args
.v1
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER3
;
913 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_LINKB
;
915 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_LINKA
;
919 args
.v3
.ucAction
= action
;
920 args
.v3
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
921 if (action
== ATOM_ENCODER_CMD_SETUP_PANEL_MODE
)
922 args
.v3
.ucPanelMode
= panel_mode
;
924 args
.v3
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
926 if (ENCODER_MODE_IS_DP(args
.v3
.ucEncoderMode
))
927 args
.v3
.ucLaneNum
= dp_lane_count
;
928 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
929 args
.v3
.ucLaneNum
= 8;
931 args
.v3
.ucLaneNum
= 4;
933 if (ENCODER_MODE_IS_DP(args
.v3
.ucEncoderMode
) && (dp_clock
== 270000))
934 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ
;
935 args
.v3
.acConfig
.ucDigSel
= dig
->dig_encoder
;
936 args
.v3
.ucBitPerColor
= radeon_atom_get_bpc(encoder
);
939 args
.v4
.ucAction
= action
;
940 args
.v4
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
941 if (action
== ATOM_ENCODER_CMD_SETUP_PANEL_MODE
)
942 args
.v4
.ucPanelMode
= panel_mode
;
944 args
.v4
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
946 if (ENCODER_MODE_IS_DP(args
.v4
.ucEncoderMode
))
947 args
.v4
.ucLaneNum
= dp_lane_count
;
948 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
949 args
.v4
.ucLaneNum
= 8;
951 args
.v4
.ucLaneNum
= 4;
953 if (ENCODER_MODE_IS_DP(args
.v4
.ucEncoderMode
)) {
954 if (dp_clock
== 540000)
955 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ
;
956 else if (dp_clock
== 324000)
957 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ
;
958 else if (dp_clock
== 270000)
959 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ
;
961 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ
;
963 args
.v4
.acConfig
.ucDigSel
= dig
->dig_encoder
;
964 args
.v4
.ucBitPerColor
= radeon_atom_get_bpc(encoder
);
965 if (hpd_id
== RADEON_HPD_NONE
)
966 args
.v4
.ucHPD_ID
= 0;
968 args
.v4
.ucHPD_ID
= hpd_id
+ 1;
971 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
976 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
980 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
984 union dig_transmitter_control
{
985 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1
;
986 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2
;
987 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3
;
988 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4
;
989 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5
;
993 atombios_dig_transmitter_setup(struct drm_encoder
*encoder
, int action
, uint8_t lane_num
, uint8_t lane_set
)
995 struct drm_device
*dev
= encoder
->dev
;
996 struct radeon_device
*rdev
= dev
->dev_private
;
997 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
998 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
999 struct drm_connector
*connector
;
1000 union dig_transmitter_control args
;
1006 int dp_lane_count
= 0;
1007 int connector_object_id
= 0;
1008 int igp_lane_info
= 0;
1009 int dig_encoder
= dig
->dig_encoder
;
1010 int hpd_id
= RADEON_HPD_NONE
;
1012 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
1013 connector
= radeon_get_connector_for_encoder_init(encoder
);
1014 /* just needed to avoid bailing in the encoder check. the encoder
1015 * isn't used for init
1019 connector
= radeon_get_connector_for_encoder(encoder
);
1022 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
1023 struct radeon_connector_atom_dig
*dig_connector
=
1024 radeon_connector
->con_priv
;
1026 hpd_id
= radeon_connector
->hpd
.hpd
;
1027 dp_clock
= dig_connector
->dp_clock
;
1028 dp_lane_count
= dig_connector
->dp_lane_count
;
1029 connector_object_id
=
1030 (radeon_connector
->connector_object_id
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
1031 igp_lane_info
= dig_connector
->igp_lane_info
;
1034 if (encoder
->crtc
) {
1035 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1036 pll_id
= radeon_crtc
->pll_id
;
1039 /* no dig encoder assigned */
1040 if (dig_encoder
== -1)
1043 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder
)))
1046 memset(&args
, 0, sizeof(args
));
1048 switch (radeon_encoder
->encoder_id
) {
1049 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1050 index
= GetIndexIntoMasterTable(COMMAND
, DVOOutputControl
);
1052 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1053 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1054 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1055 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1056 index
= GetIndexIntoMasterTable(COMMAND
, UNIPHYTransmitterControl
);
1058 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1059 index
= GetIndexIntoMasterTable(COMMAND
, LVTMATransmitterControl
);
1063 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1070 args
.v1
.ucAction
= action
;
1071 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
1072 args
.v1
.usInitInfo
= cpu_to_le16(connector_object_id
);
1073 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
1074 args
.v1
.asMode
.ucLaneSel
= lane_num
;
1075 args
.v1
.asMode
.ucLaneSet
= lane_set
;
1078 args
.v1
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
1079 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1080 args
.v1
.usPixelClock
= cpu_to_le16((radeon_encoder
->pixel_clock
/ 2) / 10);
1082 args
.v1
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1085 args
.v1
.ucConfig
= ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL
;
1088 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER
;
1090 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER
;
1092 if ((rdev
->flags
& RADEON_IS_IGP
) &&
1093 (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_UNIPHY
)) {
1095 !radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
)) {
1096 if (igp_lane_info
& 0x1)
1097 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_0_3
;
1098 else if (igp_lane_info
& 0x2)
1099 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_4_7
;
1100 else if (igp_lane_info
& 0x4)
1101 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_8_11
;
1102 else if (igp_lane_info
& 0x8)
1103 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_12_15
;
1105 if (igp_lane_info
& 0x3)
1106 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_0_7
;
1107 else if (igp_lane_info
& 0xc)
1108 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_8_15
;
1113 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LINKB
;
1115 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LINKA
;
1118 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_COHERENT
;
1119 else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1120 if (dig
->coherent_mode
)
1121 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_COHERENT
;
1122 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1123 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_8LANE_LINK
;
1127 args
.v2
.ucAction
= action
;
1128 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
1129 args
.v2
.usInitInfo
= cpu_to_le16(connector_object_id
);
1130 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
1131 args
.v2
.asMode
.ucLaneSel
= lane_num
;
1132 args
.v2
.asMode
.ucLaneSet
= lane_set
;
1135 args
.v2
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
1136 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1137 args
.v2
.usPixelClock
= cpu_to_le16((radeon_encoder
->pixel_clock
/ 2) / 10);
1139 args
.v2
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1142 args
.v2
.acConfig
.ucEncoderSel
= dig_encoder
;
1144 args
.v2
.acConfig
.ucLinkSel
= 1;
1146 switch (radeon_encoder
->encoder_id
) {
1147 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1148 args
.v2
.acConfig
.ucTransmitterSel
= 0;
1150 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1151 args
.v2
.acConfig
.ucTransmitterSel
= 1;
1153 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1154 args
.v2
.acConfig
.ucTransmitterSel
= 2;
1159 args
.v2
.acConfig
.fCoherentMode
= 1;
1160 args
.v2
.acConfig
.fDPConnector
= 1;
1161 } else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1162 if (dig
->coherent_mode
)
1163 args
.v2
.acConfig
.fCoherentMode
= 1;
1164 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1165 args
.v2
.acConfig
.fDualLinkConnector
= 1;
1169 args
.v3
.ucAction
= action
;
1170 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
1171 args
.v3
.usInitInfo
= cpu_to_le16(connector_object_id
);
1172 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
1173 args
.v3
.asMode
.ucLaneSel
= lane_num
;
1174 args
.v3
.asMode
.ucLaneSet
= lane_set
;
1177 args
.v3
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
1178 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1179 args
.v3
.usPixelClock
= cpu_to_le16((radeon_encoder
->pixel_clock
/ 2) / 10);
1181 args
.v3
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1185 args
.v3
.ucLaneNum
= dp_lane_count
;
1186 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1187 args
.v3
.ucLaneNum
= 8;
1189 args
.v3
.ucLaneNum
= 4;
1192 args
.v3
.acConfig
.ucLinkSel
= 1;
1193 if (dig_encoder
& 1)
1194 args
.v3
.acConfig
.ucEncoderSel
= 1;
1196 /* Select the PLL for the PHY
1197 * DP PHY should be clocked from external src if there is
1200 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1201 if (is_dp
&& rdev
->clock
.dp_extclk
)
1202 args
.v3
.acConfig
.ucRefClkSource
= 2; /* external src */
1204 args
.v3
.acConfig
.ucRefClkSource
= pll_id
;
1206 switch (radeon_encoder
->encoder_id
) {
1207 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1208 args
.v3
.acConfig
.ucTransmitterSel
= 0;
1210 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1211 args
.v3
.acConfig
.ucTransmitterSel
= 1;
1213 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1214 args
.v3
.acConfig
.ucTransmitterSel
= 2;
1219 args
.v3
.acConfig
.fCoherentMode
= 1; /* DP requires coherent */
1220 else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1221 if (dig
->coherent_mode
)
1222 args
.v3
.acConfig
.fCoherentMode
= 1;
1223 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1224 args
.v3
.acConfig
.fDualLinkConnector
= 1;
1228 args
.v4
.ucAction
= action
;
1229 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
1230 args
.v4
.usInitInfo
= cpu_to_le16(connector_object_id
);
1231 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
1232 args
.v4
.asMode
.ucLaneSel
= lane_num
;
1233 args
.v4
.asMode
.ucLaneSet
= lane_set
;
1236 args
.v4
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
1237 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1238 args
.v4
.usPixelClock
= cpu_to_le16((radeon_encoder
->pixel_clock
/ 2) / 10);
1240 args
.v4
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1244 args
.v4
.ucLaneNum
= dp_lane_count
;
1245 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1246 args
.v4
.ucLaneNum
= 8;
1248 args
.v4
.ucLaneNum
= 4;
1251 args
.v4
.acConfig
.ucLinkSel
= 1;
1252 if (dig_encoder
& 1)
1253 args
.v4
.acConfig
.ucEncoderSel
= 1;
1255 /* Select the PLL for the PHY
1256 * DP PHY should be clocked from external src if there is
1259 /* On DCE5 DCPLL usually generates the DP ref clock */
1261 if (rdev
->clock
.dp_extclk
)
1262 args
.v4
.acConfig
.ucRefClkSource
= ENCODER_REFCLK_SRC_EXTCLK
;
1264 args
.v4
.acConfig
.ucRefClkSource
= ENCODER_REFCLK_SRC_DCPLL
;
1266 args
.v4
.acConfig
.ucRefClkSource
= pll_id
;
1268 switch (radeon_encoder
->encoder_id
) {
1269 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1270 args
.v4
.acConfig
.ucTransmitterSel
= 0;
1272 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1273 args
.v4
.acConfig
.ucTransmitterSel
= 1;
1275 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1276 args
.v4
.acConfig
.ucTransmitterSel
= 2;
1281 args
.v4
.acConfig
.fCoherentMode
= 1; /* DP requires coherent */
1282 else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1283 if (dig
->coherent_mode
)
1284 args
.v4
.acConfig
.fCoherentMode
= 1;
1285 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1286 args
.v4
.acConfig
.fDualLinkConnector
= 1;
1290 args
.v5
.ucAction
= action
;
1292 args
.v5
.usSymClock
= cpu_to_le16(dp_clock
/ 10);
1294 args
.v5
.usSymClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1296 switch (radeon_encoder
->encoder_id
) {
1297 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1299 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYB
;
1301 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYA
;
1303 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1305 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYD
;
1307 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYC
;
1309 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1311 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYF
;
1313 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYE
;
1315 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1316 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYG
;
1320 args
.v5
.ucLaneNum
= dp_lane_count
;
1321 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1322 args
.v5
.ucLaneNum
= 8;
1324 args
.v5
.ucLaneNum
= 4;
1325 args
.v5
.ucConnObjId
= connector_object_id
;
1326 args
.v5
.ucDigMode
= atombios_get_encoder_mode(encoder
);
1328 if (is_dp
&& rdev
->clock
.dp_extclk
)
1329 args
.v5
.asConfig
.ucPhyClkSrcId
= ENCODER_REFCLK_SRC_EXTCLK
;
1331 args
.v5
.asConfig
.ucPhyClkSrcId
= pll_id
;
1334 args
.v5
.asConfig
.ucCoherentMode
= 1; /* DP requires coherent */
1335 else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1336 if (dig
->coherent_mode
)
1337 args
.v5
.asConfig
.ucCoherentMode
= 1;
1339 if (hpd_id
== RADEON_HPD_NONE
)
1340 args
.v5
.asConfig
.ucHPDSel
= 0;
1342 args
.v5
.asConfig
.ucHPDSel
= hpd_id
+ 1;
1343 args
.v5
.ucDigEncoderSel
= 1 << dig_encoder
;
1344 args
.v5
.ucDPLaneSet
= lane_set
;
1347 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
1352 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
1356 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1360 atombios_set_edp_panel_power(struct drm_connector
*connector
, int action
)
1362 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
1363 struct drm_device
*dev
= radeon_connector
->base
.dev
;
1364 struct radeon_device
*rdev
= dev
->dev_private
;
1365 union dig_transmitter_control args
;
1366 int index
= GetIndexIntoMasterTable(COMMAND
, UNIPHYTransmitterControl
);
1369 if (connector
->connector_type
!= DRM_MODE_CONNECTOR_eDP
)
1372 if (!ASIC_IS_DCE4(rdev
))
1375 if ((action
!= ATOM_TRANSMITTER_ACTION_POWER_ON
) &&
1376 (action
!= ATOM_TRANSMITTER_ACTION_POWER_OFF
))
1379 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1382 memset(&args
, 0, sizeof(args
));
1384 args
.v1
.ucAction
= action
;
1386 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1388 /* wait for the panel to power up */
1389 if (action
== ATOM_TRANSMITTER_ACTION_POWER_ON
) {
1392 for (i
= 0; i
< 300; i
++) {
1393 if (radeon_hpd_sense(rdev
, radeon_connector
->hpd
.hpd
))
1403 union external_encoder_control
{
1404 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1
;
1405 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3
;
1409 atombios_external_encoder_setup(struct drm_encoder
*encoder
,
1410 struct drm_encoder
*ext_encoder
,
1413 struct drm_device
*dev
= encoder
->dev
;
1414 struct radeon_device
*rdev
= dev
->dev_private
;
1415 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1416 struct radeon_encoder
*ext_radeon_encoder
= to_radeon_encoder(ext_encoder
);
1417 union external_encoder_control args
;
1418 struct drm_connector
*connector
;
1419 int index
= GetIndexIntoMasterTable(COMMAND
, ExternalEncoderControl
);
1422 int dp_lane_count
= 0;
1423 int connector_object_id
= 0;
1424 u32 ext_enum
= (ext_radeon_encoder
->encoder_enum
& ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
1426 if (action
== EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT
)
1427 connector
= radeon_get_connector_for_encoder_init(encoder
);
1429 connector
= radeon_get_connector_for_encoder(encoder
);
1432 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
1433 struct radeon_connector_atom_dig
*dig_connector
=
1434 radeon_connector
->con_priv
;
1436 dp_clock
= dig_connector
->dp_clock
;
1437 dp_lane_count
= dig_connector
->dp_lane_count
;
1438 connector_object_id
=
1439 (radeon_connector
->connector_object_id
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
1442 memset(&args
, 0, sizeof(args
));
1444 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1449 /* no params on frev 1 */
1455 args
.v1
.sDigEncoder
.ucAction
= action
;
1456 args
.v1
.sDigEncoder
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1457 args
.v1
.sDigEncoder
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
1459 if (ENCODER_MODE_IS_DP(args
.v1
.sDigEncoder
.ucEncoderMode
)) {
1460 if (dp_clock
== 270000)
1461 args
.v1
.sDigEncoder
.ucConfig
|= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ
;
1462 args
.v1
.sDigEncoder
.ucLaneNum
= dp_lane_count
;
1463 } else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1464 args
.v1
.sDigEncoder
.ucLaneNum
= 8;
1466 args
.v1
.sDigEncoder
.ucLaneNum
= 4;
1469 args
.v3
.sExtEncoder
.ucAction
= action
;
1470 if (action
== EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT
)
1471 args
.v3
.sExtEncoder
.usConnectorId
= cpu_to_le16(connector_object_id
);
1473 args
.v3
.sExtEncoder
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1474 args
.v3
.sExtEncoder
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
1476 if (ENCODER_MODE_IS_DP(args
.v3
.sExtEncoder
.ucEncoderMode
)) {
1477 if (dp_clock
== 270000)
1478 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ
;
1479 else if (dp_clock
== 540000)
1480 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ
;
1481 args
.v3
.sExtEncoder
.ucLaneNum
= dp_lane_count
;
1482 } else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1483 args
.v3
.sExtEncoder
.ucLaneNum
= 8;
1485 args
.v3
.sExtEncoder
.ucLaneNum
= 4;
1487 case GRAPH_OBJECT_ENUM_ID1
:
1488 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1
;
1490 case GRAPH_OBJECT_ENUM_ID2
:
1491 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2
;
1493 case GRAPH_OBJECT_ENUM_ID3
:
1494 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3
;
1497 args
.v3
.sExtEncoder
.ucBitPerColor
= radeon_atom_get_bpc(encoder
);
1500 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1505 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1508 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1512 atombios_yuv_setup(struct drm_encoder
*encoder
, bool enable
)
1514 struct drm_device
*dev
= encoder
->dev
;
1515 struct radeon_device
*rdev
= dev
->dev_private
;
1516 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1517 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1518 ENABLE_YUV_PS_ALLOCATION args
;
1519 int index
= GetIndexIntoMasterTable(COMMAND
, EnableYUV
);
1522 memset(&args
, 0, sizeof(args
));
1524 if (rdev
->family
>= CHIP_R600
)
1525 reg
= R600_BIOS_3_SCRATCH
;
1527 reg
= RADEON_BIOS_3_SCRATCH
;
1529 /* XXX: fix up scratch reg handling */
1531 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1532 WREG32(reg
, (ATOM_S3_TV1_ACTIVE
|
1533 (radeon_crtc
->crtc_id
<< 18)));
1534 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1535 WREG32(reg
, (ATOM_S3_CV_ACTIVE
| (radeon_crtc
->crtc_id
<< 24)));
1540 args
.ucEnable
= ATOM_ENABLE
;
1541 args
.ucCRTC
= radeon_crtc
->crtc_id
;
1543 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1549 radeon_atom_encoder_dpms_avivo(struct drm_encoder
*encoder
, int mode
)
1551 struct drm_device
*dev
= encoder
->dev
;
1552 struct radeon_device
*rdev
= dev
->dev_private
;
1553 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1554 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args
;
1557 memset(&args
, 0, sizeof(args
));
1559 switch (radeon_encoder
->encoder_id
) {
1560 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
1561 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
1562 index
= GetIndexIntoMasterTable(COMMAND
, TMDSAOutputControl
);
1564 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
1565 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
1566 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1567 index
= GetIndexIntoMasterTable(COMMAND
, DVOOutputControl
);
1569 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
1570 index
= GetIndexIntoMasterTable(COMMAND
, LCD1OutputControl
);
1572 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
1573 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
1574 index
= GetIndexIntoMasterTable(COMMAND
, LCD1OutputControl
);
1576 index
= GetIndexIntoMasterTable(COMMAND
, LVTMAOutputControl
);
1578 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
1579 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1580 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1581 index
= GetIndexIntoMasterTable(COMMAND
, TV1OutputControl
);
1582 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1583 index
= GetIndexIntoMasterTable(COMMAND
, CV1OutputControl
);
1585 index
= GetIndexIntoMasterTable(COMMAND
, DAC1OutputControl
);
1587 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
1588 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1589 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1590 index
= GetIndexIntoMasterTable(COMMAND
, TV1OutputControl
);
1591 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1592 index
= GetIndexIntoMasterTable(COMMAND
, CV1OutputControl
);
1594 index
= GetIndexIntoMasterTable(COMMAND
, DAC2OutputControl
);
1601 case DRM_MODE_DPMS_ON
:
1602 args
.ucAction
= ATOM_ENABLE
;
1603 /* workaround for DVOOutputControl on some RS690 systems */
1604 if (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DDI
) {
1605 u32 reg
= RREG32(RADEON_BIOS_3_SCRATCH
);
1606 WREG32(RADEON_BIOS_3_SCRATCH
, reg
& ~ATOM_S3_DFP2I_ACTIVE
);
1607 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1608 WREG32(RADEON_BIOS_3_SCRATCH
, reg
);
1610 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1611 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1612 args
.ucAction
= ATOM_LCD_BLON
;
1613 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1616 case DRM_MODE_DPMS_STANDBY
:
1617 case DRM_MODE_DPMS_SUSPEND
:
1618 case DRM_MODE_DPMS_OFF
:
1619 args
.ucAction
= ATOM_DISABLE
;
1620 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1621 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1622 args
.ucAction
= ATOM_LCD_BLOFF
;
1623 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1630 radeon_atom_encoder_dpms_dig(struct drm_encoder
*encoder
, int mode
)
1632 struct drm_device
*dev
= encoder
->dev
;
1633 struct radeon_device
*rdev
= dev
->dev_private
;
1634 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1635 struct drm_encoder
*ext_encoder
= radeon_get_external_encoder(encoder
);
1636 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
1637 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
1638 struct radeon_connector
*radeon_connector
= NULL
;
1639 struct radeon_connector_atom_dig
*radeon_dig_connector
= NULL
;
1640 bool travis_quirk
= false;
1643 radeon_connector
= to_radeon_connector(connector
);
1644 radeon_dig_connector
= radeon_connector
->con_priv
;
1645 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector
) ==
1646 ENCODER_OBJECT_ID_TRAVIS
) &&
1647 (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) &&
1648 !ASIC_IS_DCE5(rdev
))
1649 travis_quirk
= true;
1653 case DRM_MODE_DPMS_ON
:
1654 if (ASIC_IS_DCE41(rdev
) || ASIC_IS_DCE5(rdev
)) {
1656 dig
->panel_mode
= DP_PANEL_MODE_EXTERNAL_DP_MODE
;
1658 dig
->panel_mode
= radeon_dp_get_panel_mode(encoder
, connector
);
1660 /* setup and enable the encoder */
1661 atombios_dig_encoder_setup(encoder
, ATOM_ENCODER_CMD_SETUP
, 0);
1662 atombios_dig_encoder_setup(encoder
,
1663 ATOM_ENCODER_CMD_SETUP_PANEL_MODE
,
1666 if (ASIC_IS_DCE41(rdev
) || ASIC_IS_DCE61(rdev
))
1667 atombios_external_encoder_setup(encoder
, ext_encoder
,
1668 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP
);
1670 } else if (ASIC_IS_DCE4(rdev
)) {
1671 /* setup and enable the encoder */
1672 atombios_dig_encoder_setup(encoder
, ATOM_ENCODER_CMD_SETUP
, 0);
1674 /* setup and enable the encoder and transmitter */
1675 atombios_dig_encoder_setup(encoder
, ATOM_ENABLE
, 0);
1676 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_SETUP
, 0, 0);
1678 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder
)) && connector
) {
1679 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
) {
1680 atombios_set_edp_panel_power(connector
,
1681 ATOM_TRANSMITTER_ACTION_POWER_ON
);
1682 radeon_dig_connector
->edp_on
= true;
1685 /* enable the transmitter */
1686 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_ENABLE
, 0, 0);
1687 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder
)) && connector
) {
1688 /* DP_SET_POWER_D0 is set in radeon_dp_link_train */
1689 radeon_dp_link_train(encoder
, connector
);
1690 if (ASIC_IS_DCE4(rdev
))
1691 atombios_dig_encoder_setup(encoder
, ATOM_ENCODER_CMD_DP_VIDEO_ON
, 0);
1693 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
1694 atombios_dig_transmitter_setup(encoder
,
1695 ATOM_TRANSMITTER_ACTION_LCD_BLON
, 0, 0);
1697 atombios_external_encoder_setup(encoder
, ext_encoder
, ATOM_ENABLE
);
1699 case DRM_MODE_DPMS_STANDBY
:
1700 case DRM_MODE_DPMS_SUSPEND
:
1701 case DRM_MODE_DPMS_OFF
:
1702 if (ASIC_IS_DCE4(rdev
)) {
1703 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder
)) && connector
)
1704 atombios_dig_encoder_setup(encoder
, ATOM_ENCODER_CMD_DP_VIDEO_OFF
, 0);
1707 atombios_external_encoder_setup(encoder
, ext_encoder
, ATOM_DISABLE
);
1708 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
1709 atombios_dig_transmitter_setup(encoder
,
1710 ATOM_TRANSMITTER_ACTION_LCD_BLOFF
, 0, 0);
1712 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder
)) &&
1713 connector
&& !travis_quirk
)
1714 radeon_dp_set_rx_power_state(connector
, DP_SET_POWER_D3
);
1715 if (ASIC_IS_DCE4(rdev
)) {
1716 /* disable the transmitter */
1717 atombios_dig_transmitter_setup(encoder
,
1718 ATOM_TRANSMITTER_ACTION_DISABLE
, 0, 0);
1720 /* disable the encoder and transmitter */
1721 atombios_dig_transmitter_setup(encoder
,
1722 ATOM_TRANSMITTER_ACTION_DISABLE
, 0, 0);
1723 atombios_dig_encoder_setup(encoder
, ATOM_DISABLE
, 0);
1725 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder
)) && connector
) {
1727 radeon_dp_set_rx_power_state(connector
, DP_SET_POWER_D3
);
1728 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
) {
1729 atombios_set_edp_panel_power(connector
,
1730 ATOM_TRANSMITTER_ACTION_POWER_OFF
);
1731 radeon_dig_connector
->edp_on
= false;
1739 radeon_atom_encoder_dpms(struct drm_encoder
*encoder
, int mode
)
1741 struct drm_device
*dev
= encoder
->dev
;
1742 struct radeon_device
*rdev
= dev
->dev_private
;
1743 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1745 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1746 radeon_encoder
->encoder_id
, mode
, radeon_encoder
->devices
,
1747 radeon_encoder
->active_device
);
1748 switch (radeon_encoder
->encoder_id
) {
1749 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
1750 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
1751 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
1752 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
1753 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
1754 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
1755 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
1756 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1757 radeon_atom_encoder_dpms_avivo(encoder
, mode
);
1759 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1760 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1761 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1762 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1763 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1764 radeon_atom_encoder_dpms_dig(encoder
, mode
);
1766 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1767 if (ASIC_IS_DCE5(rdev
)) {
1769 case DRM_MODE_DPMS_ON
:
1770 atombios_dvo_setup(encoder
, ATOM_ENABLE
);
1772 case DRM_MODE_DPMS_STANDBY
:
1773 case DRM_MODE_DPMS_SUSPEND
:
1774 case DRM_MODE_DPMS_OFF
:
1775 atombios_dvo_setup(encoder
, ATOM_DISABLE
);
1778 } else if (ASIC_IS_DCE3(rdev
))
1779 radeon_atom_encoder_dpms_dig(encoder
, mode
);
1781 radeon_atom_encoder_dpms_avivo(encoder
, mode
);
1783 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
1784 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1785 if (ASIC_IS_DCE5(rdev
)) {
1787 case DRM_MODE_DPMS_ON
:
1788 atombios_dac_setup(encoder
, ATOM_ENABLE
);
1790 case DRM_MODE_DPMS_STANDBY
:
1791 case DRM_MODE_DPMS_SUSPEND
:
1792 case DRM_MODE_DPMS_OFF
:
1793 atombios_dac_setup(encoder
, ATOM_DISABLE
);
1797 radeon_atom_encoder_dpms_avivo(encoder
, mode
);
1803 radeon_atombios_encoder_dpms_scratch_regs(encoder
, (mode
== DRM_MODE_DPMS_ON
) ? true : false);
1807 union crtc_source_param
{
1808 SELECT_CRTC_SOURCE_PS_ALLOCATION v1
;
1809 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2
;
1813 atombios_set_encoder_crtc_source(struct drm_encoder
*encoder
)
1815 struct drm_device
*dev
= encoder
->dev
;
1816 struct radeon_device
*rdev
= dev
->dev_private
;
1817 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1818 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1819 union crtc_source_param args
;
1820 int index
= GetIndexIntoMasterTable(COMMAND
, SelectCRTC_Source
);
1822 struct radeon_encoder_atom_dig
*dig
;
1824 memset(&args
, 0, sizeof(args
));
1826 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1834 if (ASIC_IS_AVIVO(rdev
))
1835 args
.v1
.ucCRTC
= radeon_crtc
->crtc_id
;
1837 if (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DAC1
) {
1838 args
.v1
.ucCRTC
= radeon_crtc
->crtc_id
;
1840 args
.v1
.ucCRTC
= radeon_crtc
->crtc_id
<< 2;
1843 switch (radeon_encoder
->encoder_id
) {
1844 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
1845 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
1846 args
.v1
.ucDevice
= ATOM_DEVICE_DFP1_INDEX
;
1848 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
1849 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
1850 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)
1851 args
.v1
.ucDevice
= ATOM_DEVICE_LCD1_INDEX
;
1853 args
.v1
.ucDevice
= ATOM_DEVICE_DFP3_INDEX
;
1855 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
1856 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
1857 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1858 args
.v1
.ucDevice
= ATOM_DEVICE_DFP2_INDEX
;
1860 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
1861 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1862 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1863 args
.v1
.ucDevice
= ATOM_DEVICE_TV1_INDEX
;
1864 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1865 args
.v1
.ucDevice
= ATOM_DEVICE_CV_INDEX
;
1867 args
.v1
.ucDevice
= ATOM_DEVICE_CRT1_INDEX
;
1869 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
1870 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1871 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1872 args
.v1
.ucDevice
= ATOM_DEVICE_TV1_INDEX
;
1873 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1874 args
.v1
.ucDevice
= ATOM_DEVICE_CV_INDEX
;
1876 args
.v1
.ucDevice
= ATOM_DEVICE_CRT2_INDEX
;
1881 args
.v2
.ucCRTC
= radeon_crtc
->crtc_id
;
1882 if (radeon_encoder_get_dp_bridge_encoder_id(encoder
) != ENCODER_OBJECT_ID_NONE
) {
1883 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
1885 if (connector
->connector_type
== DRM_MODE_CONNECTOR_LVDS
)
1886 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_LVDS
;
1887 else if (connector
->connector_type
== DRM_MODE_CONNECTOR_VGA
)
1888 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_CRT
;
1890 args
.v2
.ucEncodeMode
= atombios_get_encoder_mode(encoder
);
1891 } else if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1892 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_LVDS
;
1894 args
.v2
.ucEncodeMode
= atombios_get_encoder_mode(encoder
);
1896 switch (radeon_encoder
->encoder_id
) {
1897 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1898 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1899 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1900 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1901 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1902 dig
= radeon_encoder
->enc_priv
;
1903 switch (dig
->dig_encoder
) {
1905 args
.v2
.ucEncoderID
= ASIC_INT_DIG1_ENCODER_ID
;
1908 args
.v2
.ucEncoderID
= ASIC_INT_DIG2_ENCODER_ID
;
1911 args
.v2
.ucEncoderID
= ASIC_INT_DIG3_ENCODER_ID
;
1914 args
.v2
.ucEncoderID
= ASIC_INT_DIG4_ENCODER_ID
;
1917 args
.v2
.ucEncoderID
= ASIC_INT_DIG5_ENCODER_ID
;
1920 args
.v2
.ucEncoderID
= ASIC_INT_DIG6_ENCODER_ID
;
1923 args
.v2
.ucEncoderID
= ASIC_INT_DIG7_ENCODER_ID
;
1927 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1928 args
.v2
.ucEncoderID
= ASIC_INT_DVO_ENCODER_ID
;
1930 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1931 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1932 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1933 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1934 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1936 args
.v2
.ucEncoderID
= ASIC_INT_DAC1_ENCODER_ID
;
1938 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1939 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1940 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1941 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1942 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1944 args
.v2
.ucEncoderID
= ASIC_INT_DAC2_ENCODER_ID
;
1951 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1955 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1957 /* update scratch regs with new routing */
1958 radeon_atombios_encoder_crtc_scratch_regs(encoder
, radeon_crtc
->crtc_id
);
1962 atombios_apply_encoder_quirks(struct drm_encoder
*encoder
,
1963 struct drm_display_mode
*mode
)
1965 struct drm_device
*dev
= encoder
->dev
;
1966 struct radeon_device
*rdev
= dev
->dev_private
;
1967 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1968 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1970 /* Funky macbooks */
1971 if ((dev
->pdev
->device
== 0x71C5) &&
1972 (dev
->pdev
->subsystem_vendor
== 0x106b) &&
1973 (dev
->pdev
->subsystem_device
== 0x0080)) {
1974 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
1975 uint32_t lvtma_bit_depth_control
= RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL
);
1977 lvtma_bit_depth_control
&= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN
;
1978 lvtma_bit_depth_control
&= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN
;
1980 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL
, lvtma_bit_depth_control
);
1984 /* set scaler clears this on some chips */
1985 if (ASIC_IS_AVIVO(rdev
) &&
1986 (!(radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
)))) {
1987 if (ASIC_IS_DCE8(rdev
)) {
1988 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1989 WREG32(CIK_LB_DATA_FORMAT
+ radeon_crtc
->crtc_offset
,
1992 WREG32(CIK_LB_DATA_FORMAT
+ radeon_crtc
->crtc_offset
, 0);
1993 } else if (ASIC_IS_DCE4(rdev
)) {
1994 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1995 WREG32(EVERGREEN_DATA_FORMAT
+ radeon_crtc
->crtc_offset
,
1996 EVERGREEN_INTERLEAVE_EN
);
1998 WREG32(EVERGREEN_DATA_FORMAT
+ radeon_crtc
->crtc_offset
, 0);
2000 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
2001 WREG32(AVIVO_D1MODE_DATA_FORMAT
+ radeon_crtc
->crtc_offset
,
2002 AVIVO_D1MODE_INTERLEAVE_EN
);
2004 WREG32(AVIVO_D1MODE_DATA_FORMAT
+ radeon_crtc
->crtc_offset
, 0);
2009 static int radeon_atom_pick_dig_encoder(struct drm_encoder
*encoder
)
2011 struct drm_device
*dev
= encoder
->dev
;
2012 struct radeon_device
*rdev
= dev
->dev_private
;
2013 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
2014 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2015 struct drm_encoder
*test_encoder
;
2016 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
2017 uint32_t dig_enc_in_use
= 0;
2019 if (ASIC_IS_DCE6(rdev
)) {
2021 switch (radeon_encoder
->encoder_id
) {
2022 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2028 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2034 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2040 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2044 } else if (ASIC_IS_DCE4(rdev
)) {
2046 if (ASIC_IS_DCE41(rdev
) && !ASIC_IS_DCE61(rdev
)) {
2047 /* ontario follows DCE4 */
2048 if (rdev
->family
== CHIP_PALM
) {
2054 /* llano follows DCE3.2 */
2055 return radeon_crtc
->crtc_id
;
2057 switch (radeon_encoder
->encoder_id
) {
2058 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2064 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2070 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2080 /* on DCE32 and encoder can driver any block so just crtc id */
2081 if (ASIC_IS_DCE32(rdev
)) {
2082 return radeon_crtc
->crtc_id
;
2085 /* on DCE3 - LVTMA can only be driven by DIGB */
2086 list_for_each_entry(test_encoder
, &dev
->mode_config
.encoder_list
, head
) {
2087 struct radeon_encoder
*radeon_test_encoder
;
2089 if (encoder
== test_encoder
)
2092 if (!radeon_encoder_is_digital(test_encoder
))
2095 radeon_test_encoder
= to_radeon_encoder(test_encoder
);
2096 dig
= radeon_test_encoder
->enc_priv
;
2098 if (dig
->dig_encoder
>= 0)
2099 dig_enc_in_use
|= (1 << dig
->dig_encoder
);
2102 if (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
) {
2103 if (dig_enc_in_use
& 0x2)
2104 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2107 if (!(dig_enc_in_use
& 1))
2112 /* This only needs to be called once at startup */
2114 radeon_atom_encoder_init(struct radeon_device
*rdev
)
2116 struct drm_device
*dev
= rdev
->ddev
;
2117 struct drm_encoder
*encoder
;
2119 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
2120 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2121 struct drm_encoder
*ext_encoder
= radeon_get_external_encoder(encoder
);
2123 switch (radeon_encoder
->encoder_id
) {
2124 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2125 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2126 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2127 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2128 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
2129 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_INIT
, 0, 0);
2135 if (ext_encoder
&& (ASIC_IS_DCE41(rdev
) || ASIC_IS_DCE61(rdev
)))
2136 atombios_external_encoder_setup(encoder
, ext_encoder
,
2137 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT
);
2142 radeon_atom_encoder_mode_set(struct drm_encoder
*encoder
,
2143 struct drm_display_mode
*mode
,
2144 struct drm_display_mode
*adjusted_mode
)
2146 struct drm_device
*dev
= encoder
->dev
;
2147 struct radeon_device
*rdev
= dev
->dev_private
;
2148 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2150 radeon_encoder
->pixel_clock
= adjusted_mode
->clock
;
2152 /* need to call this here rather than in prepare() since we need some crtc info */
2153 radeon_atom_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
2155 if (ASIC_IS_AVIVO(rdev
) && !ASIC_IS_DCE4(rdev
)) {
2156 if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
| ATOM_DEVICE_TV_SUPPORT
))
2157 atombios_yuv_setup(encoder
, true);
2159 atombios_yuv_setup(encoder
, false);
2162 switch (radeon_encoder
->encoder_id
) {
2163 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
2164 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
2165 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
2166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
2167 atombios_digital_setup(encoder
, PANEL_ENCODER_ACTION_ENABLE
);
2169 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2171 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2173 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
2174 /* handled in dpms */
2176 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
2177 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
2178 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
2179 atombios_dvo_setup(encoder
, ATOM_ENABLE
);
2181 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
2182 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
2183 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
2184 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
2185 atombios_dac_setup(encoder
, ATOM_ENABLE
);
2186 if (radeon_encoder
->devices
& (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
)) {
2187 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
))
2188 atombios_tv_setup(encoder
, ATOM_ENABLE
);
2190 atombios_tv_setup(encoder
, ATOM_DISABLE
);
2195 atombios_apply_encoder_quirks(encoder
, adjusted_mode
);
2197 if (atombios_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
) {
2198 if (rdev
->asic
->display
.hdmi_enable
)
2199 radeon_hdmi_enable(rdev
, encoder
, true);
2200 if (rdev
->asic
->display
.hdmi_setmode
)
2201 radeon_hdmi_setmode(rdev
, encoder
, adjusted_mode
);
2206 atombios_dac_load_detect(struct drm_encoder
*encoder
, struct drm_connector
*connector
)
2208 struct drm_device
*dev
= encoder
->dev
;
2209 struct radeon_device
*rdev
= dev
->dev_private
;
2210 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2211 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
2213 if (radeon_encoder
->devices
& (ATOM_DEVICE_TV_SUPPORT
|
2214 ATOM_DEVICE_CV_SUPPORT
|
2215 ATOM_DEVICE_CRT_SUPPORT
)) {
2216 DAC_LOAD_DETECTION_PS_ALLOCATION args
;
2217 int index
= GetIndexIntoMasterTable(COMMAND
, DAC_LoadDetection
);
2220 memset(&args
, 0, sizeof(args
));
2222 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
2225 args
.sDacload
.ucMisc
= 0;
2227 if ((radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DAC1
) ||
2228 (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
))
2229 args
.sDacload
.ucDacType
= ATOM_DAC_A
;
2231 args
.sDacload
.ucDacType
= ATOM_DAC_B
;
2233 if (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)
2234 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT
);
2235 else if (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)
2236 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT
);
2237 else if (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
2238 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CV_SUPPORT
);
2240 args
.sDacload
.ucMisc
= DAC_LOAD_MISC_YPrPb
;
2241 } else if (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
2242 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT
);
2244 args
.sDacload
.ucMisc
= DAC_LOAD_MISC_YPrPb
;
2247 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2254 static enum drm_connector_status
2255 radeon_atom_dac_detect(struct drm_encoder
*encoder
, struct drm_connector
*connector
)
2257 struct drm_device
*dev
= encoder
->dev
;
2258 struct radeon_device
*rdev
= dev
->dev_private
;
2259 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2260 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
2261 uint32_t bios_0_scratch
;
2263 if (!atombios_dac_load_detect(encoder
, connector
)) {
2264 DRM_DEBUG_KMS("detect returned false \n");
2265 return connector_status_unknown
;
2268 if (rdev
->family
>= CHIP_R600
)
2269 bios_0_scratch
= RREG32(R600_BIOS_0_SCRATCH
);
2271 bios_0_scratch
= RREG32(RADEON_BIOS_0_SCRATCH
);
2273 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch
, radeon_encoder
->devices
);
2274 if (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
2275 if (bios_0_scratch
& ATOM_S0_CRT1_MASK
)
2276 return connector_status_connected
;
2278 if (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
2279 if (bios_0_scratch
& ATOM_S0_CRT2_MASK
)
2280 return connector_status_connected
;
2282 if (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
2283 if (bios_0_scratch
& (ATOM_S0_CV_MASK
|ATOM_S0_CV_MASK_A
))
2284 return connector_status_connected
;
2286 if (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
2287 if (bios_0_scratch
& (ATOM_S0_TV1_COMPOSITE
| ATOM_S0_TV1_COMPOSITE_A
))
2288 return connector_status_connected
; /* CTV */
2289 else if (bios_0_scratch
& (ATOM_S0_TV1_SVIDEO
| ATOM_S0_TV1_SVIDEO_A
))
2290 return connector_status_connected
; /* STV */
2292 return connector_status_disconnected
;
2295 static enum drm_connector_status
2296 radeon_atom_dig_detect(struct drm_encoder
*encoder
, struct drm_connector
*connector
)
2298 struct drm_device
*dev
= encoder
->dev
;
2299 struct radeon_device
*rdev
= dev
->dev_private
;
2300 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2301 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
2302 struct drm_encoder
*ext_encoder
= radeon_get_external_encoder(encoder
);
2305 if (!ASIC_IS_DCE4(rdev
))
2306 return connector_status_unknown
;
2309 return connector_status_unknown
;
2311 if ((radeon_connector
->devices
& ATOM_DEVICE_CRT_SUPPORT
) == 0)
2312 return connector_status_unknown
;
2314 /* load detect on the dp bridge */
2315 atombios_external_encoder_setup(encoder
, ext_encoder
,
2316 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION
);
2318 bios_0_scratch
= RREG32(R600_BIOS_0_SCRATCH
);
2320 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch
, radeon_encoder
->devices
);
2321 if (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
2322 if (bios_0_scratch
& ATOM_S0_CRT1_MASK
)
2323 return connector_status_connected
;
2325 if (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
2326 if (bios_0_scratch
& ATOM_S0_CRT2_MASK
)
2327 return connector_status_connected
;
2329 if (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
2330 if (bios_0_scratch
& (ATOM_S0_CV_MASK
|ATOM_S0_CV_MASK_A
))
2331 return connector_status_connected
;
2333 if (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
2334 if (bios_0_scratch
& (ATOM_S0_TV1_COMPOSITE
| ATOM_S0_TV1_COMPOSITE_A
))
2335 return connector_status_connected
; /* CTV */
2336 else if (bios_0_scratch
& (ATOM_S0_TV1_SVIDEO
| ATOM_S0_TV1_SVIDEO_A
))
2337 return connector_status_connected
; /* STV */
2339 return connector_status_disconnected
;
2343 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder
*encoder
)
2345 struct drm_encoder
*ext_encoder
= radeon_get_external_encoder(encoder
);
2348 /* ddc_setup on the dp bridge */
2349 atombios_external_encoder_setup(encoder
, ext_encoder
,
2350 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP
);
2354 static void radeon_atom_encoder_prepare(struct drm_encoder
*encoder
)
2356 struct radeon_device
*rdev
= encoder
->dev
->dev_private
;
2357 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2358 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
2360 if ((radeon_encoder
->active_device
&
2361 (ATOM_DEVICE_DFP_SUPPORT
| ATOM_DEVICE_LCD_SUPPORT
)) ||
2362 (radeon_encoder_get_dp_bridge_encoder_id(encoder
) !=
2363 ENCODER_OBJECT_ID_NONE
)) {
2364 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
2366 dig
->dig_encoder
= radeon_atom_pick_dig_encoder(encoder
);
2367 if (radeon_encoder
->active_device
& ATOM_DEVICE_DFP_SUPPORT
) {
2368 if (rdev
->family
>= CHIP_R600
)
2369 dig
->afmt
= rdev
->mode_info
.afmt
[dig
->dig_encoder
];
2371 /* RS600/690/740 have only 1 afmt block */
2372 dig
->afmt
= rdev
->mode_info
.afmt
[0];
2377 radeon_atom_output_lock(encoder
, true);
2380 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
2382 /* select the clock/data port if it uses a router */
2383 if (radeon_connector
->router
.cd_valid
)
2384 radeon_router_select_cd_port(radeon_connector
);
2386 /* turn eDP panel on for mode set */
2387 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
2388 atombios_set_edp_panel_power(connector
,
2389 ATOM_TRANSMITTER_ACTION_POWER_ON
);
2392 /* this is needed for the pll/ss setup to work correctly in some cases */
2393 atombios_set_encoder_crtc_source(encoder
);
2394 /* set up the FMT blocks */
2395 if (ASIC_IS_DCE8(rdev
))
2396 dce8_program_fmt(encoder
);
2397 else if (ASIC_IS_DCE4(rdev
))
2398 dce4_program_fmt(encoder
);
2399 else if (ASIC_IS_DCE3(rdev
))
2400 dce3_program_fmt(encoder
);
2401 else if (ASIC_IS_AVIVO(rdev
))
2402 avivo_program_fmt(encoder
);
2405 static void radeon_atom_encoder_commit(struct drm_encoder
*encoder
)
2407 /* need to call this here as we need the crtc set up */
2408 radeon_atom_encoder_dpms(encoder
, DRM_MODE_DPMS_ON
);
2409 radeon_atom_output_lock(encoder
, false);
2412 static void radeon_atom_encoder_disable(struct drm_encoder
*encoder
)
2414 struct drm_device
*dev
= encoder
->dev
;
2415 struct radeon_device
*rdev
= dev
->dev_private
;
2416 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2417 struct radeon_encoder_atom_dig
*dig
;
2419 /* check for pre-DCE3 cards with shared encoders;
2420 * can't really use the links individually, so don't disable
2421 * the encoder if it's in use by another connector
2423 if (!ASIC_IS_DCE3(rdev
)) {
2424 struct drm_encoder
*other_encoder
;
2425 struct radeon_encoder
*other_radeon_encoder
;
2427 list_for_each_entry(other_encoder
, &dev
->mode_config
.encoder_list
, head
) {
2428 other_radeon_encoder
= to_radeon_encoder(other_encoder
);
2429 if ((radeon_encoder
->encoder_id
== other_radeon_encoder
->encoder_id
) &&
2430 drm_helper_encoder_in_use(other_encoder
))
2435 radeon_atom_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
2437 switch (radeon_encoder
->encoder_id
) {
2438 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
2439 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
2440 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
2441 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
2442 atombios_digital_setup(encoder
, PANEL_ENCODER_ACTION_DISABLE
);
2444 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2445 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2446 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2447 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2448 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
2449 /* handled in dpms */
2451 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
2452 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
2453 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
2454 atombios_dvo_setup(encoder
, ATOM_DISABLE
);
2456 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
2457 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
2458 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
2459 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
2460 atombios_dac_setup(encoder
, ATOM_DISABLE
);
2461 if (radeon_encoder
->devices
& (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
))
2462 atombios_tv_setup(encoder
, ATOM_DISABLE
);
2467 if (radeon_encoder_is_digital(encoder
)) {
2468 if (atombios_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
) {
2469 if (rdev
->asic
->display
.hdmi_enable
)
2470 radeon_hdmi_enable(rdev
, encoder
, false);
2472 dig
= radeon_encoder
->enc_priv
;
2473 dig
->dig_encoder
= -1;
2475 radeon_encoder
->active_device
= 0;
2478 /* these are handled by the primary encoders */
2479 static void radeon_atom_ext_prepare(struct drm_encoder
*encoder
)
2484 static void radeon_atom_ext_commit(struct drm_encoder
*encoder
)
2490 radeon_atom_ext_mode_set(struct drm_encoder
*encoder
,
2491 struct drm_display_mode
*mode
,
2492 struct drm_display_mode
*adjusted_mode
)
2497 static void radeon_atom_ext_disable(struct drm_encoder
*encoder
)
2503 radeon_atom_ext_dpms(struct drm_encoder
*encoder
, int mode
)
2508 static bool radeon_atom_ext_mode_fixup(struct drm_encoder
*encoder
,
2509 const struct drm_display_mode
*mode
,
2510 struct drm_display_mode
*adjusted_mode
)
2515 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs
= {
2516 .dpms
= radeon_atom_ext_dpms
,
2517 .mode_fixup
= radeon_atom_ext_mode_fixup
,
2518 .prepare
= radeon_atom_ext_prepare
,
2519 .mode_set
= radeon_atom_ext_mode_set
,
2520 .commit
= radeon_atom_ext_commit
,
2521 .disable
= radeon_atom_ext_disable
,
2522 /* no detect for TMDS/LVDS yet */
2525 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs
= {
2526 .dpms
= radeon_atom_encoder_dpms
,
2527 .mode_fixup
= radeon_atom_mode_fixup
,
2528 .prepare
= radeon_atom_encoder_prepare
,
2529 .mode_set
= radeon_atom_encoder_mode_set
,
2530 .commit
= radeon_atom_encoder_commit
,
2531 .disable
= radeon_atom_encoder_disable
,
2532 .detect
= radeon_atom_dig_detect
,
2535 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs
= {
2536 .dpms
= radeon_atom_encoder_dpms
,
2537 .mode_fixup
= radeon_atom_mode_fixup
,
2538 .prepare
= radeon_atom_encoder_prepare
,
2539 .mode_set
= radeon_atom_encoder_mode_set
,
2540 .commit
= radeon_atom_encoder_commit
,
2541 .detect
= radeon_atom_dac_detect
,
2544 void radeon_enc_destroy(struct drm_encoder
*encoder
)
2546 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2547 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
2548 radeon_atom_backlight_exit(radeon_encoder
);
2549 kfree(radeon_encoder
->enc_priv
);
2550 drm_encoder_cleanup(encoder
);
2551 kfree(radeon_encoder
);
2554 static const struct drm_encoder_funcs radeon_atom_enc_funcs
= {
2555 .destroy
= radeon_enc_destroy
,
2558 static struct radeon_encoder_atom_dac
*
2559 radeon_atombios_set_dac_info(struct radeon_encoder
*radeon_encoder
)
2561 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
2562 struct radeon_device
*rdev
= dev
->dev_private
;
2563 struct radeon_encoder_atom_dac
*dac
= kzalloc(sizeof(struct radeon_encoder_atom_dac
), GFP_KERNEL
);
2568 dac
->tv_std
= radeon_atombios_get_tv_info(rdev
);
2572 static struct radeon_encoder_atom_dig
*
2573 radeon_atombios_set_dig_info(struct radeon_encoder
*radeon_encoder
)
2575 int encoder_enum
= (radeon_encoder
->encoder_enum
& ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
2576 struct radeon_encoder_atom_dig
*dig
= kzalloc(sizeof(struct radeon_encoder_atom_dig
), GFP_KERNEL
);
2581 /* coherent mode by default */
2582 dig
->coherent_mode
= true;
2583 dig
->dig_encoder
= -1;
2585 if (encoder_enum
== 2)
2594 radeon_add_atom_encoder(struct drm_device
*dev
,
2595 uint32_t encoder_enum
,
2596 uint32_t supported_device
,
2599 struct radeon_device
*rdev
= dev
->dev_private
;
2600 struct drm_encoder
*encoder
;
2601 struct radeon_encoder
*radeon_encoder
;
2603 /* see if we already added it */
2604 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
2605 radeon_encoder
= to_radeon_encoder(encoder
);
2606 if (radeon_encoder
->encoder_enum
== encoder_enum
) {
2607 radeon_encoder
->devices
|= supported_device
;
2614 radeon_encoder
= kzalloc(sizeof(struct radeon_encoder
), GFP_KERNEL
);
2615 if (!radeon_encoder
)
2618 encoder
= &radeon_encoder
->base
;
2619 switch (rdev
->num_crtc
) {
2621 encoder
->possible_crtcs
= 0x1;
2625 encoder
->possible_crtcs
= 0x3;
2628 encoder
->possible_crtcs
= 0xf;
2631 encoder
->possible_crtcs
= 0x3f;
2635 radeon_encoder
->enc_priv
= NULL
;
2637 radeon_encoder
->encoder_enum
= encoder_enum
;
2638 radeon_encoder
->encoder_id
= (encoder_enum
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
2639 radeon_encoder
->devices
= supported_device
;
2640 radeon_encoder
->rmx_type
= RMX_OFF
;
2641 radeon_encoder
->underscan_type
= UNDERSCAN_OFF
;
2642 radeon_encoder
->is_ext_encoder
= false;
2643 radeon_encoder
->caps
= caps
;
2645 switch (radeon_encoder
->encoder_id
) {
2646 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
2647 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
2648 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
2649 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
2650 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
2651 radeon_encoder
->rmx_type
= RMX_FULL
;
2652 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_LVDS
);
2653 radeon_encoder
->enc_priv
= radeon_atombios_get_lvds_info(radeon_encoder
);
2655 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TMDS
);
2656 radeon_encoder
->enc_priv
= radeon_atombios_set_dig_info(radeon_encoder
);
2658 drm_encoder_helper_add(encoder
, &radeon_atom_dig_helper_funcs
);
2660 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
2661 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_DAC
);
2662 radeon_encoder
->enc_priv
= radeon_atombios_set_dac_info(radeon_encoder
);
2663 drm_encoder_helper_add(encoder
, &radeon_atom_dac_helper_funcs
);
2665 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
2666 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
2667 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
2668 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TVDAC
);
2669 radeon_encoder
->enc_priv
= radeon_atombios_set_dac_info(radeon_encoder
);
2670 drm_encoder_helper_add(encoder
, &radeon_atom_dac_helper_funcs
);
2672 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
2673 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
2674 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
2675 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2676 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
2677 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2678 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2679 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2680 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
2681 radeon_encoder
->rmx_type
= RMX_FULL
;
2682 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_LVDS
);
2683 radeon_encoder
->enc_priv
= radeon_atombios_get_lvds_info(radeon_encoder
);
2684 } else if (radeon_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
)) {
2685 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_DAC
);
2686 radeon_encoder
->enc_priv
= radeon_atombios_set_dig_info(radeon_encoder
);
2688 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TMDS
);
2689 radeon_encoder
->enc_priv
= radeon_atombios_set_dig_info(radeon_encoder
);
2691 drm_encoder_helper_add(encoder
, &radeon_atom_dig_helper_funcs
);
2693 case ENCODER_OBJECT_ID_SI170B
:
2694 case ENCODER_OBJECT_ID_CH7303
:
2695 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA
:
2696 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB
:
2697 case ENCODER_OBJECT_ID_TITFP513
:
2698 case ENCODER_OBJECT_ID_VT1623
:
2699 case ENCODER_OBJECT_ID_HDMI_SI1930
:
2700 case ENCODER_OBJECT_ID_TRAVIS
:
2701 case ENCODER_OBJECT_ID_NUTMEG
:
2702 /* these are handled by the primary encoders */
2703 radeon_encoder
->is_ext_encoder
= true;
2704 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
2705 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_LVDS
);
2706 else if (radeon_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
))
2707 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_DAC
);
2709 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TMDS
);
2710 drm_encoder_helper_add(encoder
, &radeon_atom_ext_helper_funcs
);