2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
31 #include <linux/backlight.h>
33 extern int atom_debug
;
36 radeon_atom_get_backlight_level_from_reg(struct radeon_device
*rdev
)
41 if (rdev
->family
>= CHIP_R600
)
42 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
44 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
46 backlight_level
= ((bios_2_scratch
& ATOM_S2_CURRENT_BL_LEVEL_MASK
) >>
47 ATOM_S2_CURRENT_BL_LEVEL_SHIFT
);
49 return backlight_level
;
53 radeon_atom_set_backlight_level_to_reg(struct radeon_device
*rdev
,
58 if (rdev
->family
>= CHIP_R600
)
59 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
61 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
63 bios_2_scratch
&= ~ATOM_S2_CURRENT_BL_LEVEL_MASK
;
64 bios_2_scratch
|= ((backlight_level
<< ATOM_S2_CURRENT_BL_LEVEL_SHIFT
) &
65 ATOM_S2_CURRENT_BL_LEVEL_MASK
);
67 if (rdev
->family
>= CHIP_R600
)
68 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
70 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);
74 atombios_get_backlight_level(struct radeon_encoder
*radeon_encoder
)
76 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
77 struct radeon_device
*rdev
= dev
->dev_private
;
79 if (!(rdev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
82 return radeon_atom_get_backlight_level_from_reg(rdev
);
86 atombios_set_backlight_level(struct radeon_encoder
*radeon_encoder
, u8 level
)
88 struct drm_encoder
*encoder
= &radeon_encoder
->base
;
89 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
90 struct radeon_device
*rdev
= dev
->dev_private
;
91 struct radeon_encoder_atom_dig
*dig
;
92 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args
;
95 if (!(rdev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
98 if ((radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) &&
99 radeon_encoder
->enc_priv
) {
100 dig
= radeon_encoder
->enc_priv
;
101 dig
->backlight_level
= level
;
102 radeon_atom_set_backlight_level_to_reg(rdev
, dig
->backlight_level
);
104 switch (radeon_encoder
->encoder_id
) {
105 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
106 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
107 index
= GetIndexIntoMasterTable(COMMAND
, LCD1OutputControl
);
108 if (dig
->backlight_level
== 0) {
109 args
.ucAction
= ATOM_LCD_BLOFF
;
110 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
112 args
.ucAction
= ATOM_LCD_BL_BRIGHTNESS_CONTROL
;
113 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
114 args
.ucAction
= ATOM_LCD_BLON
;
115 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
118 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
119 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
120 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
122 if (dig
->backlight_level
== 0)
123 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_LCD_BLOFF
, 0, 0);
125 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL
, 0, 0);
126 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_LCD_BLON
, 0, 0);
135 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
137 static u8
radeon_atom_bl_level(struct backlight_device
*bd
)
141 /* Convert brightness to hardware level */
142 if (bd
->props
.brightness
< 0)
144 else if (bd
->props
.brightness
> RADEON_MAX_BL_LEVEL
)
145 level
= RADEON_MAX_BL_LEVEL
;
147 level
= bd
->props
.brightness
;
152 static int radeon_atom_backlight_update_status(struct backlight_device
*bd
)
154 struct radeon_backlight_privdata
*pdata
= bl_get_data(bd
);
155 struct radeon_encoder
*radeon_encoder
= pdata
->encoder
;
157 atombios_set_backlight_level(radeon_encoder
, radeon_atom_bl_level(bd
));
162 static int radeon_atom_backlight_get_brightness(struct backlight_device
*bd
)
164 struct radeon_backlight_privdata
*pdata
= bl_get_data(bd
);
165 struct radeon_encoder
*radeon_encoder
= pdata
->encoder
;
166 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
167 struct radeon_device
*rdev
= dev
->dev_private
;
169 return radeon_atom_get_backlight_level_from_reg(rdev
);
172 static const struct backlight_ops radeon_atom_backlight_ops
= {
173 .get_brightness
= radeon_atom_backlight_get_brightness
,
174 .update_status
= radeon_atom_backlight_update_status
,
177 void radeon_atom_backlight_init(struct radeon_encoder
*radeon_encoder
,
178 struct drm_connector
*drm_connector
)
180 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
181 struct radeon_device
*rdev
= dev
->dev_private
;
182 struct backlight_device
*bd
;
183 struct backlight_properties props
;
184 struct radeon_backlight_privdata
*pdata
;
185 struct radeon_encoder_atom_dig
*dig
;
189 if (!radeon_encoder
->enc_priv
)
192 if (!rdev
->is_atom_bios
)
195 if (!(rdev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
198 pdata
= kmalloc(sizeof(struct radeon_backlight_privdata
), GFP_KERNEL
);
200 DRM_ERROR("Memory allocation failed\n");
204 memset(&props
, 0, sizeof(props
));
205 props
.max_brightness
= RADEON_MAX_BL_LEVEL
;
206 props
.type
= BACKLIGHT_RAW
;
207 snprintf(bl_name
, sizeof(bl_name
),
208 "radeon_bl%d", dev
->primary
->index
);
209 bd
= backlight_device_register(bl_name
, &drm_connector
->kdev
,
210 pdata
, &radeon_atom_backlight_ops
, &props
);
212 DRM_ERROR("Backlight registration failed\n");
216 pdata
->encoder
= radeon_encoder
;
218 backlight_level
= radeon_atom_get_backlight_level_from_reg(rdev
);
220 dig
= radeon_encoder
->enc_priv
;
223 bd
->props
.brightness
= radeon_atom_backlight_get_brightness(bd
);
224 bd
->props
.power
= FB_BLANK_UNBLANK
;
225 backlight_update_status(bd
);
227 DRM_INFO("radeon atom DIG backlight initialized\n");
236 static void radeon_atom_backlight_exit(struct radeon_encoder
*radeon_encoder
)
238 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
239 struct radeon_device
*rdev
= dev
->dev_private
;
240 struct backlight_device
*bd
= NULL
;
241 struct radeon_encoder_atom_dig
*dig
;
243 if (!radeon_encoder
->enc_priv
)
246 if (!rdev
->is_atom_bios
)
249 if (!(rdev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
252 dig
= radeon_encoder
->enc_priv
;
257 struct radeon_legacy_backlight_privdata
*pdata
;
259 pdata
= bl_get_data(bd
);
260 backlight_device_unregister(bd
);
263 DRM_INFO("radeon atom LVDS backlight unloaded\n");
267 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
269 void radeon_atom_backlight_init(struct radeon_encoder
*encoder
)
273 static void radeon_atom_backlight_exit(struct radeon_encoder
*encoder
)
279 /* evil but including atombios.h is much worse */
280 bool radeon_atom_get_tv_timings(struct radeon_device
*rdev
, int index
,
281 struct drm_display_mode
*mode
);
284 static inline bool radeon_encoder_is_digital(struct drm_encoder
*encoder
)
286 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
287 switch (radeon_encoder
->encoder_id
) {
288 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
289 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
290 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
291 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
292 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
293 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
294 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
295 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
296 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
297 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
298 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
305 static bool radeon_atom_mode_fixup(struct drm_encoder
*encoder
,
306 const struct drm_display_mode
*mode
,
307 struct drm_display_mode
*adjusted_mode
)
309 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
310 struct drm_device
*dev
= encoder
->dev
;
311 struct radeon_device
*rdev
= dev
->dev_private
;
313 /* set the active encoder to connector routing */
314 radeon_encoder_set_active_device(encoder
);
315 drm_mode_set_crtcinfo(adjusted_mode
, 0);
318 if ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
319 && (mode
->crtc_vsync_start
< (mode
->crtc_vdisplay
+ 2)))
320 adjusted_mode
->crtc_vsync_start
= adjusted_mode
->crtc_vdisplay
+ 2;
322 /* get the native mode for LVDS */
323 if (radeon_encoder
->active_device
& (ATOM_DEVICE_LCD_SUPPORT
))
324 radeon_panel_mode_fixup(encoder
, adjusted_mode
);
326 /* get the native mode for TV */
327 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
)) {
328 struct radeon_encoder_atom_dac
*tv_dac
= radeon_encoder
->enc_priv
;
330 if (tv_dac
->tv_std
== TV_STD_NTSC
||
331 tv_dac
->tv_std
== TV_STD_NTSC_J
||
332 tv_dac
->tv_std
== TV_STD_PAL_M
)
333 radeon_atom_get_tv_timings(rdev
, 0, adjusted_mode
);
335 radeon_atom_get_tv_timings(rdev
, 1, adjusted_mode
);
339 if (ASIC_IS_DCE3(rdev
) &&
340 ((radeon_encoder
->active_device
& (ATOM_DEVICE_DFP_SUPPORT
| ATOM_DEVICE_LCD_SUPPORT
)) ||
341 (radeon_encoder_get_dp_bridge_encoder_id(encoder
) != ENCODER_OBJECT_ID_NONE
))) {
342 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
343 radeon_dp_set_link_config(connector
, adjusted_mode
);
350 atombios_dac_setup(struct drm_encoder
*encoder
, int action
)
352 struct drm_device
*dev
= encoder
->dev
;
353 struct radeon_device
*rdev
= dev
->dev_private
;
354 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
355 DAC_ENCODER_CONTROL_PS_ALLOCATION args
;
357 struct radeon_encoder_atom_dac
*dac_info
= radeon_encoder
->enc_priv
;
359 memset(&args
, 0, sizeof(args
));
361 switch (radeon_encoder
->encoder_id
) {
362 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
363 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
364 index
= GetIndexIntoMasterTable(COMMAND
, DAC1EncoderControl
);
366 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
367 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
368 index
= GetIndexIntoMasterTable(COMMAND
, DAC2EncoderControl
);
372 args
.ucAction
= action
;
374 if (radeon_encoder
->active_device
& (ATOM_DEVICE_CRT_SUPPORT
))
375 args
.ucDacStandard
= ATOM_DAC1_PS2
;
376 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
377 args
.ucDacStandard
= ATOM_DAC1_CV
;
379 switch (dac_info
->tv_std
) {
382 case TV_STD_SCART_PAL
:
385 args
.ucDacStandard
= ATOM_DAC1_PAL
;
391 args
.ucDacStandard
= ATOM_DAC1_NTSC
;
395 args
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
397 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
402 atombios_tv_setup(struct drm_encoder
*encoder
, int action
)
404 struct drm_device
*dev
= encoder
->dev
;
405 struct radeon_device
*rdev
= dev
->dev_private
;
406 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
407 TV_ENCODER_CONTROL_PS_ALLOCATION args
;
409 struct radeon_encoder_atom_dac
*dac_info
= radeon_encoder
->enc_priv
;
411 memset(&args
, 0, sizeof(args
));
413 index
= GetIndexIntoMasterTable(COMMAND
, TVEncoderControl
);
415 args
.sTVEncoder
.ucAction
= action
;
417 if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
418 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_CV
;
420 switch (dac_info
->tv_std
) {
422 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_NTSC
;
425 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PAL
;
428 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PALM
;
431 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PAL60
;
434 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_NTSCJ
;
436 case TV_STD_SCART_PAL
:
437 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PAL
; /* ??? */
440 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_SECAM
;
443 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PALCN
;
446 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_NTSC
;
451 args
.sTVEncoder
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
453 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
457 static u8
radeon_atom_get_bpc(struct drm_encoder
*encoder
)
459 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
463 bpc
= radeon_get_monitor_bpc(connector
);
467 return PANEL_BPC_UNDEFINE
;
469 return PANEL_6BIT_PER_COLOR
;
472 return PANEL_8BIT_PER_COLOR
;
474 return PANEL_10BIT_PER_COLOR
;
476 return PANEL_12BIT_PER_COLOR
;
478 return PANEL_16BIT_PER_COLOR
;
483 union dvo_encoder_control
{
484 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds
;
485 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo
;
486 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3
;
490 atombios_dvo_setup(struct drm_encoder
*encoder
, int action
)
492 struct drm_device
*dev
= encoder
->dev
;
493 struct radeon_device
*rdev
= dev
->dev_private
;
494 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
495 union dvo_encoder_control args
;
496 int index
= GetIndexIntoMasterTable(COMMAND
, DVOEncoderControl
);
499 memset(&args
, 0, sizeof(args
));
501 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
504 /* some R4xx chips have the wrong frev */
505 if (rdev
->family
<= CHIP_RV410
)
513 args
.ext_tmds
.sXTmdsEncoder
.ucEnable
= action
;
515 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
516 args
.ext_tmds
.sXTmdsEncoder
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
518 args
.ext_tmds
.sXTmdsEncoder
.ucMisc
|= ATOM_PANEL_MISC_888RGB
;
522 args
.dvo
.sDVOEncoder
.ucAction
= action
;
523 args
.dvo
.sDVOEncoder
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
524 /* DFP1, CRT1, TV1 depending on the type of port */
525 args
.dvo
.sDVOEncoder
.ucDeviceType
= ATOM_DEVICE_DFP1_INDEX
;
527 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
528 args
.dvo
.sDVOEncoder
.usDevAttr
.sDigAttrib
.ucAttribute
|= PANEL_ENCODER_MISC_DUAL
;
532 args
.dvo_v3
.ucAction
= action
;
533 args
.dvo_v3
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
534 args
.dvo_v3
.ucDVOConfig
= 0; /* XXX */
537 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
542 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
546 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
549 union lvds_encoder_control
{
550 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1
;
551 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2
;
555 atombios_digital_setup(struct drm_encoder
*encoder
, int action
)
557 struct drm_device
*dev
= encoder
->dev
;
558 struct radeon_device
*rdev
= dev
->dev_private
;
559 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
560 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
561 union lvds_encoder_control args
;
563 int hdmi_detected
= 0;
569 if (atombios_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
)
572 memset(&args
, 0, sizeof(args
));
574 switch (radeon_encoder
->encoder_id
) {
575 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
576 index
= GetIndexIntoMasterTable(COMMAND
, LVDSEncoderControl
);
578 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
579 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
580 index
= GetIndexIntoMasterTable(COMMAND
, TMDS1EncoderControl
);
582 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
583 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
584 index
= GetIndexIntoMasterTable(COMMAND
, LVDSEncoderControl
);
586 index
= GetIndexIntoMasterTable(COMMAND
, TMDS2EncoderControl
);
590 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
599 args
.v1
.ucAction
= action
;
601 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_HDMI_TYPE
;
602 args
.v1
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
603 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
604 if (dig
->lcd_misc
& ATOM_PANEL_MISC_DUAL
)
605 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
606 if (dig
->lcd_misc
& ATOM_PANEL_MISC_888RGB
)
607 args
.v1
.ucMisc
|= ATOM_PANEL_MISC_888RGB
;
610 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_TMDS_LINKB
;
611 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
612 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
613 /*if (pScrn->rgbBits == 8) */
614 args
.v1
.ucMisc
|= ATOM_PANEL_MISC_888RGB
;
620 args
.v2
.ucAction
= action
;
622 if (dig
->coherent_mode
)
623 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_COHERENT
;
626 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_HDMI_TYPE
;
627 args
.v2
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
628 args
.v2
.ucTruncate
= 0;
629 args
.v2
.ucSpatial
= 0;
630 args
.v2
.ucTemporal
= 0;
632 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
633 if (dig
->lcd_misc
& ATOM_PANEL_MISC_DUAL
)
634 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
635 if (dig
->lcd_misc
& ATOM_PANEL_MISC_SPATIAL
) {
636 args
.v2
.ucSpatial
= PANEL_ENCODER_SPATIAL_DITHER_EN
;
637 if (dig
->lcd_misc
& ATOM_PANEL_MISC_888RGB
)
638 args
.v2
.ucSpatial
|= PANEL_ENCODER_SPATIAL_DITHER_DEPTH
;
640 if (dig
->lcd_misc
& ATOM_PANEL_MISC_TEMPORAL
) {
641 args
.v2
.ucTemporal
= PANEL_ENCODER_TEMPORAL_DITHER_EN
;
642 if (dig
->lcd_misc
& ATOM_PANEL_MISC_888RGB
)
643 args
.v2
.ucTemporal
|= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH
;
644 if (((dig
->lcd_misc
>> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT
) & 0x3) == 2)
645 args
.v2
.ucTemporal
|= PANEL_ENCODER_TEMPORAL_LEVEL_4
;
649 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_TMDS_LINKB
;
650 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
651 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
655 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
660 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
664 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
668 atombios_get_encoder_mode(struct drm_encoder
*encoder
)
670 struct drm_device
*dev
= encoder
->dev
;
671 struct radeon_device
*rdev
= dev
->dev_private
;
672 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
673 struct drm_connector
*connector
;
674 struct radeon_connector
*radeon_connector
;
675 struct radeon_connector_atom_dig
*dig_connector
;
677 /* dp bridges are always DP */
678 if (radeon_encoder_get_dp_bridge_encoder_id(encoder
) != ENCODER_OBJECT_ID_NONE
)
679 return ATOM_ENCODER_MODE_DP
;
681 /* DVO is always DVO */
682 if ((radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DVO1
) ||
683 (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
))
684 return ATOM_ENCODER_MODE_DVO
;
686 connector
= radeon_get_connector_for_encoder(encoder
);
687 /* if we don't have an active device yet, just use one of
688 * the connectors tied to the encoder.
691 connector
= radeon_get_connector_for_encoder_init(encoder
);
692 radeon_connector
= to_radeon_connector(connector
);
694 switch (connector
->connector_type
) {
695 case DRM_MODE_CONNECTOR_DVII
:
696 case DRM_MODE_CONNECTOR_HDMIB
: /* HDMI-B is basically DL-DVI; analog works fine */
697 if (drm_detect_hdmi_monitor(radeon_connector
->edid
) &&
699 !ASIC_IS_DCE6(rdev
)) /* remove once we support DCE6 */
700 return ATOM_ENCODER_MODE_HDMI
;
701 else if (radeon_connector
->use_digital
)
702 return ATOM_ENCODER_MODE_DVI
;
704 return ATOM_ENCODER_MODE_CRT
;
706 case DRM_MODE_CONNECTOR_DVID
:
707 case DRM_MODE_CONNECTOR_HDMIA
:
709 if (drm_detect_hdmi_monitor(radeon_connector
->edid
) &&
711 !ASIC_IS_DCE6(rdev
)) /* remove once we support DCE6 */
712 return ATOM_ENCODER_MODE_HDMI
;
714 return ATOM_ENCODER_MODE_DVI
;
716 case DRM_MODE_CONNECTOR_LVDS
:
717 return ATOM_ENCODER_MODE_LVDS
;
719 case DRM_MODE_CONNECTOR_DisplayPort
:
720 dig_connector
= radeon_connector
->con_priv
;
721 if ((dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_DISPLAYPORT
) ||
722 (dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_eDP
))
723 return ATOM_ENCODER_MODE_DP
;
724 else if (drm_detect_hdmi_monitor(radeon_connector
->edid
) &&
726 !ASIC_IS_DCE6(rdev
)) /* remove once we support DCE6 */
727 return ATOM_ENCODER_MODE_HDMI
;
729 return ATOM_ENCODER_MODE_DVI
;
731 case DRM_MODE_CONNECTOR_eDP
:
732 return ATOM_ENCODER_MODE_DP
;
733 case DRM_MODE_CONNECTOR_DVIA
:
734 case DRM_MODE_CONNECTOR_VGA
:
735 return ATOM_ENCODER_MODE_CRT
;
737 case DRM_MODE_CONNECTOR_Composite
:
738 case DRM_MODE_CONNECTOR_SVIDEO
:
739 case DRM_MODE_CONNECTOR_9PinDIN
:
741 return ATOM_ENCODER_MODE_TV
;
742 /*return ATOM_ENCODER_MODE_CV;*/
748 * DIG Encoder/Transmitter Setup
751 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
752 * Supports up to 3 digital outputs
753 * - 2 DIG encoder blocks.
754 * DIG1 can drive UNIPHY link A or link B
755 * DIG2 can drive UNIPHY link B or LVTMA
758 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
759 * Supports up to 5 digital outputs
760 * - 2 DIG encoder blocks.
761 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
764 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
765 * Supports up to 6 digital outputs
766 * - 6 DIG encoder blocks.
767 * - DIG to PHY mapping is hardcoded
768 * DIG1 drives UNIPHY0 link A, A+B
769 * DIG2 drives UNIPHY0 link B
770 * DIG3 drives UNIPHY1 link A, A+B
771 * DIG4 drives UNIPHY1 link B
772 * DIG5 drives UNIPHY2 link A, A+B
773 * DIG6 drives UNIPHY2 link B
776 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
777 * Supports up to 6 digital outputs
778 * - 2 DIG encoder blocks.
780 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
782 * DIG1 drives UNIPHY0/1/2 link A
783 * DIG2 drives UNIPHY0/1/2 link B
786 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
788 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
789 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
790 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
791 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
794 union dig_encoder_control
{
795 DIG_ENCODER_CONTROL_PS_ALLOCATION v1
;
796 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2
;
797 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3
;
798 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4
;
802 atombios_dig_encoder_setup(struct drm_encoder
*encoder
, int action
, int panel_mode
)
804 struct drm_device
*dev
= encoder
->dev
;
805 struct radeon_device
*rdev
= dev
->dev_private
;
806 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
807 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
808 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
809 union dig_encoder_control args
;
813 int dp_lane_count
= 0;
814 int hpd_id
= RADEON_HPD_NONE
;
817 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
818 struct radeon_connector_atom_dig
*dig_connector
=
819 radeon_connector
->con_priv
;
821 dp_clock
= dig_connector
->dp_clock
;
822 dp_lane_count
= dig_connector
->dp_lane_count
;
823 hpd_id
= radeon_connector
->hpd
.hpd
;
826 /* no dig encoder assigned */
827 if (dig
->dig_encoder
== -1)
830 memset(&args
, 0, sizeof(args
));
832 if (ASIC_IS_DCE4(rdev
))
833 index
= GetIndexIntoMasterTable(COMMAND
, DIGxEncoderControl
);
835 if (dig
->dig_encoder
)
836 index
= GetIndexIntoMasterTable(COMMAND
, DIG2EncoderControl
);
838 index
= GetIndexIntoMasterTable(COMMAND
, DIG1EncoderControl
);
841 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
848 args
.v1
.ucAction
= action
;
849 args
.v1
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
850 if (action
== ATOM_ENCODER_CMD_SETUP_PANEL_MODE
)
851 args
.v3
.ucPanelMode
= panel_mode
;
853 args
.v1
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
855 if (ENCODER_MODE_IS_DP(args
.v1
.ucEncoderMode
))
856 args
.v1
.ucLaneNum
= dp_lane_count
;
857 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
858 args
.v1
.ucLaneNum
= 8;
860 args
.v1
.ucLaneNum
= 4;
862 if (ENCODER_MODE_IS_DP(args
.v1
.ucEncoderMode
) && (dp_clock
== 270000))
863 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ
;
864 switch (radeon_encoder
->encoder_id
) {
865 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
866 args
.v1
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER1
;
868 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
869 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
870 args
.v1
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER2
;
872 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
873 args
.v1
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER3
;
877 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_LINKB
;
879 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_LINKA
;
883 args
.v3
.ucAction
= action
;
884 args
.v3
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
885 if (action
== ATOM_ENCODER_CMD_SETUP_PANEL_MODE
)
886 args
.v3
.ucPanelMode
= panel_mode
;
888 args
.v3
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
890 if (ENCODER_MODE_IS_DP(args
.v3
.ucEncoderMode
))
891 args
.v3
.ucLaneNum
= dp_lane_count
;
892 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
893 args
.v3
.ucLaneNum
= 8;
895 args
.v3
.ucLaneNum
= 4;
897 if (ENCODER_MODE_IS_DP(args
.v3
.ucEncoderMode
) && (dp_clock
== 270000))
898 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ
;
899 args
.v3
.acConfig
.ucDigSel
= dig
->dig_encoder
;
900 args
.v3
.ucBitPerColor
= radeon_atom_get_bpc(encoder
);
903 args
.v4
.ucAction
= action
;
904 args
.v4
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
905 if (action
== ATOM_ENCODER_CMD_SETUP_PANEL_MODE
)
906 args
.v4
.ucPanelMode
= panel_mode
;
908 args
.v4
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
910 if (ENCODER_MODE_IS_DP(args
.v4
.ucEncoderMode
))
911 args
.v4
.ucLaneNum
= dp_lane_count
;
912 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
913 args
.v4
.ucLaneNum
= 8;
915 args
.v4
.ucLaneNum
= 4;
917 if (ENCODER_MODE_IS_DP(args
.v4
.ucEncoderMode
)) {
918 if (dp_clock
== 270000)
919 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ
;
920 else if (dp_clock
== 540000)
921 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ
;
923 args
.v4
.acConfig
.ucDigSel
= dig
->dig_encoder
;
924 args
.v4
.ucBitPerColor
= radeon_atom_get_bpc(encoder
);
925 if (hpd_id
== RADEON_HPD_NONE
)
926 args
.v4
.ucHPD_ID
= 0;
928 args
.v4
.ucHPD_ID
= hpd_id
+ 1;
931 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
936 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
940 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
944 union dig_transmitter_control
{
945 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1
;
946 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2
;
947 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3
;
948 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4
;
949 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5
;
953 atombios_dig_transmitter_setup(struct drm_encoder
*encoder
, int action
, uint8_t lane_num
, uint8_t lane_set
)
955 struct drm_device
*dev
= encoder
->dev
;
956 struct radeon_device
*rdev
= dev
->dev_private
;
957 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
958 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
959 struct drm_connector
*connector
;
960 union dig_transmitter_control args
;
966 int dp_lane_count
= 0;
967 int connector_object_id
= 0;
968 int igp_lane_info
= 0;
969 int dig_encoder
= dig
->dig_encoder
;
970 int hpd_id
= RADEON_HPD_NONE
;
972 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
973 connector
= radeon_get_connector_for_encoder_init(encoder
);
974 /* just needed to avoid bailing in the encoder check. the encoder
975 * isn't used for init
979 connector
= radeon_get_connector_for_encoder(encoder
);
982 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
983 struct radeon_connector_atom_dig
*dig_connector
=
984 radeon_connector
->con_priv
;
986 hpd_id
= radeon_connector
->hpd
.hpd
;
987 dp_clock
= dig_connector
->dp_clock
;
988 dp_lane_count
= dig_connector
->dp_lane_count
;
989 connector_object_id
=
990 (radeon_connector
->connector_object_id
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
991 igp_lane_info
= dig_connector
->igp_lane_info
;
995 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
996 pll_id
= radeon_crtc
->pll_id
;
999 /* no dig encoder assigned */
1000 if (dig_encoder
== -1)
1003 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder
)))
1006 memset(&args
, 0, sizeof(args
));
1008 switch (radeon_encoder
->encoder_id
) {
1009 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1010 index
= GetIndexIntoMasterTable(COMMAND
, DVOOutputControl
);
1012 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1013 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1014 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1015 index
= GetIndexIntoMasterTable(COMMAND
, UNIPHYTransmitterControl
);
1017 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1018 index
= GetIndexIntoMasterTable(COMMAND
, LVTMATransmitterControl
);
1022 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1029 args
.v1
.ucAction
= action
;
1030 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
1031 args
.v1
.usInitInfo
= cpu_to_le16(connector_object_id
);
1032 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
1033 args
.v1
.asMode
.ucLaneSel
= lane_num
;
1034 args
.v1
.asMode
.ucLaneSet
= lane_set
;
1037 args
.v1
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
1038 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1039 args
.v1
.usPixelClock
= cpu_to_le16((radeon_encoder
->pixel_clock
/ 2) / 10);
1041 args
.v1
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1044 args
.v1
.ucConfig
= ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL
;
1047 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER
;
1049 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER
;
1051 if ((rdev
->flags
& RADEON_IS_IGP
) &&
1052 (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_UNIPHY
)) {
1054 !radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
)) {
1055 if (igp_lane_info
& 0x1)
1056 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_0_3
;
1057 else if (igp_lane_info
& 0x2)
1058 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_4_7
;
1059 else if (igp_lane_info
& 0x4)
1060 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_8_11
;
1061 else if (igp_lane_info
& 0x8)
1062 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_12_15
;
1064 if (igp_lane_info
& 0x3)
1065 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_0_7
;
1066 else if (igp_lane_info
& 0xc)
1067 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_8_15
;
1072 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LINKB
;
1074 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LINKA
;
1077 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_COHERENT
;
1078 else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1079 if (dig
->coherent_mode
)
1080 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_COHERENT
;
1081 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1082 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_8LANE_LINK
;
1086 args
.v2
.ucAction
= action
;
1087 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
1088 args
.v2
.usInitInfo
= cpu_to_le16(connector_object_id
);
1089 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
1090 args
.v2
.asMode
.ucLaneSel
= lane_num
;
1091 args
.v2
.asMode
.ucLaneSet
= lane_set
;
1094 args
.v2
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
1095 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1096 args
.v2
.usPixelClock
= cpu_to_le16((radeon_encoder
->pixel_clock
/ 2) / 10);
1098 args
.v2
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1101 args
.v2
.acConfig
.ucEncoderSel
= dig_encoder
;
1103 args
.v2
.acConfig
.ucLinkSel
= 1;
1105 switch (radeon_encoder
->encoder_id
) {
1106 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1107 args
.v2
.acConfig
.ucTransmitterSel
= 0;
1109 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1110 args
.v2
.acConfig
.ucTransmitterSel
= 1;
1112 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1113 args
.v2
.acConfig
.ucTransmitterSel
= 2;
1118 args
.v2
.acConfig
.fCoherentMode
= 1;
1119 args
.v2
.acConfig
.fDPConnector
= 1;
1120 } else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1121 if (dig
->coherent_mode
)
1122 args
.v2
.acConfig
.fCoherentMode
= 1;
1123 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1124 args
.v2
.acConfig
.fDualLinkConnector
= 1;
1128 args
.v3
.ucAction
= action
;
1129 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
1130 args
.v3
.usInitInfo
= cpu_to_le16(connector_object_id
);
1131 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
1132 args
.v3
.asMode
.ucLaneSel
= lane_num
;
1133 args
.v3
.asMode
.ucLaneSet
= lane_set
;
1136 args
.v3
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
1137 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1138 args
.v3
.usPixelClock
= cpu_to_le16((radeon_encoder
->pixel_clock
/ 2) / 10);
1140 args
.v3
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1144 args
.v3
.ucLaneNum
= dp_lane_count
;
1145 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1146 args
.v3
.ucLaneNum
= 8;
1148 args
.v3
.ucLaneNum
= 4;
1151 args
.v3
.acConfig
.ucLinkSel
= 1;
1152 if (dig_encoder
& 1)
1153 args
.v3
.acConfig
.ucEncoderSel
= 1;
1155 /* Select the PLL for the PHY
1156 * DP PHY should be clocked from external src if there is
1159 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1160 if (is_dp
&& rdev
->clock
.dp_extclk
)
1161 args
.v3
.acConfig
.ucRefClkSource
= 2; /* external src */
1163 args
.v3
.acConfig
.ucRefClkSource
= pll_id
;
1165 switch (radeon_encoder
->encoder_id
) {
1166 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1167 args
.v3
.acConfig
.ucTransmitterSel
= 0;
1169 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1170 args
.v3
.acConfig
.ucTransmitterSel
= 1;
1172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1173 args
.v3
.acConfig
.ucTransmitterSel
= 2;
1178 args
.v3
.acConfig
.fCoherentMode
= 1; /* DP requires coherent */
1179 else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1180 if (dig
->coherent_mode
)
1181 args
.v3
.acConfig
.fCoherentMode
= 1;
1182 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1183 args
.v3
.acConfig
.fDualLinkConnector
= 1;
1187 args
.v4
.ucAction
= action
;
1188 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
1189 args
.v4
.usInitInfo
= cpu_to_le16(connector_object_id
);
1190 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
1191 args
.v4
.asMode
.ucLaneSel
= lane_num
;
1192 args
.v4
.asMode
.ucLaneSet
= lane_set
;
1195 args
.v4
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
1196 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1197 args
.v4
.usPixelClock
= cpu_to_le16((radeon_encoder
->pixel_clock
/ 2) / 10);
1199 args
.v4
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1203 args
.v4
.ucLaneNum
= dp_lane_count
;
1204 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1205 args
.v4
.ucLaneNum
= 8;
1207 args
.v4
.ucLaneNum
= 4;
1210 args
.v4
.acConfig
.ucLinkSel
= 1;
1211 if (dig_encoder
& 1)
1212 args
.v4
.acConfig
.ucEncoderSel
= 1;
1214 /* Select the PLL for the PHY
1215 * DP PHY should be clocked from external src if there is
1218 /* On DCE5 DCPLL usually generates the DP ref clock */
1220 if (rdev
->clock
.dp_extclk
)
1221 args
.v4
.acConfig
.ucRefClkSource
= ENCODER_REFCLK_SRC_EXTCLK
;
1223 args
.v4
.acConfig
.ucRefClkSource
= ENCODER_REFCLK_SRC_DCPLL
;
1225 args
.v4
.acConfig
.ucRefClkSource
= pll_id
;
1227 switch (radeon_encoder
->encoder_id
) {
1228 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1229 args
.v4
.acConfig
.ucTransmitterSel
= 0;
1231 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1232 args
.v4
.acConfig
.ucTransmitterSel
= 1;
1234 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1235 args
.v4
.acConfig
.ucTransmitterSel
= 2;
1240 args
.v4
.acConfig
.fCoherentMode
= 1; /* DP requires coherent */
1241 else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1242 if (dig
->coherent_mode
)
1243 args
.v4
.acConfig
.fCoherentMode
= 1;
1244 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1245 args
.v4
.acConfig
.fDualLinkConnector
= 1;
1249 args
.v5
.ucAction
= action
;
1251 args
.v5
.usSymClock
= cpu_to_le16(dp_clock
/ 10);
1253 args
.v5
.usSymClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1255 switch (radeon_encoder
->encoder_id
) {
1256 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1258 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYB
;
1260 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYA
;
1262 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1264 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYD
;
1266 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYC
;
1268 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1270 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYF
;
1272 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYE
;
1276 args
.v5
.ucLaneNum
= dp_lane_count
;
1277 else if (radeon_encoder
->pixel_clock
> 165000)
1278 args
.v5
.ucLaneNum
= 8;
1280 args
.v5
.ucLaneNum
= 4;
1281 args
.v5
.ucConnObjId
= connector_object_id
;
1282 args
.v5
.ucDigMode
= atombios_get_encoder_mode(encoder
);
1284 if (is_dp
&& rdev
->clock
.dp_extclk
)
1285 args
.v5
.asConfig
.ucPhyClkSrcId
= ENCODER_REFCLK_SRC_EXTCLK
;
1287 args
.v5
.asConfig
.ucPhyClkSrcId
= pll_id
;
1290 args
.v5
.asConfig
.ucCoherentMode
= 1; /* DP requires coherent */
1291 else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1292 if (dig
->coherent_mode
)
1293 args
.v5
.asConfig
.ucCoherentMode
= 1;
1295 if (hpd_id
== RADEON_HPD_NONE
)
1296 args
.v5
.asConfig
.ucHPDSel
= 0;
1298 args
.v5
.asConfig
.ucHPDSel
= hpd_id
+ 1;
1299 args
.v5
.ucDigEncoderSel
= 1 << dig_encoder
;
1300 args
.v5
.ucDPLaneSet
= lane_set
;
1303 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
1308 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
1312 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1316 atombios_set_edp_panel_power(struct drm_connector
*connector
, int action
)
1318 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
1319 struct drm_device
*dev
= radeon_connector
->base
.dev
;
1320 struct radeon_device
*rdev
= dev
->dev_private
;
1321 union dig_transmitter_control args
;
1322 int index
= GetIndexIntoMasterTable(COMMAND
, UNIPHYTransmitterControl
);
1325 if (connector
->connector_type
!= DRM_MODE_CONNECTOR_eDP
)
1328 if (!ASIC_IS_DCE4(rdev
))
1331 if ((action
!= ATOM_TRANSMITTER_ACTION_POWER_ON
) &&
1332 (action
!= ATOM_TRANSMITTER_ACTION_POWER_OFF
))
1335 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1338 memset(&args
, 0, sizeof(args
));
1340 args
.v1
.ucAction
= action
;
1342 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1344 /* wait for the panel to power up */
1345 if (action
== ATOM_TRANSMITTER_ACTION_POWER_ON
) {
1348 for (i
= 0; i
< 300; i
++) {
1349 if (radeon_hpd_sense(rdev
, radeon_connector
->hpd
.hpd
))
1359 union external_encoder_control
{
1360 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1
;
1361 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3
;
1365 atombios_external_encoder_setup(struct drm_encoder
*encoder
,
1366 struct drm_encoder
*ext_encoder
,
1369 struct drm_device
*dev
= encoder
->dev
;
1370 struct radeon_device
*rdev
= dev
->dev_private
;
1371 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1372 struct radeon_encoder
*ext_radeon_encoder
= to_radeon_encoder(ext_encoder
);
1373 union external_encoder_control args
;
1374 struct drm_connector
*connector
;
1375 int index
= GetIndexIntoMasterTable(COMMAND
, ExternalEncoderControl
);
1378 int dp_lane_count
= 0;
1379 int connector_object_id
= 0;
1380 u32 ext_enum
= (ext_radeon_encoder
->encoder_enum
& ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
1382 if (action
== EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT
)
1383 connector
= radeon_get_connector_for_encoder_init(encoder
);
1385 connector
= radeon_get_connector_for_encoder(encoder
);
1388 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
1389 struct radeon_connector_atom_dig
*dig_connector
=
1390 radeon_connector
->con_priv
;
1392 dp_clock
= dig_connector
->dp_clock
;
1393 dp_lane_count
= dig_connector
->dp_lane_count
;
1394 connector_object_id
=
1395 (radeon_connector
->connector_object_id
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
1398 memset(&args
, 0, sizeof(args
));
1400 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1405 /* no params on frev 1 */
1411 args
.v1
.sDigEncoder
.ucAction
= action
;
1412 args
.v1
.sDigEncoder
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1413 args
.v1
.sDigEncoder
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
1415 if (ENCODER_MODE_IS_DP(args
.v1
.sDigEncoder
.ucEncoderMode
)) {
1416 if (dp_clock
== 270000)
1417 args
.v1
.sDigEncoder
.ucConfig
|= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ
;
1418 args
.v1
.sDigEncoder
.ucLaneNum
= dp_lane_count
;
1419 } else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1420 args
.v1
.sDigEncoder
.ucLaneNum
= 8;
1422 args
.v1
.sDigEncoder
.ucLaneNum
= 4;
1425 args
.v3
.sExtEncoder
.ucAction
= action
;
1426 if (action
== EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT
)
1427 args
.v3
.sExtEncoder
.usConnectorId
= cpu_to_le16(connector_object_id
);
1429 args
.v3
.sExtEncoder
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1430 args
.v3
.sExtEncoder
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
1432 if (ENCODER_MODE_IS_DP(args
.v3
.sExtEncoder
.ucEncoderMode
)) {
1433 if (dp_clock
== 270000)
1434 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ
;
1435 else if (dp_clock
== 540000)
1436 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ
;
1437 args
.v3
.sExtEncoder
.ucLaneNum
= dp_lane_count
;
1438 } else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1439 args
.v3
.sExtEncoder
.ucLaneNum
= 8;
1441 args
.v3
.sExtEncoder
.ucLaneNum
= 4;
1443 case GRAPH_OBJECT_ENUM_ID1
:
1444 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1
;
1446 case GRAPH_OBJECT_ENUM_ID2
:
1447 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2
;
1449 case GRAPH_OBJECT_ENUM_ID3
:
1450 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3
;
1453 args
.v3
.sExtEncoder
.ucBitPerColor
= radeon_atom_get_bpc(encoder
);
1456 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1461 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1464 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1468 atombios_yuv_setup(struct drm_encoder
*encoder
, bool enable
)
1470 struct drm_device
*dev
= encoder
->dev
;
1471 struct radeon_device
*rdev
= dev
->dev_private
;
1472 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1473 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1474 ENABLE_YUV_PS_ALLOCATION args
;
1475 int index
= GetIndexIntoMasterTable(COMMAND
, EnableYUV
);
1478 memset(&args
, 0, sizeof(args
));
1480 if (rdev
->family
>= CHIP_R600
)
1481 reg
= R600_BIOS_3_SCRATCH
;
1483 reg
= RADEON_BIOS_3_SCRATCH
;
1485 /* XXX: fix up scratch reg handling */
1487 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1488 WREG32(reg
, (ATOM_S3_TV1_ACTIVE
|
1489 (radeon_crtc
->crtc_id
<< 18)));
1490 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1491 WREG32(reg
, (ATOM_S3_CV_ACTIVE
| (radeon_crtc
->crtc_id
<< 24)));
1496 args
.ucEnable
= ATOM_ENABLE
;
1497 args
.ucCRTC
= radeon_crtc
->crtc_id
;
1499 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1505 radeon_atom_encoder_dpms_avivo(struct drm_encoder
*encoder
, int mode
)
1507 struct drm_device
*dev
= encoder
->dev
;
1508 struct radeon_device
*rdev
= dev
->dev_private
;
1509 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1510 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args
;
1513 memset(&args
, 0, sizeof(args
));
1515 switch (radeon_encoder
->encoder_id
) {
1516 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
1517 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
1518 index
= GetIndexIntoMasterTable(COMMAND
, TMDSAOutputControl
);
1520 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
1521 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
1522 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1523 index
= GetIndexIntoMasterTable(COMMAND
, DVOOutputControl
);
1525 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
1526 index
= GetIndexIntoMasterTable(COMMAND
, LCD1OutputControl
);
1528 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
1529 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
1530 index
= GetIndexIntoMasterTable(COMMAND
, LCD1OutputControl
);
1532 index
= GetIndexIntoMasterTable(COMMAND
, LVTMAOutputControl
);
1534 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
1535 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1536 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1537 index
= GetIndexIntoMasterTable(COMMAND
, TV1OutputControl
);
1538 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1539 index
= GetIndexIntoMasterTable(COMMAND
, CV1OutputControl
);
1541 index
= GetIndexIntoMasterTable(COMMAND
, DAC1OutputControl
);
1543 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
1544 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1545 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1546 index
= GetIndexIntoMasterTable(COMMAND
, TV1OutputControl
);
1547 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1548 index
= GetIndexIntoMasterTable(COMMAND
, CV1OutputControl
);
1550 index
= GetIndexIntoMasterTable(COMMAND
, DAC2OutputControl
);
1557 case DRM_MODE_DPMS_ON
:
1558 args
.ucAction
= ATOM_ENABLE
;
1559 /* workaround for DVOOutputControl on some RS690 systems */
1560 if (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DDI
) {
1561 u32 reg
= RREG32(RADEON_BIOS_3_SCRATCH
);
1562 WREG32(RADEON_BIOS_3_SCRATCH
, reg
& ~ATOM_S3_DFP2I_ACTIVE
);
1563 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1564 WREG32(RADEON_BIOS_3_SCRATCH
, reg
);
1566 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1567 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1568 args
.ucAction
= ATOM_LCD_BLON
;
1569 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1572 case DRM_MODE_DPMS_STANDBY
:
1573 case DRM_MODE_DPMS_SUSPEND
:
1574 case DRM_MODE_DPMS_OFF
:
1575 args
.ucAction
= ATOM_DISABLE
;
1576 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1577 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1578 args
.ucAction
= ATOM_LCD_BLOFF
;
1579 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1586 radeon_atom_encoder_dpms_dig(struct drm_encoder
*encoder
, int mode
)
1588 struct drm_device
*dev
= encoder
->dev
;
1589 struct radeon_device
*rdev
= dev
->dev_private
;
1590 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1591 struct drm_encoder
*ext_encoder
= radeon_get_external_encoder(encoder
);
1592 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
1593 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
1594 struct radeon_connector
*radeon_connector
= NULL
;
1595 struct radeon_connector_atom_dig
*radeon_dig_connector
= NULL
;
1598 radeon_connector
= to_radeon_connector(connector
);
1599 radeon_dig_connector
= radeon_connector
->con_priv
;
1603 case DRM_MODE_DPMS_ON
:
1604 if (ASIC_IS_DCE41(rdev
) || ASIC_IS_DCE5(rdev
)) {
1606 dig
->panel_mode
= DP_PANEL_MODE_EXTERNAL_DP_MODE
;
1608 dig
->panel_mode
= radeon_dp_get_panel_mode(encoder
, connector
);
1610 /* setup and enable the encoder */
1611 atombios_dig_encoder_setup(encoder
, ATOM_ENCODER_CMD_SETUP
, 0);
1612 atombios_dig_encoder_setup(encoder
,
1613 ATOM_ENCODER_CMD_SETUP_PANEL_MODE
,
1616 if (ASIC_IS_DCE41(rdev
) || ASIC_IS_DCE61(rdev
))
1617 atombios_external_encoder_setup(encoder
, ext_encoder
,
1618 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP
);
1620 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_ENABLE
, 0, 0);
1621 } else if (ASIC_IS_DCE4(rdev
)) {
1622 /* setup and enable the encoder */
1623 atombios_dig_encoder_setup(encoder
, ATOM_ENCODER_CMD_SETUP
, 0);
1624 /* enable the transmitter */
1625 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_ENABLE
, 0, 0);
1626 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT
, 0, 0);
1628 /* setup and enable the encoder and transmitter */
1629 atombios_dig_encoder_setup(encoder
, ATOM_ENABLE
, 0);
1630 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_SETUP
, 0, 0);
1631 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_ENABLE
, 0, 0);
1632 /* some early dce3.2 boards have a bug in their transmitter control table */
1633 if ((rdev
->family
!= CHIP_RV710
) && (rdev
->family
!= CHIP_RV730
))
1634 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT
, 0, 0);
1636 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder
)) && connector
) {
1637 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
) {
1638 atombios_set_edp_panel_power(connector
,
1639 ATOM_TRANSMITTER_ACTION_POWER_ON
);
1640 radeon_dig_connector
->edp_on
= true;
1642 radeon_dp_link_train(encoder
, connector
);
1643 if (ASIC_IS_DCE4(rdev
))
1644 atombios_dig_encoder_setup(encoder
, ATOM_ENCODER_CMD_DP_VIDEO_ON
, 0);
1646 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
1647 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_LCD_BLON
, 0, 0);
1649 case DRM_MODE_DPMS_STANDBY
:
1650 case DRM_MODE_DPMS_SUSPEND
:
1651 case DRM_MODE_DPMS_OFF
:
1652 if (ASIC_IS_DCE41(rdev
) || ASIC_IS_DCE5(rdev
)) {
1653 /* disable the transmitter */
1654 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_DISABLE
, 0, 0);
1655 } else if (ASIC_IS_DCE4(rdev
)) {
1656 /* disable the transmitter */
1657 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT
, 0, 0);
1658 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_DISABLE
, 0, 0);
1660 /* disable the encoder and transmitter */
1661 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT
, 0, 0);
1662 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_DISABLE
, 0, 0);
1663 atombios_dig_encoder_setup(encoder
, ATOM_DISABLE
, 0);
1665 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder
)) && connector
) {
1666 if (ASIC_IS_DCE4(rdev
))
1667 atombios_dig_encoder_setup(encoder
, ATOM_ENCODER_CMD_DP_VIDEO_OFF
, 0);
1668 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
) {
1669 atombios_set_edp_panel_power(connector
,
1670 ATOM_TRANSMITTER_ACTION_POWER_OFF
);
1671 radeon_dig_connector
->edp_on
= false;
1674 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
1675 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_LCD_BLOFF
, 0, 0);
1681 radeon_atom_encoder_dpms_ext(struct drm_encoder
*encoder
,
1682 struct drm_encoder
*ext_encoder
,
1685 struct drm_device
*dev
= encoder
->dev
;
1686 struct radeon_device
*rdev
= dev
->dev_private
;
1689 case DRM_MODE_DPMS_ON
:
1691 if (ASIC_IS_DCE41(rdev
) || ASIC_IS_DCE61(rdev
)) {
1692 atombios_external_encoder_setup(encoder
, ext_encoder
,
1693 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT
);
1694 atombios_external_encoder_setup(encoder
, ext_encoder
,
1695 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF
);
1697 atombios_external_encoder_setup(encoder
, ext_encoder
, ATOM_ENABLE
);
1699 case DRM_MODE_DPMS_STANDBY
:
1700 case DRM_MODE_DPMS_SUSPEND
:
1701 case DRM_MODE_DPMS_OFF
:
1702 if (ASIC_IS_DCE41(rdev
) || ASIC_IS_DCE61(rdev
)) {
1703 atombios_external_encoder_setup(encoder
, ext_encoder
,
1704 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING
);
1705 atombios_external_encoder_setup(encoder
, ext_encoder
,
1706 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT
);
1708 atombios_external_encoder_setup(encoder
, ext_encoder
, ATOM_DISABLE
);
1714 radeon_atom_encoder_dpms(struct drm_encoder
*encoder
, int mode
)
1716 struct drm_device
*dev
= encoder
->dev
;
1717 struct radeon_device
*rdev
= dev
->dev_private
;
1718 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1719 struct drm_encoder
*ext_encoder
= radeon_get_external_encoder(encoder
);
1721 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1722 radeon_encoder
->encoder_id
, mode
, radeon_encoder
->devices
,
1723 radeon_encoder
->active_device
);
1724 switch (radeon_encoder
->encoder_id
) {
1725 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
1726 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
1727 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
1728 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
1729 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
1730 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
1731 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
1732 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1733 radeon_atom_encoder_dpms_avivo(encoder
, mode
);
1735 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1736 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1737 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1738 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1739 radeon_atom_encoder_dpms_dig(encoder
, mode
);
1741 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1742 if (ASIC_IS_DCE5(rdev
)) {
1744 case DRM_MODE_DPMS_ON
:
1745 atombios_dvo_setup(encoder
, ATOM_ENABLE
);
1747 case DRM_MODE_DPMS_STANDBY
:
1748 case DRM_MODE_DPMS_SUSPEND
:
1749 case DRM_MODE_DPMS_OFF
:
1750 atombios_dvo_setup(encoder
, ATOM_DISABLE
);
1753 } else if (ASIC_IS_DCE3(rdev
))
1754 radeon_atom_encoder_dpms_dig(encoder
, mode
);
1756 radeon_atom_encoder_dpms_avivo(encoder
, mode
);
1758 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
1759 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1760 if (ASIC_IS_DCE5(rdev
)) {
1762 case DRM_MODE_DPMS_ON
:
1763 atombios_dac_setup(encoder
, ATOM_ENABLE
);
1765 case DRM_MODE_DPMS_STANDBY
:
1766 case DRM_MODE_DPMS_SUSPEND
:
1767 case DRM_MODE_DPMS_OFF
:
1768 atombios_dac_setup(encoder
, ATOM_DISABLE
);
1772 radeon_atom_encoder_dpms_avivo(encoder
, mode
);
1779 radeon_atom_encoder_dpms_ext(encoder
, ext_encoder
, mode
);
1781 radeon_atombios_encoder_dpms_scratch_regs(encoder
, (mode
== DRM_MODE_DPMS_ON
) ? true : false);
1785 union crtc_source_param
{
1786 SELECT_CRTC_SOURCE_PS_ALLOCATION v1
;
1787 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2
;
1791 atombios_set_encoder_crtc_source(struct drm_encoder
*encoder
)
1793 struct drm_device
*dev
= encoder
->dev
;
1794 struct radeon_device
*rdev
= dev
->dev_private
;
1795 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1796 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1797 union crtc_source_param args
;
1798 int index
= GetIndexIntoMasterTable(COMMAND
, SelectCRTC_Source
);
1800 struct radeon_encoder_atom_dig
*dig
;
1802 memset(&args
, 0, sizeof(args
));
1804 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1812 if (ASIC_IS_AVIVO(rdev
))
1813 args
.v1
.ucCRTC
= radeon_crtc
->crtc_id
;
1815 if (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DAC1
) {
1816 args
.v1
.ucCRTC
= radeon_crtc
->crtc_id
;
1818 args
.v1
.ucCRTC
= radeon_crtc
->crtc_id
<< 2;
1821 switch (radeon_encoder
->encoder_id
) {
1822 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
1823 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
1824 args
.v1
.ucDevice
= ATOM_DEVICE_DFP1_INDEX
;
1826 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
1827 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
1828 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)
1829 args
.v1
.ucDevice
= ATOM_DEVICE_LCD1_INDEX
;
1831 args
.v1
.ucDevice
= ATOM_DEVICE_DFP3_INDEX
;
1833 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
1834 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
1835 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1836 args
.v1
.ucDevice
= ATOM_DEVICE_DFP2_INDEX
;
1838 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
1839 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1840 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1841 args
.v1
.ucDevice
= ATOM_DEVICE_TV1_INDEX
;
1842 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1843 args
.v1
.ucDevice
= ATOM_DEVICE_CV_INDEX
;
1845 args
.v1
.ucDevice
= ATOM_DEVICE_CRT1_INDEX
;
1847 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
1848 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1849 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1850 args
.v1
.ucDevice
= ATOM_DEVICE_TV1_INDEX
;
1851 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1852 args
.v1
.ucDevice
= ATOM_DEVICE_CV_INDEX
;
1854 args
.v1
.ucDevice
= ATOM_DEVICE_CRT2_INDEX
;
1859 args
.v2
.ucCRTC
= radeon_crtc
->crtc_id
;
1860 if (radeon_encoder_get_dp_bridge_encoder_id(encoder
) != ENCODER_OBJECT_ID_NONE
) {
1861 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
1863 if (connector
->connector_type
== DRM_MODE_CONNECTOR_LVDS
)
1864 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_LVDS
;
1865 else if (connector
->connector_type
== DRM_MODE_CONNECTOR_VGA
)
1866 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_CRT
;
1868 args
.v2
.ucEncodeMode
= atombios_get_encoder_mode(encoder
);
1870 args
.v2
.ucEncodeMode
= atombios_get_encoder_mode(encoder
);
1871 switch (radeon_encoder
->encoder_id
) {
1872 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1873 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1874 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1875 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1876 dig
= radeon_encoder
->enc_priv
;
1877 switch (dig
->dig_encoder
) {
1879 args
.v2
.ucEncoderID
= ASIC_INT_DIG1_ENCODER_ID
;
1882 args
.v2
.ucEncoderID
= ASIC_INT_DIG2_ENCODER_ID
;
1885 args
.v2
.ucEncoderID
= ASIC_INT_DIG3_ENCODER_ID
;
1888 args
.v2
.ucEncoderID
= ASIC_INT_DIG4_ENCODER_ID
;
1891 args
.v2
.ucEncoderID
= ASIC_INT_DIG5_ENCODER_ID
;
1894 args
.v2
.ucEncoderID
= ASIC_INT_DIG6_ENCODER_ID
;
1898 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1899 args
.v2
.ucEncoderID
= ASIC_INT_DVO_ENCODER_ID
;
1901 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1902 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1903 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1904 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1905 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1907 args
.v2
.ucEncoderID
= ASIC_INT_DAC1_ENCODER_ID
;
1909 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1910 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1911 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1912 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1913 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1915 args
.v2
.ucEncoderID
= ASIC_INT_DAC2_ENCODER_ID
;
1922 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1926 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1928 /* update scratch regs with new routing */
1929 radeon_atombios_encoder_crtc_scratch_regs(encoder
, radeon_crtc
->crtc_id
);
1933 atombios_apply_encoder_quirks(struct drm_encoder
*encoder
,
1934 struct drm_display_mode
*mode
)
1936 struct drm_device
*dev
= encoder
->dev
;
1937 struct radeon_device
*rdev
= dev
->dev_private
;
1938 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1939 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1941 /* Funky macbooks */
1942 if ((dev
->pdev
->device
== 0x71C5) &&
1943 (dev
->pdev
->subsystem_vendor
== 0x106b) &&
1944 (dev
->pdev
->subsystem_device
== 0x0080)) {
1945 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
1946 uint32_t lvtma_bit_depth_control
= RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL
);
1948 lvtma_bit_depth_control
&= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN
;
1949 lvtma_bit_depth_control
&= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN
;
1951 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL
, lvtma_bit_depth_control
);
1955 /* set scaler clears this on some chips */
1956 if (ASIC_IS_AVIVO(rdev
) &&
1957 (!(radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
)))) {
1958 if (ASIC_IS_DCE4(rdev
)) {
1959 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1960 WREG32(EVERGREEN_DATA_FORMAT
+ radeon_crtc
->crtc_offset
,
1961 EVERGREEN_INTERLEAVE_EN
);
1963 WREG32(EVERGREEN_DATA_FORMAT
+ radeon_crtc
->crtc_offset
, 0);
1965 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1966 WREG32(AVIVO_D1MODE_DATA_FORMAT
+ radeon_crtc
->crtc_offset
,
1967 AVIVO_D1MODE_INTERLEAVE_EN
);
1969 WREG32(AVIVO_D1MODE_DATA_FORMAT
+ radeon_crtc
->crtc_offset
, 0);
1974 static int radeon_atom_pick_dig_encoder(struct drm_encoder
*encoder
)
1976 struct drm_device
*dev
= encoder
->dev
;
1977 struct radeon_device
*rdev
= dev
->dev_private
;
1978 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1979 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1980 struct drm_encoder
*test_encoder
;
1981 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
1982 uint32_t dig_enc_in_use
= 0;
1984 if (ASIC_IS_DCE6(rdev
)) {
1986 switch (radeon_encoder
->encoder_id
) {
1987 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1993 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1999 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2006 } else if (ASIC_IS_DCE4(rdev
)) {
2008 if (ASIC_IS_DCE41(rdev
) && !ASIC_IS_DCE61(rdev
)) {
2009 /* ontario follows DCE4 */
2010 if (rdev
->family
== CHIP_PALM
) {
2016 /* llano follows DCE3.2 */
2017 return radeon_crtc
->crtc_id
;
2019 switch (radeon_encoder
->encoder_id
) {
2020 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2026 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2032 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2042 /* on DCE32 and encoder can driver any block so just crtc id */
2043 if (ASIC_IS_DCE32(rdev
)) {
2044 return radeon_crtc
->crtc_id
;
2047 /* on DCE3 - LVTMA can only be driven by DIGB */
2048 list_for_each_entry(test_encoder
, &dev
->mode_config
.encoder_list
, head
) {
2049 struct radeon_encoder
*radeon_test_encoder
;
2051 if (encoder
== test_encoder
)
2054 if (!radeon_encoder_is_digital(test_encoder
))
2057 radeon_test_encoder
= to_radeon_encoder(test_encoder
);
2058 dig
= radeon_test_encoder
->enc_priv
;
2060 if (dig
->dig_encoder
>= 0)
2061 dig_enc_in_use
|= (1 << dig
->dig_encoder
);
2064 if (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
) {
2065 if (dig_enc_in_use
& 0x2)
2066 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2069 if (!(dig_enc_in_use
& 1))
2074 /* This only needs to be called once at startup */
2076 radeon_atom_encoder_init(struct radeon_device
*rdev
)
2078 struct drm_device
*dev
= rdev
->ddev
;
2079 struct drm_encoder
*encoder
;
2081 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
2082 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2083 struct drm_encoder
*ext_encoder
= radeon_get_external_encoder(encoder
);
2085 switch (radeon_encoder
->encoder_id
) {
2086 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2087 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2088 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2089 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
2090 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_INIT
, 0, 0);
2096 if (ext_encoder
&& (ASIC_IS_DCE41(rdev
) || ASIC_IS_DCE61(rdev
)))
2097 atombios_external_encoder_setup(encoder
, ext_encoder
,
2098 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT
);
2103 radeon_atom_encoder_mode_set(struct drm_encoder
*encoder
,
2104 struct drm_display_mode
*mode
,
2105 struct drm_display_mode
*adjusted_mode
)
2107 struct drm_device
*dev
= encoder
->dev
;
2108 struct radeon_device
*rdev
= dev
->dev_private
;
2109 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2111 radeon_encoder
->pixel_clock
= adjusted_mode
->clock
;
2113 /* need to call this here rather than in prepare() since we need some crtc info */
2114 radeon_atom_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
2116 if (ASIC_IS_AVIVO(rdev
) && !ASIC_IS_DCE4(rdev
)) {
2117 if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
| ATOM_DEVICE_TV_SUPPORT
))
2118 atombios_yuv_setup(encoder
, true);
2120 atombios_yuv_setup(encoder
, false);
2123 switch (radeon_encoder
->encoder_id
) {
2124 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
2125 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
2126 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
2127 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
2128 atombios_digital_setup(encoder
, PANEL_ENCODER_ACTION_ENABLE
);
2130 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2131 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2132 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2133 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
2134 /* handled in dpms */
2136 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
2137 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
2138 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
2139 atombios_dvo_setup(encoder
, ATOM_ENABLE
);
2141 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
2142 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
2143 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
2144 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
2145 atombios_dac_setup(encoder
, ATOM_ENABLE
);
2146 if (radeon_encoder
->devices
& (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
)) {
2147 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
))
2148 atombios_tv_setup(encoder
, ATOM_ENABLE
);
2150 atombios_tv_setup(encoder
, ATOM_DISABLE
);
2155 atombios_apply_encoder_quirks(encoder
, adjusted_mode
);
2157 if (atombios_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
) {
2158 if (rdev
->asic
->display
.hdmi_enable
)
2159 radeon_hdmi_enable(rdev
, encoder
, true);
2160 if (rdev
->asic
->display
.hdmi_setmode
)
2161 radeon_hdmi_setmode(rdev
, encoder
, adjusted_mode
);
2166 atombios_dac_load_detect(struct drm_encoder
*encoder
, struct drm_connector
*connector
)
2168 struct drm_device
*dev
= encoder
->dev
;
2169 struct radeon_device
*rdev
= dev
->dev_private
;
2170 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2171 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
2173 if (radeon_encoder
->devices
& (ATOM_DEVICE_TV_SUPPORT
|
2174 ATOM_DEVICE_CV_SUPPORT
|
2175 ATOM_DEVICE_CRT_SUPPORT
)) {
2176 DAC_LOAD_DETECTION_PS_ALLOCATION args
;
2177 int index
= GetIndexIntoMasterTable(COMMAND
, DAC_LoadDetection
);
2180 memset(&args
, 0, sizeof(args
));
2182 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
2185 args
.sDacload
.ucMisc
= 0;
2187 if ((radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DAC1
) ||
2188 (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
))
2189 args
.sDacload
.ucDacType
= ATOM_DAC_A
;
2191 args
.sDacload
.ucDacType
= ATOM_DAC_B
;
2193 if (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)
2194 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT
);
2195 else if (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)
2196 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT
);
2197 else if (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
2198 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CV_SUPPORT
);
2200 args
.sDacload
.ucMisc
= DAC_LOAD_MISC_YPrPb
;
2201 } else if (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
2202 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT
);
2204 args
.sDacload
.ucMisc
= DAC_LOAD_MISC_YPrPb
;
2207 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2214 static enum drm_connector_status
2215 radeon_atom_dac_detect(struct drm_encoder
*encoder
, struct drm_connector
*connector
)
2217 struct drm_device
*dev
= encoder
->dev
;
2218 struct radeon_device
*rdev
= dev
->dev_private
;
2219 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2220 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
2221 uint32_t bios_0_scratch
;
2223 if (!atombios_dac_load_detect(encoder
, connector
)) {
2224 DRM_DEBUG_KMS("detect returned false \n");
2225 return connector_status_unknown
;
2228 if (rdev
->family
>= CHIP_R600
)
2229 bios_0_scratch
= RREG32(R600_BIOS_0_SCRATCH
);
2231 bios_0_scratch
= RREG32(RADEON_BIOS_0_SCRATCH
);
2233 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch
, radeon_encoder
->devices
);
2234 if (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
2235 if (bios_0_scratch
& ATOM_S0_CRT1_MASK
)
2236 return connector_status_connected
;
2238 if (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
2239 if (bios_0_scratch
& ATOM_S0_CRT2_MASK
)
2240 return connector_status_connected
;
2242 if (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
2243 if (bios_0_scratch
& (ATOM_S0_CV_MASK
|ATOM_S0_CV_MASK_A
))
2244 return connector_status_connected
;
2246 if (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
2247 if (bios_0_scratch
& (ATOM_S0_TV1_COMPOSITE
| ATOM_S0_TV1_COMPOSITE_A
))
2248 return connector_status_connected
; /* CTV */
2249 else if (bios_0_scratch
& (ATOM_S0_TV1_SVIDEO
| ATOM_S0_TV1_SVIDEO_A
))
2250 return connector_status_connected
; /* STV */
2252 return connector_status_disconnected
;
2255 static enum drm_connector_status
2256 radeon_atom_dig_detect(struct drm_encoder
*encoder
, struct drm_connector
*connector
)
2258 struct drm_device
*dev
= encoder
->dev
;
2259 struct radeon_device
*rdev
= dev
->dev_private
;
2260 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2261 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
2262 struct drm_encoder
*ext_encoder
= radeon_get_external_encoder(encoder
);
2265 if (!ASIC_IS_DCE4(rdev
))
2266 return connector_status_unknown
;
2269 return connector_status_unknown
;
2271 if ((radeon_connector
->devices
& ATOM_DEVICE_CRT_SUPPORT
) == 0)
2272 return connector_status_unknown
;
2274 /* load detect on the dp bridge */
2275 atombios_external_encoder_setup(encoder
, ext_encoder
,
2276 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION
);
2278 bios_0_scratch
= RREG32(R600_BIOS_0_SCRATCH
);
2280 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch
, radeon_encoder
->devices
);
2281 if (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
2282 if (bios_0_scratch
& ATOM_S0_CRT1_MASK
)
2283 return connector_status_connected
;
2285 if (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
2286 if (bios_0_scratch
& ATOM_S0_CRT2_MASK
)
2287 return connector_status_connected
;
2289 if (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
2290 if (bios_0_scratch
& (ATOM_S0_CV_MASK
|ATOM_S0_CV_MASK_A
))
2291 return connector_status_connected
;
2293 if (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
2294 if (bios_0_scratch
& (ATOM_S0_TV1_COMPOSITE
| ATOM_S0_TV1_COMPOSITE_A
))
2295 return connector_status_connected
; /* CTV */
2296 else if (bios_0_scratch
& (ATOM_S0_TV1_SVIDEO
| ATOM_S0_TV1_SVIDEO_A
))
2297 return connector_status_connected
; /* STV */
2299 return connector_status_disconnected
;
2303 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder
*encoder
)
2305 struct drm_encoder
*ext_encoder
= radeon_get_external_encoder(encoder
);
2308 /* ddc_setup on the dp bridge */
2309 atombios_external_encoder_setup(encoder
, ext_encoder
,
2310 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP
);
2314 static void radeon_atom_encoder_prepare(struct drm_encoder
*encoder
)
2316 struct radeon_device
*rdev
= encoder
->dev
->dev_private
;
2317 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2318 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
2320 if ((radeon_encoder
->active_device
&
2321 (ATOM_DEVICE_DFP_SUPPORT
| ATOM_DEVICE_LCD_SUPPORT
)) ||
2322 (radeon_encoder_get_dp_bridge_encoder_id(encoder
) !=
2323 ENCODER_OBJECT_ID_NONE
)) {
2324 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
2326 dig
->dig_encoder
= radeon_atom_pick_dig_encoder(encoder
);
2327 if (radeon_encoder
->active_device
& ATOM_DEVICE_DFP_SUPPORT
) {
2328 if (rdev
->family
>= CHIP_R600
)
2329 dig
->afmt
= rdev
->mode_info
.afmt
[dig
->dig_encoder
];
2331 /* RS600/690/740 have only 1 afmt block */
2332 dig
->afmt
= rdev
->mode_info
.afmt
[0];
2337 radeon_atom_output_lock(encoder
, true);
2340 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
2342 /* select the clock/data port if it uses a router */
2343 if (radeon_connector
->router
.cd_valid
)
2344 radeon_router_select_cd_port(radeon_connector
);
2346 /* turn eDP panel on for mode set */
2347 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
2348 atombios_set_edp_panel_power(connector
,
2349 ATOM_TRANSMITTER_ACTION_POWER_ON
);
2352 /* this is needed for the pll/ss setup to work correctly in some cases */
2353 atombios_set_encoder_crtc_source(encoder
);
2356 static void radeon_atom_encoder_commit(struct drm_encoder
*encoder
)
2358 /* need to call this here as we need the crtc set up */
2359 radeon_atom_encoder_dpms(encoder
, DRM_MODE_DPMS_ON
);
2360 radeon_atom_output_lock(encoder
, false);
2363 static void radeon_atom_encoder_disable(struct drm_encoder
*encoder
)
2365 struct drm_device
*dev
= encoder
->dev
;
2366 struct radeon_device
*rdev
= dev
->dev_private
;
2367 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2368 struct radeon_encoder_atom_dig
*dig
;
2370 /* check for pre-DCE3 cards with shared encoders;
2371 * can't really use the links individually, so don't disable
2372 * the encoder if it's in use by another connector
2374 if (!ASIC_IS_DCE3(rdev
)) {
2375 struct drm_encoder
*other_encoder
;
2376 struct radeon_encoder
*other_radeon_encoder
;
2378 list_for_each_entry(other_encoder
, &dev
->mode_config
.encoder_list
, head
) {
2379 other_radeon_encoder
= to_radeon_encoder(other_encoder
);
2380 if ((radeon_encoder
->encoder_id
== other_radeon_encoder
->encoder_id
) &&
2381 drm_helper_encoder_in_use(other_encoder
))
2386 radeon_atom_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
2388 switch (radeon_encoder
->encoder_id
) {
2389 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
2390 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
2391 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
2392 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
2393 atombios_digital_setup(encoder
, PANEL_ENCODER_ACTION_DISABLE
);
2395 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2396 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2397 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2398 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
2399 /* handled in dpms */
2401 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
2402 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
2403 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
2404 atombios_dvo_setup(encoder
, ATOM_DISABLE
);
2406 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
2407 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
2408 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
2409 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
2410 atombios_dac_setup(encoder
, ATOM_DISABLE
);
2411 if (radeon_encoder
->devices
& (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
))
2412 atombios_tv_setup(encoder
, ATOM_DISABLE
);
2417 if (radeon_encoder_is_digital(encoder
)) {
2418 if (atombios_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
) {
2419 if (rdev
->asic
->display
.hdmi_enable
)
2420 radeon_hdmi_enable(rdev
, encoder
, false);
2422 dig
= radeon_encoder
->enc_priv
;
2423 dig
->dig_encoder
= -1;
2425 radeon_encoder
->active_device
= 0;
2428 /* these are handled by the primary encoders */
2429 static void radeon_atom_ext_prepare(struct drm_encoder
*encoder
)
2434 static void radeon_atom_ext_commit(struct drm_encoder
*encoder
)
2440 radeon_atom_ext_mode_set(struct drm_encoder
*encoder
,
2441 struct drm_display_mode
*mode
,
2442 struct drm_display_mode
*adjusted_mode
)
2447 static void radeon_atom_ext_disable(struct drm_encoder
*encoder
)
2453 radeon_atom_ext_dpms(struct drm_encoder
*encoder
, int mode
)
2458 static bool radeon_atom_ext_mode_fixup(struct drm_encoder
*encoder
,
2459 const struct drm_display_mode
*mode
,
2460 struct drm_display_mode
*adjusted_mode
)
2465 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs
= {
2466 .dpms
= radeon_atom_ext_dpms
,
2467 .mode_fixup
= radeon_atom_ext_mode_fixup
,
2468 .prepare
= radeon_atom_ext_prepare
,
2469 .mode_set
= radeon_atom_ext_mode_set
,
2470 .commit
= radeon_atom_ext_commit
,
2471 .disable
= radeon_atom_ext_disable
,
2472 /* no detect for TMDS/LVDS yet */
2475 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs
= {
2476 .dpms
= radeon_atom_encoder_dpms
,
2477 .mode_fixup
= radeon_atom_mode_fixup
,
2478 .prepare
= radeon_atom_encoder_prepare
,
2479 .mode_set
= radeon_atom_encoder_mode_set
,
2480 .commit
= radeon_atom_encoder_commit
,
2481 .disable
= radeon_atom_encoder_disable
,
2482 .detect
= radeon_atom_dig_detect
,
2485 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs
= {
2486 .dpms
= radeon_atom_encoder_dpms
,
2487 .mode_fixup
= radeon_atom_mode_fixup
,
2488 .prepare
= radeon_atom_encoder_prepare
,
2489 .mode_set
= radeon_atom_encoder_mode_set
,
2490 .commit
= radeon_atom_encoder_commit
,
2491 .detect
= radeon_atom_dac_detect
,
2494 void radeon_enc_destroy(struct drm_encoder
*encoder
)
2496 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2497 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
2498 radeon_atom_backlight_exit(radeon_encoder
);
2499 kfree(radeon_encoder
->enc_priv
);
2500 drm_encoder_cleanup(encoder
);
2501 kfree(radeon_encoder
);
2504 static const struct drm_encoder_funcs radeon_atom_enc_funcs
= {
2505 .destroy
= radeon_enc_destroy
,
2508 static struct radeon_encoder_atom_dac
*
2509 radeon_atombios_set_dac_info(struct radeon_encoder
*radeon_encoder
)
2511 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
2512 struct radeon_device
*rdev
= dev
->dev_private
;
2513 struct radeon_encoder_atom_dac
*dac
= kzalloc(sizeof(struct radeon_encoder_atom_dac
), GFP_KERNEL
);
2518 dac
->tv_std
= radeon_atombios_get_tv_info(rdev
);
2522 static struct radeon_encoder_atom_dig
*
2523 radeon_atombios_set_dig_info(struct radeon_encoder
*radeon_encoder
)
2525 int encoder_enum
= (radeon_encoder
->encoder_enum
& ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
2526 struct radeon_encoder_atom_dig
*dig
= kzalloc(sizeof(struct radeon_encoder_atom_dig
), GFP_KERNEL
);
2531 /* coherent mode by default */
2532 dig
->coherent_mode
= true;
2533 dig
->dig_encoder
= -1;
2535 if (encoder_enum
== 2)
2544 radeon_add_atom_encoder(struct drm_device
*dev
,
2545 uint32_t encoder_enum
,
2546 uint32_t supported_device
,
2549 struct radeon_device
*rdev
= dev
->dev_private
;
2550 struct drm_encoder
*encoder
;
2551 struct radeon_encoder
*radeon_encoder
;
2553 /* see if we already added it */
2554 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
2555 radeon_encoder
= to_radeon_encoder(encoder
);
2556 if (radeon_encoder
->encoder_enum
== encoder_enum
) {
2557 radeon_encoder
->devices
|= supported_device
;
2564 radeon_encoder
= kzalloc(sizeof(struct radeon_encoder
), GFP_KERNEL
);
2565 if (!radeon_encoder
)
2568 encoder
= &radeon_encoder
->base
;
2569 switch (rdev
->num_crtc
) {
2571 encoder
->possible_crtcs
= 0x1;
2575 encoder
->possible_crtcs
= 0x3;
2578 encoder
->possible_crtcs
= 0xf;
2581 encoder
->possible_crtcs
= 0x3f;
2585 radeon_encoder
->enc_priv
= NULL
;
2587 radeon_encoder
->encoder_enum
= encoder_enum
;
2588 radeon_encoder
->encoder_id
= (encoder_enum
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
2589 radeon_encoder
->devices
= supported_device
;
2590 radeon_encoder
->rmx_type
= RMX_OFF
;
2591 radeon_encoder
->underscan_type
= UNDERSCAN_OFF
;
2592 radeon_encoder
->is_ext_encoder
= false;
2593 radeon_encoder
->caps
= caps
;
2595 switch (radeon_encoder
->encoder_id
) {
2596 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
2597 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
2598 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
2599 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
2600 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
2601 radeon_encoder
->rmx_type
= RMX_FULL
;
2602 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_LVDS
);
2603 radeon_encoder
->enc_priv
= radeon_atombios_get_lvds_info(radeon_encoder
);
2605 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TMDS
);
2606 radeon_encoder
->enc_priv
= radeon_atombios_set_dig_info(radeon_encoder
);
2608 drm_encoder_helper_add(encoder
, &radeon_atom_dig_helper_funcs
);
2610 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
2611 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_DAC
);
2612 radeon_encoder
->enc_priv
= radeon_atombios_set_dac_info(radeon_encoder
);
2613 drm_encoder_helper_add(encoder
, &radeon_atom_dac_helper_funcs
);
2615 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
2616 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
2617 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
2618 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TVDAC
);
2619 radeon_encoder
->enc_priv
= radeon_atombios_set_dac_info(radeon_encoder
);
2620 drm_encoder_helper_add(encoder
, &radeon_atom_dac_helper_funcs
);
2622 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
2623 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
2624 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
2625 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2626 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
2627 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2628 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2629 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
2630 radeon_encoder
->rmx_type
= RMX_FULL
;
2631 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_LVDS
);
2632 radeon_encoder
->enc_priv
= radeon_atombios_get_lvds_info(radeon_encoder
);
2633 } else if (radeon_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
)) {
2634 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_DAC
);
2635 radeon_encoder
->enc_priv
= radeon_atombios_set_dig_info(radeon_encoder
);
2637 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TMDS
);
2638 radeon_encoder
->enc_priv
= radeon_atombios_set_dig_info(radeon_encoder
);
2640 drm_encoder_helper_add(encoder
, &radeon_atom_dig_helper_funcs
);
2642 case ENCODER_OBJECT_ID_SI170B
:
2643 case ENCODER_OBJECT_ID_CH7303
:
2644 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA
:
2645 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB
:
2646 case ENCODER_OBJECT_ID_TITFP513
:
2647 case ENCODER_OBJECT_ID_VT1623
:
2648 case ENCODER_OBJECT_ID_HDMI_SI1930
:
2649 case ENCODER_OBJECT_ID_TRAVIS
:
2650 case ENCODER_OBJECT_ID_NUTMEG
:
2651 /* these are handled by the primary encoders */
2652 radeon_encoder
->is_ext_encoder
= true;
2653 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
2654 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_LVDS
);
2655 else if (radeon_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
))
2656 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_DAC
);
2658 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TMDS
);
2659 drm_encoder_helper_add(encoder
, &radeon_atom_ext_helper_funcs
);