2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
31 #include <linux/backlight.h>
33 extern int atom_debug
;
36 radeon_atom_get_backlight_level_from_reg(struct radeon_device
*rdev
)
41 if (rdev
->family
>= CHIP_R600
)
42 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
44 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
46 backlight_level
= ((bios_2_scratch
& ATOM_S2_CURRENT_BL_LEVEL_MASK
) >>
47 ATOM_S2_CURRENT_BL_LEVEL_SHIFT
);
49 return backlight_level
;
53 radeon_atom_set_backlight_level_to_reg(struct radeon_device
*rdev
,
58 if (rdev
->family
>= CHIP_R600
)
59 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
61 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
63 bios_2_scratch
&= ~ATOM_S2_CURRENT_BL_LEVEL_MASK
;
64 bios_2_scratch
|= ((backlight_level
<< ATOM_S2_CURRENT_BL_LEVEL_SHIFT
) &
65 ATOM_S2_CURRENT_BL_LEVEL_MASK
);
67 if (rdev
->family
>= CHIP_R600
)
68 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
70 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);
74 atombios_get_backlight_level(struct radeon_encoder
*radeon_encoder
)
76 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
77 struct radeon_device
*rdev
= dev
->dev_private
;
79 if (!(rdev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
82 return radeon_atom_get_backlight_level_from_reg(rdev
);
86 atombios_set_backlight_level(struct radeon_encoder
*radeon_encoder
, u8 level
)
88 struct drm_encoder
*encoder
= &radeon_encoder
->base
;
89 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
90 struct radeon_device
*rdev
= dev
->dev_private
;
91 struct radeon_encoder_atom_dig
*dig
;
92 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args
;
95 if (!(rdev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
98 if ((radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) &&
99 radeon_encoder
->enc_priv
) {
100 dig
= radeon_encoder
->enc_priv
;
101 dig
->backlight_level
= level
;
102 radeon_atom_set_backlight_level_to_reg(rdev
, dig
->backlight_level
);
104 switch (radeon_encoder
->encoder_id
) {
105 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
106 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
107 index
= GetIndexIntoMasterTable(COMMAND
, LCD1OutputControl
);
108 if (dig
->backlight_level
== 0) {
109 args
.ucAction
= ATOM_LCD_BLOFF
;
110 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
112 args
.ucAction
= ATOM_LCD_BL_BRIGHTNESS_CONTROL
;
113 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
114 args
.ucAction
= ATOM_LCD_BLON
;
115 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
118 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
119 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
120 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
122 if (dig
->backlight_level
== 0)
123 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_LCD_BLOFF
, 0, 0);
125 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL
, 0, 0);
126 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_LCD_BLON
, 0, 0);
135 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
137 static u8
radeon_atom_bl_level(struct backlight_device
*bd
)
141 /* Convert brightness to hardware level */
142 if (bd
->props
.brightness
< 0)
144 else if (bd
->props
.brightness
> RADEON_MAX_BL_LEVEL
)
145 level
= RADEON_MAX_BL_LEVEL
;
147 level
= bd
->props
.brightness
;
152 static int radeon_atom_backlight_update_status(struct backlight_device
*bd
)
154 struct radeon_backlight_privdata
*pdata
= bl_get_data(bd
);
155 struct radeon_encoder
*radeon_encoder
= pdata
->encoder
;
157 atombios_set_backlight_level(radeon_encoder
, radeon_atom_bl_level(bd
));
162 static int radeon_atom_backlight_get_brightness(struct backlight_device
*bd
)
164 struct radeon_backlight_privdata
*pdata
= bl_get_data(bd
);
165 struct radeon_encoder
*radeon_encoder
= pdata
->encoder
;
166 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
167 struct radeon_device
*rdev
= dev
->dev_private
;
169 return radeon_atom_get_backlight_level_from_reg(rdev
);
172 static const struct backlight_ops radeon_atom_backlight_ops
= {
173 .get_brightness
= radeon_atom_backlight_get_brightness
,
174 .update_status
= radeon_atom_backlight_update_status
,
177 void radeon_atom_backlight_init(struct radeon_encoder
*radeon_encoder
,
178 struct drm_connector
*drm_connector
)
180 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
181 struct radeon_device
*rdev
= dev
->dev_private
;
182 struct backlight_device
*bd
;
183 struct backlight_properties props
;
184 struct radeon_backlight_privdata
*pdata
;
185 struct radeon_encoder_atom_dig
*dig
;
189 /* Mac laptops with multiple GPUs use the gmux driver for backlight
190 * so don't register a backlight device
192 if ((rdev
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_APPLE
) &&
193 (rdev
->pdev
->device
== 0x6741))
196 if (!radeon_encoder
->enc_priv
)
199 if (!rdev
->is_atom_bios
)
202 if (!(rdev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
205 pdata
= kmalloc(sizeof(struct radeon_backlight_privdata
), GFP_KERNEL
);
207 DRM_ERROR("Memory allocation failed\n");
211 memset(&props
, 0, sizeof(props
));
212 props
.max_brightness
= RADEON_MAX_BL_LEVEL
;
213 props
.type
= BACKLIGHT_RAW
;
214 snprintf(bl_name
, sizeof(bl_name
),
215 "radeon_bl%d", dev
->primary
->index
);
216 bd
= backlight_device_register(bl_name
, drm_connector
->kdev
,
217 pdata
, &radeon_atom_backlight_ops
, &props
);
219 DRM_ERROR("Backlight registration failed\n");
223 pdata
->encoder
= radeon_encoder
;
225 backlight_level
= radeon_atom_get_backlight_level_from_reg(rdev
);
227 dig
= radeon_encoder
->enc_priv
;
230 bd
->props
.brightness
= radeon_atom_backlight_get_brightness(bd
);
231 bd
->props
.power
= FB_BLANK_UNBLANK
;
232 backlight_update_status(bd
);
234 DRM_INFO("radeon atom DIG backlight initialized\n");
243 static void radeon_atom_backlight_exit(struct radeon_encoder
*radeon_encoder
)
245 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
246 struct radeon_device
*rdev
= dev
->dev_private
;
247 struct backlight_device
*bd
= NULL
;
248 struct radeon_encoder_atom_dig
*dig
;
250 if (!radeon_encoder
->enc_priv
)
253 if (!rdev
->is_atom_bios
)
256 if (!(rdev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
259 dig
= radeon_encoder
->enc_priv
;
264 struct radeon_legacy_backlight_privdata
*pdata
;
266 pdata
= bl_get_data(bd
);
267 backlight_device_unregister(bd
);
270 DRM_INFO("radeon atom LVDS backlight unloaded\n");
274 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
276 void radeon_atom_backlight_init(struct radeon_encoder
*encoder
)
280 static void radeon_atom_backlight_exit(struct radeon_encoder
*encoder
)
286 /* evil but including atombios.h is much worse */
287 bool radeon_atom_get_tv_timings(struct radeon_device
*rdev
, int index
,
288 struct drm_display_mode
*mode
);
291 static inline bool radeon_encoder_is_digital(struct drm_encoder
*encoder
)
293 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
294 switch (radeon_encoder
->encoder_id
) {
295 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
296 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
297 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
298 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
299 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
300 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
301 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
302 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
303 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
304 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
305 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
306 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
313 static bool radeon_atom_mode_fixup(struct drm_encoder
*encoder
,
314 const struct drm_display_mode
*mode
,
315 struct drm_display_mode
*adjusted_mode
)
317 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
318 struct drm_device
*dev
= encoder
->dev
;
319 struct radeon_device
*rdev
= dev
->dev_private
;
321 /* set the active encoder to connector routing */
322 radeon_encoder_set_active_device(encoder
);
323 drm_mode_set_crtcinfo(adjusted_mode
, 0);
326 if ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
327 && (mode
->crtc_vsync_start
< (mode
->crtc_vdisplay
+ 2)))
328 adjusted_mode
->crtc_vsync_start
= adjusted_mode
->crtc_vdisplay
+ 2;
330 /* get the native mode for LVDS */
331 if (radeon_encoder
->active_device
& (ATOM_DEVICE_LCD_SUPPORT
))
332 radeon_panel_mode_fixup(encoder
, adjusted_mode
);
334 /* get the native mode for TV */
335 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
)) {
336 struct radeon_encoder_atom_dac
*tv_dac
= radeon_encoder
->enc_priv
;
338 if (tv_dac
->tv_std
== TV_STD_NTSC
||
339 tv_dac
->tv_std
== TV_STD_NTSC_J
||
340 tv_dac
->tv_std
== TV_STD_PAL_M
)
341 radeon_atom_get_tv_timings(rdev
, 0, adjusted_mode
);
343 radeon_atom_get_tv_timings(rdev
, 1, adjusted_mode
);
347 if (ASIC_IS_DCE3(rdev
) &&
348 ((radeon_encoder
->active_device
& (ATOM_DEVICE_DFP_SUPPORT
| ATOM_DEVICE_LCD_SUPPORT
)) ||
349 (radeon_encoder_get_dp_bridge_encoder_id(encoder
) != ENCODER_OBJECT_ID_NONE
))) {
350 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
351 radeon_dp_set_link_config(connector
, adjusted_mode
);
358 atombios_dac_setup(struct drm_encoder
*encoder
, int action
)
360 struct drm_device
*dev
= encoder
->dev
;
361 struct radeon_device
*rdev
= dev
->dev_private
;
362 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
363 DAC_ENCODER_CONTROL_PS_ALLOCATION args
;
365 struct radeon_encoder_atom_dac
*dac_info
= radeon_encoder
->enc_priv
;
367 memset(&args
, 0, sizeof(args
));
369 switch (radeon_encoder
->encoder_id
) {
370 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
371 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
372 index
= GetIndexIntoMasterTable(COMMAND
, DAC1EncoderControl
);
374 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
375 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
376 index
= GetIndexIntoMasterTable(COMMAND
, DAC2EncoderControl
);
380 args
.ucAction
= action
;
382 if (radeon_encoder
->active_device
& (ATOM_DEVICE_CRT_SUPPORT
))
383 args
.ucDacStandard
= ATOM_DAC1_PS2
;
384 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
385 args
.ucDacStandard
= ATOM_DAC1_CV
;
387 switch (dac_info
->tv_std
) {
390 case TV_STD_SCART_PAL
:
393 args
.ucDacStandard
= ATOM_DAC1_PAL
;
399 args
.ucDacStandard
= ATOM_DAC1_NTSC
;
403 args
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
405 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
410 atombios_tv_setup(struct drm_encoder
*encoder
, int action
)
412 struct drm_device
*dev
= encoder
->dev
;
413 struct radeon_device
*rdev
= dev
->dev_private
;
414 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
415 TV_ENCODER_CONTROL_PS_ALLOCATION args
;
417 struct radeon_encoder_atom_dac
*dac_info
= radeon_encoder
->enc_priv
;
419 memset(&args
, 0, sizeof(args
));
421 index
= GetIndexIntoMasterTable(COMMAND
, TVEncoderControl
);
423 args
.sTVEncoder
.ucAction
= action
;
425 if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
426 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_CV
;
428 switch (dac_info
->tv_std
) {
430 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_NTSC
;
433 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PAL
;
436 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PALM
;
439 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PAL60
;
442 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_NTSCJ
;
444 case TV_STD_SCART_PAL
:
445 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PAL
; /* ??? */
448 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_SECAM
;
451 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PALCN
;
454 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_NTSC
;
459 args
.sTVEncoder
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
461 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
465 static u8
radeon_atom_get_bpc(struct drm_encoder
*encoder
)
470 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
471 bpc
= radeon_crtc
->bpc
;
476 return PANEL_BPC_UNDEFINE
;
478 return PANEL_6BIT_PER_COLOR
;
481 return PANEL_8BIT_PER_COLOR
;
483 return PANEL_10BIT_PER_COLOR
;
485 return PANEL_12BIT_PER_COLOR
;
487 return PANEL_16BIT_PER_COLOR
;
491 union dvo_encoder_control
{
492 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds
;
493 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo
;
494 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3
;
495 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4
;
499 atombios_dvo_setup(struct drm_encoder
*encoder
, int action
)
501 struct drm_device
*dev
= encoder
->dev
;
502 struct radeon_device
*rdev
= dev
->dev_private
;
503 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
504 union dvo_encoder_control args
;
505 int index
= GetIndexIntoMasterTable(COMMAND
, DVOEncoderControl
);
508 memset(&args
, 0, sizeof(args
));
510 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
513 /* some R4xx chips have the wrong frev */
514 if (rdev
->family
<= CHIP_RV410
)
522 args
.ext_tmds
.sXTmdsEncoder
.ucEnable
= action
;
524 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
525 args
.ext_tmds
.sXTmdsEncoder
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
527 args
.ext_tmds
.sXTmdsEncoder
.ucMisc
|= ATOM_PANEL_MISC_888RGB
;
531 args
.dvo
.sDVOEncoder
.ucAction
= action
;
532 args
.dvo
.sDVOEncoder
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
533 /* DFP1, CRT1, TV1 depending on the type of port */
534 args
.dvo
.sDVOEncoder
.ucDeviceType
= ATOM_DEVICE_DFP1_INDEX
;
536 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
537 args
.dvo
.sDVOEncoder
.usDevAttr
.sDigAttrib
.ucAttribute
|= PANEL_ENCODER_MISC_DUAL
;
541 args
.dvo_v3
.ucAction
= action
;
542 args
.dvo_v3
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
543 args
.dvo_v3
.ucDVOConfig
= 0; /* XXX */
547 args
.dvo_v4
.ucAction
= action
;
548 args
.dvo_v4
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
549 args
.dvo_v4
.ucDVOConfig
= 0; /* XXX */
550 args
.dvo_v4
.ucBitPerColor
= radeon_atom_get_bpc(encoder
);
553 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
558 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
562 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
565 union lvds_encoder_control
{
566 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1
;
567 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2
;
571 atombios_digital_setup(struct drm_encoder
*encoder
, int action
)
573 struct drm_device
*dev
= encoder
->dev
;
574 struct radeon_device
*rdev
= dev
->dev_private
;
575 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
576 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
577 union lvds_encoder_control args
;
579 int hdmi_detected
= 0;
585 if (atombios_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
)
588 memset(&args
, 0, sizeof(args
));
590 switch (radeon_encoder
->encoder_id
) {
591 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
592 index
= GetIndexIntoMasterTable(COMMAND
, LVDSEncoderControl
);
594 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
595 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
596 index
= GetIndexIntoMasterTable(COMMAND
, TMDS1EncoderControl
);
598 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
599 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
600 index
= GetIndexIntoMasterTable(COMMAND
, LVDSEncoderControl
);
602 index
= GetIndexIntoMasterTable(COMMAND
, TMDS2EncoderControl
);
606 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
615 args
.v1
.ucAction
= action
;
617 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_HDMI_TYPE
;
618 args
.v1
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
619 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
620 if (dig
->lcd_misc
& ATOM_PANEL_MISC_DUAL
)
621 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
622 if (dig
->lcd_misc
& ATOM_PANEL_MISC_888RGB
)
623 args
.v1
.ucMisc
|= ATOM_PANEL_MISC_888RGB
;
626 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_TMDS_LINKB
;
627 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
628 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
629 /*if (pScrn->rgbBits == 8) */
630 args
.v1
.ucMisc
|= ATOM_PANEL_MISC_888RGB
;
636 args
.v2
.ucAction
= action
;
638 if (dig
->coherent_mode
)
639 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_COHERENT
;
642 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_HDMI_TYPE
;
643 args
.v2
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
644 args
.v2
.ucTruncate
= 0;
645 args
.v2
.ucSpatial
= 0;
646 args
.v2
.ucTemporal
= 0;
648 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
649 if (dig
->lcd_misc
& ATOM_PANEL_MISC_DUAL
)
650 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
651 if (dig
->lcd_misc
& ATOM_PANEL_MISC_SPATIAL
) {
652 args
.v2
.ucSpatial
= PANEL_ENCODER_SPATIAL_DITHER_EN
;
653 if (dig
->lcd_misc
& ATOM_PANEL_MISC_888RGB
)
654 args
.v2
.ucSpatial
|= PANEL_ENCODER_SPATIAL_DITHER_DEPTH
;
656 if (dig
->lcd_misc
& ATOM_PANEL_MISC_TEMPORAL
) {
657 args
.v2
.ucTemporal
= PANEL_ENCODER_TEMPORAL_DITHER_EN
;
658 if (dig
->lcd_misc
& ATOM_PANEL_MISC_888RGB
)
659 args
.v2
.ucTemporal
|= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH
;
660 if (((dig
->lcd_misc
>> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT
) & 0x3) == 2)
661 args
.v2
.ucTemporal
|= PANEL_ENCODER_TEMPORAL_LEVEL_4
;
665 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_TMDS_LINKB
;
666 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
667 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
671 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
676 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
680 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
684 atombios_get_encoder_mode(struct drm_encoder
*encoder
)
686 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
687 struct drm_connector
*connector
;
688 struct radeon_connector
*radeon_connector
;
689 struct radeon_connector_atom_dig
*dig_connector
;
691 /* dp bridges are always DP */
692 if (radeon_encoder_get_dp_bridge_encoder_id(encoder
) != ENCODER_OBJECT_ID_NONE
)
693 return ATOM_ENCODER_MODE_DP
;
695 /* DVO is always DVO */
696 if ((radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DVO1
) ||
697 (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
))
698 return ATOM_ENCODER_MODE_DVO
;
700 connector
= radeon_get_connector_for_encoder(encoder
);
701 /* if we don't have an active device yet, just use one of
702 * the connectors tied to the encoder.
705 connector
= radeon_get_connector_for_encoder_init(encoder
);
706 radeon_connector
= to_radeon_connector(connector
);
708 switch (connector
->connector_type
) {
709 case DRM_MODE_CONNECTOR_DVII
:
710 case DRM_MODE_CONNECTOR_HDMIB
: /* HDMI-B is basically DL-DVI; analog works fine */
711 if (radeon_audio
!= 0) {
712 if (radeon_connector
->use_digital
&&
713 (radeon_connector
->audio
== RADEON_AUDIO_ENABLE
))
714 return ATOM_ENCODER_MODE_HDMI
;
715 else if (drm_detect_hdmi_monitor(radeon_connector
->edid
) &&
716 (radeon_connector
->audio
== RADEON_AUDIO_AUTO
))
717 return ATOM_ENCODER_MODE_HDMI
;
718 else if (radeon_connector
->use_digital
)
719 return ATOM_ENCODER_MODE_DVI
;
721 return ATOM_ENCODER_MODE_CRT
;
722 } else if (radeon_connector
->use_digital
) {
723 return ATOM_ENCODER_MODE_DVI
;
725 return ATOM_ENCODER_MODE_CRT
;
728 case DRM_MODE_CONNECTOR_DVID
:
729 case DRM_MODE_CONNECTOR_HDMIA
:
731 if (radeon_audio
!= 0) {
732 if (radeon_connector
->audio
== RADEON_AUDIO_ENABLE
)
733 return ATOM_ENCODER_MODE_HDMI
;
734 else if (drm_detect_hdmi_monitor(radeon_connector
->edid
) &&
735 (radeon_connector
->audio
== RADEON_AUDIO_AUTO
))
736 return ATOM_ENCODER_MODE_HDMI
;
738 return ATOM_ENCODER_MODE_DVI
;
740 return ATOM_ENCODER_MODE_DVI
;
743 case DRM_MODE_CONNECTOR_LVDS
:
744 return ATOM_ENCODER_MODE_LVDS
;
746 case DRM_MODE_CONNECTOR_DisplayPort
:
747 dig_connector
= radeon_connector
->con_priv
;
748 if ((dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_DISPLAYPORT
) ||
749 (dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_eDP
)) {
750 return ATOM_ENCODER_MODE_DP
;
751 } else if (radeon_audio
!= 0) {
752 if (radeon_connector
->audio
== RADEON_AUDIO_ENABLE
)
753 return ATOM_ENCODER_MODE_HDMI
;
754 else if (drm_detect_hdmi_monitor(radeon_connector
->edid
) &&
755 (radeon_connector
->audio
== RADEON_AUDIO_AUTO
))
756 return ATOM_ENCODER_MODE_HDMI
;
758 return ATOM_ENCODER_MODE_DVI
;
760 return ATOM_ENCODER_MODE_DVI
;
763 case DRM_MODE_CONNECTOR_eDP
:
764 return ATOM_ENCODER_MODE_DP
;
765 case DRM_MODE_CONNECTOR_DVIA
:
766 case DRM_MODE_CONNECTOR_VGA
:
767 return ATOM_ENCODER_MODE_CRT
;
769 case DRM_MODE_CONNECTOR_Composite
:
770 case DRM_MODE_CONNECTOR_SVIDEO
:
771 case DRM_MODE_CONNECTOR_9PinDIN
:
773 return ATOM_ENCODER_MODE_TV
;
774 /*return ATOM_ENCODER_MODE_CV;*/
780 * DIG Encoder/Transmitter Setup
783 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
784 * Supports up to 3 digital outputs
785 * - 2 DIG encoder blocks.
786 * DIG1 can drive UNIPHY link A or link B
787 * DIG2 can drive UNIPHY link B or LVTMA
790 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
791 * Supports up to 5 digital outputs
792 * - 2 DIG encoder blocks.
793 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
796 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
797 * Supports up to 6 digital outputs
798 * - 6 DIG encoder blocks.
799 * - DIG to PHY mapping is hardcoded
800 * DIG1 drives UNIPHY0 link A, A+B
801 * DIG2 drives UNIPHY0 link B
802 * DIG3 drives UNIPHY1 link A, A+B
803 * DIG4 drives UNIPHY1 link B
804 * DIG5 drives UNIPHY2 link A, A+B
805 * DIG6 drives UNIPHY2 link B
808 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
809 * Supports up to 6 digital outputs
810 * - 2 DIG encoder blocks.
812 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
814 * DIG1 drives UNIPHY0/1/2 link A
815 * DIG2 drives UNIPHY0/1/2 link B
818 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
820 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
821 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
822 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
823 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
826 union dig_encoder_control
{
827 DIG_ENCODER_CONTROL_PS_ALLOCATION v1
;
828 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2
;
829 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3
;
830 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4
;
834 atombios_dig_encoder_setup(struct drm_encoder
*encoder
, int action
, int panel_mode
)
836 struct drm_device
*dev
= encoder
->dev
;
837 struct radeon_device
*rdev
= dev
->dev_private
;
838 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
839 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
840 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
841 union dig_encoder_control args
;
845 int dp_lane_count
= 0;
846 int hpd_id
= RADEON_HPD_NONE
;
849 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
850 struct radeon_connector_atom_dig
*dig_connector
=
851 radeon_connector
->con_priv
;
853 dp_clock
= dig_connector
->dp_clock
;
854 dp_lane_count
= dig_connector
->dp_lane_count
;
855 hpd_id
= radeon_connector
->hpd
.hpd
;
858 /* no dig encoder assigned */
859 if (dig
->dig_encoder
== -1)
862 memset(&args
, 0, sizeof(args
));
864 if (ASIC_IS_DCE4(rdev
))
865 index
= GetIndexIntoMasterTable(COMMAND
, DIGxEncoderControl
);
867 if (dig
->dig_encoder
)
868 index
= GetIndexIntoMasterTable(COMMAND
, DIG2EncoderControl
);
870 index
= GetIndexIntoMasterTable(COMMAND
, DIG1EncoderControl
);
873 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
880 args
.v1
.ucAction
= action
;
881 args
.v1
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
882 if (action
== ATOM_ENCODER_CMD_SETUP_PANEL_MODE
)
883 args
.v3
.ucPanelMode
= panel_mode
;
885 args
.v1
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
887 if (ENCODER_MODE_IS_DP(args
.v1
.ucEncoderMode
))
888 args
.v1
.ucLaneNum
= dp_lane_count
;
889 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
890 args
.v1
.ucLaneNum
= 8;
892 args
.v1
.ucLaneNum
= 4;
894 if (ENCODER_MODE_IS_DP(args
.v1
.ucEncoderMode
) && (dp_clock
== 270000))
895 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ
;
896 switch (radeon_encoder
->encoder_id
) {
897 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
898 args
.v1
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER1
;
900 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
901 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
902 args
.v1
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER2
;
904 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
905 args
.v1
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER3
;
909 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_LINKB
;
911 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_LINKA
;
915 args
.v3
.ucAction
= action
;
916 args
.v3
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
917 if (action
== ATOM_ENCODER_CMD_SETUP_PANEL_MODE
)
918 args
.v3
.ucPanelMode
= panel_mode
;
920 args
.v3
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
922 if (ENCODER_MODE_IS_DP(args
.v3
.ucEncoderMode
))
923 args
.v3
.ucLaneNum
= dp_lane_count
;
924 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
925 args
.v3
.ucLaneNum
= 8;
927 args
.v3
.ucLaneNum
= 4;
929 if (ENCODER_MODE_IS_DP(args
.v3
.ucEncoderMode
) && (dp_clock
== 270000))
930 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ
;
931 args
.v3
.acConfig
.ucDigSel
= dig
->dig_encoder
;
932 args
.v3
.ucBitPerColor
= radeon_atom_get_bpc(encoder
);
935 args
.v4
.ucAction
= action
;
936 args
.v4
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
937 if (action
== ATOM_ENCODER_CMD_SETUP_PANEL_MODE
)
938 args
.v4
.ucPanelMode
= panel_mode
;
940 args
.v4
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
942 if (ENCODER_MODE_IS_DP(args
.v4
.ucEncoderMode
))
943 args
.v4
.ucLaneNum
= dp_lane_count
;
944 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
945 args
.v4
.ucLaneNum
= 8;
947 args
.v4
.ucLaneNum
= 4;
949 if (ENCODER_MODE_IS_DP(args
.v4
.ucEncoderMode
)) {
950 if (dp_clock
== 540000)
951 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ
;
952 else if (dp_clock
== 324000)
953 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ
;
954 else if (dp_clock
== 270000)
955 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ
;
957 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ
;
959 args
.v4
.acConfig
.ucDigSel
= dig
->dig_encoder
;
960 args
.v4
.ucBitPerColor
= radeon_atom_get_bpc(encoder
);
961 if (hpd_id
== RADEON_HPD_NONE
)
962 args
.v4
.ucHPD_ID
= 0;
964 args
.v4
.ucHPD_ID
= hpd_id
+ 1;
967 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
972 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
976 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
980 union dig_transmitter_control
{
981 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1
;
982 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2
;
983 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3
;
984 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4
;
985 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5
;
989 atombios_dig_transmitter_setup(struct drm_encoder
*encoder
, int action
, uint8_t lane_num
, uint8_t lane_set
)
991 struct drm_device
*dev
= encoder
->dev
;
992 struct radeon_device
*rdev
= dev
->dev_private
;
993 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
994 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
995 struct drm_connector
*connector
;
996 union dig_transmitter_control args
;
1002 int dp_lane_count
= 0;
1003 int connector_object_id
= 0;
1004 int igp_lane_info
= 0;
1005 int dig_encoder
= dig
->dig_encoder
;
1006 int hpd_id
= RADEON_HPD_NONE
;
1008 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
1009 connector
= radeon_get_connector_for_encoder_init(encoder
);
1010 /* just needed to avoid bailing in the encoder check. the encoder
1011 * isn't used for init
1015 connector
= radeon_get_connector_for_encoder(encoder
);
1018 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
1019 struct radeon_connector_atom_dig
*dig_connector
=
1020 radeon_connector
->con_priv
;
1022 hpd_id
= radeon_connector
->hpd
.hpd
;
1023 dp_clock
= dig_connector
->dp_clock
;
1024 dp_lane_count
= dig_connector
->dp_lane_count
;
1025 connector_object_id
=
1026 (radeon_connector
->connector_object_id
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
1027 igp_lane_info
= dig_connector
->igp_lane_info
;
1030 if (encoder
->crtc
) {
1031 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1032 pll_id
= radeon_crtc
->pll_id
;
1035 /* no dig encoder assigned */
1036 if (dig_encoder
== -1)
1039 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder
)))
1042 memset(&args
, 0, sizeof(args
));
1044 switch (radeon_encoder
->encoder_id
) {
1045 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1046 index
= GetIndexIntoMasterTable(COMMAND
, DVOOutputControl
);
1048 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1049 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1050 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1051 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1052 index
= GetIndexIntoMasterTable(COMMAND
, UNIPHYTransmitterControl
);
1054 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1055 index
= GetIndexIntoMasterTable(COMMAND
, LVTMATransmitterControl
);
1059 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1066 args
.v1
.ucAction
= action
;
1067 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
1068 args
.v1
.usInitInfo
= cpu_to_le16(connector_object_id
);
1069 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
1070 args
.v1
.asMode
.ucLaneSel
= lane_num
;
1071 args
.v1
.asMode
.ucLaneSet
= lane_set
;
1074 args
.v1
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
1075 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1076 args
.v1
.usPixelClock
= cpu_to_le16((radeon_encoder
->pixel_clock
/ 2) / 10);
1078 args
.v1
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1081 args
.v1
.ucConfig
= ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL
;
1084 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER
;
1086 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER
;
1088 if ((rdev
->flags
& RADEON_IS_IGP
) &&
1089 (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_UNIPHY
)) {
1091 !radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
)) {
1092 if (igp_lane_info
& 0x1)
1093 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_0_3
;
1094 else if (igp_lane_info
& 0x2)
1095 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_4_7
;
1096 else if (igp_lane_info
& 0x4)
1097 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_8_11
;
1098 else if (igp_lane_info
& 0x8)
1099 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_12_15
;
1101 if (igp_lane_info
& 0x3)
1102 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_0_7
;
1103 else if (igp_lane_info
& 0xc)
1104 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_8_15
;
1109 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LINKB
;
1111 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LINKA
;
1114 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_COHERENT
;
1115 else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1116 if (dig
->coherent_mode
)
1117 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_COHERENT
;
1118 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1119 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_8LANE_LINK
;
1123 args
.v2
.ucAction
= action
;
1124 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
1125 args
.v2
.usInitInfo
= cpu_to_le16(connector_object_id
);
1126 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
1127 args
.v2
.asMode
.ucLaneSel
= lane_num
;
1128 args
.v2
.asMode
.ucLaneSet
= lane_set
;
1131 args
.v2
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
1132 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1133 args
.v2
.usPixelClock
= cpu_to_le16((radeon_encoder
->pixel_clock
/ 2) / 10);
1135 args
.v2
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1138 args
.v2
.acConfig
.ucEncoderSel
= dig_encoder
;
1140 args
.v2
.acConfig
.ucLinkSel
= 1;
1142 switch (radeon_encoder
->encoder_id
) {
1143 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1144 args
.v2
.acConfig
.ucTransmitterSel
= 0;
1146 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1147 args
.v2
.acConfig
.ucTransmitterSel
= 1;
1149 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1150 args
.v2
.acConfig
.ucTransmitterSel
= 2;
1155 args
.v2
.acConfig
.fCoherentMode
= 1;
1156 args
.v2
.acConfig
.fDPConnector
= 1;
1157 } else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1158 if (dig
->coherent_mode
)
1159 args
.v2
.acConfig
.fCoherentMode
= 1;
1160 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1161 args
.v2
.acConfig
.fDualLinkConnector
= 1;
1165 args
.v3
.ucAction
= action
;
1166 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
1167 args
.v3
.usInitInfo
= cpu_to_le16(connector_object_id
);
1168 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
1169 args
.v3
.asMode
.ucLaneSel
= lane_num
;
1170 args
.v3
.asMode
.ucLaneSet
= lane_set
;
1173 args
.v3
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
1174 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1175 args
.v3
.usPixelClock
= cpu_to_le16((radeon_encoder
->pixel_clock
/ 2) / 10);
1177 args
.v3
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1181 args
.v3
.ucLaneNum
= dp_lane_count
;
1182 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1183 args
.v3
.ucLaneNum
= 8;
1185 args
.v3
.ucLaneNum
= 4;
1188 args
.v3
.acConfig
.ucLinkSel
= 1;
1189 if (dig_encoder
& 1)
1190 args
.v3
.acConfig
.ucEncoderSel
= 1;
1192 /* Select the PLL for the PHY
1193 * DP PHY should be clocked from external src if there is
1196 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1197 if (is_dp
&& rdev
->clock
.dp_extclk
)
1198 args
.v3
.acConfig
.ucRefClkSource
= 2; /* external src */
1200 args
.v3
.acConfig
.ucRefClkSource
= pll_id
;
1202 switch (radeon_encoder
->encoder_id
) {
1203 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1204 args
.v3
.acConfig
.ucTransmitterSel
= 0;
1206 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1207 args
.v3
.acConfig
.ucTransmitterSel
= 1;
1209 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1210 args
.v3
.acConfig
.ucTransmitterSel
= 2;
1215 args
.v3
.acConfig
.fCoherentMode
= 1; /* DP requires coherent */
1216 else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1217 if (dig
->coherent_mode
)
1218 args
.v3
.acConfig
.fCoherentMode
= 1;
1219 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1220 args
.v3
.acConfig
.fDualLinkConnector
= 1;
1224 args
.v4
.ucAction
= action
;
1225 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
1226 args
.v4
.usInitInfo
= cpu_to_le16(connector_object_id
);
1227 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
1228 args
.v4
.asMode
.ucLaneSel
= lane_num
;
1229 args
.v4
.asMode
.ucLaneSet
= lane_set
;
1232 args
.v4
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
1233 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1234 args
.v4
.usPixelClock
= cpu_to_le16((radeon_encoder
->pixel_clock
/ 2) / 10);
1236 args
.v4
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1240 args
.v4
.ucLaneNum
= dp_lane_count
;
1241 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1242 args
.v4
.ucLaneNum
= 8;
1244 args
.v4
.ucLaneNum
= 4;
1247 args
.v4
.acConfig
.ucLinkSel
= 1;
1248 if (dig_encoder
& 1)
1249 args
.v4
.acConfig
.ucEncoderSel
= 1;
1251 /* Select the PLL for the PHY
1252 * DP PHY should be clocked from external src if there is
1255 /* On DCE5 DCPLL usually generates the DP ref clock */
1257 if (rdev
->clock
.dp_extclk
)
1258 args
.v4
.acConfig
.ucRefClkSource
= ENCODER_REFCLK_SRC_EXTCLK
;
1260 args
.v4
.acConfig
.ucRefClkSource
= ENCODER_REFCLK_SRC_DCPLL
;
1262 args
.v4
.acConfig
.ucRefClkSource
= pll_id
;
1264 switch (radeon_encoder
->encoder_id
) {
1265 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1266 args
.v4
.acConfig
.ucTransmitterSel
= 0;
1268 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1269 args
.v4
.acConfig
.ucTransmitterSel
= 1;
1271 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1272 args
.v4
.acConfig
.ucTransmitterSel
= 2;
1277 args
.v4
.acConfig
.fCoherentMode
= 1; /* DP requires coherent */
1278 else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1279 if (dig
->coherent_mode
)
1280 args
.v4
.acConfig
.fCoherentMode
= 1;
1281 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1282 args
.v4
.acConfig
.fDualLinkConnector
= 1;
1286 args
.v5
.ucAction
= action
;
1288 args
.v5
.usSymClock
= cpu_to_le16(dp_clock
/ 10);
1290 args
.v5
.usSymClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1292 switch (radeon_encoder
->encoder_id
) {
1293 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1295 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYB
;
1297 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYA
;
1299 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1301 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYD
;
1303 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYC
;
1305 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1307 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYF
;
1309 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYE
;
1311 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1312 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYG
;
1316 args
.v5
.ucLaneNum
= dp_lane_count
;
1317 else if (radeon_encoder
->pixel_clock
> 165000)
1318 args
.v5
.ucLaneNum
= 8;
1320 args
.v5
.ucLaneNum
= 4;
1321 args
.v5
.ucConnObjId
= connector_object_id
;
1322 args
.v5
.ucDigMode
= atombios_get_encoder_mode(encoder
);
1324 if (is_dp
&& rdev
->clock
.dp_extclk
)
1325 args
.v5
.asConfig
.ucPhyClkSrcId
= ENCODER_REFCLK_SRC_EXTCLK
;
1327 args
.v5
.asConfig
.ucPhyClkSrcId
= pll_id
;
1330 args
.v5
.asConfig
.ucCoherentMode
= 1; /* DP requires coherent */
1331 else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1332 if (dig
->coherent_mode
)
1333 args
.v5
.asConfig
.ucCoherentMode
= 1;
1335 if (hpd_id
== RADEON_HPD_NONE
)
1336 args
.v5
.asConfig
.ucHPDSel
= 0;
1338 args
.v5
.asConfig
.ucHPDSel
= hpd_id
+ 1;
1339 args
.v5
.ucDigEncoderSel
= 1 << dig_encoder
;
1340 args
.v5
.ucDPLaneSet
= lane_set
;
1343 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
1348 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
1352 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1356 atombios_set_edp_panel_power(struct drm_connector
*connector
, int action
)
1358 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
1359 struct drm_device
*dev
= radeon_connector
->base
.dev
;
1360 struct radeon_device
*rdev
= dev
->dev_private
;
1361 union dig_transmitter_control args
;
1362 int index
= GetIndexIntoMasterTable(COMMAND
, UNIPHYTransmitterControl
);
1365 if (connector
->connector_type
!= DRM_MODE_CONNECTOR_eDP
)
1368 if (!ASIC_IS_DCE4(rdev
))
1371 if ((action
!= ATOM_TRANSMITTER_ACTION_POWER_ON
) &&
1372 (action
!= ATOM_TRANSMITTER_ACTION_POWER_OFF
))
1375 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1378 memset(&args
, 0, sizeof(args
));
1380 args
.v1
.ucAction
= action
;
1382 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1384 /* wait for the panel to power up */
1385 if (action
== ATOM_TRANSMITTER_ACTION_POWER_ON
) {
1388 for (i
= 0; i
< 300; i
++) {
1389 if (radeon_hpd_sense(rdev
, radeon_connector
->hpd
.hpd
))
1399 union external_encoder_control
{
1400 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1
;
1401 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3
;
1405 atombios_external_encoder_setup(struct drm_encoder
*encoder
,
1406 struct drm_encoder
*ext_encoder
,
1409 struct drm_device
*dev
= encoder
->dev
;
1410 struct radeon_device
*rdev
= dev
->dev_private
;
1411 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1412 struct radeon_encoder
*ext_radeon_encoder
= to_radeon_encoder(ext_encoder
);
1413 union external_encoder_control args
;
1414 struct drm_connector
*connector
;
1415 int index
= GetIndexIntoMasterTable(COMMAND
, ExternalEncoderControl
);
1418 int dp_lane_count
= 0;
1419 int connector_object_id
= 0;
1420 u32 ext_enum
= (ext_radeon_encoder
->encoder_enum
& ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
1422 if (action
== EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT
)
1423 connector
= radeon_get_connector_for_encoder_init(encoder
);
1425 connector
= radeon_get_connector_for_encoder(encoder
);
1428 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
1429 struct radeon_connector_atom_dig
*dig_connector
=
1430 radeon_connector
->con_priv
;
1432 dp_clock
= dig_connector
->dp_clock
;
1433 dp_lane_count
= dig_connector
->dp_lane_count
;
1434 connector_object_id
=
1435 (radeon_connector
->connector_object_id
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
1438 memset(&args
, 0, sizeof(args
));
1440 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1445 /* no params on frev 1 */
1451 args
.v1
.sDigEncoder
.ucAction
= action
;
1452 args
.v1
.sDigEncoder
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1453 args
.v1
.sDigEncoder
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
1455 if (ENCODER_MODE_IS_DP(args
.v1
.sDigEncoder
.ucEncoderMode
)) {
1456 if (dp_clock
== 270000)
1457 args
.v1
.sDigEncoder
.ucConfig
|= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ
;
1458 args
.v1
.sDigEncoder
.ucLaneNum
= dp_lane_count
;
1459 } else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1460 args
.v1
.sDigEncoder
.ucLaneNum
= 8;
1462 args
.v1
.sDigEncoder
.ucLaneNum
= 4;
1465 args
.v3
.sExtEncoder
.ucAction
= action
;
1466 if (action
== EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT
)
1467 args
.v3
.sExtEncoder
.usConnectorId
= cpu_to_le16(connector_object_id
);
1469 args
.v3
.sExtEncoder
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1470 args
.v3
.sExtEncoder
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
1472 if (ENCODER_MODE_IS_DP(args
.v3
.sExtEncoder
.ucEncoderMode
)) {
1473 if (dp_clock
== 270000)
1474 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ
;
1475 else if (dp_clock
== 540000)
1476 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ
;
1477 args
.v3
.sExtEncoder
.ucLaneNum
= dp_lane_count
;
1478 } else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1479 args
.v3
.sExtEncoder
.ucLaneNum
= 8;
1481 args
.v3
.sExtEncoder
.ucLaneNum
= 4;
1483 case GRAPH_OBJECT_ENUM_ID1
:
1484 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1
;
1486 case GRAPH_OBJECT_ENUM_ID2
:
1487 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2
;
1489 case GRAPH_OBJECT_ENUM_ID3
:
1490 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3
;
1493 args
.v3
.sExtEncoder
.ucBitPerColor
= radeon_atom_get_bpc(encoder
);
1496 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1501 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1504 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1508 atombios_yuv_setup(struct drm_encoder
*encoder
, bool enable
)
1510 struct drm_device
*dev
= encoder
->dev
;
1511 struct radeon_device
*rdev
= dev
->dev_private
;
1512 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1513 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1514 ENABLE_YUV_PS_ALLOCATION args
;
1515 int index
= GetIndexIntoMasterTable(COMMAND
, EnableYUV
);
1518 memset(&args
, 0, sizeof(args
));
1520 if (rdev
->family
>= CHIP_R600
)
1521 reg
= R600_BIOS_3_SCRATCH
;
1523 reg
= RADEON_BIOS_3_SCRATCH
;
1525 /* XXX: fix up scratch reg handling */
1527 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1528 WREG32(reg
, (ATOM_S3_TV1_ACTIVE
|
1529 (radeon_crtc
->crtc_id
<< 18)));
1530 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1531 WREG32(reg
, (ATOM_S3_CV_ACTIVE
| (radeon_crtc
->crtc_id
<< 24)));
1536 args
.ucEnable
= ATOM_ENABLE
;
1537 args
.ucCRTC
= radeon_crtc
->crtc_id
;
1539 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1545 radeon_atom_encoder_dpms_avivo(struct drm_encoder
*encoder
, int mode
)
1547 struct drm_device
*dev
= encoder
->dev
;
1548 struct radeon_device
*rdev
= dev
->dev_private
;
1549 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1550 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args
;
1553 memset(&args
, 0, sizeof(args
));
1555 switch (radeon_encoder
->encoder_id
) {
1556 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
1557 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
1558 index
= GetIndexIntoMasterTable(COMMAND
, TMDSAOutputControl
);
1560 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
1561 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
1562 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1563 index
= GetIndexIntoMasterTable(COMMAND
, DVOOutputControl
);
1565 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
1566 index
= GetIndexIntoMasterTable(COMMAND
, LCD1OutputControl
);
1568 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
1569 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
1570 index
= GetIndexIntoMasterTable(COMMAND
, LCD1OutputControl
);
1572 index
= GetIndexIntoMasterTable(COMMAND
, LVTMAOutputControl
);
1574 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
1575 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1576 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1577 index
= GetIndexIntoMasterTable(COMMAND
, TV1OutputControl
);
1578 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1579 index
= GetIndexIntoMasterTable(COMMAND
, CV1OutputControl
);
1581 index
= GetIndexIntoMasterTable(COMMAND
, DAC1OutputControl
);
1583 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
1584 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1585 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1586 index
= GetIndexIntoMasterTable(COMMAND
, TV1OutputControl
);
1587 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1588 index
= GetIndexIntoMasterTable(COMMAND
, CV1OutputControl
);
1590 index
= GetIndexIntoMasterTable(COMMAND
, DAC2OutputControl
);
1597 case DRM_MODE_DPMS_ON
:
1598 args
.ucAction
= ATOM_ENABLE
;
1599 /* workaround for DVOOutputControl on some RS690 systems */
1600 if (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DDI
) {
1601 u32 reg
= RREG32(RADEON_BIOS_3_SCRATCH
);
1602 WREG32(RADEON_BIOS_3_SCRATCH
, reg
& ~ATOM_S3_DFP2I_ACTIVE
);
1603 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1604 WREG32(RADEON_BIOS_3_SCRATCH
, reg
);
1606 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1607 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1608 args
.ucAction
= ATOM_LCD_BLON
;
1609 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1612 case DRM_MODE_DPMS_STANDBY
:
1613 case DRM_MODE_DPMS_SUSPEND
:
1614 case DRM_MODE_DPMS_OFF
:
1615 args
.ucAction
= ATOM_DISABLE
;
1616 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1617 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1618 args
.ucAction
= ATOM_LCD_BLOFF
;
1619 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1626 radeon_atom_encoder_dpms_dig(struct drm_encoder
*encoder
, int mode
)
1628 struct drm_device
*dev
= encoder
->dev
;
1629 struct radeon_device
*rdev
= dev
->dev_private
;
1630 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1631 struct drm_encoder
*ext_encoder
= radeon_get_external_encoder(encoder
);
1632 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
1633 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
1634 struct radeon_connector
*radeon_connector
= NULL
;
1635 struct radeon_connector_atom_dig
*radeon_dig_connector
= NULL
;
1638 radeon_connector
= to_radeon_connector(connector
);
1639 radeon_dig_connector
= radeon_connector
->con_priv
;
1643 case DRM_MODE_DPMS_ON
:
1644 if (ASIC_IS_DCE41(rdev
) || ASIC_IS_DCE5(rdev
)) {
1646 dig
->panel_mode
= DP_PANEL_MODE_EXTERNAL_DP_MODE
;
1648 dig
->panel_mode
= radeon_dp_get_panel_mode(encoder
, connector
);
1650 /* setup and enable the encoder */
1651 atombios_dig_encoder_setup(encoder
, ATOM_ENCODER_CMD_SETUP
, 0);
1652 atombios_dig_encoder_setup(encoder
,
1653 ATOM_ENCODER_CMD_SETUP_PANEL_MODE
,
1656 if (ASIC_IS_DCE41(rdev
) || ASIC_IS_DCE61(rdev
))
1657 atombios_external_encoder_setup(encoder
, ext_encoder
,
1658 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP
);
1660 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_ENABLE
, 0, 0);
1661 } else if (ASIC_IS_DCE4(rdev
)) {
1662 /* setup and enable the encoder */
1663 atombios_dig_encoder_setup(encoder
, ATOM_ENCODER_CMD_SETUP
, 0);
1664 /* enable the transmitter */
1665 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_ENABLE
, 0, 0);
1667 /* setup and enable the encoder and transmitter */
1668 atombios_dig_encoder_setup(encoder
, ATOM_ENABLE
, 0);
1669 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_SETUP
, 0, 0);
1670 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_ENABLE
, 0, 0);
1672 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder
)) && connector
) {
1673 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
) {
1674 atombios_set_edp_panel_power(connector
,
1675 ATOM_TRANSMITTER_ACTION_POWER_ON
);
1676 radeon_dig_connector
->edp_on
= true;
1678 radeon_dp_link_train(encoder
, connector
);
1679 if (ASIC_IS_DCE4(rdev
))
1680 atombios_dig_encoder_setup(encoder
, ATOM_ENCODER_CMD_DP_VIDEO_ON
, 0);
1682 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
1683 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_LCD_BLON
, 0, 0);
1685 case DRM_MODE_DPMS_STANDBY
:
1686 case DRM_MODE_DPMS_SUSPEND
:
1687 case DRM_MODE_DPMS_OFF
:
1688 if (ASIC_IS_DCE4(rdev
)) {
1689 /* disable the transmitter */
1690 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_DISABLE
, 0, 0);
1692 /* disable the encoder and transmitter */
1693 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_DISABLE
, 0, 0);
1694 atombios_dig_encoder_setup(encoder
, ATOM_DISABLE
, 0);
1696 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder
)) && connector
) {
1697 if (ASIC_IS_DCE4(rdev
))
1698 atombios_dig_encoder_setup(encoder
, ATOM_ENCODER_CMD_DP_VIDEO_OFF
, 0);
1699 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
) {
1700 atombios_set_edp_panel_power(connector
,
1701 ATOM_TRANSMITTER_ACTION_POWER_OFF
);
1702 radeon_dig_connector
->edp_on
= false;
1705 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
1706 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_LCD_BLOFF
, 0, 0);
1712 radeon_atom_encoder_dpms_ext(struct drm_encoder
*encoder
,
1713 struct drm_encoder
*ext_encoder
,
1716 struct drm_device
*dev
= encoder
->dev
;
1717 struct radeon_device
*rdev
= dev
->dev_private
;
1720 case DRM_MODE_DPMS_ON
:
1722 if (ASIC_IS_DCE41(rdev
) || ASIC_IS_DCE61(rdev
)) {
1723 atombios_external_encoder_setup(encoder
, ext_encoder
,
1724 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT
);
1725 atombios_external_encoder_setup(encoder
, ext_encoder
,
1726 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF
);
1728 atombios_external_encoder_setup(encoder
, ext_encoder
, ATOM_ENABLE
);
1730 case DRM_MODE_DPMS_STANDBY
:
1731 case DRM_MODE_DPMS_SUSPEND
:
1732 case DRM_MODE_DPMS_OFF
:
1733 if (ASIC_IS_DCE41(rdev
) || ASIC_IS_DCE61(rdev
)) {
1734 atombios_external_encoder_setup(encoder
, ext_encoder
,
1735 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING
);
1736 atombios_external_encoder_setup(encoder
, ext_encoder
,
1737 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT
);
1739 atombios_external_encoder_setup(encoder
, ext_encoder
, ATOM_DISABLE
);
1745 radeon_atom_encoder_dpms(struct drm_encoder
*encoder
, int mode
)
1747 struct drm_device
*dev
= encoder
->dev
;
1748 struct radeon_device
*rdev
= dev
->dev_private
;
1749 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1750 struct drm_encoder
*ext_encoder
= radeon_get_external_encoder(encoder
);
1752 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1753 radeon_encoder
->encoder_id
, mode
, radeon_encoder
->devices
,
1754 radeon_encoder
->active_device
);
1755 switch (radeon_encoder
->encoder_id
) {
1756 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
1757 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
1758 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
1759 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
1760 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
1761 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
1762 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
1763 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1764 radeon_atom_encoder_dpms_avivo(encoder
, mode
);
1766 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1767 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1768 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1769 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1770 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1771 radeon_atom_encoder_dpms_dig(encoder
, mode
);
1773 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1774 if (ASIC_IS_DCE5(rdev
)) {
1776 case DRM_MODE_DPMS_ON
:
1777 atombios_dvo_setup(encoder
, ATOM_ENABLE
);
1779 case DRM_MODE_DPMS_STANDBY
:
1780 case DRM_MODE_DPMS_SUSPEND
:
1781 case DRM_MODE_DPMS_OFF
:
1782 atombios_dvo_setup(encoder
, ATOM_DISABLE
);
1785 } else if (ASIC_IS_DCE3(rdev
))
1786 radeon_atom_encoder_dpms_dig(encoder
, mode
);
1788 radeon_atom_encoder_dpms_avivo(encoder
, mode
);
1790 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
1791 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1792 if (ASIC_IS_DCE5(rdev
)) {
1794 case DRM_MODE_DPMS_ON
:
1795 atombios_dac_setup(encoder
, ATOM_ENABLE
);
1797 case DRM_MODE_DPMS_STANDBY
:
1798 case DRM_MODE_DPMS_SUSPEND
:
1799 case DRM_MODE_DPMS_OFF
:
1800 atombios_dac_setup(encoder
, ATOM_DISABLE
);
1804 radeon_atom_encoder_dpms_avivo(encoder
, mode
);
1811 radeon_atom_encoder_dpms_ext(encoder
, ext_encoder
, mode
);
1813 radeon_atombios_encoder_dpms_scratch_regs(encoder
, (mode
== DRM_MODE_DPMS_ON
) ? true : false);
1817 union crtc_source_param
{
1818 SELECT_CRTC_SOURCE_PS_ALLOCATION v1
;
1819 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2
;
1823 atombios_set_encoder_crtc_source(struct drm_encoder
*encoder
)
1825 struct drm_device
*dev
= encoder
->dev
;
1826 struct radeon_device
*rdev
= dev
->dev_private
;
1827 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1828 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1829 union crtc_source_param args
;
1830 int index
= GetIndexIntoMasterTable(COMMAND
, SelectCRTC_Source
);
1832 struct radeon_encoder_atom_dig
*dig
;
1834 memset(&args
, 0, sizeof(args
));
1836 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1844 if (ASIC_IS_AVIVO(rdev
))
1845 args
.v1
.ucCRTC
= radeon_crtc
->crtc_id
;
1847 if (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DAC1
) {
1848 args
.v1
.ucCRTC
= radeon_crtc
->crtc_id
;
1850 args
.v1
.ucCRTC
= radeon_crtc
->crtc_id
<< 2;
1853 switch (radeon_encoder
->encoder_id
) {
1854 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
1855 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
1856 args
.v1
.ucDevice
= ATOM_DEVICE_DFP1_INDEX
;
1858 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
1859 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
1860 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)
1861 args
.v1
.ucDevice
= ATOM_DEVICE_LCD1_INDEX
;
1863 args
.v1
.ucDevice
= ATOM_DEVICE_DFP3_INDEX
;
1865 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
1866 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
1867 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1868 args
.v1
.ucDevice
= ATOM_DEVICE_DFP2_INDEX
;
1870 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
1871 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1872 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1873 args
.v1
.ucDevice
= ATOM_DEVICE_TV1_INDEX
;
1874 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1875 args
.v1
.ucDevice
= ATOM_DEVICE_CV_INDEX
;
1877 args
.v1
.ucDevice
= ATOM_DEVICE_CRT1_INDEX
;
1879 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
1880 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1881 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1882 args
.v1
.ucDevice
= ATOM_DEVICE_TV1_INDEX
;
1883 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1884 args
.v1
.ucDevice
= ATOM_DEVICE_CV_INDEX
;
1886 args
.v1
.ucDevice
= ATOM_DEVICE_CRT2_INDEX
;
1891 args
.v2
.ucCRTC
= radeon_crtc
->crtc_id
;
1892 if (radeon_encoder_get_dp_bridge_encoder_id(encoder
) != ENCODER_OBJECT_ID_NONE
) {
1893 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
1895 if (connector
->connector_type
== DRM_MODE_CONNECTOR_LVDS
)
1896 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_LVDS
;
1897 else if (connector
->connector_type
== DRM_MODE_CONNECTOR_VGA
)
1898 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_CRT
;
1900 args
.v2
.ucEncodeMode
= atombios_get_encoder_mode(encoder
);
1902 args
.v2
.ucEncodeMode
= atombios_get_encoder_mode(encoder
);
1903 switch (radeon_encoder
->encoder_id
) {
1904 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1905 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1906 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1907 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1908 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1909 dig
= radeon_encoder
->enc_priv
;
1910 switch (dig
->dig_encoder
) {
1912 args
.v2
.ucEncoderID
= ASIC_INT_DIG1_ENCODER_ID
;
1915 args
.v2
.ucEncoderID
= ASIC_INT_DIG2_ENCODER_ID
;
1918 args
.v2
.ucEncoderID
= ASIC_INT_DIG3_ENCODER_ID
;
1921 args
.v2
.ucEncoderID
= ASIC_INT_DIG4_ENCODER_ID
;
1924 args
.v2
.ucEncoderID
= ASIC_INT_DIG5_ENCODER_ID
;
1927 args
.v2
.ucEncoderID
= ASIC_INT_DIG6_ENCODER_ID
;
1930 args
.v2
.ucEncoderID
= ASIC_INT_DIG7_ENCODER_ID
;
1934 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1935 args
.v2
.ucEncoderID
= ASIC_INT_DVO_ENCODER_ID
;
1937 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1938 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1939 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1940 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1941 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1943 args
.v2
.ucEncoderID
= ASIC_INT_DAC1_ENCODER_ID
;
1945 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1946 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1947 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1948 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1949 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1951 args
.v2
.ucEncoderID
= ASIC_INT_DAC2_ENCODER_ID
;
1958 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1962 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1964 /* update scratch regs with new routing */
1965 radeon_atombios_encoder_crtc_scratch_regs(encoder
, radeon_crtc
->crtc_id
);
1969 atombios_apply_encoder_quirks(struct drm_encoder
*encoder
,
1970 struct drm_display_mode
*mode
)
1972 struct drm_device
*dev
= encoder
->dev
;
1973 struct radeon_device
*rdev
= dev
->dev_private
;
1974 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1975 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1977 /* Funky macbooks */
1978 if ((dev
->pdev
->device
== 0x71C5) &&
1979 (dev
->pdev
->subsystem_vendor
== 0x106b) &&
1980 (dev
->pdev
->subsystem_device
== 0x0080)) {
1981 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
1982 uint32_t lvtma_bit_depth_control
= RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL
);
1984 lvtma_bit_depth_control
&= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN
;
1985 lvtma_bit_depth_control
&= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN
;
1987 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL
, lvtma_bit_depth_control
);
1991 /* set scaler clears this on some chips */
1992 if (ASIC_IS_AVIVO(rdev
) &&
1993 (!(radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
)))) {
1994 if (ASIC_IS_DCE8(rdev
)) {
1995 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1996 WREG32(CIK_LB_DATA_FORMAT
+ radeon_crtc
->crtc_offset
,
1999 WREG32(CIK_LB_DATA_FORMAT
+ radeon_crtc
->crtc_offset
, 0);
2000 } else if (ASIC_IS_DCE4(rdev
)) {
2001 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
2002 WREG32(EVERGREEN_DATA_FORMAT
+ radeon_crtc
->crtc_offset
,
2003 EVERGREEN_INTERLEAVE_EN
);
2005 WREG32(EVERGREEN_DATA_FORMAT
+ radeon_crtc
->crtc_offset
, 0);
2007 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
2008 WREG32(AVIVO_D1MODE_DATA_FORMAT
+ radeon_crtc
->crtc_offset
,
2009 AVIVO_D1MODE_INTERLEAVE_EN
);
2011 WREG32(AVIVO_D1MODE_DATA_FORMAT
+ radeon_crtc
->crtc_offset
, 0);
2016 static int radeon_atom_pick_dig_encoder(struct drm_encoder
*encoder
)
2018 struct drm_device
*dev
= encoder
->dev
;
2019 struct radeon_device
*rdev
= dev
->dev_private
;
2020 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
2021 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2022 struct drm_encoder
*test_encoder
;
2023 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
2024 uint32_t dig_enc_in_use
= 0;
2026 if (ASIC_IS_DCE6(rdev
)) {
2028 switch (radeon_encoder
->encoder_id
) {
2029 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2035 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2041 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2047 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2051 } else if (ASIC_IS_DCE4(rdev
)) {
2053 if (ASIC_IS_DCE41(rdev
) && !ASIC_IS_DCE61(rdev
)) {
2054 /* ontario follows DCE4 */
2055 if (rdev
->family
== CHIP_PALM
) {
2061 /* llano follows DCE3.2 */
2062 return radeon_crtc
->crtc_id
;
2064 switch (radeon_encoder
->encoder_id
) {
2065 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2071 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2077 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2087 /* on DCE32 and encoder can driver any block so just crtc id */
2088 if (ASIC_IS_DCE32(rdev
)) {
2089 return radeon_crtc
->crtc_id
;
2092 /* on DCE3 - LVTMA can only be driven by DIGB */
2093 list_for_each_entry(test_encoder
, &dev
->mode_config
.encoder_list
, head
) {
2094 struct radeon_encoder
*radeon_test_encoder
;
2096 if (encoder
== test_encoder
)
2099 if (!radeon_encoder_is_digital(test_encoder
))
2102 radeon_test_encoder
= to_radeon_encoder(test_encoder
);
2103 dig
= radeon_test_encoder
->enc_priv
;
2105 if (dig
->dig_encoder
>= 0)
2106 dig_enc_in_use
|= (1 << dig
->dig_encoder
);
2109 if (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
) {
2110 if (dig_enc_in_use
& 0x2)
2111 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2114 if (!(dig_enc_in_use
& 1))
2119 /* This only needs to be called once at startup */
2121 radeon_atom_encoder_init(struct radeon_device
*rdev
)
2123 struct drm_device
*dev
= rdev
->ddev
;
2124 struct drm_encoder
*encoder
;
2126 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
2127 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2128 struct drm_encoder
*ext_encoder
= radeon_get_external_encoder(encoder
);
2130 switch (radeon_encoder
->encoder_id
) {
2131 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2132 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2133 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2134 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2135 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
2136 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_INIT
, 0, 0);
2142 if (ext_encoder
&& (ASIC_IS_DCE41(rdev
) || ASIC_IS_DCE61(rdev
)))
2143 atombios_external_encoder_setup(encoder
, ext_encoder
,
2144 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT
);
2149 radeon_atom_encoder_mode_set(struct drm_encoder
*encoder
,
2150 struct drm_display_mode
*mode
,
2151 struct drm_display_mode
*adjusted_mode
)
2153 struct drm_device
*dev
= encoder
->dev
;
2154 struct radeon_device
*rdev
= dev
->dev_private
;
2155 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2157 radeon_encoder
->pixel_clock
= adjusted_mode
->clock
;
2159 /* need to call this here rather than in prepare() since we need some crtc info */
2160 radeon_atom_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
2162 if (ASIC_IS_AVIVO(rdev
) && !ASIC_IS_DCE4(rdev
)) {
2163 if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
| ATOM_DEVICE_TV_SUPPORT
))
2164 atombios_yuv_setup(encoder
, true);
2166 atombios_yuv_setup(encoder
, false);
2169 switch (radeon_encoder
->encoder_id
) {
2170 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
2171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
2172 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
2173 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
2174 atombios_digital_setup(encoder
, PANEL_ENCODER_ACTION_ENABLE
);
2176 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2177 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2178 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2179 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2180 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
2181 /* handled in dpms */
2183 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
2184 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
2185 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
2186 atombios_dvo_setup(encoder
, ATOM_ENABLE
);
2188 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
2189 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
2190 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
2191 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
2192 atombios_dac_setup(encoder
, ATOM_ENABLE
);
2193 if (radeon_encoder
->devices
& (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
)) {
2194 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
))
2195 atombios_tv_setup(encoder
, ATOM_ENABLE
);
2197 atombios_tv_setup(encoder
, ATOM_DISABLE
);
2202 atombios_apply_encoder_quirks(encoder
, adjusted_mode
);
2204 if (atombios_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
) {
2205 if (rdev
->asic
->display
.hdmi_enable
)
2206 radeon_hdmi_enable(rdev
, encoder
, true);
2207 if (rdev
->asic
->display
.hdmi_setmode
)
2208 radeon_hdmi_setmode(rdev
, encoder
, adjusted_mode
);
2213 atombios_dac_load_detect(struct drm_encoder
*encoder
, struct drm_connector
*connector
)
2215 struct drm_device
*dev
= encoder
->dev
;
2216 struct radeon_device
*rdev
= dev
->dev_private
;
2217 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2218 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
2220 if (radeon_encoder
->devices
& (ATOM_DEVICE_TV_SUPPORT
|
2221 ATOM_DEVICE_CV_SUPPORT
|
2222 ATOM_DEVICE_CRT_SUPPORT
)) {
2223 DAC_LOAD_DETECTION_PS_ALLOCATION args
;
2224 int index
= GetIndexIntoMasterTable(COMMAND
, DAC_LoadDetection
);
2227 memset(&args
, 0, sizeof(args
));
2229 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
2232 args
.sDacload
.ucMisc
= 0;
2234 if ((radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DAC1
) ||
2235 (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
))
2236 args
.sDacload
.ucDacType
= ATOM_DAC_A
;
2238 args
.sDacload
.ucDacType
= ATOM_DAC_B
;
2240 if (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)
2241 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT
);
2242 else if (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)
2243 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT
);
2244 else if (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
2245 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CV_SUPPORT
);
2247 args
.sDacload
.ucMisc
= DAC_LOAD_MISC_YPrPb
;
2248 } else if (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
2249 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT
);
2251 args
.sDacload
.ucMisc
= DAC_LOAD_MISC_YPrPb
;
2254 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2261 static enum drm_connector_status
2262 radeon_atom_dac_detect(struct drm_encoder
*encoder
, struct drm_connector
*connector
)
2264 struct drm_device
*dev
= encoder
->dev
;
2265 struct radeon_device
*rdev
= dev
->dev_private
;
2266 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2267 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
2268 uint32_t bios_0_scratch
;
2270 if (!atombios_dac_load_detect(encoder
, connector
)) {
2271 DRM_DEBUG_KMS("detect returned false \n");
2272 return connector_status_unknown
;
2275 if (rdev
->family
>= CHIP_R600
)
2276 bios_0_scratch
= RREG32(R600_BIOS_0_SCRATCH
);
2278 bios_0_scratch
= RREG32(RADEON_BIOS_0_SCRATCH
);
2280 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch
, radeon_encoder
->devices
);
2281 if (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
2282 if (bios_0_scratch
& ATOM_S0_CRT1_MASK
)
2283 return connector_status_connected
;
2285 if (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
2286 if (bios_0_scratch
& ATOM_S0_CRT2_MASK
)
2287 return connector_status_connected
;
2289 if (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
2290 if (bios_0_scratch
& (ATOM_S0_CV_MASK
|ATOM_S0_CV_MASK_A
))
2291 return connector_status_connected
;
2293 if (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
2294 if (bios_0_scratch
& (ATOM_S0_TV1_COMPOSITE
| ATOM_S0_TV1_COMPOSITE_A
))
2295 return connector_status_connected
; /* CTV */
2296 else if (bios_0_scratch
& (ATOM_S0_TV1_SVIDEO
| ATOM_S0_TV1_SVIDEO_A
))
2297 return connector_status_connected
; /* STV */
2299 return connector_status_disconnected
;
2302 static enum drm_connector_status
2303 radeon_atom_dig_detect(struct drm_encoder
*encoder
, struct drm_connector
*connector
)
2305 struct drm_device
*dev
= encoder
->dev
;
2306 struct radeon_device
*rdev
= dev
->dev_private
;
2307 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2308 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
2309 struct drm_encoder
*ext_encoder
= radeon_get_external_encoder(encoder
);
2312 if (!ASIC_IS_DCE4(rdev
))
2313 return connector_status_unknown
;
2316 return connector_status_unknown
;
2318 if ((radeon_connector
->devices
& ATOM_DEVICE_CRT_SUPPORT
) == 0)
2319 return connector_status_unknown
;
2321 /* load detect on the dp bridge */
2322 atombios_external_encoder_setup(encoder
, ext_encoder
,
2323 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION
);
2325 bios_0_scratch
= RREG32(R600_BIOS_0_SCRATCH
);
2327 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch
, radeon_encoder
->devices
);
2328 if (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
2329 if (bios_0_scratch
& ATOM_S0_CRT1_MASK
)
2330 return connector_status_connected
;
2332 if (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
2333 if (bios_0_scratch
& ATOM_S0_CRT2_MASK
)
2334 return connector_status_connected
;
2336 if (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
2337 if (bios_0_scratch
& (ATOM_S0_CV_MASK
|ATOM_S0_CV_MASK_A
))
2338 return connector_status_connected
;
2340 if (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
2341 if (bios_0_scratch
& (ATOM_S0_TV1_COMPOSITE
| ATOM_S0_TV1_COMPOSITE_A
))
2342 return connector_status_connected
; /* CTV */
2343 else if (bios_0_scratch
& (ATOM_S0_TV1_SVIDEO
| ATOM_S0_TV1_SVIDEO_A
))
2344 return connector_status_connected
; /* STV */
2346 return connector_status_disconnected
;
2350 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder
*encoder
)
2352 struct drm_encoder
*ext_encoder
= radeon_get_external_encoder(encoder
);
2355 /* ddc_setup on the dp bridge */
2356 atombios_external_encoder_setup(encoder
, ext_encoder
,
2357 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP
);
2361 static void radeon_atom_encoder_prepare(struct drm_encoder
*encoder
)
2363 struct radeon_device
*rdev
= encoder
->dev
->dev_private
;
2364 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2365 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
2367 if ((radeon_encoder
->active_device
&
2368 (ATOM_DEVICE_DFP_SUPPORT
| ATOM_DEVICE_LCD_SUPPORT
)) ||
2369 (radeon_encoder_get_dp_bridge_encoder_id(encoder
) !=
2370 ENCODER_OBJECT_ID_NONE
)) {
2371 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
2373 dig
->dig_encoder
= radeon_atom_pick_dig_encoder(encoder
);
2374 if (radeon_encoder
->active_device
& ATOM_DEVICE_DFP_SUPPORT
) {
2375 if (rdev
->family
>= CHIP_R600
)
2376 dig
->afmt
= rdev
->mode_info
.afmt
[dig
->dig_encoder
];
2378 /* RS600/690/740 have only 1 afmt block */
2379 dig
->afmt
= rdev
->mode_info
.afmt
[0];
2384 radeon_atom_output_lock(encoder
, true);
2387 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
2389 /* select the clock/data port if it uses a router */
2390 if (radeon_connector
->router
.cd_valid
)
2391 radeon_router_select_cd_port(radeon_connector
);
2393 /* turn eDP panel on for mode set */
2394 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
2395 atombios_set_edp_panel_power(connector
,
2396 ATOM_TRANSMITTER_ACTION_POWER_ON
);
2399 /* this is needed for the pll/ss setup to work correctly in some cases */
2400 atombios_set_encoder_crtc_source(encoder
);
2401 /* set up the FMT blocks */
2402 if (ASIC_IS_DCE8(rdev
))
2403 dce8_program_fmt(encoder
);
2404 else if (ASIC_IS_DCE4(rdev
))
2405 dce4_program_fmt(encoder
);
2406 else if (ASIC_IS_DCE3(rdev
))
2407 dce3_program_fmt(encoder
);
2408 else if (ASIC_IS_AVIVO(rdev
))
2409 avivo_program_fmt(encoder
);
2412 static void radeon_atom_encoder_commit(struct drm_encoder
*encoder
)
2414 /* need to call this here as we need the crtc set up */
2415 radeon_atom_encoder_dpms(encoder
, DRM_MODE_DPMS_ON
);
2416 radeon_atom_output_lock(encoder
, false);
2419 static void radeon_atom_encoder_disable(struct drm_encoder
*encoder
)
2421 struct drm_device
*dev
= encoder
->dev
;
2422 struct radeon_device
*rdev
= dev
->dev_private
;
2423 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2424 struct radeon_encoder_atom_dig
*dig
;
2426 /* check for pre-DCE3 cards with shared encoders;
2427 * can't really use the links individually, so don't disable
2428 * the encoder if it's in use by another connector
2430 if (!ASIC_IS_DCE3(rdev
)) {
2431 struct drm_encoder
*other_encoder
;
2432 struct radeon_encoder
*other_radeon_encoder
;
2434 list_for_each_entry(other_encoder
, &dev
->mode_config
.encoder_list
, head
) {
2435 other_radeon_encoder
= to_radeon_encoder(other_encoder
);
2436 if ((radeon_encoder
->encoder_id
== other_radeon_encoder
->encoder_id
) &&
2437 drm_helper_encoder_in_use(other_encoder
))
2442 radeon_atom_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
2444 switch (radeon_encoder
->encoder_id
) {
2445 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
2446 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
2447 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
2448 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
2449 atombios_digital_setup(encoder
, PANEL_ENCODER_ACTION_DISABLE
);
2451 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2452 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2453 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2454 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2455 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
2456 /* handled in dpms */
2458 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
2459 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
2460 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
2461 atombios_dvo_setup(encoder
, ATOM_DISABLE
);
2463 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
2464 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
2465 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
2466 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
2467 atombios_dac_setup(encoder
, ATOM_DISABLE
);
2468 if (radeon_encoder
->devices
& (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
))
2469 atombios_tv_setup(encoder
, ATOM_DISABLE
);
2474 if (radeon_encoder_is_digital(encoder
)) {
2475 if (atombios_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
) {
2476 if (rdev
->asic
->display
.hdmi_enable
)
2477 radeon_hdmi_enable(rdev
, encoder
, false);
2479 dig
= radeon_encoder
->enc_priv
;
2480 dig
->dig_encoder
= -1;
2482 radeon_encoder
->active_device
= 0;
2485 /* these are handled by the primary encoders */
2486 static void radeon_atom_ext_prepare(struct drm_encoder
*encoder
)
2491 static void radeon_atom_ext_commit(struct drm_encoder
*encoder
)
2497 radeon_atom_ext_mode_set(struct drm_encoder
*encoder
,
2498 struct drm_display_mode
*mode
,
2499 struct drm_display_mode
*adjusted_mode
)
2504 static void radeon_atom_ext_disable(struct drm_encoder
*encoder
)
2510 radeon_atom_ext_dpms(struct drm_encoder
*encoder
, int mode
)
2515 static bool radeon_atom_ext_mode_fixup(struct drm_encoder
*encoder
,
2516 const struct drm_display_mode
*mode
,
2517 struct drm_display_mode
*adjusted_mode
)
2522 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs
= {
2523 .dpms
= radeon_atom_ext_dpms
,
2524 .mode_fixup
= radeon_atom_ext_mode_fixup
,
2525 .prepare
= radeon_atom_ext_prepare
,
2526 .mode_set
= radeon_atom_ext_mode_set
,
2527 .commit
= radeon_atom_ext_commit
,
2528 .disable
= radeon_atom_ext_disable
,
2529 /* no detect for TMDS/LVDS yet */
2532 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs
= {
2533 .dpms
= radeon_atom_encoder_dpms
,
2534 .mode_fixup
= radeon_atom_mode_fixup
,
2535 .prepare
= radeon_atom_encoder_prepare
,
2536 .mode_set
= radeon_atom_encoder_mode_set
,
2537 .commit
= radeon_atom_encoder_commit
,
2538 .disable
= radeon_atom_encoder_disable
,
2539 .detect
= radeon_atom_dig_detect
,
2542 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs
= {
2543 .dpms
= radeon_atom_encoder_dpms
,
2544 .mode_fixup
= radeon_atom_mode_fixup
,
2545 .prepare
= radeon_atom_encoder_prepare
,
2546 .mode_set
= radeon_atom_encoder_mode_set
,
2547 .commit
= radeon_atom_encoder_commit
,
2548 .detect
= radeon_atom_dac_detect
,
2551 void radeon_enc_destroy(struct drm_encoder
*encoder
)
2553 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2554 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
2555 radeon_atom_backlight_exit(radeon_encoder
);
2556 kfree(radeon_encoder
->enc_priv
);
2557 drm_encoder_cleanup(encoder
);
2558 kfree(radeon_encoder
);
2561 static const struct drm_encoder_funcs radeon_atom_enc_funcs
= {
2562 .destroy
= radeon_enc_destroy
,
2565 static struct radeon_encoder_atom_dac
*
2566 radeon_atombios_set_dac_info(struct radeon_encoder
*radeon_encoder
)
2568 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
2569 struct radeon_device
*rdev
= dev
->dev_private
;
2570 struct radeon_encoder_atom_dac
*dac
= kzalloc(sizeof(struct radeon_encoder_atom_dac
), GFP_KERNEL
);
2575 dac
->tv_std
= radeon_atombios_get_tv_info(rdev
);
2579 static struct radeon_encoder_atom_dig
*
2580 radeon_atombios_set_dig_info(struct radeon_encoder
*radeon_encoder
)
2582 int encoder_enum
= (radeon_encoder
->encoder_enum
& ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
2583 struct radeon_encoder_atom_dig
*dig
= kzalloc(sizeof(struct radeon_encoder_atom_dig
), GFP_KERNEL
);
2588 /* coherent mode by default */
2589 dig
->coherent_mode
= true;
2590 dig
->dig_encoder
= -1;
2592 if (encoder_enum
== 2)
2601 radeon_add_atom_encoder(struct drm_device
*dev
,
2602 uint32_t encoder_enum
,
2603 uint32_t supported_device
,
2606 struct radeon_device
*rdev
= dev
->dev_private
;
2607 struct drm_encoder
*encoder
;
2608 struct radeon_encoder
*radeon_encoder
;
2610 /* see if we already added it */
2611 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
2612 radeon_encoder
= to_radeon_encoder(encoder
);
2613 if (radeon_encoder
->encoder_enum
== encoder_enum
) {
2614 radeon_encoder
->devices
|= supported_device
;
2621 radeon_encoder
= kzalloc(sizeof(struct radeon_encoder
), GFP_KERNEL
);
2622 if (!radeon_encoder
)
2625 encoder
= &radeon_encoder
->base
;
2626 switch (rdev
->num_crtc
) {
2628 encoder
->possible_crtcs
= 0x1;
2632 encoder
->possible_crtcs
= 0x3;
2635 encoder
->possible_crtcs
= 0xf;
2638 encoder
->possible_crtcs
= 0x3f;
2642 radeon_encoder
->enc_priv
= NULL
;
2644 radeon_encoder
->encoder_enum
= encoder_enum
;
2645 radeon_encoder
->encoder_id
= (encoder_enum
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
2646 radeon_encoder
->devices
= supported_device
;
2647 radeon_encoder
->rmx_type
= RMX_OFF
;
2648 radeon_encoder
->underscan_type
= UNDERSCAN_OFF
;
2649 radeon_encoder
->is_ext_encoder
= false;
2650 radeon_encoder
->caps
= caps
;
2652 switch (radeon_encoder
->encoder_id
) {
2653 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
2654 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
2655 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
2656 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
2657 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
2658 radeon_encoder
->rmx_type
= RMX_FULL
;
2659 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_LVDS
);
2660 radeon_encoder
->enc_priv
= radeon_atombios_get_lvds_info(radeon_encoder
);
2662 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TMDS
);
2663 radeon_encoder
->enc_priv
= radeon_atombios_set_dig_info(radeon_encoder
);
2665 drm_encoder_helper_add(encoder
, &radeon_atom_dig_helper_funcs
);
2667 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
2668 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_DAC
);
2669 radeon_encoder
->enc_priv
= radeon_atombios_set_dac_info(radeon_encoder
);
2670 drm_encoder_helper_add(encoder
, &radeon_atom_dac_helper_funcs
);
2672 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
2673 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
2674 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
2675 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TVDAC
);
2676 radeon_encoder
->enc_priv
= radeon_atombios_set_dac_info(radeon_encoder
);
2677 drm_encoder_helper_add(encoder
, &radeon_atom_dac_helper_funcs
);
2679 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
2680 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
2681 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
2682 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2683 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
2684 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2685 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2686 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2687 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
2688 radeon_encoder
->rmx_type
= RMX_FULL
;
2689 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_LVDS
);
2690 radeon_encoder
->enc_priv
= radeon_atombios_get_lvds_info(radeon_encoder
);
2691 } else if (radeon_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
)) {
2692 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_DAC
);
2693 radeon_encoder
->enc_priv
= radeon_atombios_set_dig_info(radeon_encoder
);
2695 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TMDS
);
2696 radeon_encoder
->enc_priv
= radeon_atombios_set_dig_info(radeon_encoder
);
2698 drm_encoder_helper_add(encoder
, &radeon_atom_dig_helper_funcs
);
2700 case ENCODER_OBJECT_ID_SI170B
:
2701 case ENCODER_OBJECT_ID_CH7303
:
2702 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA
:
2703 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB
:
2704 case ENCODER_OBJECT_ID_TITFP513
:
2705 case ENCODER_OBJECT_ID_VT1623
:
2706 case ENCODER_OBJECT_ID_HDMI_SI1930
:
2707 case ENCODER_OBJECT_ID_TRAVIS
:
2708 case ENCODER_OBJECT_ID_NUTMEG
:
2709 /* these are handled by the primary encoders */
2710 radeon_encoder
->is_ext_encoder
= true;
2711 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
2712 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_LVDS
);
2713 else if (radeon_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
))
2714 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_DAC
);
2716 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TMDS
);
2717 drm_encoder_helper_add(encoder
, &radeon_atom_ext_helper_funcs
);