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drm/radeon: bind fan control on CI cards to hwmon interface (v2)
[deliverable/linux.git] / drivers / gpu / drm / radeon / ci_dpm.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include "drmP.h"
26 #include "radeon.h"
27 #include "radeon_asic.h"
28 #include "radeon_ucode.h"
29 #include "cikd.h"
30 #include "r600_dpm.h"
31 #include "ci_dpm.h"
32 #include "atom.h"
33 #include <linux/seq_file.h>
34
35 #define MC_CG_ARB_FREQ_F0 0x0a
36 #define MC_CG_ARB_FREQ_F1 0x0b
37 #define MC_CG_ARB_FREQ_F2 0x0c
38 #define MC_CG_ARB_FREQ_F3 0x0d
39
40 #define SMC_RAM_END 0x40000
41
42 #define VOLTAGE_SCALE 4
43 #define VOLTAGE_VID_OFFSET_SCALE1 625
44 #define VOLTAGE_VID_OFFSET_SCALE2 100
45
46 static const struct ci_pt_defaults defaults_hawaii_xt =
47 {
48 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
49 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
50 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
51 };
52
53 static const struct ci_pt_defaults defaults_hawaii_pro =
54 {
55 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
56 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
57 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
58 };
59
60 static const struct ci_pt_defaults defaults_bonaire_xt =
61 {
62 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
63 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 },
64 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
65 };
66
67 static const struct ci_pt_defaults defaults_bonaire_pro =
68 {
69 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
70 { 0x8C, 0x23F, 0x244, 0xA6, 0x83, 0x85, 0x86, 0x86, 0x83, 0xDB, 0xDB, 0xDA, 0x67, 0x60, 0x5F },
71 { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
72 };
73
74 static const struct ci_pt_defaults defaults_saturn_xt =
75 {
76 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
77 { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D },
78 { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
79 };
80
81 static const struct ci_pt_defaults defaults_saturn_pro =
82 {
83 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
84 { 0x96, 0x21D, 0x23B, 0xA1, 0x85, 0x87, 0x83, 0x84, 0x81, 0xE6, 0xE6, 0xE6, 0x71, 0x6A, 0x6A },
85 { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
86 };
87
88 static const struct ci_pt_config_reg didt_config_ci[] =
89 {
90 { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
91 { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
92 { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
93 { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
94 { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
95 { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
96 { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
97 { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
98 { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
99 { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
100 { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
101 { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
102 { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
103 { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
104 { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
105 { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
106 { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
107 { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
108 { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
109 { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
110 { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
111 { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
112 { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
113 { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
114 { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
115 { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
116 { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
117 { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
118 { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
119 { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
120 { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
121 { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
122 { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
123 { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
124 { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
125 { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
126 { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
127 { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
128 { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
129 { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
130 { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
131 { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
132 { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
133 { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
134 { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
135 { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
136 { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
137 { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
138 { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
139 { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
140 { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
141 { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
142 { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
143 { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
144 { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
145 { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
146 { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
147 { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
148 { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
149 { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
150 { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
151 { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
152 { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
153 { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
154 { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
155 { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
156 { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
157 { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
158 { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
159 { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
160 { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
161 { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
162 { 0xFFFFFFFF }
163 };
164
165 extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);
166 extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
167 u32 arb_freq_src, u32 arb_freq_dest);
168 extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
169 extern u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
170 extern void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
171 u32 max_voltage_steps,
172 struct atom_voltage_table *voltage_table);
173 extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
174 extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
175 extern int ci_mc_load_microcode(struct radeon_device *rdev);
176 extern void cik_update_cg(struct radeon_device *rdev,
177 u32 block, bool enable);
178
179 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
180 struct atom_voltage_table_entry *voltage_table,
181 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
182 static int ci_set_power_limit(struct radeon_device *rdev, u32 n);
183 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
184 u32 target_tdp);
185 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate);
186
187 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
188 PPSMC_Msg msg, u32 parameter);
189
190 static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev);
191 static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev);
192
193 static struct ci_power_info *ci_get_pi(struct radeon_device *rdev)
194 {
195 struct ci_power_info *pi = rdev->pm.dpm.priv;
196
197 return pi;
198 }
199
200 static struct ci_ps *ci_get_ps(struct radeon_ps *rps)
201 {
202 struct ci_ps *ps = rps->ps_priv;
203
204 return ps;
205 }
206
207 static void ci_initialize_powertune_defaults(struct radeon_device *rdev)
208 {
209 struct ci_power_info *pi = ci_get_pi(rdev);
210
211 switch (rdev->pdev->device) {
212 case 0x6649:
213 case 0x6650:
214 case 0x6651:
215 case 0x6658:
216 case 0x665C:
217 case 0x665D:
218 default:
219 pi->powertune_defaults = &defaults_bonaire_xt;
220 break;
221 case 0x6640:
222 case 0x6641:
223 case 0x6646:
224 case 0x6647:
225 pi->powertune_defaults = &defaults_saturn_xt;
226 break;
227 case 0x67B8:
228 case 0x67B0:
229 pi->powertune_defaults = &defaults_hawaii_xt;
230 break;
231 case 0x67BA:
232 case 0x67B1:
233 pi->powertune_defaults = &defaults_hawaii_pro;
234 break;
235 case 0x67A0:
236 case 0x67A1:
237 case 0x67A2:
238 case 0x67A8:
239 case 0x67A9:
240 case 0x67AA:
241 case 0x67B9:
242 case 0x67BE:
243 pi->powertune_defaults = &defaults_bonaire_xt;
244 break;
245 }
246
247 pi->dte_tj_offset = 0;
248
249 pi->caps_power_containment = true;
250 pi->caps_cac = false;
251 pi->caps_sq_ramping = false;
252 pi->caps_db_ramping = false;
253 pi->caps_td_ramping = false;
254 pi->caps_tcp_ramping = false;
255
256 if (pi->caps_power_containment) {
257 pi->caps_cac = true;
258 if (rdev->family == CHIP_HAWAII)
259 pi->enable_bapm_feature = false;
260 else
261 pi->enable_bapm_feature = true;
262 pi->enable_tdc_limit_feature = true;
263 pi->enable_pkg_pwr_tracking_feature = true;
264 }
265 }
266
267 static u8 ci_convert_to_vid(u16 vddc)
268 {
269 return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
270 }
271
272 static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev)
273 {
274 struct ci_power_info *pi = ci_get_pi(rdev);
275 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
276 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
277 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
278 u32 i;
279
280 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
281 return -EINVAL;
282 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
283 return -EINVAL;
284 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count !=
285 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
286 return -EINVAL;
287
288 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
289 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
290 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
291 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
292 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
293 } else {
294 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
295 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
296 }
297 }
298 return 0;
299 }
300
301 static int ci_populate_vddc_vid(struct radeon_device *rdev)
302 {
303 struct ci_power_info *pi = ci_get_pi(rdev);
304 u8 *vid = pi->smc_powertune_table.VddCVid;
305 u32 i;
306
307 if (pi->vddc_voltage_table.count > 8)
308 return -EINVAL;
309
310 for (i = 0; i < pi->vddc_voltage_table.count; i++)
311 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
312
313 return 0;
314 }
315
316 static int ci_populate_svi_load_line(struct radeon_device *rdev)
317 {
318 struct ci_power_info *pi = ci_get_pi(rdev);
319 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
320
321 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
322 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
323 pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
324 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
325
326 return 0;
327 }
328
329 static int ci_populate_tdc_limit(struct radeon_device *rdev)
330 {
331 struct ci_power_info *pi = ci_get_pi(rdev);
332 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
333 u16 tdc_limit;
334
335 tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
336 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
337 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
338 pt_defaults->tdc_vddc_throttle_release_limit_perc;
339 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
340
341 return 0;
342 }
343
344 static int ci_populate_dw8(struct radeon_device *rdev)
345 {
346 struct ci_power_info *pi = ci_get_pi(rdev);
347 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
348 int ret;
349
350 ret = ci_read_smc_sram_dword(rdev,
351 SMU7_FIRMWARE_HEADER_LOCATION +
352 offsetof(SMU7_Firmware_Header, PmFuseTable) +
353 offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
354 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
355 pi->sram_end);
356 if (ret)
357 return -EINVAL;
358 else
359 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
360
361 return 0;
362 }
363
364 static int ci_populate_fuzzy_fan(struct radeon_device *rdev)
365 {
366 struct ci_power_info *pi = ci_get_pi(rdev);
367
368 if ((rdev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) ||
369 (rdev->pm.dpm.fan.fan_output_sensitivity == 0))
370 rdev->pm.dpm.fan.fan_output_sensitivity =
371 rdev->pm.dpm.fan.default_fan_output_sensitivity;
372
373 pi->smc_powertune_table.FuzzyFan_PwmSetDelta =
374 cpu_to_be16(rdev->pm.dpm.fan.fan_output_sensitivity);
375
376 return 0;
377 }
378
379 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev)
380 {
381 struct ci_power_info *pi = ci_get_pi(rdev);
382 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
383 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
384 int i, min, max;
385
386 min = max = hi_vid[0];
387 for (i = 0; i < 8; i++) {
388 if (0 != hi_vid[i]) {
389 if (min > hi_vid[i])
390 min = hi_vid[i];
391 if (max < hi_vid[i])
392 max = hi_vid[i];
393 }
394
395 if (0 != lo_vid[i]) {
396 if (min > lo_vid[i])
397 min = lo_vid[i];
398 if (max < lo_vid[i])
399 max = lo_vid[i];
400 }
401 }
402
403 if ((min == 0) || (max == 0))
404 return -EINVAL;
405 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
406 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
407
408 return 0;
409 }
410
411 static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev)
412 {
413 struct ci_power_info *pi = ci_get_pi(rdev);
414 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
415 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
416 struct radeon_cac_tdp_table *cac_tdp_table =
417 rdev->pm.dpm.dyn_state.cac_tdp_table;
418
419 hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
420 lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
421
422 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
423 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
424
425 return 0;
426 }
427
428 static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev)
429 {
430 struct ci_power_info *pi = ci_get_pi(rdev);
431 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
432 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table;
433 struct radeon_cac_tdp_table *cac_tdp_table =
434 rdev->pm.dpm.dyn_state.cac_tdp_table;
435 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
436 int i, j, k;
437 const u16 *def1;
438 const u16 *def2;
439
440 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
441 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
442
443 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
444 dpm_table->GpuTjMax =
445 (u8)(pi->thermal_temp_setting.temperature_high / 1000);
446 dpm_table->GpuTjHyst = 8;
447
448 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
449
450 if (ppm) {
451 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
452 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
453 } else {
454 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
455 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
456 }
457
458 dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
459 def1 = pt_defaults->bapmti_r;
460 def2 = pt_defaults->bapmti_rc;
461
462 for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
463 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
464 for (k = 0; k < SMU7_DTE_SINKS; k++) {
465 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
466 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
467 def1++;
468 def2++;
469 }
470 }
471 }
472
473 return 0;
474 }
475
476 static int ci_populate_pm_base(struct radeon_device *rdev)
477 {
478 struct ci_power_info *pi = ci_get_pi(rdev);
479 u32 pm_fuse_table_offset;
480 int ret;
481
482 if (pi->caps_power_containment) {
483 ret = ci_read_smc_sram_dword(rdev,
484 SMU7_FIRMWARE_HEADER_LOCATION +
485 offsetof(SMU7_Firmware_Header, PmFuseTable),
486 &pm_fuse_table_offset, pi->sram_end);
487 if (ret)
488 return ret;
489 ret = ci_populate_bapm_vddc_vid_sidd(rdev);
490 if (ret)
491 return ret;
492 ret = ci_populate_vddc_vid(rdev);
493 if (ret)
494 return ret;
495 ret = ci_populate_svi_load_line(rdev);
496 if (ret)
497 return ret;
498 ret = ci_populate_tdc_limit(rdev);
499 if (ret)
500 return ret;
501 ret = ci_populate_dw8(rdev);
502 if (ret)
503 return ret;
504 ret = ci_populate_fuzzy_fan(rdev);
505 if (ret)
506 return ret;
507 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev);
508 if (ret)
509 return ret;
510 ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev);
511 if (ret)
512 return ret;
513 ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset,
514 (u8 *)&pi->smc_powertune_table,
515 sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
516 if (ret)
517 return ret;
518 }
519
520 return 0;
521 }
522
523 static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable)
524 {
525 struct ci_power_info *pi = ci_get_pi(rdev);
526 u32 data;
527
528 if (pi->caps_sq_ramping) {
529 data = RREG32_DIDT(DIDT_SQ_CTRL0);
530 if (enable)
531 data |= DIDT_CTRL_EN;
532 else
533 data &= ~DIDT_CTRL_EN;
534 WREG32_DIDT(DIDT_SQ_CTRL0, data);
535 }
536
537 if (pi->caps_db_ramping) {
538 data = RREG32_DIDT(DIDT_DB_CTRL0);
539 if (enable)
540 data |= DIDT_CTRL_EN;
541 else
542 data &= ~DIDT_CTRL_EN;
543 WREG32_DIDT(DIDT_DB_CTRL0, data);
544 }
545
546 if (pi->caps_td_ramping) {
547 data = RREG32_DIDT(DIDT_TD_CTRL0);
548 if (enable)
549 data |= DIDT_CTRL_EN;
550 else
551 data &= ~DIDT_CTRL_EN;
552 WREG32_DIDT(DIDT_TD_CTRL0, data);
553 }
554
555 if (pi->caps_tcp_ramping) {
556 data = RREG32_DIDT(DIDT_TCP_CTRL0);
557 if (enable)
558 data |= DIDT_CTRL_EN;
559 else
560 data &= ~DIDT_CTRL_EN;
561 WREG32_DIDT(DIDT_TCP_CTRL0, data);
562 }
563 }
564
565 static int ci_program_pt_config_registers(struct radeon_device *rdev,
566 const struct ci_pt_config_reg *cac_config_regs)
567 {
568 const struct ci_pt_config_reg *config_regs = cac_config_regs;
569 u32 data;
570 u32 cache = 0;
571
572 if (config_regs == NULL)
573 return -EINVAL;
574
575 while (config_regs->offset != 0xFFFFFFFF) {
576 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
577 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
578 } else {
579 switch (config_regs->type) {
580 case CISLANDS_CONFIGREG_SMC_IND:
581 data = RREG32_SMC(config_regs->offset);
582 break;
583 case CISLANDS_CONFIGREG_DIDT_IND:
584 data = RREG32_DIDT(config_regs->offset);
585 break;
586 default:
587 data = RREG32(config_regs->offset << 2);
588 break;
589 }
590
591 data &= ~config_regs->mask;
592 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
593 data |= cache;
594
595 switch (config_regs->type) {
596 case CISLANDS_CONFIGREG_SMC_IND:
597 WREG32_SMC(config_regs->offset, data);
598 break;
599 case CISLANDS_CONFIGREG_DIDT_IND:
600 WREG32_DIDT(config_regs->offset, data);
601 break;
602 default:
603 WREG32(config_regs->offset << 2, data);
604 break;
605 }
606 cache = 0;
607 }
608 config_regs++;
609 }
610 return 0;
611 }
612
613 static int ci_enable_didt(struct radeon_device *rdev, bool enable)
614 {
615 struct ci_power_info *pi = ci_get_pi(rdev);
616 int ret;
617
618 if (pi->caps_sq_ramping || pi->caps_db_ramping ||
619 pi->caps_td_ramping || pi->caps_tcp_ramping) {
620 cik_enter_rlc_safe_mode(rdev);
621
622 if (enable) {
623 ret = ci_program_pt_config_registers(rdev, didt_config_ci);
624 if (ret) {
625 cik_exit_rlc_safe_mode(rdev);
626 return ret;
627 }
628 }
629
630 ci_do_enable_didt(rdev, enable);
631
632 cik_exit_rlc_safe_mode(rdev);
633 }
634
635 return 0;
636 }
637
638 static int ci_enable_power_containment(struct radeon_device *rdev, bool enable)
639 {
640 struct ci_power_info *pi = ci_get_pi(rdev);
641 PPSMC_Result smc_result;
642 int ret = 0;
643
644 if (enable) {
645 pi->power_containment_features = 0;
646 if (pi->caps_power_containment) {
647 if (pi->enable_bapm_feature) {
648 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
649 if (smc_result != PPSMC_Result_OK)
650 ret = -EINVAL;
651 else
652 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
653 }
654
655 if (pi->enable_tdc_limit_feature) {
656 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable);
657 if (smc_result != PPSMC_Result_OK)
658 ret = -EINVAL;
659 else
660 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
661 }
662
663 if (pi->enable_pkg_pwr_tracking_feature) {
664 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable);
665 if (smc_result != PPSMC_Result_OK) {
666 ret = -EINVAL;
667 } else {
668 struct radeon_cac_tdp_table *cac_tdp_table =
669 rdev->pm.dpm.dyn_state.cac_tdp_table;
670 u32 default_pwr_limit =
671 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
672
673 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
674
675 ci_set_power_limit(rdev, default_pwr_limit);
676 }
677 }
678 }
679 } else {
680 if (pi->caps_power_containment && pi->power_containment_features) {
681 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
682 ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable);
683
684 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
685 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
686
687 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
688 ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable);
689 pi->power_containment_features = 0;
690 }
691 }
692
693 return ret;
694 }
695
696 static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable)
697 {
698 struct ci_power_info *pi = ci_get_pi(rdev);
699 PPSMC_Result smc_result;
700 int ret = 0;
701
702 if (pi->caps_cac) {
703 if (enable) {
704 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
705 if (smc_result != PPSMC_Result_OK) {
706 ret = -EINVAL;
707 pi->cac_enabled = false;
708 } else {
709 pi->cac_enabled = true;
710 }
711 } else if (pi->cac_enabled) {
712 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
713 pi->cac_enabled = false;
714 }
715 }
716
717 return ret;
718 }
719
720 static int ci_enable_thermal_based_sclk_dpm(struct radeon_device *rdev,
721 bool enable)
722 {
723 struct ci_power_info *pi = ci_get_pi(rdev);
724 PPSMC_Result smc_result = PPSMC_Result_OK;
725
726 if (pi->thermal_sclk_dpm_enabled) {
727 if (enable)
728 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_ENABLE_THERMAL_DPM);
729 else
730 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DISABLE_THERMAL_DPM);
731 }
732
733 if (smc_result == PPSMC_Result_OK)
734 return 0;
735 else
736 return -EINVAL;
737 }
738
739 static int ci_power_control_set_level(struct radeon_device *rdev)
740 {
741 struct ci_power_info *pi = ci_get_pi(rdev);
742 struct radeon_cac_tdp_table *cac_tdp_table =
743 rdev->pm.dpm.dyn_state.cac_tdp_table;
744 s32 adjust_percent;
745 s32 target_tdp;
746 int ret = 0;
747 bool adjust_polarity = false; /* ??? */
748
749 if (pi->caps_power_containment) {
750 adjust_percent = adjust_polarity ?
751 rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment);
752 target_tdp = ((100 + adjust_percent) *
753 (s32)cac_tdp_table->configurable_tdp) / 100;
754
755 ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp);
756 }
757
758 return ret;
759 }
760
761 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
762 {
763 struct ci_power_info *pi = ci_get_pi(rdev);
764
765 if (pi->uvd_power_gated == gate)
766 return;
767
768 pi->uvd_power_gated = gate;
769
770 ci_update_uvd_dpm(rdev, gate);
771 }
772
773 bool ci_dpm_vblank_too_short(struct radeon_device *rdev)
774 {
775 struct ci_power_info *pi = ci_get_pi(rdev);
776 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
777 u32 switch_limit = pi->mem_gddr5 ? 450 : 300;
778
779 if (vblank_time < switch_limit)
780 return true;
781 else
782 return false;
783
784 }
785
786 static void ci_apply_state_adjust_rules(struct radeon_device *rdev,
787 struct radeon_ps *rps)
788 {
789 struct ci_ps *ps = ci_get_ps(rps);
790 struct ci_power_info *pi = ci_get_pi(rdev);
791 struct radeon_clock_and_voltage_limits *max_limits;
792 bool disable_mclk_switching;
793 u32 sclk, mclk;
794 int i;
795
796 if (rps->vce_active) {
797 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
798 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
799 } else {
800 rps->evclk = 0;
801 rps->ecclk = 0;
802 }
803
804 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
805 ci_dpm_vblank_too_short(rdev))
806 disable_mclk_switching = true;
807 else
808 disable_mclk_switching = false;
809
810 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
811 pi->battery_state = true;
812 else
813 pi->battery_state = false;
814
815 if (rdev->pm.dpm.ac_power)
816 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
817 else
818 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
819
820 if (rdev->pm.dpm.ac_power == false) {
821 for (i = 0; i < ps->performance_level_count; i++) {
822 if (ps->performance_levels[i].mclk > max_limits->mclk)
823 ps->performance_levels[i].mclk = max_limits->mclk;
824 if (ps->performance_levels[i].sclk > max_limits->sclk)
825 ps->performance_levels[i].sclk = max_limits->sclk;
826 }
827 }
828
829 /* XXX validate the min clocks required for display */
830
831 if (disable_mclk_switching) {
832 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
833 sclk = ps->performance_levels[0].sclk;
834 } else {
835 mclk = ps->performance_levels[0].mclk;
836 sclk = ps->performance_levels[0].sclk;
837 }
838
839 if (rps->vce_active) {
840 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
841 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
842 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
843 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
844 }
845
846 ps->performance_levels[0].sclk = sclk;
847 ps->performance_levels[0].mclk = mclk;
848
849 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
850 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
851
852 if (disable_mclk_switching) {
853 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
854 ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
855 } else {
856 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
857 ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
858 }
859 }
860
861 static int ci_thermal_set_temperature_range(struct radeon_device *rdev,
862 int min_temp, int max_temp)
863 {
864 int low_temp = 0 * 1000;
865 int high_temp = 255 * 1000;
866 u32 tmp;
867
868 if (low_temp < min_temp)
869 low_temp = min_temp;
870 if (high_temp > max_temp)
871 high_temp = max_temp;
872 if (high_temp < low_temp) {
873 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
874 return -EINVAL;
875 }
876
877 tmp = RREG32_SMC(CG_THERMAL_INT);
878 tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK);
879 tmp |= CI_DIG_THERM_INTH(high_temp / 1000) |
880 CI_DIG_THERM_INTL(low_temp / 1000);
881 WREG32_SMC(CG_THERMAL_INT, tmp);
882
883 #if 0
884 /* XXX: need to figure out how to handle this properly */
885 tmp = RREG32_SMC(CG_THERMAL_CTRL);
886 tmp &= DIG_THERM_DPM_MASK;
887 tmp |= DIG_THERM_DPM(high_temp / 1000);
888 WREG32_SMC(CG_THERMAL_CTRL, tmp);
889 #endif
890
891 rdev->pm.dpm.thermal.min_temp = low_temp;
892 rdev->pm.dpm.thermal.max_temp = high_temp;
893
894 return 0;
895 }
896
897 static int ci_thermal_enable_alert(struct radeon_device *rdev,
898 bool enable)
899 {
900 u32 thermal_int = RREG32_SMC(CG_THERMAL_INT);
901 PPSMC_Result result;
902
903 if (enable) {
904 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
905 WREG32_SMC(CG_THERMAL_INT, thermal_int);
906 rdev->irq.dpm_thermal = false;
907 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Enable);
908 if (result != PPSMC_Result_OK) {
909 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
910 return -EINVAL;
911 }
912 } else {
913 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
914 WREG32_SMC(CG_THERMAL_INT, thermal_int);
915 rdev->irq.dpm_thermal = true;
916 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Disable);
917 if (result != PPSMC_Result_OK) {
918 DRM_DEBUG_KMS("Could not disable thermal interrupts.\n");
919 return -EINVAL;
920 }
921 }
922
923 return 0;
924 }
925
926 static void ci_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
927 {
928 struct ci_power_info *pi = ci_get_pi(rdev);
929 u32 tmp;
930
931 if (pi->fan_ctrl_is_in_default_mode) {
932 tmp = (RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
933 pi->fan_ctrl_default_mode = tmp;
934 tmp = (RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
935 pi->t_min = tmp;
936 pi->fan_ctrl_is_in_default_mode = false;
937 }
938
939 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;
940 tmp |= TMIN(0);
941 WREG32_SMC(CG_FDO_CTRL2, tmp);
942
943 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
944 tmp |= FDO_PWM_MODE(mode);
945 WREG32_SMC(CG_FDO_CTRL2, tmp);
946 }
947
948 static int ci_thermal_setup_fan_table(struct radeon_device *rdev)
949 {
950 struct ci_power_info *pi = ci_get_pi(rdev);
951 SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
952 u32 duty100;
953 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
954 u16 fdo_min, slope1, slope2;
955 u32 reference_clock, tmp;
956 int ret;
957 u64 tmp64;
958
959 if (!pi->fan_table_start) {
960 rdev->pm.dpm.fan.ucode_fan_control = false;
961 return 0;
962 }
963
964 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
965
966 if (duty100 == 0) {
967 rdev->pm.dpm.fan.ucode_fan_control = false;
968 return 0;
969 }
970
971 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
972 do_div(tmp64, 10000);
973 fdo_min = (u16)tmp64;
974
975 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
976 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
977
978 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
979 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
980
981 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
982 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
983
984 fan_table.TempMin = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
985 fan_table.TempMed = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
986 fan_table.TempMax = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
987
988 fan_table.Slope1 = cpu_to_be16(slope1);
989 fan_table.Slope2 = cpu_to_be16(slope2);
990
991 fan_table.FdoMin = cpu_to_be16(fdo_min);
992
993 fan_table.HystDown = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
994
995 fan_table.HystUp = cpu_to_be16(1);
996
997 fan_table.HystSlope = cpu_to_be16(1);
998
999 fan_table.TempRespLim = cpu_to_be16(5);
1000
1001 reference_clock = radeon_get_xclk(rdev);
1002
1003 fan_table.RefreshPeriod = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
1004 reference_clock) / 1600);
1005
1006 fan_table.FdoMax = cpu_to_be16((u16)duty100);
1007
1008 tmp = (RREG32_SMC(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
1009 fan_table.TempSrc = (uint8_t)tmp;
1010
1011 ret = ci_copy_bytes_to_smc(rdev,
1012 pi->fan_table_start,
1013 (u8 *)(&fan_table),
1014 sizeof(fan_table),
1015 pi->sram_end);
1016
1017 if (ret) {
1018 DRM_ERROR("Failed to load fan table to the SMC.");
1019 rdev->pm.dpm.fan.ucode_fan_control = false;
1020 }
1021
1022 return 0;
1023 }
1024
1025 static int ci_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
1026 {
1027 struct ci_power_info *pi = ci_get_pi(rdev);
1028 PPSMC_Result ret;
1029
1030 if (pi->caps_od_fuzzy_fan_control_support) {
1031 ret = ci_send_msg_to_smc_with_parameter(rdev,
1032 PPSMC_StartFanControl,
1033 FAN_CONTROL_FUZZY);
1034 if (ret != PPSMC_Result_OK)
1035 return -EINVAL;
1036 ret = ci_send_msg_to_smc_with_parameter(rdev,
1037 PPSMC_MSG_SetFanPwmMax,
1038 rdev->pm.dpm.fan.default_max_fan_pwm);
1039 if (ret != PPSMC_Result_OK)
1040 return -EINVAL;
1041 } else {
1042 ret = ci_send_msg_to_smc_with_parameter(rdev,
1043 PPSMC_StartFanControl,
1044 FAN_CONTROL_TABLE);
1045 if (ret != PPSMC_Result_OK)
1046 return -EINVAL;
1047 }
1048
1049 pi->fan_is_controlled_by_smc = true;
1050 return 0;
1051 }
1052
1053 static int ci_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
1054 {
1055 PPSMC_Result ret;
1056 struct ci_power_info *pi = ci_get_pi(rdev);
1057
1058 ret = ci_send_msg_to_smc(rdev, PPSMC_StopFanControl);
1059 if (ret == PPSMC_Result_OK) {
1060 pi->fan_is_controlled_by_smc = false;
1061 return 0;
1062 } else
1063 return -EINVAL;
1064 }
1065
1066 int ci_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
1067 u32 *speed)
1068 {
1069 u32 duty, duty100;
1070 u64 tmp64;
1071
1072 if (rdev->pm.no_fan)
1073 return -ENOENT;
1074
1075 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
1076 duty = (RREG32_SMC(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
1077
1078 if (duty100 == 0)
1079 return -EINVAL;
1080
1081 tmp64 = (u64)duty * 100;
1082 do_div(tmp64, duty100);
1083 *speed = (u32)tmp64;
1084
1085 if (*speed > 100)
1086 *speed = 100;
1087
1088 return 0;
1089 }
1090
1091 int ci_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
1092 u32 speed)
1093 {
1094 u32 tmp;
1095 u32 duty, duty100;
1096 u64 tmp64;
1097 struct ci_power_info *pi = ci_get_pi(rdev);
1098
1099 if (rdev->pm.no_fan)
1100 return -ENOENT;
1101
1102 if (pi->fan_is_controlled_by_smc)
1103 return -EINVAL;
1104
1105 if (speed > 100)
1106 return -EINVAL;
1107
1108 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
1109
1110 if (duty100 == 0)
1111 return -EINVAL;
1112
1113 tmp64 = (u64)speed * duty100;
1114 do_div(tmp64, 100);
1115 duty = (u32)tmp64;
1116
1117 tmp = RREG32_SMC(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
1118 tmp |= FDO_STATIC_DUTY(duty);
1119 WREG32_SMC(CG_FDO_CTRL0, tmp);
1120
1121 return 0;
1122 }
1123
1124 void ci_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
1125 {
1126 if (mode) {
1127 /* stop auto-manage */
1128 if (rdev->pm.dpm.fan.ucode_fan_control)
1129 ci_fan_ctrl_stop_smc_fan_control(rdev);
1130 ci_fan_ctrl_set_static_mode(rdev, mode);
1131 } else {
1132 /* restart auto-manage */
1133 if (rdev->pm.dpm.fan.ucode_fan_control)
1134 ci_thermal_start_smc_fan_control(rdev);
1135 else
1136 ci_fan_ctrl_set_default_mode(rdev);
1137 }
1138 }
1139
1140 u32 ci_fan_ctrl_get_mode(struct radeon_device *rdev)
1141 {
1142 struct ci_power_info *pi = ci_get_pi(rdev);
1143 u32 tmp;
1144
1145 if (pi->fan_is_controlled_by_smc)
1146 return 0;
1147
1148 tmp = RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
1149 return (tmp >> FDO_PWM_MODE_SHIFT);
1150 }
1151
1152 #if 0
1153 static int ci_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
1154 u32 *speed)
1155 {
1156 u32 tach_period;
1157 u32 xclk = radeon_get_xclk(rdev);
1158
1159 if (rdev->pm.no_fan)
1160 return -ENOENT;
1161
1162 if (rdev->pm.fan_pulses_per_revolution == 0)
1163 return -ENOENT;
1164
1165 tach_period = (RREG32_SMC(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
1166 if (tach_period == 0)
1167 return -ENOENT;
1168
1169 *speed = 60 * xclk * 10000 / tach_period;
1170
1171 return 0;
1172 }
1173
1174 static int ci_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
1175 u32 speed)
1176 {
1177 u32 tach_period, tmp;
1178 u32 xclk = radeon_get_xclk(rdev);
1179
1180 if (rdev->pm.no_fan)
1181 return -ENOENT;
1182
1183 if (rdev->pm.fan_pulses_per_revolution == 0)
1184 return -ENOENT;
1185
1186 if ((speed < rdev->pm.fan_min_rpm) ||
1187 (speed > rdev->pm.fan_max_rpm))
1188 return -EINVAL;
1189
1190 if (rdev->pm.dpm.fan.ucode_fan_control)
1191 ci_fan_ctrl_stop_smc_fan_control(rdev);
1192
1193 tach_period = 60 * xclk * 10000 / (8 * speed);
1194 tmp = RREG32_SMC(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
1195 tmp |= TARGET_PERIOD(tach_period);
1196 WREG32_SMC(CG_TACH_CTRL, tmp);
1197
1198 ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
1199
1200 return 0;
1201 }
1202 #endif
1203
1204 static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev)
1205 {
1206 struct ci_power_info *pi = ci_get_pi(rdev);
1207 u32 tmp;
1208
1209 if (!pi->fan_ctrl_is_in_default_mode) {
1210 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
1211 tmp |= FDO_PWM_MODE(pi->fan_ctrl_default_mode);
1212 WREG32_SMC(CG_FDO_CTRL2, tmp);
1213
1214 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;
1215 tmp |= TMIN(pi->t_min);
1216 WREG32_SMC(CG_FDO_CTRL2, tmp);
1217 pi->fan_ctrl_is_in_default_mode = true;
1218 }
1219 }
1220
1221 static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev)
1222 {
1223 if (rdev->pm.dpm.fan.ucode_fan_control) {
1224 ci_fan_ctrl_start_smc_fan_control(rdev);
1225 ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
1226 }
1227 }
1228
1229 static void ci_thermal_initialize(struct radeon_device *rdev)
1230 {
1231 u32 tmp;
1232
1233 if (rdev->pm.fan_pulses_per_revolution) {
1234 tmp = RREG32_SMC(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
1235 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
1236 WREG32_SMC(CG_TACH_CTRL, tmp);
1237 }
1238
1239 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
1240 tmp |= TACH_PWM_RESP_RATE(0x28);
1241 WREG32_SMC(CG_FDO_CTRL2, tmp);
1242 }
1243
1244 static int ci_thermal_start_thermal_controller(struct radeon_device *rdev)
1245 {
1246 int ret;
1247
1248 ci_thermal_initialize(rdev);
1249 ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1250 if (ret)
1251 return ret;
1252 ret = ci_thermal_enable_alert(rdev, true);
1253 if (ret)
1254 return ret;
1255 if (rdev->pm.dpm.fan.ucode_fan_control) {
1256 ret = ci_thermal_setup_fan_table(rdev);
1257 if (ret)
1258 return ret;
1259 ci_thermal_start_smc_fan_control(rdev);
1260 }
1261
1262 return 0;
1263 }
1264
1265 static void ci_thermal_stop_thermal_controller(struct radeon_device *rdev)
1266 {
1267 if (!rdev->pm.no_fan)
1268 ci_fan_ctrl_set_default_mode(rdev);
1269 }
1270
1271 #if 0
1272 static int ci_read_smc_soft_register(struct radeon_device *rdev,
1273 u16 reg_offset, u32 *value)
1274 {
1275 struct ci_power_info *pi = ci_get_pi(rdev);
1276
1277 return ci_read_smc_sram_dword(rdev,
1278 pi->soft_regs_start + reg_offset,
1279 value, pi->sram_end);
1280 }
1281 #endif
1282
1283 static int ci_write_smc_soft_register(struct radeon_device *rdev,
1284 u16 reg_offset, u32 value)
1285 {
1286 struct ci_power_info *pi = ci_get_pi(rdev);
1287
1288 return ci_write_smc_sram_dword(rdev,
1289 pi->soft_regs_start + reg_offset,
1290 value, pi->sram_end);
1291 }
1292
1293 static void ci_init_fps_limits(struct radeon_device *rdev)
1294 {
1295 struct ci_power_info *pi = ci_get_pi(rdev);
1296 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
1297
1298 if (pi->caps_fps) {
1299 u16 tmp;
1300
1301 tmp = 45;
1302 table->FpsHighT = cpu_to_be16(tmp);
1303
1304 tmp = 30;
1305 table->FpsLowT = cpu_to_be16(tmp);
1306 }
1307 }
1308
1309 static int ci_update_sclk_t(struct radeon_device *rdev)
1310 {
1311 struct ci_power_info *pi = ci_get_pi(rdev);
1312 int ret = 0;
1313 u32 low_sclk_interrupt_t = 0;
1314
1315 if (pi->caps_sclk_throttle_low_notification) {
1316 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
1317
1318 ret = ci_copy_bytes_to_smc(rdev,
1319 pi->dpm_table_start +
1320 offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
1321 (u8 *)&low_sclk_interrupt_t,
1322 sizeof(u32), pi->sram_end);
1323
1324 }
1325
1326 return ret;
1327 }
1328
1329 static void ci_get_leakage_voltages(struct radeon_device *rdev)
1330 {
1331 struct ci_power_info *pi = ci_get_pi(rdev);
1332 u16 leakage_id, virtual_voltage_id;
1333 u16 vddc, vddci;
1334 int i;
1335
1336 pi->vddc_leakage.count = 0;
1337 pi->vddci_leakage.count = 0;
1338
1339 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
1340 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1341 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1342 if (radeon_atom_get_voltage_evv(rdev, virtual_voltage_id, &vddc) != 0)
1343 continue;
1344 if (vddc != 0 && vddc != virtual_voltage_id) {
1345 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1346 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1347 pi->vddc_leakage.count++;
1348 }
1349 }
1350 } else if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) {
1351 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1352 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1353 if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci,
1354 virtual_voltage_id,
1355 leakage_id) == 0) {
1356 if (vddc != 0 && vddc != virtual_voltage_id) {
1357 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1358 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1359 pi->vddc_leakage.count++;
1360 }
1361 if (vddci != 0 && vddci != virtual_voltage_id) {
1362 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
1363 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
1364 pi->vddci_leakage.count++;
1365 }
1366 }
1367 }
1368 }
1369 }
1370
1371 static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
1372 {
1373 struct ci_power_info *pi = ci_get_pi(rdev);
1374 bool want_thermal_protection;
1375 enum radeon_dpm_event_src dpm_event_src;
1376 u32 tmp;
1377
1378 switch (sources) {
1379 case 0:
1380 default:
1381 want_thermal_protection = false;
1382 break;
1383 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
1384 want_thermal_protection = true;
1385 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
1386 break;
1387 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
1388 want_thermal_protection = true;
1389 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
1390 break;
1391 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
1392 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
1393 want_thermal_protection = true;
1394 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
1395 break;
1396 }
1397
1398 if (want_thermal_protection) {
1399 #if 0
1400 /* XXX: need to figure out how to handle this properly */
1401 tmp = RREG32_SMC(CG_THERMAL_CTRL);
1402 tmp &= DPM_EVENT_SRC_MASK;
1403 tmp |= DPM_EVENT_SRC(dpm_event_src);
1404 WREG32_SMC(CG_THERMAL_CTRL, tmp);
1405 #endif
1406
1407 tmp = RREG32_SMC(GENERAL_PWRMGT);
1408 if (pi->thermal_protection)
1409 tmp &= ~THERMAL_PROTECTION_DIS;
1410 else
1411 tmp |= THERMAL_PROTECTION_DIS;
1412 WREG32_SMC(GENERAL_PWRMGT, tmp);
1413 } else {
1414 tmp = RREG32_SMC(GENERAL_PWRMGT);
1415 tmp |= THERMAL_PROTECTION_DIS;
1416 WREG32_SMC(GENERAL_PWRMGT, tmp);
1417 }
1418 }
1419
1420 static void ci_enable_auto_throttle_source(struct radeon_device *rdev,
1421 enum radeon_dpm_auto_throttle_src source,
1422 bool enable)
1423 {
1424 struct ci_power_info *pi = ci_get_pi(rdev);
1425
1426 if (enable) {
1427 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1428 pi->active_auto_throttle_sources |= 1 << source;
1429 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1430 }
1431 } else {
1432 if (pi->active_auto_throttle_sources & (1 << source)) {
1433 pi->active_auto_throttle_sources &= ~(1 << source);
1434 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1435 }
1436 }
1437 }
1438
1439 static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev)
1440 {
1441 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1442 ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1443 }
1444
1445 static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev)
1446 {
1447 struct ci_power_info *pi = ci_get_pi(rdev);
1448 PPSMC_Result smc_result;
1449
1450 if (!pi->need_update_smu7_dpm_table)
1451 return 0;
1452
1453 if ((!pi->sclk_dpm_key_disabled) &&
1454 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1455 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1456 if (smc_result != PPSMC_Result_OK)
1457 return -EINVAL;
1458 }
1459
1460 if ((!pi->mclk_dpm_key_disabled) &&
1461 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1462 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1463 if (smc_result != PPSMC_Result_OK)
1464 return -EINVAL;
1465 }
1466
1467 pi->need_update_smu7_dpm_table = 0;
1468 return 0;
1469 }
1470
1471 static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable)
1472 {
1473 struct ci_power_info *pi = ci_get_pi(rdev);
1474 PPSMC_Result smc_result;
1475
1476 if (enable) {
1477 if (!pi->sclk_dpm_key_disabled) {
1478 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable);
1479 if (smc_result != PPSMC_Result_OK)
1480 return -EINVAL;
1481 }
1482
1483 if (!pi->mclk_dpm_key_disabled) {
1484 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable);
1485 if (smc_result != PPSMC_Result_OK)
1486 return -EINVAL;
1487
1488 WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN);
1489
1490 WREG32_SMC(LCAC_MC0_CNTL, 0x05);
1491 WREG32_SMC(LCAC_MC1_CNTL, 0x05);
1492 WREG32_SMC(LCAC_CPL_CNTL, 0x100005);
1493
1494 udelay(10);
1495
1496 WREG32_SMC(LCAC_MC0_CNTL, 0x400005);
1497 WREG32_SMC(LCAC_MC1_CNTL, 0x400005);
1498 WREG32_SMC(LCAC_CPL_CNTL, 0x500005);
1499 }
1500 } else {
1501 if (!pi->sclk_dpm_key_disabled) {
1502 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable);
1503 if (smc_result != PPSMC_Result_OK)
1504 return -EINVAL;
1505 }
1506
1507 if (!pi->mclk_dpm_key_disabled) {
1508 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable);
1509 if (smc_result != PPSMC_Result_OK)
1510 return -EINVAL;
1511 }
1512 }
1513
1514 return 0;
1515 }
1516
1517 static int ci_start_dpm(struct radeon_device *rdev)
1518 {
1519 struct ci_power_info *pi = ci_get_pi(rdev);
1520 PPSMC_Result smc_result;
1521 int ret;
1522 u32 tmp;
1523
1524 tmp = RREG32_SMC(GENERAL_PWRMGT);
1525 tmp |= GLOBAL_PWRMGT_EN;
1526 WREG32_SMC(GENERAL_PWRMGT, tmp);
1527
1528 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1529 tmp |= DYNAMIC_PM_EN;
1530 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1531
1532 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1533
1534 WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN);
1535
1536 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable);
1537 if (smc_result != PPSMC_Result_OK)
1538 return -EINVAL;
1539
1540 ret = ci_enable_sclk_mclk_dpm(rdev, true);
1541 if (ret)
1542 return ret;
1543
1544 if (!pi->pcie_dpm_key_disabled) {
1545 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable);
1546 if (smc_result != PPSMC_Result_OK)
1547 return -EINVAL;
1548 }
1549
1550 return 0;
1551 }
1552
1553 static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev)
1554 {
1555 struct ci_power_info *pi = ci_get_pi(rdev);
1556 PPSMC_Result smc_result;
1557
1558 if (!pi->need_update_smu7_dpm_table)
1559 return 0;
1560
1561 if ((!pi->sclk_dpm_key_disabled) &&
1562 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1563 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1564 if (smc_result != PPSMC_Result_OK)
1565 return -EINVAL;
1566 }
1567
1568 if ((!pi->mclk_dpm_key_disabled) &&
1569 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1570 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1571 if (smc_result != PPSMC_Result_OK)
1572 return -EINVAL;
1573 }
1574
1575 return 0;
1576 }
1577
1578 static int ci_stop_dpm(struct radeon_device *rdev)
1579 {
1580 struct ci_power_info *pi = ci_get_pi(rdev);
1581 PPSMC_Result smc_result;
1582 int ret;
1583 u32 tmp;
1584
1585 tmp = RREG32_SMC(GENERAL_PWRMGT);
1586 tmp &= ~GLOBAL_PWRMGT_EN;
1587 WREG32_SMC(GENERAL_PWRMGT, tmp);
1588
1589 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1590 tmp &= ~DYNAMIC_PM_EN;
1591 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1592
1593 if (!pi->pcie_dpm_key_disabled) {
1594 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable);
1595 if (smc_result != PPSMC_Result_OK)
1596 return -EINVAL;
1597 }
1598
1599 ret = ci_enable_sclk_mclk_dpm(rdev, false);
1600 if (ret)
1601 return ret;
1602
1603 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable);
1604 if (smc_result != PPSMC_Result_OK)
1605 return -EINVAL;
1606
1607 return 0;
1608 }
1609
1610 static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable)
1611 {
1612 u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1613
1614 if (enable)
1615 tmp &= ~SCLK_PWRMGT_OFF;
1616 else
1617 tmp |= SCLK_PWRMGT_OFF;
1618 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1619 }
1620
1621 #if 0
1622 static int ci_notify_hw_of_power_source(struct radeon_device *rdev,
1623 bool ac_power)
1624 {
1625 struct ci_power_info *pi = ci_get_pi(rdev);
1626 struct radeon_cac_tdp_table *cac_tdp_table =
1627 rdev->pm.dpm.dyn_state.cac_tdp_table;
1628 u32 power_limit;
1629
1630 if (ac_power)
1631 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1632 else
1633 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1634
1635 ci_set_power_limit(rdev, power_limit);
1636
1637 if (pi->caps_automatic_dc_transition) {
1638 if (ac_power)
1639 ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC);
1640 else
1641 ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp);
1642 }
1643
1644 return 0;
1645 }
1646 #endif
1647
1648 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
1649 PPSMC_Msg msg, u32 parameter)
1650 {
1651 WREG32(SMC_MSG_ARG_0, parameter);
1652 return ci_send_msg_to_smc(rdev, msg);
1653 }
1654
1655 static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev,
1656 PPSMC_Msg msg, u32 *parameter)
1657 {
1658 PPSMC_Result smc_result;
1659
1660 smc_result = ci_send_msg_to_smc(rdev, msg);
1661
1662 if ((smc_result == PPSMC_Result_OK) && parameter)
1663 *parameter = RREG32(SMC_MSG_ARG_0);
1664
1665 return smc_result;
1666 }
1667
1668 static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n)
1669 {
1670 struct ci_power_info *pi = ci_get_pi(rdev);
1671
1672 if (!pi->sclk_dpm_key_disabled) {
1673 PPSMC_Result smc_result =
1674 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n);
1675 if (smc_result != PPSMC_Result_OK)
1676 return -EINVAL;
1677 }
1678
1679 return 0;
1680 }
1681
1682 static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n)
1683 {
1684 struct ci_power_info *pi = ci_get_pi(rdev);
1685
1686 if (!pi->mclk_dpm_key_disabled) {
1687 PPSMC_Result smc_result =
1688 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n);
1689 if (smc_result != PPSMC_Result_OK)
1690 return -EINVAL;
1691 }
1692
1693 return 0;
1694 }
1695
1696 static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n)
1697 {
1698 struct ci_power_info *pi = ci_get_pi(rdev);
1699
1700 if (!pi->pcie_dpm_key_disabled) {
1701 PPSMC_Result smc_result =
1702 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1703 if (smc_result != PPSMC_Result_OK)
1704 return -EINVAL;
1705 }
1706
1707 return 0;
1708 }
1709
1710 static int ci_set_power_limit(struct radeon_device *rdev, u32 n)
1711 {
1712 struct ci_power_info *pi = ci_get_pi(rdev);
1713
1714 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1715 PPSMC_Result smc_result =
1716 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n);
1717 if (smc_result != PPSMC_Result_OK)
1718 return -EINVAL;
1719 }
1720
1721 return 0;
1722 }
1723
1724 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
1725 u32 target_tdp)
1726 {
1727 PPSMC_Result smc_result =
1728 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1729 if (smc_result != PPSMC_Result_OK)
1730 return -EINVAL;
1731 return 0;
1732 }
1733
1734 static int ci_set_boot_state(struct radeon_device *rdev)
1735 {
1736 return ci_enable_sclk_mclk_dpm(rdev, false);
1737 }
1738
1739 static u32 ci_get_average_sclk_freq(struct radeon_device *rdev)
1740 {
1741 u32 sclk_freq;
1742 PPSMC_Result smc_result =
1743 ci_send_msg_to_smc_return_parameter(rdev,
1744 PPSMC_MSG_API_GetSclkFrequency,
1745 &sclk_freq);
1746 if (smc_result != PPSMC_Result_OK)
1747 sclk_freq = 0;
1748
1749 return sclk_freq;
1750 }
1751
1752 static u32 ci_get_average_mclk_freq(struct radeon_device *rdev)
1753 {
1754 u32 mclk_freq;
1755 PPSMC_Result smc_result =
1756 ci_send_msg_to_smc_return_parameter(rdev,
1757 PPSMC_MSG_API_GetMclkFrequency,
1758 &mclk_freq);
1759 if (smc_result != PPSMC_Result_OK)
1760 mclk_freq = 0;
1761
1762 return mclk_freq;
1763 }
1764
1765 static void ci_dpm_start_smc(struct radeon_device *rdev)
1766 {
1767 int i;
1768
1769 ci_program_jump_on_start(rdev);
1770 ci_start_smc_clock(rdev);
1771 ci_start_smc(rdev);
1772 for (i = 0; i < rdev->usec_timeout; i++) {
1773 if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED)
1774 break;
1775 }
1776 }
1777
1778 static void ci_dpm_stop_smc(struct radeon_device *rdev)
1779 {
1780 ci_reset_smc(rdev);
1781 ci_stop_smc_clock(rdev);
1782 }
1783
1784 static int ci_process_firmware_header(struct radeon_device *rdev)
1785 {
1786 struct ci_power_info *pi = ci_get_pi(rdev);
1787 u32 tmp;
1788 int ret;
1789
1790 ret = ci_read_smc_sram_dword(rdev,
1791 SMU7_FIRMWARE_HEADER_LOCATION +
1792 offsetof(SMU7_Firmware_Header, DpmTable),
1793 &tmp, pi->sram_end);
1794 if (ret)
1795 return ret;
1796
1797 pi->dpm_table_start = tmp;
1798
1799 ret = ci_read_smc_sram_dword(rdev,
1800 SMU7_FIRMWARE_HEADER_LOCATION +
1801 offsetof(SMU7_Firmware_Header, SoftRegisters),
1802 &tmp, pi->sram_end);
1803 if (ret)
1804 return ret;
1805
1806 pi->soft_regs_start = tmp;
1807
1808 ret = ci_read_smc_sram_dword(rdev,
1809 SMU7_FIRMWARE_HEADER_LOCATION +
1810 offsetof(SMU7_Firmware_Header, mcRegisterTable),
1811 &tmp, pi->sram_end);
1812 if (ret)
1813 return ret;
1814
1815 pi->mc_reg_table_start = tmp;
1816
1817 ret = ci_read_smc_sram_dword(rdev,
1818 SMU7_FIRMWARE_HEADER_LOCATION +
1819 offsetof(SMU7_Firmware_Header, FanTable),
1820 &tmp, pi->sram_end);
1821 if (ret)
1822 return ret;
1823
1824 pi->fan_table_start = tmp;
1825
1826 ret = ci_read_smc_sram_dword(rdev,
1827 SMU7_FIRMWARE_HEADER_LOCATION +
1828 offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1829 &tmp, pi->sram_end);
1830 if (ret)
1831 return ret;
1832
1833 pi->arb_table_start = tmp;
1834
1835 return 0;
1836 }
1837
1838 static void ci_read_clock_registers(struct radeon_device *rdev)
1839 {
1840 struct ci_power_info *pi = ci_get_pi(rdev);
1841
1842 pi->clock_registers.cg_spll_func_cntl =
1843 RREG32_SMC(CG_SPLL_FUNC_CNTL);
1844 pi->clock_registers.cg_spll_func_cntl_2 =
1845 RREG32_SMC(CG_SPLL_FUNC_CNTL_2);
1846 pi->clock_registers.cg_spll_func_cntl_3 =
1847 RREG32_SMC(CG_SPLL_FUNC_CNTL_3);
1848 pi->clock_registers.cg_spll_func_cntl_4 =
1849 RREG32_SMC(CG_SPLL_FUNC_CNTL_4);
1850 pi->clock_registers.cg_spll_spread_spectrum =
1851 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1852 pi->clock_registers.cg_spll_spread_spectrum_2 =
1853 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2);
1854 pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
1855 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
1856 pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
1857 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
1858 pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
1859 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
1860 pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
1861 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
1862 pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
1863 }
1864
1865 static void ci_init_sclk_t(struct radeon_device *rdev)
1866 {
1867 struct ci_power_info *pi = ci_get_pi(rdev);
1868
1869 pi->low_sclk_interrupt_t = 0;
1870 }
1871
1872 static void ci_enable_thermal_protection(struct radeon_device *rdev,
1873 bool enable)
1874 {
1875 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1876
1877 if (enable)
1878 tmp &= ~THERMAL_PROTECTION_DIS;
1879 else
1880 tmp |= THERMAL_PROTECTION_DIS;
1881 WREG32_SMC(GENERAL_PWRMGT, tmp);
1882 }
1883
1884 static void ci_enable_acpi_power_management(struct radeon_device *rdev)
1885 {
1886 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1887
1888 tmp |= STATIC_PM_EN;
1889
1890 WREG32_SMC(GENERAL_PWRMGT, tmp);
1891 }
1892
1893 #if 0
1894 static int ci_enter_ulp_state(struct radeon_device *rdev)
1895 {
1896
1897 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
1898
1899 udelay(25000);
1900
1901 return 0;
1902 }
1903
1904 static int ci_exit_ulp_state(struct radeon_device *rdev)
1905 {
1906 int i;
1907
1908 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
1909
1910 udelay(7000);
1911
1912 for (i = 0; i < rdev->usec_timeout; i++) {
1913 if (RREG32(SMC_RESP_0) == 1)
1914 break;
1915 udelay(1000);
1916 }
1917
1918 return 0;
1919 }
1920 #endif
1921
1922 static int ci_notify_smc_display_change(struct radeon_device *rdev,
1923 bool has_display)
1924 {
1925 PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
1926
1927 return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL;
1928 }
1929
1930 static int ci_enable_ds_master_switch(struct radeon_device *rdev,
1931 bool enable)
1932 {
1933 struct ci_power_info *pi = ci_get_pi(rdev);
1934
1935 if (enable) {
1936 if (pi->caps_sclk_ds) {
1937 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
1938 return -EINVAL;
1939 } else {
1940 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1941 return -EINVAL;
1942 }
1943 } else {
1944 if (pi->caps_sclk_ds) {
1945 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1946 return -EINVAL;
1947 }
1948 }
1949
1950 return 0;
1951 }
1952
1953 static void ci_program_display_gap(struct radeon_device *rdev)
1954 {
1955 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1956 u32 pre_vbi_time_in_us;
1957 u32 frame_time_in_us;
1958 u32 ref_clock = rdev->clock.spll.reference_freq;
1959 u32 refresh_rate = r600_dpm_get_vrefresh(rdev);
1960 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
1961
1962 tmp &= ~DISP_GAP_MASK;
1963 if (rdev->pm.dpm.new_active_crtc_count > 0)
1964 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1965 else
1966 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1967 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1968
1969 if (refresh_rate == 0)
1970 refresh_rate = 60;
1971 if (vblank_time == 0xffffffff)
1972 vblank_time = 500;
1973 frame_time_in_us = 1000000 / refresh_rate;
1974 pre_vbi_time_in_us =
1975 frame_time_in_us - 200 - vblank_time;
1976 tmp = pre_vbi_time_in_us * (ref_clock / 100);
1977
1978 WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp);
1979 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
1980 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
1981
1982
1983 ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1));
1984
1985 }
1986
1987 static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
1988 {
1989 struct ci_power_info *pi = ci_get_pi(rdev);
1990 u32 tmp;
1991
1992 if (enable) {
1993 if (pi->caps_sclk_ss_support) {
1994 tmp = RREG32_SMC(GENERAL_PWRMGT);
1995 tmp |= DYN_SPREAD_SPECTRUM_EN;
1996 WREG32_SMC(GENERAL_PWRMGT, tmp);
1997 }
1998 } else {
1999 tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
2000 tmp &= ~SSEN;
2001 WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp);
2002
2003 tmp = RREG32_SMC(GENERAL_PWRMGT);
2004 tmp &= ~DYN_SPREAD_SPECTRUM_EN;
2005 WREG32_SMC(GENERAL_PWRMGT, tmp);
2006 }
2007 }
2008
2009 static void ci_program_sstp(struct radeon_device *rdev)
2010 {
2011 WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
2012 }
2013
2014 static void ci_enable_display_gap(struct radeon_device *rdev)
2015 {
2016 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
2017
2018 tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK);
2019 tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
2020 DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK));
2021
2022 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
2023 }
2024
2025 static void ci_program_vc(struct radeon_device *rdev)
2026 {
2027 u32 tmp;
2028
2029 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
2030 tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
2031 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
2032
2033 WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0);
2034 WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1);
2035 WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2);
2036 WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3);
2037 WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4);
2038 WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5);
2039 WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6);
2040 WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7);
2041 }
2042
2043 static void ci_clear_vc(struct radeon_device *rdev)
2044 {
2045 u32 tmp;
2046
2047 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
2048 tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
2049 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
2050
2051 WREG32_SMC(CG_FTV_0, 0);
2052 WREG32_SMC(CG_FTV_1, 0);
2053 WREG32_SMC(CG_FTV_2, 0);
2054 WREG32_SMC(CG_FTV_3, 0);
2055 WREG32_SMC(CG_FTV_4, 0);
2056 WREG32_SMC(CG_FTV_5, 0);
2057 WREG32_SMC(CG_FTV_6, 0);
2058 WREG32_SMC(CG_FTV_7, 0);
2059 }
2060
2061 static int ci_upload_firmware(struct radeon_device *rdev)
2062 {
2063 struct ci_power_info *pi = ci_get_pi(rdev);
2064 int i, ret;
2065
2066 for (i = 0; i < rdev->usec_timeout; i++) {
2067 if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE)
2068 break;
2069 }
2070 WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1);
2071
2072 ci_stop_smc_clock(rdev);
2073 ci_reset_smc(rdev);
2074
2075 ret = ci_load_smc_ucode(rdev, pi->sram_end);
2076
2077 return ret;
2078
2079 }
2080
2081 static int ci_get_svi2_voltage_table(struct radeon_device *rdev,
2082 struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
2083 struct atom_voltage_table *voltage_table)
2084 {
2085 u32 i;
2086
2087 if (voltage_dependency_table == NULL)
2088 return -EINVAL;
2089
2090 voltage_table->mask_low = 0;
2091 voltage_table->phase_delay = 0;
2092
2093 voltage_table->count = voltage_dependency_table->count;
2094 for (i = 0; i < voltage_table->count; i++) {
2095 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
2096 voltage_table->entries[i].smio_low = 0;
2097 }
2098
2099 return 0;
2100 }
2101
2102 static int ci_construct_voltage_tables(struct radeon_device *rdev)
2103 {
2104 struct ci_power_info *pi = ci_get_pi(rdev);
2105 int ret;
2106
2107 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2108 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
2109 VOLTAGE_OBJ_GPIO_LUT,
2110 &pi->vddc_voltage_table);
2111 if (ret)
2112 return ret;
2113 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2114 ret = ci_get_svi2_voltage_table(rdev,
2115 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2116 &pi->vddc_voltage_table);
2117 if (ret)
2118 return ret;
2119 }
2120
2121 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
2122 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC,
2123 &pi->vddc_voltage_table);
2124
2125 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2126 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
2127 VOLTAGE_OBJ_GPIO_LUT,
2128 &pi->vddci_voltage_table);
2129 if (ret)
2130 return ret;
2131 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2132 ret = ci_get_svi2_voltage_table(rdev,
2133 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2134 &pi->vddci_voltage_table);
2135 if (ret)
2136 return ret;
2137 }
2138
2139 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
2140 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI,
2141 &pi->vddci_voltage_table);
2142
2143 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2144 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
2145 VOLTAGE_OBJ_GPIO_LUT,
2146 &pi->mvdd_voltage_table);
2147 if (ret)
2148 return ret;
2149 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2150 ret = ci_get_svi2_voltage_table(rdev,
2151 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2152 &pi->mvdd_voltage_table);
2153 if (ret)
2154 return ret;
2155 }
2156
2157 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
2158 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD,
2159 &pi->mvdd_voltage_table);
2160
2161 return 0;
2162 }
2163
2164 static void ci_populate_smc_voltage_table(struct radeon_device *rdev,
2165 struct atom_voltage_table_entry *voltage_table,
2166 SMU7_Discrete_VoltageLevel *smc_voltage_table)
2167 {
2168 int ret;
2169
2170 ret = ci_get_std_voltage_value_sidd(rdev, voltage_table,
2171 &smc_voltage_table->StdVoltageHiSidd,
2172 &smc_voltage_table->StdVoltageLoSidd);
2173
2174 if (ret) {
2175 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
2176 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
2177 }
2178
2179 smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
2180 smc_voltage_table->StdVoltageHiSidd =
2181 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
2182 smc_voltage_table->StdVoltageLoSidd =
2183 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
2184 }
2185
2186 static int ci_populate_smc_vddc_table(struct radeon_device *rdev,
2187 SMU7_Discrete_DpmTable *table)
2188 {
2189 struct ci_power_info *pi = ci_get_pi(rdev);
2190 unsigned int count;
2191
2192 table->VddcLevelCount = pi->vddc_voltage_table.count;
2193 for (count = 0; count < table->VddcLevelCount; count++) {
2194 ci_populate_smc_voltage_table(rdev,
2195 &pi->vddc_voltage_table.entries[count],
2196 &table->VddcLevel[count]);
2197
2198 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2199 table->VddcLevel[count].Smio |=
2200 pi->vddc_voltage_table.entries[count].smio_low;
2201 else
2202 table->VddcLevel[count].Smio = 0;
2203 }
2204 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
2205
2206 return 0;
2207 }
2208
2209 static int ci_populate_smc_vddci_table(struct radeon_device *rdev,
2210 SMU7_Discrete_DpmTable *table)
2211 {
2212 unsigned int count;
2213 struct ci_power_info *pi = ci_get_pi(rdev);
2214
2215 table->VddciLevelCount = pi->vddci_voltage_table.count;
2216 for (count = 0; count < table->VddciLevelCount; count++) {
2217 ci_populate_smc_voltage_table(rdev,
2218 &pi->vddci_voltage_table.entries[count],
2219 &table->VddciLevel[count]);
2220
2221 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2222 table->VddciLevel[count].Smio |=
2223 pi->vddci_voltage_table.entries[count].smio_low;
2224 else
2225 table->VddciLevel[count].Smio = 0;
2226 }
2227 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
2228
2229 return 0;
2230 }
2231
2232 static int ci_populate_smc_mvdd_table(struct radeon_device *rdev,
2233 SMU7_Discrete_DpmTable *table)
2234 {
2235 struct ci_power_info *pi = ci_get_pi(rdev);
2236 unsigned int count;
2237
2238 table->MvddLevelCount = pi->mvdd_voltage_table.count;
2239 for (count = 0; count < table->MvddLevelCount; count++) {
2240 ci_populate_smc_voltage_table(rdev,
2241 &pi->mvdd_voltage_table.entries[count],
2242 &table->MvddLevel[count]);
2243
2244 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2245 table->MvddLevel[count].Smio |=
2246 pi->mvdd_voltage_table.entries[count].smio_low;
2247 else
2248 table->MvddLevel[count].Smio = 0;
2249 }
2250 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
2251
2252 return 0;
2253 }
2254
2255 static int ci_populate_smc_voltage_tables(struct radeon_device *rdev,
2256 SMU7_Discrete_DpmTable *table)
2257 {
2258 int ret;
2259
2260 ret = ci_populate_smc_vddc_table(rdev, table);
2261 if (ret)
2262 return ret;
2263
2264 ret = ci_populate_smc_vddci_table(rdev, table);
2265 if (ret)
2266 return ret;
2267
2268 ret = ci_populate_smc_mvdd_table(rdev, table);
2269 if (ret)
2270 return ret;
2271
2272 return 0;
2273 }
2274
2275 static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
2276 SMU7_Discrete_VoltageLevel *voltage)
2277 {
2278 struct ci_power_info *pi = ci_get_pi(rdev);
2279 u32 i = 0;
2280
2281 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2282 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
2283 if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
2284 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
2285 break;
2286 }
2287 }
2288
2289 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
2290 return -EINVAL;
2291 }
2292
2293 return -EINVAL;
2294 }
2295
2296 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
2297 struct atom_voltage_table_entry *voltage_table,
2298 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
2299 {
2300 u16 v_index, idx;
2301 bool voltage_found = false;
2302 *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
2303 *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
2304
2305 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
2306 return -EINVAL;
2307
2308 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
2309 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2310 if (voltage_table->value ==
2311 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2312 voltage_found = true;
2313 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
2314 idx = v_index;
2315 else
2316 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2317 *std_voltage_lo_sidd =
2318 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2319 *std_voltage_hi_sidd =
2320 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2321 break;
2322 }
2323 }
2324
2325 if (!voltage_found) {
2326 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2327 if (voltage_table->value <=
2328 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2329 voltage_found = true;
2330 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
2331 idx = v_index;
2332 else
2333 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2334 *std_voltage_lo_sidd =
2335 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2336 *std_voltage_hi_sidd =
2337 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2338 break;
2339 }
2340 }
2341 }
2342 }
2343
2344 return 0;
2345 }
2346
2347 static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev,
2348 const struct radeon_phase_shedding_limits_table *limits,
2349 u32 sclk,
2350 u32 *phase_shedding)
2351 {
2352 unsigned int i;
2353
2354 *phase_shedding = 1;
2355
2356 for (i = 0; i < limits->count; i++) {
2357 if (sclk < limits->entries[i].sclk) {
2358 *phase_shedding = i;
2359 break;
2360 }
2361 }
2362 }
2363
2364 static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev,
2365 const struct radeon_phase_shedding_limits_table *limits,
2366 u32 mclk,
2367 u32 *phase_shedding)
2368 {
2369 unsigned int i;
2370
2371 *phase_shedding = 1;
2372
2373 for (i = 0; i < limits->count; i++) {
2374 if (mclk < limits->entries[i].mclk) {
2375 *phase_shedding = i;
2376 break;
2377 }
2378 }
2379 }
2380
2381 static int ci_init_arb_table_index(struct radeon_device *rdev)
2382 {
2383 struct ci_power_info *pi = ci_get_pi(rdev);
2384 u32 tmp;
2385 int ret;
2386
2387 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start,
2388 &tmp, pi->sram_end);
2389 if (ret)
2390 return ret;
2391
2392 tmp &= 0x00FFFFFF;
2393 tmp |= MC_CG_ARB_FREQ_F1 << 24;
2394
2395 return ci_write_smc_sram_dword(rdev, pi->arb_table_start,
2396 tmp, pi->sram_end);
2397 }
2398
2399 static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev,
2400 struct radeon_clock_voltage_dependency_table *allowed_clock_voltage_table,
2401 u32 clock, u32 *voltage)
2402 {
2403 u32 i = 0;
2404
2405 if (allowed_clock_voltage_table->count == 0)
2406 return -EINVAL;
2407
2408 for (i = 0; i < allowed_clock_voltage_table->count; i++) {
2409 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
2410 *voltage = allowed_clock_voltage_table->entries[i].v;
2411 return 0;
2412 }
2413 }
2414
2415 *voltage = allowed_clock_voltage_table->entries[i-1].v;
2416
2417 return 0;
2418 }
2419
2420 static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
2421 u32 sclk, u32 min_sclk_in_sr)
2422 {
2423 u32 i;
2424 u32 tmp;
2425 u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ?
2426 min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK;
2427
2428 if (sclk < min)
2429 return 0;
2430
2431 for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
2432 tmp = sclk / (1 << i);
2433 if (tmp >= min || i == 0)
2434 break;
2435 }
2436
2437 return (u8)i;
2438 }
2439
2440 static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
2441 {
2442 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2443 }
2444
2445 static int ci_reset_to_default(struct radeon_device *rdev)
2446 {
2447 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2448 0 : -EINVAL;
2449 }
2450
2451 static int ci_force_switch_to_arb_f0(struct radeon_device *rdev)
2452 {
2453 u32 tmp;
2454
2455 tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8;
2456
2457 if (tmp == MC_CG_ARB_FREQ_F0)
2458 return 0;
2459
2460 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
2461 }
2462
2463 static void ci_register_patching_mc_arb(struct radeon_device *rdev,
2464 const u32 engine_clock,
2465 const u32 memory_clock,
2466 u32 *dram_timimg2)
2467 {
2468 bool patch;
2469 u32 tmp, tmp2;
2470
2471 tmp = RREG32(MC_SEQ_MISC0);
2472 patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
2473
2474 if (patch &&
2475 ((rdev->pdev->device == 0x67B0) ||
2476 (rdev->pdev->device == 0x67B1))) {
2477 if ((memory_clock > 100000) && (memory_clock <= 125000)) {
2478 tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff;
2479 *dram_timimg2 &= ~0x00ff0000;
2480 *dram_timimg2 |= tmp2 << 16;
2481 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) {
2482 tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff;
2483 *dram_timimg2 &= ~0x00ff0000;
2484 *dram_timimg2 |= tmp2 << 16;
2485 }
2486 }
2487 }
2488
2489
2490 static int ci_populate_memory_timing_parameters(struct radeon_device *rdev,
2491 u32 sclk,
2492 u32 mclk,
2493 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2494 {
2495 u32 dram_timing;
2496 u32 dram_timing2;
2497 u32 burst_time;
2498
2499 radeon_atom_set_engine_dram_timings(rdev, sclk, mclk);
2500
2501 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
2502 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
2503 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
2504
2505 ci_register_patching_mc_arb(rdev, sclk, mclk, &dram_timing2);
2506
2507 arb_regs->McArbDramTiming = cpu_to_be32(dram_timing);
2508 arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2509 arb_regs->McArbBurstTime = (u8)burst_time;
2510
2511 return 0;
2512 }
2513
2514 static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev)
2515 {
2516 struct ci_power_info *pi = ci_get_pi(rdev);
2517 SMU7_Discrete_MCArbDramTimingTable arb_regs;
2518 u32 i, j;
2519 int ret = 0;
2520
2521 memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2522
2523 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2524 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2525 ret = ci_populate_memory_timing_parameters(rdev,
2526 pi->dpm_table.sclk_table.dpm_levels[i].value,
2527 pi->dpm_table.mclk_table.dpm_levels[j].value,
2528 &arb_regs.entries[i][j]);
2529 if (ret)
2530 break;
2531 }
2532 }
2533
2534 if (ret == 0)
2535 ret = ci_copy_bytes_to_smc(rdev,
2536 pi->arb_table_start,
2537 (u8 *)&arb_regs,
2538 sizeof(SMU7_Discrete_MCArbDramTimingTable),
2539 pi->sram_end);
2540
2541 return ret;
2542 }
2543
2544 static int ci_program_memory_timing_parameters(struct radeon_device *rdev)
2545 {
2546 struct ci_power_info *pi = ci_get_pi(rdev);
2547
2548 if (pi->need_update_smu7_dpm_table == 0)
2549 return 0;
2550
2551 return ci_do_program_memory_timing_parameters(rdev);
2552 }
2553
2554 static void ci_populate_smc_initial_state(struct radeon_device *rdev,
2555 struct radeon_ps *radeon_boot_state)
2556 {
2557 struct ci_ps *boot_state = ci_get_ps(radeon_boot_state);
2558 struct ci_power_info *pi = ci_get_pi(rdev);
2559 u32 level = 0;
2560
2561 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2562 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2563 boot_state->performance_levels[0].sclk) {
2564 pi->smc_state_table.GraphicsBootLevel = level;
2565 break;
2566 }
2567 }
2568
2569 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2570 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2571 boot_state->performance_levels[0].mclk) {
2572 pi->smc_state_table.MemoryBootLevel = level;
2573 break;
2574 }
2575 }
2576 }
2577
2578 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2579 {
2580 u32 i;
2581 u32 mask_value = 0;
2582
2583 for (i = dpm_table->count; i > 0; i--) {
2584 mask_value = mask_value << 1;
2585 if (dpm_table->dpm_levels[i-1].enabled)
2586 mask_value |= 0x1;
2587 else
2588 mask_value &= 0xFFFFFFFE;
2589 }
2590
2591 return mask_value;
2592 }
2593
2594 static void ci_populate_smc_link_level(struct radeon_device *rdev,
2595 SMU7_Discrete_DpmTable *table)
2596 {
2597 struct ci_power_info *pi = ci_get_pi(rdev);
2598 struct ci_dpm_table *dpm_table = &pi->dpm_table;
2599 u32 i;
2600
2601 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2602 table->LinkLevel[i].PcieGenSpeed =
2603 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2604 table->LinkLevel[i].PcieLaneCount =
2605 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2606 table->LinkLevel[i].EnabledForActivity = 1;
2607 table->LinkLevel[i].DownT = cpu_to_be32(5);
2608 table->LinkLevel[i].UpT = cpu_to_be32(30);
2609 }
2610
2611 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2612 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2613 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2614 }
2615
2616 static int ci_populate_smc_uvd_level(struct radeon_device *rdev,
2617 SMU7_Discrete_DpmTable *table)
2618 {
2619 u32 count;
2620 struct atom_clock_dividers dividers;
2621 int ret = -EINVAL;
2622
2623 table->UvdLevelCount =
2624 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2625
2626 for (count = 0; count < table->UvdLevelCount; count++) {
2627 table->UvdLevel[count].VclkFrequency =
2628 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2629 table->UvdLevel[count].DclkFrequency =
2630 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2631 table->UvdLevel[count].MinVddc =
2632 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2633 table->UvdLevel[count].MinVddcPhases = 1;
2634
2635 ret = radeon_atom_get_clock_dividers(rdev,
2636 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2637 table->UvdLevel[count].VclkFrequency, false, &dividers);
2638 if (ret)
2639 return ret;
2640
2641 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2642
2643 ret = radeon_atom_get_clock_dividers(rdev,
2644 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2645 table->UvdLevel[count].DclkFrequency, false, &dividers);
2646 if (ret)
2647 return ret;
2648
2649 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2650
2651 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2652 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2653 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2654 }
2655
2656 return ret;
2657 }
2658
2659 static int ci_populate_smc_vce_level(struct radeon_device *rdev,
2660 SMU7_Discrete_DpmTable *table)
2661 {
2662 u32 count;
2663 struct atom_clock_dividers dividers;
2664 int ret = -EINVAL;
2665
2666 table->VceLevelCount =
2667 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2668
2669 for (count = 0; count < table->VceLevelCount; count++) {
2670 table->VceLevel[count].Frequency =
2671 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2672 table->VceLevel[count].MinVoltage =
2673 (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2674 table->VceLevel[count].MinPhases = 1;
2675
2676 ret = radeon_atom_get_clock_dividers(rdev,
2677 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2678 table->VceLevel[count].Frequency, false, &dividers);
2679 if (ret)
2680 return ret;
2681
2682 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2683
2684 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2685 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2686 }
2687
2688 return ret;
2689
2690 }
2691
2692 static int ci_populate_smc_acp_level(struct radeon_device *rdev,
2693 SMU7_Discrete_DpmTable *table)
2694 {
2695 u32 count;
2696 struct atom_clock_dividers dividers;
2697 int ret = -EINVAL;
2698
2699 table->AcpLevelCount = (u8)
2700 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2701
2702 for (count = 0; count < table->AcpLevelCount; count++) {
2703 table->AcpLevel[count].Frequency =
2704 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2705 table->AcpLevel[count].MinVoltage =
2706 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2707 table->AcpLevel[count].MinPhases = 1;
2708
2709 ret = radeon_atom_get_clock_dividers(rdev,
2710 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2711 table->AcpLevel[count].Frequency, false, &dividers);
2712 if (ret)
2713 return ret;
2714
2715 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2716
2717 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2718 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2719 }
2720
2721 return ret;
2722 }
2723
2724 static int ci_populate_smc_samu_level(struct radeon_device *rdev,
2725 SMU7_Discrete_DpmTable *table)
2726 {
2727 u32 count;
2728 struct atom_clock_dividers dividers;
2729 int ret = -EINVAL;
2730
2731 table->SamuLevelCount =
2732 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2733
2734 for (count = 0; count < table->SamuLevelCount; count++) {
2735 table->SamuLevel[count].Frequency =
2736 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2737 table->SamuLevel[count].MinVoltage =
2738 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2739 table->SamuLevel[count].MinPhases = 1;
2740
2741 ret = radeon_atom_get_clock_dividers(rdev,
2742 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2743 table->SamuLevel[count].Frequency, false, &dividers);
2744 if (ret)
2745 return ret;
2746
2747 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2748
2749 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2750 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2751 }
2752
2753 return ret;
2754 }
2755
2756 static int ci_calculate_mclk_params(struct radeon_device *rdev,
2757 u32 memory_clock,
2758 SMU7_Discrete_MemoryLevel *mclk,
2759 bool strobe_mode,
2760 bool dll_state_on)
2761 {
2762 struct ci_power_info *pi = ci_get_pi(rdev);
2763 u32 dll_cntl = pi->clock_registers.dll_cntl;
2764 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2765 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2766 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2767 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2768 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2769 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2770 u32 mpll_ss1 = pi->clock_registers.mpll_ss1;
2771 u32 mpll_ss2 = pi->clock_registers.mpll_ss2;
2772 struct atom_mpll_param mpll_param;
2773 int ret;
2774
2775 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
2776 if (ret)
2777 return ret;
2778
2779 mpll_func_cntl &= ~BWCTRL_MASK;
2780 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
2781
2782 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
2783 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
2784 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
2785
2786 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
2787 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
2788
2789 if (pi->mem_gddr5) {
2790 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
2791 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
2792 YCLK_POST_DIV(mpll_param.post_div);
2793 }
2794
2795 if (pi->caps_mclk_ss_support) {
2796 struct radeon_atom_ss ss;
2797 u32 freq_nom;
2798 u32 tmp;
2799 u32 reference_clock = rdev->clock.mpll.reference_freq;
2800
2801 if (mpll_param.qdr == 1)
2802 freq_nom = memory_clock * 4 * (1 << mpll_param.post_div);
2803 else
2804 freq_nom = memory_clock * 2 * (1 << mpll_param.post_div);
2805
2806 tmp = (freq_nom / reference_clock);
2807 tmp = tmp * tmp;
2808 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2809 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2810 u32 clks = reference_clock * 5 / ss.rate;
2811 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2812
2813 mpll_ss1 &= ~CLKV_MASK;
2814 mpll_ss1 |= CLKV(clkv);
2815
2816 mpll_ss2 &= ~CLKS_MASK;
2817 mpll_ss2 |= CLKS(clks);
2818 }
2819 }
2820
2821 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
2822 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
2823
2824 if (dll_state_on)
2825 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
2826 else
2827 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2828
2829 mclk->MclkFrequency = memory_clock;
2830 mclk->MpllFuncCntl = mpll_func_cntl;
2831 mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
2832 mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
2833 mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
2834 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
2835 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
2836 mclk->DllCntl = dll_cntl;
2837 mclk->MpllSs1 = mpll_ss1;
2838 mclk->MpllSs2 = mpll_ss2;
2839
2840 return 0;
2841 }
2842
2843 static int ci_populate_single_memory_level(struct radeon_device *rdev,
2844 u32 memory_clock,
2845 SMU7_Discrete_MemoryLevel *memory_level)
2846 {
2847 struct ci_power_info *pi = ci_get_pi(rdev);
2848 int ret;
2849 bool dll_state_on;
2850
2851 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
2852 ret = ci_get_dependency_volt_by_clk(rdev,
2853 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2854 memory_clock, &memory_level->MinVddc);
2855 if (ret)
2856 return ret;
2857 }
2858
2859 if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
2860 ret = ci_get_dependency_volt_by_clk(rdev,
2861 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2862 memory_clock, &memory_level->MinVddci);
2863 if (ret)
2864 return ret;
2865 }
2866
2867 if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
2868 ret = ci_get_dependency_volt_by_clk(rdev,
2869 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2870 memory_clock, &memory_level->MinMvdd);
2871 if (ret)
2872 return ret;
2873 }
2874
2875 memory_level->MinVddcPhases = 1;
2876
2877 if (pi->vddc_phase_shed_control)
2878 ci_populate_phase_value_based_on_mclk(rdev,
2879 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2880 memory_clock,
2881 &memory_level->MinVddcPhases);
2882
2883 memory_level->EnabledForThrottle = 1;
2884 memory_level->UpH = 0;
2885 memory_level->DownH = 100;
2886 memory_level->VoltageDownH = 0;
2887 memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
2888
2889 memory_level->StutterEnable = false;
2890 memory_level->StrobeEnable = false;
2891 memory_level->EdcReadEnable = false;
2892 memory_level->EdcWriteEnable = false;
2893 memory_level->RttEnable = false;
2894
2895 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2896
2897 if (pi->mclk_stutter_mode_threshold &&
2898 (memory_clock <= pi->mclk_stutter_mode_threshold) &&
2899 (pi->uvd_enabled == false) &&
2900 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
2901 (rdev->pm.dpm.new_active_crtc_count <= 2))
2902 memory_level->StutterEnable = true;
2903
2904 if (pi->mclk_strobe_mode_threshold &&
2905 (memory_clock <= pi->mclk_strobe_mode_threshold))
2906 memory_level->StrobeEnable = 1;
2907
2908 if (pi->mem_gddr5) {
2909 memory_level->StrobeRatio =
2910 si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
2911 if (pi->mclk_edc_enable_threshold &&
2912 (memory_clock > pi->mclk_edc_enable_threshold))
2913 memory_level->EdcReadEnable = true;
2914
2915 if (pi->mclk_edc_wr_enable_threshold &&
2916 (memory_clock > pi->mclk_edc_wr_enable_threshold))
2917 memory_level->EdcWriteEnable = true;
2918
2919 if (memory_level->StrobeEnable) {
2920 if (si_get_mclk_frequency_ratio(memory_clock, true) >=
2921 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
2922 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2923 else
2924 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
2925 } else {
2926 dll_state_on = pi->dll_default_on;
2927 }
2928 } else {
2929 memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock);
2930 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2931 }
2932
2933 ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
2934 if (ret)
2935 return ret;
2936
2937 memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
2938 memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
2939 memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
2940 memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
2941
2942 memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
2943 memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
2944 memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
2945 memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
2946 memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
2947 memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
2948 memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
2949 memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
2950 memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
2951 memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
2952 memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
2953
2954 return 0;
2955 }
2956
2957 static int ci_populate_smc_acpi_level(struct radeon_device *rdev,
2958 SMU7_Discrete_DpmTable *table)
2959 {
2960 struct ci_power_info *pi = ci_get_pi(rdev);
2961 struct atom_clock_dividers dividers;
2962 SMU7_Discrete_VoltageLevel voltage_level;
2963 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
2964 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
2965 u32 dll_cntl = pi->clock_registers.dll_cntl;
2966 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2967 int ret;
2968
2969 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2970
2971 if (pi->acpi_vddc)
2972 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
2973 else
2974 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
2975
2976 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
2977
2978 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq;
2979
2980 ret = radeon_atom_get_clock_dividers(rdev,
2981 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
2982 table->ACPILevel.SclkFrequency, false, &dividers);
2983 if (ret)
2984 return ret;
2985
2986 table->ACPILevel.SclkDid = (u8)dividers.post_divider;
2987 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2988 table->ACPILevel.DeepSleepDivId = 0;
2989
2990 spll_func_cntl &= ~SPLL_PWRON;
2991 spll_func_cntl |= SPLL_RESET;
2992
2993 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
2994 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
2995
2996 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2997 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2998 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
2999 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
3000 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
3001 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3002 table->ACPILevel.CcPwrDynRm = 0;
3003 table->ACPILevel.CcPwrDynRm1 = 0;
3004
3005 table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
3006 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
3007 table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
3008 table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
3009 table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
3010 table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
3011 table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
3012 table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
3013 table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
3014 table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
3015 table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
3016
3017 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
3018 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
3019
3020 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
3021 if (pi->acpi_vddci)
3022 table->MemoryACPILevel.MinVddci =
3023 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
3024 else
3025 table->MemoryACPILevel.MinVddci =
3026 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
3027 }
3028
3029 if (ci_populate_mvdd_value(rdev, 0, &voltage_level))
3030 table->MemoryACPILevel.MinMvdd = 0;
3031 else
3032 table->MemoryACPILevel.MinMvdd =
3033 cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
3034
3035 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
3036 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
3037
3038 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
3039
3040 table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
3041 table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
3042 table->MemoryACPILevel.MpllAdFuncCntl =
3043 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
3044 table->MemoryACPILevel.MpllDqFuncCntl =
3045 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
3046 table->MemoryACPILevel.MpllFuncCntl =
3047 cpu_to_be32(pi->clock_registers.mpll_func_cntl);
3048 table->MemoryACPILevel.MpllFuncCntl_1 =
3049 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
3050 table->MemoryACPILevel.MpllFuncCntl_2 =
3051 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
3052 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
3053 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
3054
3055 table->MemoryACPILevel.EnabledForThrottle = 0;
3056 table->MemoryACPILevel.EnabledForActivity = 0;
3057 table->MemoryACPILevel.UpH = 0;
3058 table->MemoryACPILevel.DownH = 100;
3059 table->MemoryACPILevel.VoltageDownH = 0;
3060 table->MemoryACPILevel.ActivityLevel =
3061 cpu_to_be16((u16)pi->mclk_activity_target);
3062
3063 table->MemoryACPILevel.StutterEnable = false;
3064 table->MemoryACPILevel.StrobeEnable = false;
3065 table->MemoryACPILevel.EdcReadEnable = false;
3066 table->MemoryACPILevel.EdcWriteEnable = false;
3067 table->MemoryACPILevel.RttEnable = false;
3068
3069 return 0;
3070 }
3071
3072
3073 static int ci_enable_ulv(struct radeon_device *rdev, bool enable)
3074 {
3075 struct ci_power_info *pi = ci_get_pi(rdev);
3076 struct ci_ulv_parm *ulv = &pi->ulv;
3077
3078 if (ulv->supported) {
3079 if (enable)
3080 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
3081 0 : -EINVAL;
3082 else
3083 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
3084 0 : -EINVAL;
3085 }
3086
3087 return 0;
3088 }
3089
3090 static int ci_populate_ulv_level(struct radeon_device *rdev,
3091 SMU7_Discrete_Ulv *state)
3092 {
3093 struct ci_power_info *pi = ci_get_pi(rdev);
3094 u16 ulv_voltage = rdev->pm.dpm.backbias_response_time;
3095
3096 state->CcPwrDynRm = 0;
3097 state->CcPwrDynRm1 = 0;
3098
3099 if (ulv_voltage == 0) {
3100 pi->ulv.supported = false;
3101 return 0;
3102 }
3103
3104 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
3105 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3106 state->VddcOffset = 0;
3107 else
3108 state->VddcOffset =
3109 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
3110 } else {
3111 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3112 state->VddcOffsetVid = 0;
3113 else
3114 state->VddcOffsetVid = (u8)
3115 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
3116 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
3117 }
3118 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
3119
3120 state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
3121 state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
3122 state->VddcOffset = cpu_to_be16(state->VddcOffset);
3123
3124 return 0;
3125 }
3126
3127 static int ci_calculate_sclk_params(struct radeon_device *rdev,
3128 u32 engine_clock,
3129 SMU7_Discrete_GraphicsLevel *sclk)
3130 {
3131 struct ci_power_info *pi = ci_get_pi(rdev);
3132 struct atom_clock_dividers dividers;
3133 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
3134 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
3135 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
3136 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3137 u32 reference_clock = rdev->clock.spll.reference_freq;
3138 u32 reference_divider;
3139 u32 fbdiv;
3140 int ret;
3141
3142 ret = radeon_atom_get_clock_dividers(rdev,
3143 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
3144 engine_clock, false, &dividers);
3145 if (ret)
3146 return ret;
3147
3148 reference_divider = 1 + dividers.ref_div;
3149 fbdiv = dividers.fb_div & 0x3FFFFFF;
3150
3151 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
3152 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
3153 spll_func_cntl_3 |= SPLL_DITHEN;
3154
3155 if (pi->caps_sclk_ss_support) {
3156 struct radeon_atom_ss ss;
3157 u32 vco_freq = engine_clock * dividers.post_div;
3158
3159 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
3160 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
3161 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
3162 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
3163
3164 cg_spll_spread_spectrum &= ~CLK_S_MASK;
3165 cg_spll_spread_spectrum |= CLK_S(clk_s);
3166 cg_spll_spread_spectrum |= SSEN;
3167
3168 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
3169 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
3170 }
3171 }
3172
3173 sclk->SclkFrequency = engine_clock;
3174 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
3175 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
3176 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
3177 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
3178 sclk->SclkDid = (u8)dividers.post_divider;
3179
3180 return 0;
3181 }
3182
3183 static int ci_populate_single_graphic_level(struct radeon_device *rdev,
3184 u32 engine_clock,
3185 u16 sclk_activity_level_t,
3186 SMU7_Discrete_GraphicsLevel *graphic_level)
3187 {
3188 struct ci_power_info *pi = ci_get_pi(rdev);
3189 int ret;
3190
3191 ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level);
3192 if (ret)
3193 return ret;
3194
3195 ret = ci_get_dependency_volt_by_clk(rdev,
3196 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3197 engine_clock, &graphic_level->MinVddc);
3198 if (ret)
3199 return ret;
3200
3201 graphic_level->SclkFrequency = engine_clock;
3202
3203 graphic_level->Flags = 0;
3204 graphic_level->MinVddcPhases = 1;
3205
3206 if (pi->vddc_phase_shed_control)
3207 ci_populate_phase_value_based_on_sclk(rdev,
3208 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
3209 engine_clock,
3210 &graphic_level->MinVddcPhases);
3211
3212 graphic_level->ActivityLevel = sclk_activity_level_t;
3213
3214 graphic_level->CcPwrDynRm = 0;
3215 graphic_level->CcPwrDynRm1 = 0;
3216 graphic_level->EnabledForThrottle = 1;
3217 graphic_level->UpH = 0;
3218 graphic_level->DownH = 0;
3219 graphic_level->VoltageDownH = 0;
3220 graphic_level->PowerThrottle = 0;
3221
3222 if (pi->caps_sclk_ds)
3223 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev,
3224 engine_clock,
3225 CISLAND_MINIMUM_ENGINE_CLOCK);
3226
3227 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3228
3229 graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
3230 graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
3231 graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
3232 graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
3233 graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
3234 graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
3235 graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
3236 graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
3237 graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
3238 graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
3239 graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
3240
3241 return 0;
3242 }
3243
3244 static int ci_populate_all_graphic_levels(struct radeon_device *rdev)
3245 {
3246 struct ci_power_info *pi = ci_get_pi(rdev);
3247 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3248 u32 level_array_address = pi->dpm_table_start +
3249 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
3250 u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
3251 SMU7_MAX_LEVELS_GRAPHICS;
3252 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
3253 u32 i, ret;
3254
3255 memset(levels, 0, level_array_size);
3256
3257 for (i = 0; i < dpm_table->sclk_table.count; i++) {
3258 ret = ci_populate_single_graphic_level(rdev,
3259 dpm_table->sclk_table.dpm_levels[i].value,
3260 (u16)pi->activity_target[i],
3261 &pi->smc_state_table.GraphicsLevel[i]);
3262 if (ret)
3263 return ret;
3264 if (i > 1)
3265 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
3266 if (i == (dpm_table->sclk_table.count - 1))
3267 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
3268 PPSMC_DISPLAY_WATERMARK_HIGH;
3269 }
3270 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
3271
3272 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
3273 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3274 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
3275
3276 ret = ci_copy_bytes_to_smc(rdev, level_array_address,
3277 (u8 *)levels, level_array_size,
3278 pi->sram_end);
3279 if (ret)
3280 return ret;
3281
3282 return 0;
3283 }
3284
3285 static int ci_populate_ulv_state(struct radeon_device *rdev,
3286 SMU7_Discrete_Ulv *ulv_level)
3287 {
3288 return ci_populate_ulv_level(rdev, ulv_level);
3289 }
3290
3291 static int ci_populate_all_memory_levels(struct radeon_device *rdev)
3292 {
3293 struct ci_power_info *pi = ci_get_pi(rdev);
3294 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3295 u32 level_array_address = pi->dpm_table_start +
3296 offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
3297 u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
3298 SMU7_MAX_LEVELS_MEMORY;
3299 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
3300 u32 i, ret;
3301
3302 memset(levels, 0, level_array_size);
3303
3304 for (i = 0; i < dpm_table->mclk_table.count; i++) {
3305 if (dpm_table->mclk_table.dpm_levels[i].value == 0)
3306 return -EINVAL;
3307 ret = ci_populate_single_memory_level(rdev,
3308 dpm_table->mclk_table.dpm_levels[i].value,
3309 &pi->smc_state_table.MemoryLevel[i]);
3310 if (ret)
3311 return ret;
3312 }
3313
3314 pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
3315
3316 if ((dpm_table->mclk_table.count >= 2) &&
3317 ((rdev->pdev->device == 0x67B0) || (rdev->pdev->device == 0x67B1))) {
3318 pi->smc_state_table.MemoryLevel[1].MinVddc =
3319 pi->smc_state_table.MemoryLevel[0].MinVddc;
3320 pi->smc_state_table.MemoryLevel[1].MinVddcPhases =
3321 pi->smc_state_table.MemoryLevel[0].MinVddcPhases;
3322 }
3323
3324 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
3325
3326 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
3327 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3328 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
3329
3330 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
3331 PPSMC_DISPLAY_WATERMARK_HIGH;
3332
3333 ret = ci_copy_bytes_to_smc(rdev, level_array_address,
3334 (u8 *)levels, level_array_size,
3335 pi->sram_end);
3336 if (ret)
3337 return ret;
3338
3339 return 0;
3340 }
3341
3342 static void ci_reset_single_dpm_table(struct radeon_device *rdev,
3343 struct ci_single_dpm_table* dpm_table,
3344 u32 count)
3345 {
3346 u32 i;
3347
3348 dpm_table->count = count;
3349 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
3350 dpm_table->dpm_levels[i].enabled = false;
3351 }
3352
3353 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
3354 u32 index, u32 pcie_gen, u32 pcie_lanes)
3355 {
3356 dpm_table->dpm_levels[index].value = pcie_gen;
3357 dpm_table->dpm_levels[index].param1 = pcie_lanes;
3358 dpm_table->dpm_levels[index].enabled = true;
3359 }
3360
3361 static int ci_setup_default_pcie_tables(struct radeon_device *rdev)
3362 {
3363 struct ci_power_info *pi = ci_get_pi(rdev);
3364
3365 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
3366 return -EINVAL;
3367
3368 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
3369 pi->pcie_gen_powersaving = pi->pcie_gen_performance;
3370 pi->pcie_lane_powersaving = pi->pcie_lane_performance;
3371 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
3372 pi->pcie_gen_performance = pi->pcie_gen_powersaving;
3373 pi->pcie_lane_performance = pi->pcie_lane_powersaving;
3374 }
3375
3376 ci_reset_single_dpm_table(rdev,
3377 &pi->dpm_table.pcie_speed_table,
3378 SMU7_MAX_LEVELS_LINK);
3379
3380 if (rdev->family == CHIP_BONAIRE)
3381 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3382 pi->pcie_gen_powersaving.min,
3383 pi->pcie_lane_powersaving.max);
3384 else
3385 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3386 pi->pcie_gen_powersaving.min,
3387 pi->pcie_lane_powersaving.min);
3388 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
3389 pi->pcie_gen_performance.min,
3390 pi->pcie_lane_performance.min);
3391 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
3392 pi->pcie_gen_powersaving.min,
3393 pi->pcie_lane_powersaving.max);
3394 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
3395 pi->pcie_gen_performance.min,
3396 pi->pcie_lane_performance.max);
3397 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
3398 pi->pcie_gen_powersaving.max,
3399 pi->pcie_lane_powersaving.max);
3400 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
3401 pi->pcie_gen_performance.max,
3402 pi->pcie_lane_performance.max);
3403
3404 pi->dpm_table.pcie_speed_table.count = 6;
3405
3406 return 0;
3407 }
3408
3409 static int ci_setup_default_dpm_tables(struct radeon_device *rdev)
3410 {
3411 struct ci_power_info *pi = ci_get_pi(rdev);
3412 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
3413 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3414 struct radeon_clock_voltage_dependency_table *allowed_mclk_table =
3415 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
3416 struct radeon_cac_leakage_table *std_voltage_table =
3417 &rdev->pm.dpm.dyn_state.cac_leakage_table;
3418 u32 i;
3419
3420 if (allowed_sclk_vddc_table == NULL)
3421 return -EINVAL;
3422 if (allowed_sclk_vddc_table->count < 1)
3423 return -EINVAL;
3424 if (allowed_mclk_table == NULL)
3425 return -EINVAL;
3426 if (allowed_mclk_table->count < 1)
3427 return -EINVAL;
3428
3429 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
3430
3431 ci_reset_single_dpm_table(rdev,
3432 &pi->dpm_table.sclk_table,
3433 SMU7_MAX_LEVELS_GRAPHICS);
3434 ci_reset_single_dpm_table(rdev,
3435 &pi->dpm_table.mclk_table,
3436 SMU7_MAX_LEVELS_MEMORY);
3437 ci_reset_single_dpm_table(rdev,
3438 &pi->dpm_table.vddc_table,
3439 SMU7_MAX_LEVELS_VDDC);
3440 ci_reset_single_dpm_table(rdev,
3441 &pi->dpm_table.vddci_table,
3442 SMU7_MAX_LEVELS_VDDCI);
3443 ci_reset_single_dpm_table(rdev,
3444 &pi->dpm_table.mvdd_table,
3445 SMU7_MAX_LEVELS_MVDD);
3446
3447 pi->dpm_table.sclk_table.count = 0;
3448 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3449 if ((i == 0) ||
3450 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
3451 allowed_sclk_vddc_table->entries[i].clk)) {
3452 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
3453 allowed_sclk_vddc_table->entries[i].clk;
3454 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled =
3455 (i == 0) ? true : false;
3456 pi->dpm_table.sclk_table.count++;
3457 }
3458 }
3459
3460 pi->dpm_table.mclk_table.count = 0;
3461 for (i = 0; i < allowed_mclk_table->count; i++) {
3462 if ((i == 0) ||
3463 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
3464 allowed_mclk_table->entries[i].clk)) {
3465 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
3466 allowed_mclk_table->entries[i].clk;
3467 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled =
3468 (i == 0) ? true : false;
3469 pi->dpm_table.mclk_table.count++;
3470 }
3471 }
3472
3473 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3474 pi->dpm_table.vddc_table.dpm_levels[i].value =
3475 allowed_sclk_vddc_table->entries[i].v;
3476 pi->dpm_table.vddc_table.dpm_levels[i].param1 =
3477 std_voltage_table->entries[i].leakage;
3478 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
3479 }
3480 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
3481
3482 allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3483 if (allowed_mclk_table) {
3484 for (i = 0; i < allowed_mclk_table->count; i++) {
3485 pi->dpm_table.vddci_table.dpm_levels[i].value =
3486 allowed_mclk_table->entries[i].v;
3487 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
3488 }
3489 pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
3490 }
3491
3492 allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3493 if (allowed_mclk_table) {
3494 for (i = 0; i < allowed_mclk_table->count; i++) {
3495 pi->dpm_table.mvdd_table.dpm_levels[i].value =
3496 allowed_mclk_table->entries[i].v;
3497 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
3498 }
3499 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
3500 }
3501
3502 ci_setup_default_pcie_tables(rdev);
3503
3504 return 0;
3505 }
3506
3507 static int ci_find_boot_level(struct ci_single_dpm_table *table,
3508 u32 value, u32 *boot_level)
3509 {
3510 u32 i;
3511 int ret = -EINVAL;
3512
3513 for(i = 0; i < table->count; i++) {
3514 if (value == table->dpm_levels[i].value) {
3515 *boot_level = i;
3516 ret = 0;
3517 }
3518 }
3519
3520 return ret;
3521 }
3522
3523 static int ci_init_smc_table(struct radeon_device *rdev)
3524 {
3525 struct ci_power_info *pi = ci_get_pi(rdev);
3526 struct ci_ulv_parm *ulv = &pi->ulv;
3527 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
3528 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
3529 int ret;
3530
3531 ret = ci_setup_default_dpm_tables(rdev);
3532 if (ret)
3533 return ret;
3534
3535 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
3536 ci_populate_smc_voltage_tables(rdev, table);
3537
3538 ci_init_fps_limits(rdev);
3539
3540 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3541 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
3542
3543 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3544 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3545
3546 if (pi->mem_gddr5)
3547 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3548
3549 if (ulv->supported) {
3550 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv);
3551 if (ret)
3552 return ret;
3553 WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
3554 }
3555
3556 ret = ci_populate_all_graphic_levels(rdev);
3557 if (ret)
3558 return ret;
3559
3560 ret = ci_populate_all_memory_levels(rdev);
3561 if (ret)
3562 return ret;
3563
3564 ci_populate_smc_link_level(rdev, table);
3565
3566 ret = ci_populate_smc_acpi_level(rdev, table);
3567 if (ret)
3568 return ret;
3569
3570 ret = ci_populate_smc_vce_level(rdev, table);
3571 if (ret)
3572 return ret;
3573
3574 ret = ci_populate_smc_acp_level(rdev, table);
3575 if (ret)
3576 return ret;
3577
3578 ret = ci_populate_smc_samu_level(rdev, table);
3579 if (ret)
3580 return ret;
3581
3582 ret = ci_do_program_memory_timing_parameters(rdev);
3583 if (ret)
3584 return ret;
3585
3586 ret = ci_populate_smc_uvd_level(rdev, table);
3587 if (ret)
3588 return ret;
3589
3590 table->UvdBootLevel = 0;
3591 table->VceBootLevel = 0;
3592 table->AcpBootLevel = 0;
3593 table->SamuBootLevel = 0;
3594 table->GraphicsBootLevel = 0;
3595 table->MemoryBootLevel = 0;
3596
3597 ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
3598 pi->vbios_boot_state.sclk_bootup_value,
3599 (u32 *)&pi->smc_state_table.GraphicsBootLevel);
3600
3601 ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
3602 pi->vbios_boot_state.mclk_bootup_value,
3603 (u32 *)&pi->smc_state_table.MemoryBootLevel);
3604
3605 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
3606 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
3607 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
3608
3609 ci_populate_smc_initial_state(rdev, radeon_boot_state);
3610
3611 ret = ci_populate_bapm_parameters_in_dpm_table(rdev);
3612 if (ret)
3613 return ret;
3614
3615 table->UVDInterval = 1;
3616 table->VCEInterval = 1;
3617 table->ACPInterval = 1;
3618 table->SAMUInterval = 1;
3619 table->GraphicsVoltageChangeEnable = 1;
3620 table->GraphicsThermThrottleEnable = 1;
3621 table->GraphicsInterval = 1;
3622 table->VoltageInterval = 1;
3623 table->ThermalInterval = 1;
3624 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
3625 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3626 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
3627 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3628 table->MemoryVoltageChangeEnable = 1;
3629 table->MemoryInterval = 1;
3630 table->VoltageResponseTime = 0;
3631 table->VddcVddciDelta = 4000;
3632 table->PhaseResponseTime = 0;
3633 table->MemoryThermThrottleEnable = 1;
3634 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;
3635 table->PCIeGenInterval = 1;
3636 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
3637 table->SVI2Enable = 1;
3638 else
3639 table->SVI2Enable = 0;
3640
3641 table->ThermGpio = 17;
3642 table->SclkStepSize = 0x4000;
3643
3644 table->SystemFlags = cpu_to_be32(table->SystemFlags);
3645 table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
3646 table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
3647 table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
3648 table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
3649 table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
3650 table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
3651 table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
3652 table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
3653 table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
3654 table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
3655 table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
3656 table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
3657 table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
3658
3659 ret = ci_copy_bytes_to_smc(rdev,
3660 pi->dpm_table_start +
3661 offsetof(SMU7_Discrete_DpmTable, SystemFlags),
3662 (u8 *)&table->SystemFlags,
3663 sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
3664 pi->sram_end);
3665 if (ret)
3666 return ret;
3667
3668 return 0;
3669 }
3670
3671 static void ci_trim_single_dpm_states(struct radeon_device *rdev,
3672 struct ci_single_dpm_table *dpm_table,
3673 u32 low_limit, u32 high_limit)
3674 {
3675 u32 i;
3676
3677 for (i = 0; i < dpm_table->count; i++) {
3678 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3679 (dpm_table->dpm_levels[i].value > high_limit))
3680 dpm_table->dpm_levels[i].enabled = false;
3681 else
3682 dpm_table->dpm_levels[i].enabled = true;
3683 }
3684 }
3685
3686 static void ci_trim_pcie_dpm_states(struct radeon_device *rdev,
3687 u32 speed_low, u32 lanes_low,
3688 u32 speed_high, u32 lanes_high)
3689 {
3690 struct ci_power_info *pi = ci_get_pi(rdev);
3691 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
3692 u32 i, j;
3693
3694 for (i = 0; i < pcie_table->count; i++) {
3695 if ((pcie_table->dpm_levels[i].value < speed_low) ||
3696 (pcie_table->dpm_levels[i].param1 < lanes_low) ||
3697 (pcie_table->dpm_levels[i].value > speed_high) ||
3698 (pcie_table->dpm_levels[i].param1 > lanes_high))
3699 pcie_table->dpm_levels[i].enabled = false;
3700 else
3701 pcie_table->dpm_levels[i].enabled = true;
3702 }
3703
3704 for (i = 0; i < pcie_table->count; i++) {
3705 if (pcie_table->dpm_levels[i].enabled) {
3706 for (j = i + 1; j < pcie_table->count; j++) {
3707 if (pcie_table->dpm_levels[j].enabled) {
3708 if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
3709 (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
3710 pcie_table->dpm_levels[j].enabled = false;
3711 }
3712 }
3713 }
3714 }
3715 }
3716
3717 static int ci_trim_dpm_states(struct radeon_device *rdev,
3718 struct radeon_ps *radeon_state)
3719 {
3720 struct ci_ps *state = ci_get_ps(radeon_state);
3721 struct ci_power_info *pi = ci_get_pi(rdev);
3722 u32 high_limit_count;
3723
3724 if (state->performance_level_count < 1)
3725 return -EINVAL;
3726
3727 if (state->performance_level_count == 1)
3728 high_limit_count = 0;
3729 else
3730 high_limit_count = 1;
3731
3732 ci_trim_single_dpm_states(rdev,
3733 &pi->dpm_table.sclk_table,
3734 state->performance_levels[0].sclk,
3735 state->performance_levels[high_limit_count].sclk);
3736
3737 ci_trim_single_dpm_states(rdev,
3738 &pi->dpm_table.mclk_table,
3739 state->performance_levels[0].mclk,
3740 state->performance_levels[high_limit_count].mclk);
3741
3742 ci_trim_pcie_dpm_states(rdev,
3743 state->performance_levels[0].pcie_gen,
3744 state->performance_levels[0].pcie_lane,
3745 state->performance_levels[high_limit_count].pcie_gen,
3746 state->performance_levels[high_limit_count].pcie_lane);
3747
3748 return 0;
3749 }
3750
3751 static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev)
3752 {
3753 struct radeon_clock_voltage_dependency_table *disp_voltage_table =
3754 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3755 struct radeon_clock_voltage_dependency_table *vddc_table =
3756 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3757 u32 requested_voltage = 0;
3758 u32 i;
3759
3760 if (disp_voltage_table == NULL)
3761 return -EINVAL;
3762 if (!disp_voltage_table->count)
3763 return -EINVAL;
3764
3765 for (i = 0; i < disp_voltage_table->count; i++) {
3766 if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3767 requested_voltage = disp_voltage_table->entries[i].v;
3768 }
3769
3770 for (i = 0; i < vddc_table->count; i++) {
3771 if (requested_voltage <= vddc_table->entries[i].v) {
3772 requested_voltage = vddc_table->entries[i].v;
3773 return (ci_send_msg_to_smc_with_parameter(rdev,
3774 PPSMC_MSG_VddC_Request,
3775 requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
3776 0 : -EINVAL;
3777 }
3778 }
3779
3780 return -EINVAL;
3781 }
3782
3783 static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev)
3784 {
3785 struct ci_power_info *pi = ci_get_pi(rdev);
3786 PPSMC_Result result;
3787
3788 ci_apply_disp_minimum_voltage_request(rdev);
3789
3790 if (!pi->sclk_dpm_key_disabled) {
3791 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3792 result = ci_send_msg_to_smc_with_parameter(rdev,
3793 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3794 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3795 if (result != PPSMC_Result_OK)
3796 return -EINVAL;
3797 }
3798 }
3799
3800 if (!pi->mclk_dpm_key_disabled) {
3801 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3802 result = ci_send_msg_to_smc_with_parameter(rdev,
3803 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3804 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3805 if (result != PPSMC_Result_OK)
3806 return -EINVAL;
3807 }
3808 }
3809 #if 0
3810 if (!pi->pcie_dpm_key_disabled) {
3811 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3812 result = ci_send_msg_to_smc_with_parameter(rdev,
3813 PPSMC_MSG_PCIeDPM_SetEnabledMask,
3814 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3815 if (result != PPSMC_Result_OK)
3816 return -EINVAL;
3817 }
3818 }
3819 #endif
3820 return 0;
3821 }
3822
3823 static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev,
3824 struct radeon_ps *radeon_state)
3825 {
3826 struct ci_power_info *pi = ci_get_pi(rdev);
3827 struct ci_ps *state = ci_get_ps(radeon_state);
3828 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
3829 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3830 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
3831 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3832 u32 i;
3833
3834 pi->need_update_smu7_dpm_table = 0;
3835
3836 for (i = 0; i < sclk_table->count; i++) {
3837 if (sclk == sclk_table->dpm_levels[i].value)
3838 break;
3839 }
3840
3841 if (i >= sclk_table->count) {
3842 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3843 } else {
3844 /* XXX check display min clock requirements */
3845 if (CISLAND_MINIMUM_ENGINE_CLOCK != CISLAND_MINIMUM_ENGINE_CLOCK)
3846 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3847 }
3848
3849 for (i = 0; i < mclk_table->count; i++) {
3850 if (mclk == mclk_table->dpm_levels[i].value)
3851 break;
3852 }
3853
3854 if (i >= mclk_table->count)
3855 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3856
3857 if (rdev->pm.dpm.current_active_crtc_count !=
3858 rdev->pm.dpm.new_active_crtc_count)
3859 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3860 }
3861
3862 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev,
3863 struct radeon_ps *radeon_state)
3864 {
3865 struct ci_power_info *pi = ci_get_pi(rdev);
3866 struct ci_ps *state = ci_get_ps(radeon_state);
3867 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3868 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3869 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3870 int ret;
3871
3872 if (!pi->need_update_smu7_dpm_table)
3873 return 0;
3874
3875 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
3876 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
3877
3878 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
3879 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
3880
3881 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
3882 ret = ci_populate_all_graphic_levels(rdev);
3883 if (ret)
3884 return ret;
3885 }
3886
3887 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
3888 ret = ci_populate_all_memory_levels(rdev);
3889 if (ret)
3890 return ret;
3891 }
3892
3893 return 0;
3894 }
3895
3896 static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
3897 {
3898 struct ci_power_info *pi = ci_get_pi(rdev);
3899 const struct radeon_clock_and_voltage_limits *max_limits;
3900 int i;
3901
3902 if (rdev->pm.dpm.ac_power)
3903 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3904 else
3905 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3906
3907 if (enable) {
3908 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
3909
3910 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3911 if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3912 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
3913
3914 if (!pi->caps_uvd_dpm)
3915 break;
3916 }
3917 }
3918
3919 ci_send_msg_to_smc_with_parameter(rdev,
3920 PPSMC_MSG_UVDDPM_SetEnabledMask,
3921 pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
3922
3923 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3924 pi->uvd_enabled = true;
3925 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3926 ci_send_msg_to_smc_with_parameter(rdev,
3927 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3928 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3929 }
3930 } else {
3931 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3932 pi->uvd_enabled = false;
3933 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
3934 ci_send_msg_to_smc_with_parameter(rdev,
3935 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3936 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3937 }
3938 }
3939
3940 return (ci_send_msg_to_smc(rdev, enable ?
3941 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
3942 0 : -EINVAL;
3943 }
3944
3945 static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable)
3946 {
3947 struct ci_power_info *pi = ci_get_pi(rdev);
3948 const struct radeon_clock_and_voltage_limits *max_limits;
3949 int i;
3950
3951 if (rdev->pm.dpm.ac_power)
3952 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3953 else
3954 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3955
3956 if (enable) {
3957 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
3958 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3959 if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3960 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
3961
3962 if (!pi->caps_vce_dpm)
3963 break;
3964 }
3965 }
3966
3967 ci_send_msg_to_smc_with_parameter(rdev,
3968 PPSMC_MSG_VCEDPM_SetEnabledMask,
3969 pi->dpm_level_enable_mask.vce_dpm_enable_mask);
3970 }
3971
3972 return (ci_send_msg_to_smc(rdev, enable ?
3973 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
3974 0 : -EINVAL;
3975 }
3976
3977 #if 0
3978 static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable)
3979 {
3980 struct ci_power_info *pi = ci_get_pi(rdev);
3981 const struct radeon_clock_and_voltage_limits *max_limits;
3982 int i;
3983
3984 if (rdev->pm.dpm.ac_power)
3985 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3986 else
3987 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3988
3989 if (enable) {
3990 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
3991 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3992 if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3993 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
3994
3995 if (!pi->caps_samu_dpm)
3996 break;
3997 }
3998 }
3999
4000 ci_send_msg_to_smc_with_parameter(rdev,
4001 PPSMC_MSG_SAMUDPM_SetEnabledMask,
4002 pi->dpm_level_enable_mask.samu_dpm_enable_mask);
4003 }
4004 return (ci_send_msg_to_smc(rdev, enable ?
4005 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
4006 0 : -EINVAL;
4007 }
4008
4009 static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable)
4010 {
4011 struct ci_power_info *pi = ci_get_pi(rdev);
4012 const struct radeon_clock_and_voltage_limits *max_limits;
4013 int i;
4014
4015 if (rdev->pm.dpm.ac_power)
4016 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4017 else
4018 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4019
4020 if (enable) {
4021 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4022 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4023 if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4024 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
4025
4026 if (!pi->caps_acp_dpm)
4027 break;
4028 }
4029 }
4030
4031 ci_send_msg_to_smc_with_parameter(rdev,
4032 PPSMC_MSG_ACPDPM_SetEnabledMask,
4033 pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4034 }
4035
4036 return (ci_send_msg_to_smc(rdev, enable ?
4037 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
4038 0 : -EINVAL;
4039 }
4040 #endif
4041
4042 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate)
4043 {
4044 struct ci_power_info *pi = ci_get_pi(rdev);
4045 u32 tmp;
4046
4047 if (!gate) {
4048 if (pi->caps_uvd_dpm ||
4049 (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
4050 pi->smc_state_table.UvdBootLevel = 0;
4051 else
4052 pi->smc_state_table.UvdBootLevel =
4053 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
4054
4055 tmp = RREG32_SMC(DPM_TABLE_475);
4056 tmp &= ~UvdBootLevel_MASK;
4057 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel);
4058 WREG32_SMC(DPM_TABLE_475, tmp);
4059 }
4060
4061 return ci_enable_uvd_dpm(rdev, !gate);
4062 }
4063
4064 static u8 ci_get_vce_boot_level(struct radeon_device *rdev)
4065 {
4066 u8 i;
4067 u32 min_evclk = 30000; /* ??? */
4068 struct radeon_vce_clock_voltage_dependency_table *table =
4069 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
4070
4071 for (i = 0; i < table->count; i++) {
4072 if (table->entries[i].evclk >= min_evclk)
4073 return i;
4074 }
4075
4076 return table->count - 1;
4077 }
4078
4079 static int ci_update_vce_dpm(struct radeon_device *rdev,
4080 struct radeon_ps *radeon_new_state,
4081 struct radeon_ps *radeon_current_state)
4082 {
4083 struct ci_power_info *pi = ci_get_pi(rdev);
4084 int ret = 0;
4085 u32 tmp;
4086
4087 if (radeon_current_state->evclk != radeon_new_state->evclk) {
4088 if (radeon_new_state->evclk) {
4089 /* turn the clocks on when encoding */
4090 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false);
4091
4092 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev);
4093 tmp = RREG32_SMC(DPM_TABLE_475);
4094 tmp &= ~VceBootLevel_MASK;
4095 tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel);
4096 WREG32_SMC(DPM_TABLE_475, tmp);
4097
4098 ret = ci_enable_vce_dpm(rdev, true);
4099 } else {
4100 /* turn the clocks off when not encoding */
4101 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true);
4102
4103 ret = ci_enable_vce_dpm(rdev, false);
4104 }
4105 }
4106 return ret;
4107 }
4108
4109 #if 0
4110 static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate)
4111 {
4112 return ci_enable_samu_dpm(rdev, gate);
4113 }
4114
4115 static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate)
4116 {
4117 struct ci_power_info *pi = ci_get_pi(rdev);
4118 u32 tmp;
4119
4120 if (!gate) {
4121 pi->smc_state_table.AcpBootLevel = 0;
4122
4123 tmp = RREG32_SMC(DPM_TABLE_475);
4124 tmp &= ~AcpBootLevel_MASK;
4125 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
4126 WREG32_SMC(DPM_TABLE_475, tmp);
4127 }
4128
4129 return ci_enable_acp_dpm(rdev, !gate);
4130 }
4131 #endif
4132
4133 static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev,
4134 struct radeon_ps *radeon_state)
4135 {
4136 struct ci_power_info *pi = ci_get_pi(rdev);
4137 int ret;
4138
4139 ret = ci_trim_dpm_states(rdev, radeon_state);
4140 if (ret)
4141 return ret;
4142
4143 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
4144 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
4145 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
4146 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
4147 pi->last_mclk_dpm_enable_mask =
4148 pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4149 if (pi->uvd_enabled) {
4150 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
4151 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4152 }
4153 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
4154 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
4155
4156 return 0;
4157 }
4158
4159 static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev,
4160 u32 level_mask)
4161 {
4162 u32 level = 0;
4163
4164 while ((level_mask & (1 << level)) == 0)
4165 level++;
4166
4167 return level;
4168 }
4169
4170
4171 int ci_dpm_force_performance_level(struct radeon_device *rdev,
4172 enum radeon_dpm_forced_level level)
4173 {
4174 struct ci_power_info *pi = ci_get_pi(rdev);
4175 u32 tmp, levels, i;
4176 int ret;
4177
4178 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
4179 if ((!pi->pcie_dpm_key_disabled) &&
4180 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4181 levels = 0;
4182 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
4183 while (tmp >>= 1)
4184 levels++;
4185 if (levels) {
4186 ret = ci_dpm_force_state_pcie(rdev, level);
4187 if (ret)
4188 return ret;
4189 for (i = 0; i < rdev->usec_timeout; i++) {
4190 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
4191 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
4192 if (tmp == levels)
4193 break;
4194 udelay(1);
4195 }
4196 }
4197 }
4198 if ((!pi->sclk_dpm_key_disabled) &&
4199 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4200 levels = 0;
4201 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
4202 while (tmp >>= 1)
4203 levels++;
4204 if (levels) {
4205 ret = ci_dpm_force_state_sclk(rdev, levels);
4206 if (ret)
4207 return ret;
4208 for (i = 0; i < rdev->usec_timeout; i++) {
4209 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4210 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
4211 if (tmp == levels)
4212 break;
4213 udelay(1);
4214 }
4215 }
4216 }
4217 if ((!pi->mclk_dpm_key_disabled) &&
4218 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4219 levels = 0;
4220 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4221 while (tmp >>= 1)
4222 levels++;
4223 if (levels) {
4224 ret = ci_dpm_force_state_mclk(rdev, levels);
4225 if (ret)
4226 return ret;
4227 for (i = 0; i < rdev->usec_timeout; i++) {
4228 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4229 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
4230 if (tmp == levels)
4231 break;
4232 udelay(1);
4233 }
4234 }
4235 }
4236 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
4237 if ((!pi->sclk_dpm_key_disabled) &&
4238 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4239 levels = ci_get_lowest_enabled_level(rdev,
4240 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
4241 ret = ci_dpm_force_state_sclk(rdev, levels);
4242 if (ret)
4243 return ret;
4244 for (i = 0; i < rdev->usec_timeout; i++) {
4245 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4246 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
4247 if (tmp == levels)
4248 break;
4249 udelay(1);
4250 }
4251 }
4252 if ((!pi->mclk_dpm_key_disabled) &&
4253 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4254 levels = ci_get_lowest_enabled_level(rdev,
4255 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4256 ret = ci_dpm_force_state_mclk(rdev, levels);
4257 if (ret)
4258 return ret;
4259 for (i = 0; i < rdev->usec_timeout; i++) {
4260 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4261 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
4262 if (tmp == levels)
4263 break;
4264 udelay(1);
4265 }
4266 }
4267 if ((!pi->pcie_dpm_key_disabled) &&
4268 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4269 levels = ci_get_lowest_enabled_level(rdev,
4270 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
4271 ret = ci_dpm_force_state_pcie(rdev, levels);
4272 if (ret)
4273 return ret;
4274 for (i = 0; i < rdev->usec_timeout; i++) {
4275 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
4276 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
4277 if (tmp == levels)
4278 break;
4279 udelay(1);
4280 }
4281 }
4282 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
4283 if (!pi->pcie_dpm_key_disabled) {
4284 PPSMC_Result smc_result;
4285
4286 smc_result = ci_send_msg_to_smc(rdev,
4287 PPSMC_MSG_PCIeDPM_UnForceLevel);
4288 if (smc_result != PPSMC_Result_OK)
4289 return -EINVAL;
4290 }
4291 ret = ci_upload_dpm_level_enable_mask(rdev);
4292 if (ret)
4293 return ret;
4294 }
4295
4296 rdev->pm.dpm.forced_level = level;
4297
4298 return 0;
4299 }
4300
4301 static int ci_set_mc_special_registers(struct radeon_device *rdev,
4302 struct ci_mc_reg_table *table)
4303 {
4304 struct ci_power_info *pi = ci_get_pi(rdev);
4305 u8 i, j, k;
4306 u32 temp_reg;
4307
4308 for (i = 0, j = table->last; i < table->last; i++) {
4309 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4310 return -EINVAL;
4311 switch(table->mc_reg_address[i].s1 << 2) {
4312 case MC_SEQ_MISC1:
4313 temp_reg = RREG32(MC_PMG_CMD_EMRS);
4314 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
4315 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
4316 for (k = 0; k < table->num_entries; k++) {
4317 table->mc_reg_table_entry[k].mc_data[j] =
4318 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
4319 }
4320 j++;
4321 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4322 return -EINVAL;
4323
4324 temp_reg = RREG32(MC_PMG_CMD_MRS);
4325 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
4326 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
4327 for (k = 0; k < table->num_entries; k++) {
4328 table->mc_reg_table_entry[k].mc_data[j] =
4329 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4330 if (!pi->mem_gddr5)
4331 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
4332 }
4333 j++;
4334 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4335 return -EINVAL;
4336
4337 if (!pi->mem_gddr5) {
4338 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
4339 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
4340 for (k = 0; k < table->num_entries; k++) {
4341 table->mc_reg_table_entry[k].mc_data[j] =
4342 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
4343 }
4344 j++;
4345 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4346 return -EINVAL;
4347 }
4348 break;
4349 case MC_SEQ_RESERVE_M:
4350 temp_reg = RREG32(MC_PMG_CMD_MRS1);
4351 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
4352 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
4353 for (k = 0; k < table->num_entries; k++) {
4354 table->mc_reg_table_entry[k].mc_data[j] =
4355 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4356 }
4357 j++;
4358 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4359 return -EINVAL;
4360 break;
4361 default:
4362 break;
4363 }
4364
4365 }
4366
4367 table->last = j;
4368
4369 return 0;
4370 }
4371
4372 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
4373 {
4374 bool result = true;
4375
4376 switch(in_reg) {
4377 case MC_SEQ_RAS_TIMING >> 2:
4378 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
4379 break;
4380 case MC_SEQ_DLL_STBY >> 2:
4381 *out_reg = MC_SEQ_DLL_STBY_LP >> 2;
4382 break;
4383 case MC_SEQ_G5PDX_CMD0 >> 2:
4384 *out_reg = MC_SEQ_G5PDX_CMD0_LP >> 2;
4385 break;
4386 case MC_SEQ_G5PDX_CMD1 >> 2:
4387 *out_reg = MC_SEQ_G5PDX_CMD1_LP >> 2;
4388 break;
4389 case MC_SEQ_G5PDX_CTRL >> 2:
4390 *out_reg = MC_SEQ_G5PDX_CTRL_LP >> 2;
4391 break;
4392 case MC_SEQ_CAS_TIMING >> 2:
4393 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
4394 break;
4395 case MC_SEQ_MISC_TIMING >> 2:
4396 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
4397 break;
4398 case MC_SEQ_MISC_TIMING2 >> 2:
4399 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
4400 break;
4401 case MC_SEQ_PMG_DVS_CMD >> 2:
4402 *out_reg = MC_SEQ_PMG_DVS_CMD_LP >> 2;
4403 break;
4404 case MC_SEQ_PMG_DVS_CTL >> 2:
4405 *out_reg = MC_SEQ_PMG_DVS_CTL_LP >> 2;
4406 break;
4407 case MC_SEQ_RD_CTL_D0 >> 2:
4408 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
4409 break;
4410 case MC_SEQ_RD_CTL_D1 >> 2:
4411 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
4412 break;
4413 case MC_SEQ_WR_CTL_D0 >> 2:
4414 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
4415 break;
4416 case MC_SEQ_WR_CTL_D1 >> 2:
4417 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
4418 break;
4419 case MC_PMG_CMD_EMRS >> 2:
4420 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
4421 break;
4422 case MC_PMG_CMD_MRS >> 2:
4423 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
4424 break;
4425 case MC_PMG_CMD_MRS1 >> 2:
4426 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
4427 break;
4428 case MC_SEQ_PMG_TIMING >> 2:
4429 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
4430 break;
4431 case MC_PMG_CMD_MRS2 >> 2:
4432 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
4433 break;
4434 case MC_SEQ_WR_CTL_2 >> 2:
4435 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
4436 break;
4437 default:
4438 result = false;
4439 break;
4440 }
4441
4442 return result;
4443 }
4444
4445 static void ci_set_valid_flag(struct ci_mc_reg_table *table)
4446 {
4447 u8 i, j;
4448
4449 for (i = 0; i < table->last; i++) {
4450 for (j = 1; j < table->num_entries; j++) {
4451 if (table->mc_reg_table_entry[j-1].mc_data[i] !=
4452 table->mc_reg_table_entry[j].mc_data[i]) {
4453 table->valid_flag |= 1 << i;
4454 break;
4455 }
4456 }
4457 }
4458 }
4459
4460 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
4461 {
4462 u32 i;
4463 u16 address;
4464
4465 for (i = 0; i < table->last; i++) {
4466 table->mc_reg_address[i].s0 =
4467 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
4468 address : table->mc_reg_address[i].s1;
4469 }
4470 }
4471
4472 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
4473 struct ci_mc_reg_table *ci_table)
4474 {
4475 u8 i, j;
4476
4477 if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4478 return -EINVAL;
4479 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
4480 return -EINVAL;
4481
4482 for (i = 0; i < table->last; i++)
4483 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
4484
4485 ci_table->last = table->last;
4486
4487 for (i = 0; i < table->num_entries; i++) {
4488 ci_table->mc_reg_table_entry[i].mclk_max =
4489 table->mc_reg_table_entry[i].mclk_max;
4490 for (j = 0; j < table->last; j++)
4491 ci_table->mc_reg_table_entry[i].mc_data[j] =
4492 table->mc_reg_table_entry[i].mc_data[j];
4493 }
4494 ci_table->num_entries = table->num_entries;
4495
4496 return 0;
4497 }
4498
4499 static int ci_register_patching_mc_seq(struct radeon_device *rdev,
4500 struct ci_mc_reg_table *table)
4501 {
4502 u8 i, k;
4503 u32 tmp;
4504 bool patch;
4505
4506 tmp = RREG32(MC_SEQ_MISC0);
4507 patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
4508
4509 if (patch &&
4510 ((rdev->pdev->device == 0x67B0) ||
4511 (rdev->pdev->device == 0x67B1))) {
4512 for (i = 0; i < table->last; i++) {
4513 if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4514 return -EINVAL;
4515 switch(table->mc_reg_address[i].s1 >> 2) {
4516 case MC_SEQ_MISC1:
4517 for (k = 0; k < table->num_entries; k++) {
4518 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4519 (table->mc_reg_table_entry[k].mclk_max == 137500))
4520 table->mc_reg_table_entry[k].mc_data[i] =
4521 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) |
4522 0x00000007;
4523 }
4524 break;
4525 case MC_SEQ_WR_CTL_D0:
4526 for (k = 0; k < table->num_entries; k++) {
4527 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4528 (table->mc_reg_table_entry[k].mclk_max == 137500))
4529 table->mc_reg_table_entry[k].mc_data[i] =
4530 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4531 0x0000D0DD;
4532 }
4533 break;
4534 case MC_SEQ_WR_CTL_D1:
4535 for (k = 0; k < table->num_entries; k++) {
4536 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4537 (table->mc_reg_table_entry[k].mclk_max == 137500))
4538 table->mc_reg_table_entry[k].mc_data[i] =
4539 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4540 0x0000D0DD;
4541 }
4542 break;
4543 case MC_SEQ_WR_CTL_2:
4544 for (k = 0; k < table->num_entries; k++) {
4545 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4546 (table->mc_reg_table_entry[k].mclk_max == 137500))
4547 table->mc_reg_table_entry[k].mc_data[i] = 0;
4548 }
4549 break;
4550 case MC_SEQ_CAS_TIMING:
4551 for (k = 0; k < table->num_entries; k++) {
4552 if (table->mc_reg_table_entry[k].mclk_max == 125000)
4553 table->mc_reg_table_entry[k].mc_data[i] =
4554 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4555 0x000C0140;
4556 else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4557 table->mc_reg_table_entry[k].mc_data[i] =
4558 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4559 0x000C0150;
4560 }
4561 break;
4562 case MC_SEQ_MISC_TIMING:
4563 for (k = 0; k < table->num_entries; k++) {
4564 if (table->mc_reg_table_entry[k].mclk_max == 125000)
4565 table->mc_reg_table_entry[k].mc_data[i] =
4566 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4567 0x00000030;
4568 else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4569 table->mc_reg_table_entry[k].mc_data[i] =
4570 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4571 0x00000035;
4572 }
4573 break;
4574 default:
4575 break;
4576 }
4577 }
4578
4579 WREG32(MC_SEQ_IO_DEBUG_INDEX, 3);
4580 tmp = RREG32(MC_SEQ_IO_DEBUG_DATA);
4581 tmp = (tmp & 0xFFF8FFFF) | (1 << 16);
4582 WREG32(MC_SEQ_IO_DEBUG_INDEX, 3);
4583 WREG32(MC_SEQ_IO_DEBUG_DATA, tmp);
4584 }
4585
4586 return 0;
4587 }
4588
4589 static int ci_initialize_mc_reg_table(struct radeon_device *rdev)
4590 {
4591 struct ci_power_info *pi = ci_get_pi(rdev);
4592 struct atom_mc_reg_table *table;
4593 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
4594 u8 module_index = rv770_get_memory_module_index(rdev);
4595 int ret;
4596
4597 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
4598 if (!table)
4599 return -ENOMEM;
4600
4601 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
4602 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
4603 WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY));
4604 WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0));
4605 WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1));
4606 WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL));
4607 WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD));
4608 WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL));
4609 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
4610 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
4611 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
4612 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
4613 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
4614 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
4615 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
4616 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
4617 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
4618 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
4619 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
4620 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
4621
4622 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
4623 if (ret)
4624 goto init_mc_done;
4625
4626 ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4627 if (ret)
4628 goto init_mc_done;
4629
4630 ci_set_s0_mc_reg_index(ci_table);
4631
4632 ret = ci_register_patching_mc_seq(rdev, ci_table);
4633 if (ret)
4634 goto init_mc_done;
4635
4636 ret = ci_set_mc_special_registers(rdev, ci_table);
4637 if (ret)
4638 goto init_mc_done;
4639
4640 ci_set_valid_flag(ci_table);
4641
4642 init_mc_done:
4643 kfree(table);
4644
4645 return ret;
4646 }
4647
4648 static int ci_populate_mc_reg_addresses(struct radeon_device *rdev,
4649 SMU7_Discrete_MCRegisters *mc_reg_table)
4650 {
4651 struct ci_power_info *pi = ci_get_pi(rdev);
4652 u32 i, j;
4653
4654 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
4655 if (pi->mc_reg_table.valid_flag & (1 << j)) {
4656 if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4657 return -EINVAL;
4658 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
4659 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
4660 i++;
4661 }
4662 }
4663
4664 mc_reg_table->last = (u8)i;
4665
4666 return 0;
4667 }
4668
4669 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
4670 SMU7_Discrete_MCRegisterSet *data,
4671 u32 num_entries, u32 valid_flag)
4672 {
4673 u32 i, j;
4674
4675 for (i = 0, j = 0; j < num_entries; j++) {
4676 if (valid_flag & (1 << j)) {
4677 data->value[i] = cpu_to_be32(entry->mc_data[j]);
4678 i++;
4679 }
4680 }
4681 }
4682
4683 static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
4684 const u32 memory_clock,
4685 SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
4686 {
4687 struct ci_power_info *pi = ci_get_pi(rdev);
4688 u32 i = 0;
4689
4690 for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
4691 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
4692 break;
4693 }
4694
4695 if ((i == pi->mc_reg_table.num_entries) && (i > 0))
4696 --i;
4697
4698 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
4699 mc_reg_table_data, pi->mc_reg_table.last,
4700 pi->mc_reg_table.valid_flag);
4701 }
4702
4703 static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
4704 SMU7_Discrete_MCRegisters *mc_reg_table)
4705 {
4706 struct ci_power_info *pi = ci_get_pi(rdev);
4707 u32 i;
4708
4709 for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
4710 ci_convert_mc_reg_table_entry_to_smc(rdev,
4711 pi->dpm_table.mclk_table.dpm_levels[i].value,
4712 &mc_reg_table->data[i]);
4713 }
4714
4715 static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev)
4716 {
4717 struct ci_power_info *pi = ci_get_pi(rdev);
4718 int ret;
4719
4720 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4721
4722 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table);
4723 if (ret)
4724 return ret;
4725 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4726
4727 return ci_copy_bytes_to_smc(rdev,
4728 pi->mc_reg_table_start,
4729 (u8 *)&pi->smc_mc_reg_table,
4730 sizeof(SMU7_Discrete_MCRegisters),
4731 pi->sram_end);
4732 }
4733
4734 static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev)
4735 {
4736 struct ci_power_info *pi = ci_get_pi(rdev);
4737
4738 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
4739 return 0;
4740
4741 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4742
4743 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4744
4745 return ci_copy_bytes_to_smc(rdev,
4746 pi->mc_reg_table_start +
4747 offsetof(SMU7_Discrete_MCRegisters, data[0]),
4748 (u8 *)&pi->smc_mc_reg_table.data[0],
4749 sizeof(SMU7_Discrete_MCRegisterSet) *
4750 pi->dpm_table.mclk_table.count,
4751 pi->sram_end);
4752 }
4753
4754 static void ci_enable_voltage_control(struct radeon_device *rdev)
4755 {
4756 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
4757
4758 tmp |= VOLT_PWRMGT_EN;
4759 WREG32_SMC(GENERAL_PWRMGT, tmp);
4760 }
4761
4762 static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev,
4763 struct radeon_ps *radeon_state)
4764 {
4765 struct ci_ps *state = ci_get_ps(radeon_state);
4766 int i;
4767 u16 pcie_speed, max_speed = 0;
4768
4769 for (i = 0; i < state->performance_level_count; i++) {
4770 pcie_speed = state->performance_levels[i].pcie_gen;
4771 if (max_speed < pcie_speed)
4772 max_speed = pcie_speed;
4773 }
4774
4775 return max_speed;
4776 }
4777
4778 static u16 ci_get_current_pcie_speed(struct radeon_device *rdev)
4779 {
4780 u32 speed_cntl = 0;
4781
4782 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
4783 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
4784
4785 return (u16)speed_cntl;
4786 }
4787
4788 static int ci_get_current_pcie_lane_number(struct radeon_device *rdev)
4789 {
4790 u32 link_width = 0;
4791
4792 link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK;
4793 link_width >>= LC_LINK_WIDTH_RD_SHIFT;
4794
4795 switch (link_width) {
4796 case RADEON_PCIE_LC_LINK_WIDTH_X1:
4797 return 1;
4798 case RADEON_PCIE_LC_LINK_WIDTH_X2:
4799 return 2;
4800 case RADEON_PCIE_LC_LINK_WIDTH_X4:
4801 return 4;
4802 case RADEON_PCIE_LC_LINK_WIDTH_X8:
4803 return 8;
4804 case RADEON_PCIE_LC_LINK_WIDTH_X12:
4805 /* not actually supported */
4806 return 12;
4807 case RADEON_PCIE_LC_LINK_WIDTH_X0:
4808 case RADEON_PCIE_LC_LINK_WIDTH_X16:
4809 default:
4810 return 16;
4811 }
4812 }
4813
4814 static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev,
4815 struct radeon_ps *radeon_new_state,
4816 struct radeon_ps *radeon_current_state)
4817 {
4818 struct ci_power_info *pi = ci_get_pi(rdev);
4819 enum radeon_pcie_gen target_link_speed =
4820 ci_get_maximum_link_speed(rdev, radeon_new_state);
4821 enum radeon_pcie_gen current_link_speed;
4822
4823 if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
4824 current_link_speed = ci_get_maximum_link_speed(rdev, radeon_current_state);
4825 else
4826 current_link_speed = pi->force_pcie_gen;
4827
4828 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
4829 pi->pspp_notify_required = false;
4830 if (target_link_speed > current_link_speed) {
4831 switch (target_link_speed) {
4832 #ifdef CONFIG_ACPI
4833 case RADEON_PCIE_GEN3:
4834 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
4835 break;
4836 pi->force_pcie_gen = RADEON_PCIE_GEN2;
4837 if (current_link_speed == RADEON_PCIE_GEN2)
4838 break;
4839 case RADEON_PCIE_GEN2:
4840 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
4841 break;
4842 #endif
4843 default:
4844 pi->force_pcie_gen = ci_get_current_pcie_speed(rdev);
4845 break;
4846 }
4847 } else {
4848 if (target_link_speed < current_link_speed)
4849 pi->pspp_notify_required = true;
4850 }
4851 }
4852
4853 static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
4854 struct radeon_ps *radeon_new_state,
4855 struct radeon_ps *radeon_current_state)
4856 {
4857 struct ci_power_info *pi = ci_get_pi(rdev);
4858 enum radeon_pcie_gen target_link_speed =
4859 ci_get_maximum_link_speed(rdev, radeon_new_state);
4860 u8 request;
4861
4862 if (pi->pspp_notify_required) {
4863 if (target_link_speed == RADEON_PCIE_GEN3)
4864 request = PCIE_PERF_REQ_PECI_GEN3;
4865 else if (target_link_speed == RADEON_PCIE_GEN2)
4866 request = PCIE_PERF_REQ_PECI_GEN2;
4867 else
4868 request = PCIE_PERF_REQ_PECI_GEN1;
4869
4870 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
4871 (ci_get_current_pcie_speed(rdev) > 0))
4872 return;
4873
4874 #ifdef CONFIG_ACPI
4875 radeon_acpi_pcie_performance_request(rdev, request, false);
4876 #endif
4877 }
4878 }
4879
4880 static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev)
4881 {
4882 struct ci_power_info *pi = ci_get_pi(rdev);
4883 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
4884 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
4885 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddc_table =
4886 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
4887 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddci_table =
4888 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
4889
4890 if (allowed_sclk_vddc_table == NULL)
4891 return -EINVAL;
4892 if (allowed_sclk_vddc_table->count < 1)
4893 return -EINVAL;
4894 if (allowed_mclk_vddc_table == NULL)
4895 return -EINVAL;
4896 if (allowed_mclk_vddc_table->count < 1)
4897 return -EINVAL;
4898 if (allowed_mclk_vddci_table == NULL)
4899 return -EINVAL;
4900 if (allowed_mclk_vddci_table->count < 1)
4901 return -EINVAL;
4902
4903 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
4904 pi->max_vddc_in_pp_table =
4905 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4906
4907 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
4908 pi->max_vddci_in_pp_table =
4909 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4910
4911 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
4912 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4913 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
4914 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4915 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
4916 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4917 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
4918 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4919
4920 return 0;
4921 }
4922
4923 static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc)
4924 {
4925 struct ci_power_info *pi = ci_get_pi(rdev);
4926 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
4927 u32 leakage_index;
4928
4929 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4930 if (leakage_table->leakage_id[leakage_index] == *vddc) {
4931 *vddc = leakage_table->actual_voltage[leakage_index];
4932 break;
4933 }
4934 }
4935 }
4936
4937 static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci)
4938 {
4939 struct ci_power_info *pi = ci_get_pi(rdev);
4940 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
4941 u32 leakage_index;
4942
4943 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4944 if (leakage_table->leakage_id[leakage_index] == *vddci) {
4945 *vddci = leakage_table->actual_voltage[leakage_index];
4946 break;
4947 }
4948 }
4949 }
4950
4951 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4952 struct radeon_clock_voltage_dependency_table *table)
4953 {
4954 u32 i;
4955
4956 if (table) {
4957 for (i = 0; i < table->count; i++)
4958 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4959 }
4960 }
4961
4962 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev,
4963 struct radeon_clock_voltage_dependency_table *table)
4964 {
4965 u32 i;
4966
4967 if (table) {
4968 for (i = 0; i < table->count; i++)
4969 ci_patch_with_vddci_leakage(rdev, &table->entries[i].v);
4970 }
4971 }
4972
4973 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4974 struct radeon_vce_clock_voltage_dependency_table *table)
4975 {
4976 u32 i;
4977
4978 if (table) {
4979 for (i = 0; i < table->count; i++)
4980 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4981 }
4982 }
4983
4984 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4985 struct radeon_uvd_clock_voltage_dependency_table *table)
4986 {
4987 u32 i;
4988
4989 if (table) {
4990 for (i = 0; i < table->count; i++)
4991 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4992 }
4993 }
4994
4995 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev,
4996 struct radeon_phase_shedding_limits_table *table)
4997 {
4998 u32 i;
4999
5000 if (table) {
5001 for (i = 0; i < table->count; i++)
5002 ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage);
5003 }
5004 }
5005
5006 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev,
5007 struct radeon_clock_and_voltage_limits *table)
5008 {
5009 if (table) {
5010 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc);
5011 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci);
5012 }
5013 }
5014
5015 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev,
5016 struct radeon_cac_leakage_table *table)
5017 {
5018 u32 i;
5019
5020 if (table) {
5021 for (i = 0; i < table->count; i++)
5022 ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc);
5023 }
5024 }
5025
5026 static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev)
5027 {
5028
5029 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5030 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5031 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5032 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5033 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5034 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
5035 ci_patch_clock_voltage_dependency_table_with_vddci_leakage(rdev,
5036 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5037 ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5038 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
5039 ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5040 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
5041 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5042 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
5043 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5044 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
5045 ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(rdev,
5046 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table);
5047 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
5048 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
5049 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
5050 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
5051 ci_patch_cac_leakage_table_with_vddc_leakage(rdev,
5052 &rdev->pm.dpm.dyn_state.cac_leakage_table);
5053
5054 }
5055
5056 static void ci_get_memory_type(struct radeon_device *rdev)
5057 {
5058 struct ci_power_info *pi = ci_get_pi(rdev);
5059 u32 tmp;
5060
5061 tmp = RREG32(MC_SEQ_MISC0);
5062
5063 if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==
5064 MC_SEQ_MISC0_GDDR5_VALUE)
5065 pi->mem_gddr5 = true;
5066 else
5067 pi->mem_gddr5 = false;
5068
5069 }
5070
5071 static void ci_update_current_ps(struct radeon_device *rdev,
5072 struct radeon_ps *rps)
5073 {
5074 struct ci_ps *new_ps = ci_get_ps(rps);
5075 struct ci_power_info *pi = ci_get_pi(rdev);
5076
5077 pi->current_rps = *rps;
5078 pi->current_ps = *new_ps;
5079 pi->current_rps.ps_priv = &pi->current_ps;
5080 }
5081
5082 static void ci_update_requested_ps(struct radeon_device *rdev,
5083 struct radeon_ps *rps)
5084 {
5085 struct ci_ps *new_ps = ci_get_ps(rps);
5086 struct ci_power_info *pi = ci_get_pi(rdev);
5087
5088 pi->requested_rps = *rps;
5089 pi->requested_ps = *new_ps;
5090 pi->requested_rps.ps_priv = &pi->requested_ps;
5091 }
5092
5093 int ci_dpm_pre_set_power_state(struct radeon_device *rdev)
5094 {
5095 struct ci_power_info *pi = ci_get_pi(rdev);
5096 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
5097 struct radeon_ps *new_ps = &requested_ps;
5098
5099 ci_update_requested_ps(rdev, new_ps);
5100
5101 ci_apply_state_adjust_rules(rdev, &pi->requested_rps);
5102
5103 return 0;
5104 }
5105
5106 void ci_dpm_post_set_power_state(struct radeon_device *rdev)
5107 {
5108 struct ci_power_info *pi = ci_get_pi(rdev);
5109 struct radeon_ps *new_ps = &pi->requested_rps;
5110
5111 ci_update_current_ps(rdev, new_ps);
5112 }
5113
5114
5115 void ci_dpm_setup_asic(struct radeon_device *rdev)
5116 {
5117 int r;
5118
5119 r = ci_mc_load_microcode(rdev);
5120 if (r)
5121 DRM_ERROR("Failed to load MC firmware!\n");
5122 ci_read_clock_registers(rdev);
5123 ci_get_memory_type(rdev);
5124 ci_enable_acpi_power_management(rdev);
5125 ci_init_sclk_t(rdev);
5126 }
5127
5128 int ci_dpm_enable(struct radeon_device *rdev)
5129 {
5130 struct ci_power_info *pi = ci_get_pi(rdev);
5131 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5132 int ret;
5133
5134 if (ci_is_smc_running(rdev))
5135 return -EINVAL;
5136 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
5137 ci_enable_voltage_control(rdev);
5138 ret = ci_construct_voltage_tables(rdev);
5139 if (ret) {
5140 DRM_ERROR("ci_construct_voltage_tables failed\n");
5141 return ret;
5142 }
5143 }
5144 if (pi->caps_dynamic_ac_timing) {
5145 ret = ci_initialize_mc_reg_table(rdev);
5146 if (ret)
5147 pi->caps_dynamic_ac_timing = false;
5148 }
5149 if (pi->dynamic_ss)
5150 ci_enable_spread_spectrum(rdev, true);
5151 if (pi->thermal_protection)
5152 ci_enable_thermal_protection(rdev, true);
5153 ci_program_sstp(rdev);
5154 ci_enable_display_gap(rdev);
5155 ci_program_vc(rdev);
5156 ret = ci_upload_firmware(rdev);
5157 if (ret) {
5158 DRM_ERROR("ci_upload_firmware failed\n");
5159 return ret;
5160 }
5161 ret = ci_process_firmware_header(rdev);
5162 if (ret) {
5163 DRM_ERROR("ci_process_firmware_header failed\n");
5164 return ret;
5165 }
5166 ret = ci_initial_switch_from_arb_f0_to_f1(rdev);
5167 if (ret) {
5168 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
5169 return ret;
5170 }
5171 ret = ci_init_smc_table(rdev);
5172 if (ret) {
5173 DRM_ERROR("ci_init_smc_table failed\n");
5174 return ret;
5175 }
5176 ret = ci_init_arb_table_index(rdev);
5177 if (ret) {
5178 DRM_ERROR("ci_init_arb_table_index failed\n");
5179 return ret;
5180 }
5181 if (pi->caps_dynamic_ac_timing) {
5182 ret = ci_populate_initial_mc_reg_table(rdev);
5183 if (ret) {
5184 DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
5185 return ret;
5186 }
5187 }
5188 ret = ci_populate_pm_base(rdev);
5189 if (ret) {
5190 DRM_ERROR("ci_populate_pm_base failed\n");
5191 return ret;
5192 }
5193 ci_dpm_start_smc(rdev);
5194 ci_enable_vr_hot_gpio_interrupt(rdev);
5195 ret = ci_notify_smc_display_change(rdev, false);
5196 if (ret) {
5197 DRM_ERROR("ci_notify_smc_display_change failed\n");
5198 return ret;
5199 }
5200 ci_enable_sclk_control(rdev, true);
5201 ret = ci_enable_ulv(rdev, true);
5202 if (ret) {
5203 DRM_ERROR("ci_enable_ulv failed\n");
5204 return ret;
5205 }
5206 ret = ci_enable_ds_master_switch(rdev, true);
5207 if (ret) {
5208 DRM_ERROR("ci_enable_ds_master_switch failed\n");
5209 return ret;
5210 }
5211 ret = ci_start_dpm(rdev);
5212 if (ret) {
5213 DRM_ERROR("ci_start_dpm failed\n");
5214 return ret;
5215 }
5216 ret = ci_enable_didt(rdev, true);
5217 if (ret) {
5218 DRM_ERROR("ci_enable_didt failed\n");
5219 return ret;
5220 }
5221 ret = ci_enable_smc_cac(rdev, true);
5222 if (ret) {
5223 DRM_ERROR("ci_enable_smc_cac failed\n");
5224 return ret;
5225 }
5226 ret = ci_enable_power_containment(rdev, true);
5227 if (ret) {
5228 DRM_ERROR("ci_enable_power_containment failed\n");
5229 return ret;
5230 }
5231
5232 ret = ci_power_control_set_level(rdev);
5233 if (ret) {
5234 DRM_ERROR("ci_power_control_set_level failed\n");
5235 return ret;
5236 }
5237
5238 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5239
5240 ret = ci_enable_thermal_based_sclk_dpm(rdev, true);
5241 if (ret) {
5242 DRM_ERROR("ci_enable_thermal_based_sclk_dpm failed\n");
5243 return ret;
5244 }
5245
5246 ci_thermal_start_thermal_controller(rdev);
5247
5248 ci_update_current_ps(rdev, boot_ps);
5249
5250 return 0;
5251 }
5252
5253 static int ci_set_temperature_range(struct radeon_device *rdev)
5254 {
5255 int ret;
5256
5257 ret = ci_thermal_enable_alert(rdev, false);
5258 if (ret)
5259 return ret;
5260 ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
5261 if (ret)
5262 return ret;
5263 ret = ci_thermal_enable_alert(rdev, true);
5264 if (ret)
5265 return ret;
5266
5267 return ret;
5268 }
5269
5270 int ci_dpm_late_enable(struct radeon_device *rdev)
5271 {
5272 int ret;
5273
5274 ret = ci_set_temperature_range(rdev);
5275 if (ret)
5276 return ret;
5277
5278 ci_dpm_powergate_uvd(rdev, true);
5279
5280 return 0;
5281 }
5282
5283 void ci_dpm_disable(struct radeon_device *rdev)
5284 {
5285 struct ci_power_info *pi = ci_get_pi(rdev);
5286 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5287
5288 ci_dpm_powergate_uvd(rdev, false);
5289
5290 if (!ci_is_smc_running(rdev))
5291 return;
5292
5293 ci_thermal_stop_thermal_controller(rdev);
5294
5295 if (pi->thermal_protection)
5296 ci_enable_thermal_protection(rdev, false);
5297 ci_enable_power_containment(rdev, false);
5298 ci_enable_smc_cac(rdev, false);
5299 ci_enable_didt(rdev, false);
5300 ci_enable_spread_spectrum(rdev, false);
5301 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
5302 ci_stop_dpm(rdev);
5303 ci_enable_ds_master_switch(rdev, false);
5304 ci_enable_ulv(rdev, false);
5305 ci_clear_vc(rdev);
5306 ci_reset_to_default(rdev);
5307 ci_dpm_stop_smc(rdev);
5308 ci_force_switch_to_arb_f0(rdev);
5309 ci_enable_thermal_based_sclk_dpm(rdev, false);
5310
5311 ci_update_current_ps(rdev, boot_ps);
5312 }
5313
5314 int ci_dpm_set_power_state(struct radeon_device *rdev)
5315 {
5316 struct ci_power_info *pi = ci_get_pi(rdev);
5317 struct radeon_ps *new_ps = &pi->requested_rps;
5318 struct radeon_ps *old_ps = &pi->current_rps;
5319 int ret;
5320
5321 ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps);
5322 if (pi->pcie_performance_request)
5323 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
5324 ret = ci_freeze_sclk_mclk_dpm(rdev);
5325 if (ret) {
5326 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
5327 return ret;
5328 }
5329 ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps);
5330 if (ret) {
5331 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
5332 return ret;
5333 }
5334 ret = ci_generate_dpm_level_enable_mask(rdev, new_ps);
5335 if (ret) {
5336 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
5337 return ret;
5338 }
5339
5340 ret = ci_update_vce_dpm(rdev, new_ps, old_ps);
5341 if (ret) {
5342 DRM_ERROR("ci_update_vce_dpm failed\n");
5343 return ret;
5344 }
5345
5346 ret = ci_update_sclk_t(rdev);
5347 if (ret) {
5348 DRM_ERROR("ci_update_sclk_t failed\n");
5349 return ret;
5350 }
5351 if (pi->caps_dynamic_ac_timing) {
5352 ret = ci_update_and_upload_mc_reg_table(rdev);
5353 if (ret) {
5354 DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
5355 return ret;
5356 }
5357 }
5358 ret = ci_program_memory_timing_parameters(rdev);
5359 if (ret) {
5360 DRM_ERROR("ci_program_memory_timing_parameters failed\n");
5361 return ret;
5362 }
5363 ret = ci_unfreeze_sclk_mclk_dpm(rdev);
5364 if (ret) {
5365 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
5366 return ret;
5367 }
5368 ret = ci_upload_dpm_level_enable_mask(rdev);
5369 if (ret) {
5370 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
5371 return ret;
5372 }
5373 if (pi->pcie_performance_request)
5374 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
5375
5376 return 0;
5377 }
5378
5379 void ci_dpm_reset_asic(struct radeon_device *rdev)
5380 {
5381 ci_set_boot_state(rdev);
5382 }
5383
5384 void ci_dpm_display_configuration_changed(struct radeon_device *rdev)
5385 {
5386 ci_program_display_gap(rdev);
5387 }
5388
5389 union power_info {
5390 struct _ATOM_POWERPLAY_INFO info;
5391 struct _ATOM_POWERPLAY_INFO_V2 info_2;
5392 struct _ATOM_POWERPLAY_INFO_V3 info_3;
5393 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
5394 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
5395 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
5396 };
5397
5398 union pplib_clock_info {
5399 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
5400 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
5401 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
5402 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
5403 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
5404 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
5405 };
5406
5407 union pplib_power_state {
5408 struct _ATOM_PPLIB_STATE v1;
5409 struct _ATOM_PPLIB_STATE_V2 v2;
5410 };
5411
5412 static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev,
5413 struct radeon_ps *rps,
5414 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
5415 u8 table_rev)
5416 {
5417 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
5418 rps->class = le16_to_cpu(non_clock_info->usClassification);
5419 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
5420
5421 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
5422 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
5423 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
5424 } else {
5425 rps->vclk = 0;
5426 rps->dclk = 0;
5427 }
5428
5429 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
5430 rdev->pm.dpm.boot_ps = rps;
5431 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
5432 rdev->pm.dpm.uvd_ps = rps;
5433 }
5434
5435 static void ci_parse_pplib_clock_info(struct radeon_device *rdev,
5436 struct radeon_ps *rps, int index,
5437 union pplib_clock_info *clock_info)
5438 {
5439 struct ci_power_info *pi = ci_get_pi(rdev);
5440 struct ci_ps *ps = ci_get_ps(rps);
5441 struct ci_pl *pl = &ps->performance_levels[index];
5442
5443 ps->performance_level_count = index + 1;
5444
5445 pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5446 pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
5447 pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5448 pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5449
5450 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
5451 pi->sys_pcie_mask,
5452 pi->vbios_boot_state.pcie_gen_bootup_value,
5453 clock_info->ci.ucPCIEGen);
5454 pl->pcie_lane = r600_get_pcie_lane_support(rdev,
5455 pi->vbios_boot_state.pcie_lane_bootup_value,
5456 le16_to_cpu(clock_info->ci.usPCIELane));
5457
5458 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
5459 pi->acpi_pcie_gen = pl->pcie_gen;
5460 }
5461
5462 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
5463 pi->ulv.supported = true;
5464 pi->ulv.pl = *pl;
5465 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
5466 }
5467
5468 /* patch up boot state */
5469 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
5470 pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
5471 pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
5472 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
5473 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
5474 }
5475
5476 switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
5477 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
5478 pi->use_pcie_powersaving_levels = true;
5479 if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
5480 pi->pcie_gen_powersaving.max = pl->pcie_gen;
5481 if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
5482 pi->pcie_gen_powersaving.min = pl->pcie_gen;
5483 if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
5484 pi->pcie_lane_powersaving.max = pl->pcie_lane;
5485 if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
5486 pi->pcie_lane_powersaving.min = pl->pcie_lane;
5487 break;
5488 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
5489 pi->use_pcie_performance_levels = true;
5490 if (pi->pcie_gen_performance.max < pl->pcie_gen)
5491 pi->pcie_gen_performance.max = pl->pcie_gen;
5492 if (pi->pcie_gen_performance.min > pl->pcie_gen)
5493 pi->pcie_gen_performance.min = pl->pcie_gen;
5494 if (pi->pcie_lane_performance.max < pl->pcie_lane)
5495 pi->pcie_lane_performance.max = pl->pcie_lane;
5496 if (pi->pcie_lane_performance.min > pl->pcie_lane)
5497 pi->pcie_lane_performance.min = pl->pcie_lane;
5498 break;
5499 default:
5500 break;
5501 }
5502 }
5503
5504 static int ci_parse_power_table(struct radeon_device *rdev)
5505 {
5506 struct radeon_mode_info *mode_info = &rdev->mode_info;
5507 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
5508 union pplib_power_state *power_state;
5509 int i, j, k, non_clock_array_index, clock_array_index;
5510 union pplib_clock_info *clock_info;
5511 struct _StateArray *state_array;
5512 struct _ClockInfoArray *clock_info_array;
5513 struct _NonClockInfoArray *non_clock_info_array;
5514 union power_info *power_info;
5515 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
5516 u16 data_offset;
5517 u8 frev, crev;
5518 u8 *power_state_offset;
5519 struct ci_ps *ps;
5520
5521 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
5522 &frev, &crev, &data_offset))
5523 return -EINVAL;
5524 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
5525
5526 state_array = (struct _StateArray *)
5527 (mode_info->atom_context->bios + data_offset +
5528 le16_to_cpu(power_info->pplib.usStateArrayOffset));
5529 clock_info_array = (struct _ClockInfoArray *)
5530 (mode_info->atom_context->bios + data_offset +
5531 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
5532 non_clock_info_array = (struct _NonClockInfoArray *)
5533 (mode_info->atom_context->bios + data_offset +
5534 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
5535
5536 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
5537 state_array->ucNumEntries, GFP_KERNEL);
5538 if (!rdev->pm.dpm.ps)
5539 return -ENOMEM;
5540 power_state_offset = (u8 *)state_array->states;
5541 for (i = 0; i < state_array->ucNumEntries; i++) {
5542 u8 *idx;
5543 power_state = (union pplib_power_state *)power_state_offset;
5544 non_clock_array_index = power_state->v2.nonClockInfoIndex;
5545 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
5546 &non_clock_info_array->nonClockInfo[non_clock_array_index];
5547 if (!rdev->pm.power_state[i].clock_info)
5548 return -EINVAL;
5549 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
5550 if (ps == NULL) {
5551 kfree(rdev->pm.dpm.ps);
5552 return -ENOMEM;
5553 }
5554 rdev->pm.dpm.ps[i].ps_priv = ps;
5555 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
5556 non_clock_info,
5557 non_clock_info_array->ucEntrySize);
5558 k = 0;
5559 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
5560 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
5561 clock_array_index = idx[j];
5562 if (clock_array_index >= clock_info_array->ucNumEntries)
5563 continue;
5564 if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
5565 break;
5566 clock_info = (union pplib_clock_info *)
5567 ((u8 *)&clock_info_array->clockInfo[0] +
5568 (clock_array_index * clock_info_array->ucEntrySize));
5569 ci_parse_pplib_clock_info(rdev,
5570 &rdev->pm.dpm.ps[i], k,
5571 clock_info);
5572 k++;
5573 }
5574 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
5575 }
5576 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
5577
5578 /* fill in the vce power states */
5579 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
5580 u32 sclk, mclk;
5581 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
5582 clock_info = (union pplib_clock_info *)
5583 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
5584 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5585 sclk |= clock_info->ci.ucEngineClockHigh << 16;
5586 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5587 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5588 rdev->pm.dpm.vce_states[i].sclk = sclk;
5589 rdev->pm.dpm.vce_states[i].mclk = mclk;
5590 }
5591
5592 return 0;
5593 }
5594
5595 static int ci_get_vbios_boot_values(struct radeon_device *rdev,
5596 struct ci_vbios_boot_state *boot_state)
5597 {
5598 struct radeon_mode_info *mode_info = &rdev->mode_info;
5599 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5600 ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
5601 u8 frev, crev;
5602 u16 data_offset;
5603
5604 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
5605 &frev, &crev, &data_offset)) {
5606 firmware_info =
5607 (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
5608 data_offset);
5609 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
5610 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
5611 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
5612 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev);
5613 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev);
5614 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
5615 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
5616
5617 return 0;
5618 }
5619 return -EINVAL;
5620 }
5621
5622 void ci_dpm_fini(struct radeon_device *rdev)
5623 {
5624 int i;
5625
5626 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
5627 kfree(rdev->pm.dpm.ps[i].ps_priv);
5628 }
5629 kfree(rdev->pm.dpm.ps);
5630 kfree(rdev->pm.dpm.priv);
5631 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5632 r600_free_extended_power_table(rdev);
5633 }
5634
5635 int ci_dpm_init(struct radeon_device *rdev)
5636 {
5637 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
5638 SMU7_Discrete_DpmTable *dpm_table;
5639 struct radeon_gpio_rec gpio;
5640 u16 data_offset, size;
5641 u8 frev, crev;
5642 struct ci_power_info *pi;
5643 int ret;
5644 u32 mask;
5645
5646 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5647 if (pi == NULL)
5648 return -ENOMEM;
5649 rdev->pm.dpm.priv = pi;
5650
5651 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
5652 if (ret)
5653 pi->sys_pcie_mask = 0;
5654 else
5655 pi->sys_pcie_mask = mask;
5656 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5657
5658 pi->pcie_gen_performance.max = RADEON_PCIE_GEN1;
5659 pi->pcie_gen_performance.min = RADEON_PCIE_GEN3;
5660 pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1;
5661 pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3;
5662
5663 pi->pcie_lane_performance.max = 0;
5664 pi->pcie_lane_performance.min = 16;
5665 pi->pcie_lane_powersaving.max = 0;
5666 pi->pcie_lane_powersaving.min = 16;
5667
5668 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state);
5669 if (ret) {
5670 ci_dpm_fini(rdev);
5671 return ret;
5672 }
5673
5674 ret = r600_get_platform_caps(rdev);
5675 if (ret) {
5676 ci_dpm_fini(rdev);
5677 return ret;
5678 }
5679
5680 ret = r600_parse_extended_power_table(rdev);
5681 if (ret) {
5682 ci_dpm_fini(rdev);
5683 return ret;
5684 }
5685
5686 ret = ci_parse_power_table(rdev);
5687 if (ret) {
5688 ci_dpm_fini(rdev);
5689 return ret;
5690 }
5691
5692 pi->dll_default_on = false;
5693 pi->sram_end = SMC_RAM_END;
5694
5695 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
5696 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
5697 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
5698 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
5699 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
5700 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
5701 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
5702 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
5703
5704 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
5705
5706 pi->sclk_dpm_key_disabled = 0;
5707 pi->mclk_dpm_key_disabled = 0;
5708 pi->pcie_dpm_key_disabled = 0;
5709 pi->thermal_sclk_dpm_enabled = 0;
5710
5711 /* mclk dpm is unstable on some R7 260X cards with the old mc ucode */
5712 if ((rdev->pdev->device == 0x6658) &&
5713 (rdev->mc_fw->size == (BONAIRE_MC_UCODE_SIZE * 4))) {
5714 pi->mclk_dpm_key_disabled = 1;
5715 }
5716
5717 pi->caps_sclk_ds = true;
5718
5719 pi->mclk_strobe_mode_threshold = 40000;
5720 pi->mclk_stutter_mode_threshold = 40000;
5721 pi->mclk_edc_enable_threshold = 40000;
5722 pi->mclk_edc_wr_enable_threshold = 40000;
5723
5724 ci_initialize_powertune_defaults(rdev);
5725
5726 pi->caps_fps = false;
5727
5728 pi->caps_sclk_throttle_low_notification = false;
5729
5730 pi->caps_uvd_dpm = true;
5731 pi->caps_vce_dpm = true;
5732
5733 ci_get_leakage_voltages(rdev);
5734 ci_patch_dependency_tables_with_leakage(rdev);
5735 ci_set_private_data_variables_based_on_pptable(rdev);
5736
5737 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5738 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
5739 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5740 ci_dpm_fini(rdev);
5741 return -ENOMEM;
5742 }
5743 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5744 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5745 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5746 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5747 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5748 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5749 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5750 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5751 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5752
5753 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5754 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5755 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5756
5757 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5758 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5759 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5760 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5761
5762 if (rdev->family == CHIP_HAWAII) {
5763 pi->thermal_temp_setting.temperature_low = 94500;
5764 pi->thermal_temp_setting.temperature_high = 95000;
5765 pi->thermal_temp_setting.temperature_shutdown = 104000;
5766 } else {
5767 pi->thermal_temp_setting.temperature_low = 99500;
5768 pi->thermal_temp_setting.temperature_high = 100000;
5769 pi->thermal_temp_setting.temperature_shutdown = 104000;
5770 }
5771
5772 pi->uvd_enabled = false;
5773
5774 dpm_table = &pi->smc_state_table;
5775
5776 gpio = radeon_atombios_lookup_gpio(rdev, VDDC_VRHOT_GPIO_PINID);
5777 if (gpio.valid) {
5778 dpm_table->VRHotGpio = gpio.shift;
5779 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5780 } else {
5781 dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN;
5782 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5783 }
5784
5785 gpio = radeon_atombios_lookup_gpio(rdev, PP_AC_DC_SWITCH_GPIO_PINID);
5786 if (gpio.valid) {
5787 dpm_table->AcDcGpio = gpio.shift;
5788 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5789 } else {
5790 dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN;
5791 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5792 }
5793
5794 gpio = radeon_atombios_lookup_gpio(rdev, VDDC_PCC_GPIO_PINID);
5795 if (gpio.valid) {
5796 u32 tmp = RREG32_SMC(CNB_PWRMGT_CNTL);
5797
5798 switch (gpio.shift) {
5799 case 0:
5800 tmp &= ~GNB_SLOW_MODE_MASK;
5801 tmp |= GNB_SLOW_MODE(1);
5802 break;
5803 case 1:
5804 tmp &= ~GNB_SLOW_MODE_MASK;
5805 tmp |= GNB_SLOW_MODE(2);
5806 break;
5807 case 2:
5808 tmp |= GNB_SLOW;
5809 break;
5810 case 3:
5811 tmp |= FORCE_NB_PS1;
5812 break;
5813 case 4:
5814 tmp |= DPM_ENABLED;
5815 break;
5816 default:
5817 DRM_ERROR("Invalid PCC GPIO: %u!\n", gpio.shift);
5818 break;
5819 }
5820 WREG32_SMC(CNB_PWRMGT_CNTL, tmp);
5821 }
5822
5823 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5824 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5825 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5826 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
5827 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5828 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
5829 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5830
5831 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
5832 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
5833 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5834 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
5835 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5836 else
5837 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
5838 }
5839
5840 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
5841 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
5842 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5843 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
5844 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5845 else
5846 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
5847 }
5848
5849 pi->vddc_phase_shed_control = true;
5850
5851 #if defined(CONFIG_ACPI)
5852 pi->pcie_performance_request =
5853 radeon_acpi_is_pcie_performance_request_supported(rdev);
5854 #else
5855 pi->pcie_performance_request = false;
5856 #endif
5857
5858 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
5859 &frev, &crev, &data_offset)) {
5860 pi->caps_sclk_ss_support = true;
5861 pi->caps_mclk_ss_support = true;
5862 pi->dynamic_ss = true;
5863 } else {
5864 pi->caps_sclk_ss_support = false;
5865 pi->caps_mclk_ss_support = false;
5866 pi->dynamic_ss = true;
5867 }
5868
5869 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
5870 pi->thermal_protection = true;
5871 else
5872 pi->thermal_protection = false;
5873
5874 pi->caps_dynamic_ac_timing = true;
5875
5876 pi->uvd_power_gated = false;
5877
5878 /* make sure dc limits are valid */
5879 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
5880 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
5881 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
5882 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
5883
5884 pi->fan_ctrl_is_in_default_mode = true;
5885
5886 return 0;
5887 }
5888
5889 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
5890 struct seq_file *m)
5891 {
5892 struct ci_power_info *pi = ci_get_pi(rdev);
5893 struct radeon_ps *rps = &pi->current_rps;
5894 u32 sclk = ci_get_average_sclk_freq(rdev);
5895 u32 mclk = ci_get_average_mclk_freq(rdev);
5896
5897 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis");
5898 seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis");
5899 seq_printf(m, "power level avg sclk: %u mclk: %u\n",
5900 sclk, mclk);
5901 }
5902
5903 void ci_dpm_print_power_state(struct radeon_device *rdev,
5904 struct radeon_ps *rps)
5905 {
5906 struct ci_ps *ps = ci_get_ps(rps);
5907 struct ci_pl *pl;
5908 int i;
5909
5910 r600_dpm_print_class_info(rps->class, rps->class2);
5911 r600_dpm_print_cap_info(rps->caps);
5912 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
5913 for (i = 0; i < ps->performance_level_count; i++) {
5914 pl = &ps->performance_levels[i];
5915 printk("\t\tpower level %d sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
5916 i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
5917 }
5918 r600_dpm_print_ps_status(rdev, rps);
5919 }
5920
5921 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low)
5922 {
5923 struct ci_power_info *pi = ci_get_pi(rdev);
5924 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5925
5926 if (low)
5927 return requested_state->performance_levels[0].sclk;
5928 else
5929 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
5930 }
5931
5932 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low)
5933 {
5934 struct ci_power_info *pi = ci_get_pi(rdev);
5935 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5936
5937 if (low)
5938 return requested_state->performance_levels[0].mclk;
5939 else
5940 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
5941 }
Linux kernel - Deliverables
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