2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
27 #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001
29 #define CIK_RB_BITMAP_WIDTH_PER_SH 2
31 /* SMC IND registers */
32 #define GENERAL_PWRMGT 0xC0200000
33 # define GPU_COUNTER_CLK (1 << 15)
35 #define MPLL_BYPASSCLK_SEL 0xC050019C
36 # define MPLL_CLKOUT_SEL(x) ((x) << 8)
37 # define MPLL_CLKOUT_SEL_MASK 0xFF00
38 #define CG_CLKPIN_CNTL 0xC05001A0
39 # define XTALIN_DIVIDE (1 << 1)
40 # define BCLK_AS_XCLK (1 << 2)
41 #define CG_CLKPIN_CNTL_2 0xC05001A4
42 # define FORCE_BIF_REFCLK_EN (1 << 3)
43 # define MUX_TCLK_TO_XCLK (1 << 8)
44 #define THM_CLK_CNTL 0xC05001A8
45 # define CMON_CLK_SEL(x) ((x) << 0)
46 # define CMON_CLK_SEL_MASK 0xFF
47 # define TMON_CLK_SEL(x) ((x) << 8)
48 # define TMON_CLK_SEL_MASK 0xFF00
49 #define MISC_CLK_CTRL 0xC05001AC
50 # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0)
51 # define DEEP_SLEEP_CLK_SEL_MASK 0xFF
52 # define ZCLK_SEL(x) ((x) << 8)
53 # define ZCLK_SEL_MASK 0xFF00
55 /* PCIE registers idx/data 0x38/0x3c */
56 #define PB0_PIF_PWRDOWN_0 0x1100012 /* PCIE */
57 # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7)
58 # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7)
59 # define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7
60 # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10)
61 # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10)
62 # define PLL_POWER_STATE_IN_OFF_0_SHIFT 10
63 # define PLL_RAMP_UP_TIME_0(x) ((x) << 24)
64 # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24)
65 # define PLL_RAMP_UP_TIME_0_SHIFT 24
66 #define PB0_PIF_PWRDOWN_1 0x1100013 /* PCIE */
67 # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7)
68 # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7)
69 # define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7
70 # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10)
71 # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10)
72 # define PLL_POWER_STATE_IN_OFF_1_SHIFT 10
73 # define PLL_RAMP_UP_TIME_1(x) ((x) << 24)
74 # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24)
75 # define PLL_RAMP_UP_TIME_1_SHIFT 24
77 #define PCIE_CNTL2 0x1001001c /* PCIE */
78 # define SLV_MEM_LS_EN (1 << 16)
79 # define MST_MEM_LS_EN (1 << 18)
80 # define REPLAY_MEM_LS_EN (1 << 19)
82 #define PCIE_LC_STATUS1 0x1400028 /* PCIE */
83 # define LC_REVERSE_RCVR (1 << 0)
84 # define LC_REVERSE_XMIT (1 << 1)
85 # define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2)
86 # define LC_OPERATING_LINK_WIDTH_SHIFT 2
87 # define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5)
88 # define LC_DETECTED_LINK_WIDTH_SHIFT 5
90 #define PCIE_P_CNTL 0x1400040 /* PCIE */
91 # define P_IGNORE_EDB_ERR (1 << 6)
93 #define PB1_PIF_PWRDOWN_0 0x2100012 /* PCIE */
94 #define PB1_PIF_PWRDOWN_1 0x2100013 /* PCIE */
96 #define PCIE_LC_CNTL 0x100100A0 /* PCIE */
97 # define LC_L0S_INACTIVITY(x) ((x) << 8)
98 # define LC_L0S_INACTIVITY_MASK (0xf << 8)
99 # define LC_L0S_INACTIVITY_SHIFT 8
100 # define LC_L1_INACTIVITY(x) ((x) << 12)
101 # define LC_L1_INACTIVITY_MASK (0xf << 12)
102 # define LC_L1_INACTIVITY_SHIFT 12
103 # define LC_PMI_TO_L1_DIS (1 << 16)
104 # define LC_ASPM_TO_L1_DIS (1 << 24)
106 #define PCIE_LC_LINK_WIDTH_CNTL 0x100100A2 /* PCIE */
107 # define LC_LINK_WIDTH_SHIFT 0
108 # define LC_LINK_WIDTH_MASK 0x7
109 # define LC_LINK_WIDTH_X0 0
110 # define LC_LINK_WIDTH_X1 1
111 # define LC_LINK_WIDTH_X2 2
112 # define LC_LINK_WIDTH_X4 3
113 # define LC_LINK_WIDTH_X8 4
114 # define LC_LINK_WIDTH_X16 6
115 # define LC_LINK_WIDTH_RD_SHIFT 4
116 # define LC_LINK_WIDTH_RD_MASK 0x70
117 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
118 # define LC_RECONFIG_NOW (1 << 8)
119 # define LC_RENEGOTIATION_SUPPORT (1 << 9)
120 # define LC_RENEGOTIATE_EN (1 << 10)
121 # define LC_SHORT_RECONFIG_EN (1 << 11)
122 # define LC_UPCONFIGURE_SUPPORT (1 << 12)
123 # define LC_UPCONFIGURE_DIS (1 << 13)
124 # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21)
125 # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21)
126 # define LC_DYN_LANES_PWR_STATE_SHIFT 21
127 #define PCIE_LC_N_FTS_CNTL 0x100100a3 /* PCIE */
128 # define LC_XMIT_N_FTS(x) ((x) << 0)
129 # define LC_XMIT_N_FTS_MASK (0xff << 0)
130 # define LC_XMIT_N_FTS_SHIFT 0
131 # define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8)
132 # define LC_N_FTS_MASK (0xff << 24)
133 #define PCIE_LC_SPEED_CNTL 0x100100A4 /* PCIE */
134 # define LC_GEN2_EN_STRAP (1 << 0)
135 # define LC_GEN3_EN_STRAP (1 << 1)
136 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2)
137 # define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3)
138 # define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3
139 # define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5)
140 # define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6)
141 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7)
142 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8)
143 # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9)
144 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10)
145 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10
146 # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */
147 # define LC_CURRENT_DATA_RATE_SHIFT 13
148 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16)
149 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18)
150 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19)
151 # define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20)
152 # define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21)
154 #define PCIE_LC_CNTL2 0x100100B1 /* PCIE */
155 # define LC_ALLOW_PDWN_IN_L1 (1 << 17)
156 # define LC_ALLOW_PDWN_IN_L23 (1 << 18)
158 #define PCIE_LC_CNTL3 0x100100B5 /* PCIE */
159 # define LC_GO_TO_RECOVERY (1 << 30)
160 #define PCIE_LC_CNTL4 0x100100B6 /* PCIE */
161 # define LC_REDO_EQ (1 << 5)
162 # define LC_SET_QUIESCE (1 << 13)
164 /* direct registers */
165 #define PCIE_INDEX 0x38
166 #define PCIE_DATA 0x3C
168 #define VGA_HDP_CONTROL 0x328
169 #define VGA_MEMORY_DISABLE (1 << 4)
171 #define DMIF_ADDR_CALC 0xC00
173 #define SRBM_GFX_CNTL 0xE44
174 #define PIPEID(x) ((x) << 0)
175 #define MEID(x) ((x) << 2)
176 #define VMID(x) ((x) << 4)
177 #define QUEUEID(x) ((x) << 8)
179 #define SRBM_STATUS2 0xE4C
180 #define SDMA_BUSY (1 << 5)
181 #define SDMA1_BUSY (1 << 6)
182 #define SRBM_STATUS 0xE50
183 #define UVD_RQ_PENDING (1 << 1)
184 #define GRBM_RQ_PENDING (1 << 5)
185 #define VMC_BUSY (1 << 8)
186 #define MCB_BUSY (1 << 9)
187 #define MCB_NON_DISPLAY_BUSY (1 << 10)
188 #define MCC_BUSY (1 << 11)
189 #define MCD_BUSY (1 << 12)
190 #define SEM_BUSY (1 << 14)
191 #define IH_BUSY (1 << 17)
192 #define UVD_BUSY (1 << 19)
194 #define SRBM_SOFT_RESET 0xE60
195 #define SOFT_RESET_BIF (1 << 1)
196 #define SOFT_RESET_R0PLL (1 << 4)
197 #define SOFT_RESET_DC (1 << 5)
198 #define SOFT_RESET_SDMA1 (1 << 6)
199 #define SOFT_RESET_GRBM (1 << 8)
200 #define SOFT_RESET_HDP (1 << 9)
201 #define SOFT_RESET_IH (1 << 10)
202 #define SOFT_RESET_MC (1 << 11)
203 #define SOFT_RESET_ROM (1 << 14)
204 #define SOFT_RESET_SEM (1 << 15)
205 #define SOFT_RESET_VMC (1 << 17)
206 #define SOFT_RESET_SDMA (1 << 20)
207 #define SOFT_RESET_TST (1 << 21)
208 #define SOFT_RESET_REGBB (1 << 22)
209 #define SOFT_RESET_ORB (1 << 23)
210 #define SOFT_RESET_VCE (1 << 24)
212 #define VM_L2_CNTL 0x1400
213 #define ENABLE_L2_CACHE (1 << 0)
214 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
215 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2)
216 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4)
217 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
218 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
219 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15)
220 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19)
221 #define VM_L2_CNTL2 0x1404
222 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
223 #define INVALIDATE_L2_CACHE (1 << 1)
224 #define INVALIDATE_CACHE_MODE(x) ((x) << 26)
225 #define INVALIDATE_PTE_AND_PDE_CACHES 0
226 #define INVALIDATE_ONLY_PTE_CACHES 1
227 #define INVALIDATE_ONLY_PDE_CACHES 2
228 #define VM_L2_CNTL3 0x1408
229 #define BANK_SELECT(x) ((x) << 0)
230 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6)
231 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)
232 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
233 #define VM_L2_STATUS 0x140C
234 #define L2_BUSY (1 << 0)
235 #define VM_CONTEXT0_CNTL 0x1410
236 #define ENABLE_CONTEXT (1 << 0)
237 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
238 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)
239 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
240 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)
241 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)
242 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)
243 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)
244 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)
245 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)
246 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)
247 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)
248 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)
249 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)
250 #define VM_CONTEXT1_CNTL 0x1414
251 #define VM_CONTEXT0_CNTL2 0x1430
252 #define VM_CONTEXT1_CNTL2 0x1434
253 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438
254 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c
255 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440
256 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444
257 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448
258 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c
259 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450
260 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454
262 #define VM_INVALIDATE_REQUEST 0x1478
263 #define VM_INVALIDATE_RESPONSE 0x147c
265 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC
266 #define PROTECTIONS_MASK (0xf << 0)
267 #define PROTECTIONS_SHIFT 0
274 #define MEMORY_CLIENT_ID_MASK (0xff << 12)
275 #define MEMORY_CLIENT_ID_SHIFT 12
276 #define MEMORY_CLIENT_RW_MASK (1 << 24)
277 #define MEMORY_CLIENT_RW_SHIFT 24
278 #define FAULT_VMID_MASK (0xf << 25)
279 #define FAULT_VMID_SHIFT 25
281 #define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x14E4
283 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC
285 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
286 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
288 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
289 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540
290 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544
291 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548
292 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c
293 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550
294 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554
295 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558
296 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
297 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560
299 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
300 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580
302 #define VM_L2_CG 0x15c0
303 #define MC_CG_ENABLE (1 << 18)
304 #define MC_LS_ENABLE (1 << 19)
306 #define MC_SHARED_CHMAP 0x2004
307 #define NOOFCHAN_SHIFT 12
308 #define NOOFCHAN_MASK 0x0000f000
309 #define MC_SHARED_CHREMAP 0x2008
311 #define CHUB_CONTROL 0x1864
312 #define BYPASS_VM (1 << 0)
314 #define MC_VM_FB_LOCATION 0x2024
315 #define MC_VM_AGP_TOP 0x2028
316 #define MC_VM_AGP_BOT 0x202C
317 #define MC_VM_AGP_BASE 0x2030
318 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
319 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
320 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
322 #define MC_VM_MX_L1_TLB_CNTL 0x2064
323 #define ENABLE_L1_TLB (1 << 0)
324 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
325 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
326 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
327 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
328 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
329 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
330 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
331 #define MC_VM_FB_OFFSET 0x2068
333 #define MC_SHARED_BLACKOUT_CNTL 0x20ac
335 #define MC_HUB_MISC_HUB_CG 0x20b8
336 #define MC_HUB_MISC_VM_CG 0x20bc
338 #define MC_HUB_MISC_SIP_CG 0x20c0
340 #define MC_XPB_CLK_GAT 0x2478
342 #define MC_CITF_MISC_RD_CG 0x2648
343 #define MC_CITF_MISC_WR_CG 0x264c
344 #define MC_CITF_MISC_VM_CG 0x2650
346 #define MC_ARB_RAMCFG 0x2760
347 #define NOOFBANK_SHIFT 0
348 #define NOOFBANK_MASK 0x00000003
349 #define NOOFRANK_SHIFT 2
350 #define NOOFRANK_MASK 0x00000004
351 #define NOOFROWS_SHIFT 3
352 #define NOOFROWS_MASK 0x00000038
353 #define NOOFCOLS_SHIFT 6
354 #define NOOFCOLS_MASK 0x000000C0
355 #define CHANSIZE_SHIFT 8
356 #define CHANSIZE_MASK 0x00000100
357 #define NOOFGROUPS_SHIFT 12
358 #define NOOFGROUPS_MASK 0x00001000
360 #define MC_SEQ_SUP_CNTL 0x28c8
361 #define RUN_MASK (1 << 0)
362 #define MC_SEQ_SUP_PGM 0x28cc
364 #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8
365 #define TRAIN_DONE_D0 (1 << 30)
366 #define TRAIN_DONE_D1 (1 << 31)
368 #define MC_IO_PAD_CNTL_D0 0x29d0
369 #define MEM_FALL_OUT_CMD (1 << 8)
371 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44
372 #define MC_SEQ_IO_DEBUG_DATA 0x2a48
374 #define HDP_HOST_PATH_CNTL 0x2C00
375 #define CLOCK_GATING_DIS (1 << 23)
376 #define HDP_NONSURFACE_BASE 0x2C04
377 #define HDP_NONSURFACE_INFO 0x2C08
378 #define HDP_NONSURFACE_SIZE 0x2C0C
380 #define HDP_ADDR_CONFIG 0x2F48
381 #define HDP_MISC_CNTL 0x2F4C
382 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
383 #define HDP_MEM_POWER_LS 0x2F50
384 #define HDP_LS_ENABLE (1 << 0)
386 #define ATC_MISC_CG 0x3350
388 #define IH_RB_CNTL 0x3e00
389 # define IH_RB_ENABLE (1 << 0)
390 # define IH_RB_SIZE(x) ((x) << 1) /* log2 */
391 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
392 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
393 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
394 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
395 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
396 #define IH_RB_BASE 0x3e04
397 #define IH_RB_RPTR 0x3e08
398 #define IH_RB_WPTR 0x3e0c
399 # define RB_OVERFLOW (1 << 0)
400 # define WPTR_OFFSET_MASK 0x3fffc
401 #define IH_RB_WPTR_ADDR_HI 0x3e10
402 #define IH_RB_WPTR_ADDR_LO 0x3e14
403 #define IH_CNTL 0x3e18
404 # define ENABLE_INTR (1 << 0)
405 # define IH_MC_SWAP(x) ((x) << 1)
406 # define IH_MC_SWAP_NONE 0
407 # define IH_MC_SWAP_16BIT 1
408 # define IH_MC_SWAP_32BIT 2
409 # define IH_MC_SWAP_64BIT 3
410 # define RPTR_REARM (1 << 4)
411 # define MC_WRREQ_CREDIT(x) ((x) << 15)
412 # define MC_WR_CLEAN_CNT(x) ((x) << 20)
413 # define MC_VMID(x) ((x) << 25)
415 #define CONFIG_MEMSIZE 0x5428
417 #define INTERRUPT_CNTL 0x5468
418 # define IH_DUMMY_RD_OVERRIDE (1 << 0)
419 # define IH_DUMMY_RD_EN (1 << 1)
420 # define IH_REQ_NONSNOOP_EN (1 << 3)
421 # define GEN_IH_INT_EN (1 << 8)
422 #define INTERRUPT_CNTL2 0x546c
424 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
426 #define BIF_FB_EN 0x5490
427 #define FB_READ_EN (1 << 0)
428 #define FB_WRITE_EN (1 << 1)
430 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
432 #define GPU_HDP_FLUSH_REQ 0x54DC
433 #define GPU_HDP_FLUSH_DONE 0x54E0
444 #define SDMA0 (1 << 10)
445 #define SDMA1 (1 << 11)
447 /* 0x6b04, 0x7704, 0x10304, 0x10f04, 0x11b04, 0x12704 */
448 #define LB_MEMORY_CTRL 0x6b04
449 #define LB_MEMORY_SIZE(x) ((x) << 0)
450 #define LB_MEMORY_CONFIG(x) ((x) << 20)
452 #define DPG_WATERMARK_MASK_CONTROL 0x6cc8
453 # define LATENCY_WATERMARK_MASK(x) ((x) << 8)
454 #define DPG_PIPE_LATENCY_CONTROL 0x6ccc
455 # define LATENCY_LOW_WATERMARK(x) ((x) << 0)
456 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
458 /* 0x6b24, 0x7724, 0x10324, 0x10f24, 0x11b24, 0x12724 */
459 #define LB_VLINE_STATUS 0x6b24
460 # define VLINE_OCCURRED (1 << 0)
461 # define VLINE_ACK (1 << 4)
462 # define VLINE_STAT (1 << 12)
463 # define VLINE_INTERRUPT (1 << 16)
464 # define VLINE_INTERRUPT_TYPE (1 << 17)
465 /* 0x6b2c, 0x772c, 0x1032c, 0x10f2c, 0x11b2c, 0x1272c */
466 #define LB_VBLANK_STATUS 0x6b2c
467 # define VBLANK_OCCURRED (1 << 0)
468 # define VBLANK_ACK (1 << 4)
469 # define VBLANK_STAT (1 << 12)
470 # define VBLANK_INTERRUPT (1 << 16)
471 # define VBLANK_INTERRUPT_TYPE (1 << 17)
473 /* 0x6b20, 0x7720, 0x10320, 0x10f20, 0x11b20, 0x12720 */
474 #define LB_INTERRUPT_MASK 0x6b20
475 # define VBLANK_INTERRUPT_MASK (1 << 0)
476 # define VLINE_INTERRUPT_MASK (1 << 4)
477 # define VLINE2_INTERRUPT_MASK (1 << 8)
479 #define DISP_INTERRUPT_STATUS 0x60f4
480 # define LB_D1_VLINE_INTERRUPT (1 << 2)
481 # define LB_D1_VBLANK_INTERRUPT (1 << 3)
482 # define DC_HPD1_INTERRUPT (1 << 17)
483 # define DC_HPD1_RX_INTERRUPT (1 << 18)
484 # define DACA_AUTODETECT_INTERRUPT (1 << 22)
485 # define DACB_AUTODETECT_INTERRUPT (1 << 23)
486 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
487 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
488 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
489 # define LB_D2_VLINE_INTERRUPT (1 << 2)
490 # define LB_D2_VBLANK_INTERRUPT (1 << 3)
491 # define DC_HPD2_INTERRUPT (1 << 17)
492 # define DC_HPD2_RX_INTERRUPT (1 << 18)
493 # define DISP_TIMER_INTERRUPT (1 << 24)
494 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
495 # define LB_D3_VLINE_INTERRUPT (1 << 2)
496 # define LB_D3_VBLANK_INTERRUPT (1 << 3)
497 # define DC_HPD3_INTERRUPT (1 << 17)
498 # define DC_HPD3_RX_INTERRUPT (1 << 18)
499 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
500 # define LB_D4_VLINE_INTERRUPT (1 << 2)
501 # define LB_D4_VBLANK_INTERRUPT (1 << 3)
502 # define DC_HPD4_INTERRUPT (1 << 17)
503 # define DC_HPD4_RX_INTERRUPT (1 << 18)
504 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
505 # define LB_D5_VLINE_INTERRUPT (1 << 2)
506 # define LB_D5_VBLANK_INTERRUPT (1 << 3)
507 # define DC_HPD5_INTERRUPT (1 << 17)
508 # define DC_HPD5_RX_INTERRUPT (1 << 18)
509 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150
510 # define LB_D6_VLINE_INTERRUPT (1 << 2)
511 # define LB_D6_VBLANK_INTERRUPT (1 << 3)
512 # define DC_HPD6_INTERRUPT (1 << 17)
513 # define DC_HPD6_RX_INTERRUPT (1 << 18)
514 #define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780
516 #define DAC_AUTODETECT_INT_CONTROL 0x67c8
518 #define DC_HPD1_INT_STATUS 0x601c
519 #define DC_HPD2_INT_STATUS 0x6028
520 #define DC_HPD3_INT_STATUS 0x6034
521 #define DC_HPD4_INT_STATUS 0x6040
522 #define DC_HPD5_INT_STATUS 0x604c
523 #define DC_HPD6_INT_STATUS 0x6058
524 # define DC_HPDx_INT_STATUS (1 << 0)
525 # define DC_HPDx_SENSE (1 << 1)
526 # define DC_HPDx_SENSE_DELAYED (1 << 4)
527 # define DC_HPDx_RX_INT_STATUS (1 << 8)
529 #define DC_HPD1_INT_CONTROL 0x6020
530 #define DC_HPD2_INT_CONTROL 0x602c
531 #define DC_HPD3_INT_CONTROL 0x6038
532 #define DC_HPD4_INT_CONTROL 0x6044
533 #define DC_HPD5_INT_CONTROL 0x6050
534 #define DC_HPD6_INT_CONTROL 0x605c
535 # define DC_HPDx_INT_ACK (1 << 0)
536 # define DC_HPDx_INT_POLARITY (1 << 8)
537 # define DC_HPDx_INT_EN (1 << 16)
538 # define DC_HPDx_RX_INT_ACK (1 << 20)
539 # define DC_HPDx_RX_INT_EN (1 << 24)
541 #define DC_HPD1_CONTROL 0x6024
542 #define DC_HPD2_CONTROL 0x6030
543 #define DC_HPD3_CONTROL 0x603c
544 #define DC_HPD4_CONTROL 0x6048
545 #define DC_HPD5_CONTROL 0x6054
546 #define DC_HPD6_CONTROL 0x6060
547 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
548 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
549 # define DC_HPDx_EN (1 << 28)
551 #define GRBM_CNTL 0x8000
552 #define GRBM_READ_TIMEOUT(x) ((x) << 0)
554 #define GRBM_STATUS2 0x8008
555 #define ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000F
556 #define ME0PIPE1_CF_RQ_PENDING (1 << 4)
557 #define ME0PIPE1_PF_RQ_PENDING (1 << 5)
558 #define ME1PIPE0_RQ_PENDING (1 << 6)
559 #define ME1PIPE1_RQ_PENDING (1 << 7)
560 #define ME1PIPE2_RQ_PENDING (1 << 8)
561 #define ME1PIPE3_RQ_PENDING (1 << 9)
562 #define ME2PIPE0_RQ_PENDING (1 << 10)
563 #define ME2PIPE1_RQ_PENDING (1 << 11)
564 #define ME2PIPE2_RQ_PENDING (1 << 12)
565 #define ME2PIPE3_RQ_PENDING (1 << 13)
566 #define RLC_RQ_PENDING (1 << 14)
567 #define RLC_BUSY (1 << 24)
568 #define TC_BUSY (1 << 25)
569 #define CPF_BUSY (1 << 28)
570 #define CPC_BUSY (1 << 29)
571 #define CPG_BUSY (1 << 30)
573 #define GRBM_STATUS 0x8010
574 #define ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000F
575 #define SRBM_RQ_PENDING (1 << 5)
576 #define ME0PIPE0_CF_RQ_PENDING (1 << 7)
577 #define ME0PIPE0_PF_RQ_PENDING (1 << 8)
578 #define GDS_DMA_RQ_PENDING (1 << 9)
579 #define DB_CLEAN (1 << 12)
580 #define CB_CLEAN (1 << 13)
581 #define TA_BUSY (1 << 14)
582 #define GDS_BUSY (1 << 15)
583 #define WD_BUSY_NO_DMA (1 << 16)
584 #define VGT_BUSY (1 << 17)
585 #define IA_BUSY_NO_DMA (1 << 18)
586 #define IA_BUSY (1 << 19)
587 #define SX_BUSY (1 << 20)
588 #define WD_BUSY (1 << 21)
589 #define SPI_BUSY (1 << 22)
590 #define BCI_BUSY (1 << 23)
591 #define SC_BUSY (1 << 24)
592 #define PA_BUSY (1 << 25)
593 #define DB_BUSY (1 << 26)
594 #define CP_COHERENCY_BUSY (1 << 28)
595 #define CP_BUSY (1 << 29)
596 #define CB_BUSY (1 << 30)
597 #define GUI_ACTIVE (1 << 31)
598 #define GRBM_STATUS_SE0 0x8014
599 #define GRBM_STATUS_SE1 0x8018
600 #define GRBM_STATUS_SE2 0x8038
601 #define GRBM_STATUS_SE3 0x803C
602 #define SE_DB_CLEAN (1 << 1)
603 #define SE_CB_CLEAN (1 << 2)
604 #define SE_BCI_BUSY (1 << 22)
605 #define SE_VGT_BUSY (1 << 23)
606 #define SE_PA_BUSY (1 << 24)
607 #define SE_TA_BUSY (1 << 25)
608 #define SE_SX_BUSY (1 << 26)
609 #define SE_SPI_BUSY (1 << 27)
610 #define SE_SC_BUSY (1 << 29)
611 #define SE_DB_BUSY (1 << 30)
612 #define SE_CB_BUSY (1 << 31)
614 #define GRBM_SOFT_RESET 0x8020
615 #define SOFT_RESET_CP (1 << 0) /* All CP blocks */
616 #define SOFT_RESET_RLC (1 << 2) /* RLC */
617 #define SOFT_RESET_GFX (1 << 16) /* GFX */
618 #define SOFT_RESET_CPF (1 << 17) /* CP fetcher shared by gfx and compute */
619 #define SOFT_RESET_CPC (1 << 18) /* CP Compute (MEC1/2) */
620 #define SOFT_RESET_CPG (1 << 19) /* CP GFX (PFP, ME, CE) */
622 #define GRBM_INT_CNTL 0x8060
623 # define RDERR_INT_ENABLE (1 << 0)
624 # define GUI_IDLE_INT_ENABLE (1 << 19)
626 #define CP_CPC_STATUS 0x8210
627 #define CP_CPC_BUSY_STAT 0x8214
628 #define CP_CPC_STALLED_STAT1 0x8218
629 #define CP_CPF_STATUS 0x821c
630 #define CP_CPF_BUSY_STAT 0x8220
631 #define CP_CPF_STALLED_STAT1 0x8224
633 #define CP_MEC_CNTL 0x8234
634 #define MEC_ME2_HALT (1 << 28)
635 #define MEC_ME1_HALT (1 << 30)
637 #define CP_MEC_CNTL 0x8234
638 #define MEC_ME2_HALT (1 << 28)
639 #define MEC_ME1_HALT (1 << 30)
641 #define CP_STALLED_STAT3 0x8670
642 #define CP_STALLED_STAT1 0x8674
643 #define CP_STALLED_STAT2 0x8678
645 #define CP_STAT 0x8680
647 #define CP_ME_CNTL 0x86D8
648 #define CP_CE_HALT (1 << 24)
649 #define CP_PFP_HALT (1 << 26)
650 #define CP_ME_HALT (1 << 28)
652 #define CP_RB0_RPTR 0x8700
653 #define CP_RB_WPTR_DELAY 0x8704
654 #define CP_RB_WPTR_POLL_CNTL 0x8708
655 #define IDLE_POLL_COUNT(x) ((x) << 16)
656 #define IDLE_POLL_COUNT_MASK (0xffff << 16)
658 #define CP_MEQ_THRESHOLDS 0x8764
659 #define MEQ1_START(x) ((x) << 0)
660 #define MEQ2_START(x) ((x) << 8)
662 #define VGT_VTX_VECT_EJECT_REG 0x88B0
664 #define VGT_CACHE_INVALIDATION 0x88C4
665 #define CACHE_INVALIDATION(x) ((x) << 0)
669 #define AUTO_INVLD_EN(x) ((x) << 6)
673 #define ES_AND_GS_AUTO 3
675 #define VGT_GS_VERTEX_REUSE 0x88D4
677 #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc
678 #define INACTIVE_CUS_MASK 0xFFFF0000
679 #define INACTIVE_CUS_SHIFT 16
680 #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0
682 #define PA_CL_ENHANCE 0x8A14
683 #define CLIP_VTX_REORDER_ENA (1 << 0)
684 #define NUM_CLIP_SEQ(x) ((x) << 1)
686 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
687 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
688 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
690 #define PA_SC_FIFO_SIZE 0x8BCC
691 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0)
692 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6)
693 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15)
694 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23)
696 #define PA_SC_ENHANCE 0x8BF0
697 #define ENABLE_PA_SC_OUT_OF_ORDER (1 << 0)
698 #define DISABLE_PA_SC_GUIDANCE (1 << 13)
700 #define SQ_CONFIG 0x8C00
702 #define SH_MEM_BASES 0x8C28
703 /* if PTR32, these are the bases for scratch and lds */
704 #define PRIVATE_BASE(x) ((x) << 0) /* scratch */
705 #define SHARED_BASE(x) ((x) << 16) /* LDS */
706 #define SH_MEM_APE1_BASE 0x8C2C
707 /* if PTR32, this is the base location of GPUVM */
708 #define SH_MEM_APE1_LIMIT 0x8C30
709 /* if PTR32, this is the upper limit of GPUVM */
710 #define SH_MEM_CONFIG 0x8C34
711 #define PTR32 (1 << 0)
712 #define ALIGNMENT_MODE(x) ((x) << 2)
713 #define SH_MEM_ALIGNMENT_MODE_DWORD 0
714 #define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1
715 #define SH_MEM_ALIGNMENT_MODE_STRICT 2
716 #define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3
717 #define DEFAULT_MTYPE(x) ((x) << 4)
718 #define APE1_MTYPE(x) ((x) << 7)
720 #define SX_DEBUG_1 0x9060
722 #define SPI_CONFIG_CNTL 0x9100
724 #define SPI_CONFIG_CNTL_1 0x913C
725 #define VTX_DONE_DELAY(x) ((x) << 0)
726 #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
728 #define TA_CNTL_AUX 0x9508
730 #define DB_DEBUG 0x9830
731 #define DB_DEBUG2 0x9834
732 #define DB_DEBUG3 0x9838
734 #define CC_RB_BACKEND_DISABLE 0x98F4
735 #define BACKEND_DISABLE(x) ((x) << 16)
736 #define GB_ADDR_CONFIG 0x98F8
737 #define NUM_PIPES(x) ((x) << 0)
738 #define NUM_PIPES_MASK 0x00000007
739 #define NUM_PIPES_SHIFT 0
740 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
741 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
742 #define PIPE_INTERLEAVE_SIZE_SHIFT 4
743 #define NUM_SHADER_ENGINES(x) ((x) << 12)
744 #define NUM_SHADER_ENGINES_MASK 0x00003000
745 #define NUM_SHADER_ENGINES_SHIFT 12
746 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
747 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
748 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16
749 #define ROW_SIZE(x) ((x) << 28)
750 #define ROW_SIZE_MASK 0x30000000
751 #define ROW_SIZE_SHIFT 28
753 #define GB_TILE_MODE0 0x9910
754 # define ARRAY_MODE(x) ((x) << 2)
755 # define ARRAY_LINEAR_GENERAL 0
756 # define ARRAY_LINEAR_ALIGNED 1
757 # define ARRAY_1D_TILED_THIN1 2
758 # define ARRAY_2D_TILED_THIN1 4
759 # define ARRAY_PRT_TILED_THIN1 5
760 # define ARRAY_PRT_2D_TILED_THIN1 6
761 # define PIPE_CONFIG(x) ((x) << 6)
762 # define ADDR_SURF_P2 0
763 # define ADDR_SURF_P4_8x16 4
764 # define ADDR_SURF_P4_16x16 5
765 # define ADDR_SURF_P4_16x32 6
766 # define ADDR_SURF_P4_32x32 7
767 # define ADDR_SURF_P8_16x16_8x16 8
768 # define ADDR_SURF_P8_16x32_8x16 9
769 # define ADDR_SURF_P8_32x32_8x16 10
770 # define ADDR_SURF_P8_16x32_16x16 11
771 # define ADDR_SURF_P8_32x32_16x16 12
772 # define ADDR_SURF_P8_32x32_16x32 13
773 # define ADDR_SURF_P8_32x64_32x32 14
774 # define TILE_SPLIT(x) ((x) << 11)
775 # define ADDR_SURF_TILE_SPLIT_64B 0
776 # define ADDR_SURF_TILE_SPLIT_128B 1
777 # define ADDR_SURF_TILE_SPLIT_256B 2
778 # define ADDR_SURF_TILE_SPLIT_512B 3
779 # define ADDR_SURF_TILE_SPLIT_1KB 4
780 # define ADDR_SURF_TILE_SPLIT_2KB 5
781 # define ADDR_SURF_TILE_SPLIT_4KB 6
782 # define MICRO_TILE_MODE_NEW(x) ((x) << 22)
783 # define ADDR_SURF_DISPLAY_MICRO_TILING 0
784 # define ADDR_SURF_THIN_MICRO_TILING 1
785 # define ADDR_SURF_DEPTH_MICRO_TILING 2
786 # define ADDR_SURF_ROTATED_MICRO_TILING 3
787 # define SAMPLE_SPLIT(x) ((x) << 25)
788 # define ADDR_SURF_SAMPLE_SPLIT_1 0
789 # define ADDR_SURF_SAMPLE_SPLIT_2 1
790 # define ADDR_SURF_SAMPLE_SPLIT_4 2
791 # define ADDR_SURF_SAMPLE_SPLIT_8 3
793 #define GB_MACROTILE_MODE0 0x9990
794 # define BANK_WIDTH(x) ((x) << 0)
795 # define ADDR_SURF_BANK_WIDTH_1 0
796 # define ADDR_SURF_BANK_WIDTH_2 1
797 # define ADDR_SURF_BANK_WIDTH_4 2
798 # define ADDR_SURF_BANK_WIDTH_8 3
799 # define BANK_HEIGHT(x) ((x) << 2)
800 # define ADDR_SURF_BANK_HEIGHT_1 0
801 # define ADDR_SURF_BANK_HEIGHT_2 1
802 # define ADDR_SURF_BANK_HEIGHT_4 2
803 # define ADDR_SURF_BANK_HEIGHT_8 3
804 # define MACRO_TILE_ASPECT(x) ((x) << 4)
805 # define ADDR_SURF_MACRO_ASPECT_1 0
806 # define ADDR_SURF_MACRO_ASPECT_2 1
807 # define ADDR_SURF_MACRO_ASPECT_4 2
808 # define ADDR_SURF_MACRO_ASPECT_8 3
809 # define NUM_BANKS(x) ((x) << 6)
810 # define ADDR_SURF_2_BANK 0
811 # define ADDR_SURF_4_BANK 1
812 # define ADDR_SURF_8_BANK 2
813 # define ADDR_SURF_16_BANK 3
815 #define CB_HW_CONTROL 0x9A10
817 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C
818 #define BACKEND_DISABLE_MASK 0x00FF0000
819 #define BACKEND_DISABLE_SHIFT 16
821 #define TCP_CHAN_STEER_LO 0xac0c
822 #define TCP_CHAN_STEER_HI 0xac10
824 #define TC_CFG_L1_LOAD_POLICY0 0xAC68
825 #define TC_CFG_L1_LOAD_POLICY1 0xAC6C
826 #define TC_CFG_L1_STORE_POLICY 0xAC70
827 #define TC_CFG_L2_LOAD_POLICY0 0xAC74
828 #define TC_CFG_L2_LOAD_POLICY1 0xAC78
829 #define TC_CFG_L2_STORE_POLICY0 0xAC7C
830 #define TC_CFG_L2_STORE_POLICY1 0xAC80
831 #define TC_CFG_L2_ATOMIC_POLICY 0xAC84
832 #define TC_CFG_L1_VOLATILE 0xAC88
833 #define TC_CFG_L2_VOLATILE 0xAC8C
835 #define CP_RB0_BASE 0xC100
836 #define CP_RB0_CNTL 0xC104
837 #define RB_BUFSZ(x) ((x) << 0)
838 #define RB_BLKSZ(x) ((x) << 8)
839 #define BUF_SWAP_32BIT (2 << 16)
840 #define RB_NO_UPDATE (1 << 27)
841 #define RB_RPTR_WR_ENA (1 << 31)
843 #define CP_RB0_RPTR_ADDR 0xC10C
844 #define RB_RPTR_SWAP_32BIT (2 << 0)
845 #define CP_RB0_RPTR_ADDR_HI 0xC110
846 #define CP_RB0_WPTR 0xC114
848 #define CP_DEVICE_ID 0xC12C
849 #define CP_ENDIAN_SWAP 0xC140
850 #define CP_RB_VMID 0xC144
852 #define CP_PFP_UCODE_ADDR 0xC150
853 #define CP_PFP_UCODE_DATA 0xC154
854 #define CP_ME_RAM_RADDR 0xC158
855 #define CP_ME_RAM_WADDR 0xC15C
856 #define CP_ME_RAM_DATA 0xC160
858 #define CP_CE_UCODE_ADDR 0xC168
859 #define CP_CE_UCODE_DATA 0xC16C
860 #define CP_MEC_ME1_UCODE_ADDR 0xC170
861 #define CP_MEC_ME1_UCODE_DATA 0xC174
862 #define CP_MEC_ME2_UCODE_ADDR 0xC178
863 #define CP_MEC_ME2_UCODE_DATA 0xC17C
865 #define CP_INT_CNTL_RING0 0xC1A8
866 # define CNTX_BUSY_INT_ENABLE (1 << 19)
867 # define CNTX_EMPTY_INT_ENABLE (1 << 20)
868 # define PRIV_INSTR_INT_ENABLE (1 << 22)
869 # define PRIV_REG_INT_ENABLE (1 << 23)
870 # define TIME_STAMP_INT_ENABLE (1 << 26)
871 # define CP_RINGID2_INT_ENABLE (1 << 29)
872 # define CP_RINGID1_INT_ENABLE (1 << 30)
873 # define CP_RINGID0_INT_ENABLE (1 << 31)
875 #define CP_INT_STATUS_RING0 0xC1B4
876 # define PRIV_INSTR_INT_STAT (1 << 22)
877 # define PRIV_REG_INT_STAT (1 << 23)
878 # define TIME_STAMP_INT_STAT (1 << 26)
879 # define CP_RINGID2_INT_STAT (1 << 29)
880 # define CP_RINGID1_INT_STAT (1 << 30)
881 # define CP_RINGID0_INT_STAT (1 << 31)
883 #define CP_MEM_SLP_CNTL 0xC1E4
884 # define CP_MEM_LS_EN (1 << 0)
886 #define CP_CPF_DEBUG 0xC200
888 #define CP_PQ_WPTR_POLL_CNTL 0xC20C
889 #define WPTR_POLL_EN (1 << 31)
891 #define CP_ME1_PIPE0_INT_CNTL 0xC214
892 #define CP_ME1_PIPE1_INT_CNTL 0xC218
893 #define CP_ME1_PIPE2_INT_CNTL 0xC21C
894 #define CP_ME1_PIPE3_INT_CNTL 0xC220
895 #define CP_ME2_PIPE0_INT_CNTL 0xC224
896 #define CP_ME2_PIPE1_INT_CNTL 0xC228
897 #define CP_ME2_PIPE2_INT_CNTL 0xC22C
898 #define CP_ME2_PIPE3_INT_CNTL 0xC230
899 # define DEQUEUE_REQUEST_INT_ENABLE (1 << 13)
900 # define WRM_POLL_TIMEOUT_INT_ENABLE (1 << 17)
901 # define PRIV_REG_INT_ENABLE (1 << 23)
902 # define TIME_STAMP_INT_ENABLE (1 << 26)
903 # define GENERIC2_INT_ENABLE (1 << 29)
904 # define GENERIC1_INT_ENABLE (1 << 30)
905 # define GENERIC0_INT_ENABLE (1 << 31)
906 #define CP_ME1_PIPE0_INT_STATUS 0xC214
907 #define CP_ME1_PIPE1_INT_STATUS 0xC218
908 #define CP_ME1_PIPE2_INT_STATUS 0xC21C
909 #define CP_ME1_PIPE3_INT_STATUS 0xC220
910 #define CP_ME2_PIPE0_INT_STATUS 0xC224
911 #define CP_ME2_PIPE1_INT_STATUS 0xC228
912 #define CP_ME2_PIPE2_INT_STATUS 0xC22C
913 #define CP_ME2_PIPE3_INT_STATUS 0xC230
914 # define DEQUEUE_REQUEST_INT_STATUS (1 << 13)
915 # define WRM_POLL_TIMEOUT_INT_STATUS (1 << 17)
916 # define PRIV_REG_INT_STATUS (1 << 23)
917 # define TIME_STAMP_INT_STATUS (1 << 26)
918 # define GENERIC2_INT_STATUS (1 << 29)
919 # define GENERIC1_INT_STATUS (1 << 30)
920 # define GENERIC0_INT_STATUS (1 << 31)
922 #define CP_MAX_CONTEXT 0xC2B8
924 #define CP_RB0_BASE_HI 0xC2C4
926 #define RLC_CNTL 0xC300
927 # define RLC_ENABLE (1 << 0)
929 #define RLC_MC_CNTL 0xC30C
931 #define RLC_MEM_SLP_CNTL 0xC318
932 # define RLC_MEM_LS_EN (1 << 0)
934 #define RLC_LB_CNTR_MAX 0xC348
936 #define RLC_LB_CNTL 0xC364
937 # define LOAD_BALANCE_ENABLE (1 << 0)
939 #define RLC_LB_CNTR_INIT 0xC36C
941 #define RLC_SAVE_AND_RESTORE_BASE 0xC374
942 #define RLC_DRIVER_DMA_STATUS 0xC378 /* dGPU */
943 #define RLC_CP_TABLE_RESTORE 0xC378 /* APU */
944 #define RLC_PG_DELAY_2 0xC37C
946 #define RLC_GPM_UCODE_ADDR 0xC388
947 #define RLC_GPM_UCODE_DATA 0xC38C
948 #define RLC_GPU_CLOCK_COUNT_LSB 0xC390
949 #define RLC_GPU_CLOCK_COUNT_MSB 0xC394
950 #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC398
951 #define RLC_UCODE_CNTL 0xC39C
953 #define RLC_GPM_STAT 0xC400
954 # define RLC_GPM_BUSY (1 << 0)
956 #define RLC_PG_CNTL 0xC40C
957 # define GFX_PG_ENABLE (1 << 0)
958 # define GFX_PG_SRC (1 << 1)
959 # define DYN_PER_CU_PG_ENABLE (1 << 2)
960 # define STATIC_PER_CU_PG_ENABLE (1 << 3)
961 # define DISABLE_GDS_PG (1 << 13)
962 # define DISABLE_CP_PG (1 << 15)
963 # define SMU_CLK_SLOWDOWN_ON_PU_ENABLE (1 << 17)
964 # define SMU_CLK_SLOWDOWN_ON_PD_ENABLE (1 << 18)
966 #define RLC_CGTT_MGCG_OVERRIDE 0xC420
967 #define RLC_CGCG_CGLS_CTRL 0xC424
968 # define CGCG_EN (1 << 0)
969 # define CGLS_EN (1 << 1)
971 #define RLC_PG_DELAY 0xC434
973 #define RLC_LB_INIT_CU_MASK 0xC43C
975 #define RLC_LB_PARAMS 0xC444
977 #define RLC_PG_AO_CU_MASK 0xC44C
979 #define RLC_MAX_PG_CU 0xC450
980 # define MAX_PU_CU(x) ((x) << 0)
981 # define MAX_PU_CU_MASK (0xff << 0)
982 #define RLC_AUTO_PG_CTRL 0xC454
983 # define AUTO_PG_EN (1 << 0)
984 # define GRBM_REG_SGIT(x) ((x) << 3)
985 # define GRBM_REG_SGIT_MASK (0xffff << 3)
987 #define RLC_SERDES_WR_CU_MASTER_MASK 0xC474
988 #define RLC_SERDES_WR_NONCU_MASTER_MASK 0xC478
989 #define RLC_SERDES_WR_CTRL 0xC47C
990 #define BPM_ADDR(x) ((x) << 0)
991 #define BPM_ADDR_MASK (0xff << 0)
992 #define CGLS_ENABLE (1 << 16)
993 #define CGCG_OVERRIDE_0 (1 << 20)
994 #define MGCG_OVERRIDE_0 (1 << 22)
995 #define MGCG_OVERRIDE_1 (1 << 23)
997 #define RLC_SERDES_CU_MASTER_BUSY 0xC484
998 #define RLC_SERDES_NONCU_MASTER_BUSY 0xC488
999 # define SE_MASTER_BUSY_MASK 0x0000ffff
1000 # define GC_MASTER_BUSY (1 << 16)
1001 # define TC0_MASTER_BUSY (1 << 17)
1002 # define TC1_MASTER_BUSY (1 << 18)
1004 #define RLC_GPM_SCRATCH_ADDR 0xC4B0
1005 #define RLC_GPM_SCRATCH_DATA 0xC4B4
1007 #define CP_HPD_EOP_BASE_ADDR 0xC904
1008 #define CP_HPD_EOP_BASE_ADDR_HI 0xC908
1009 #define CP_HPD_EOP_VMID 0xC90C
1010 #define CP_HPD_EOP_CONTROL 0xC910
1011 #define EOP_SIZE(x) ((x) << 0)
1012 #define EOP_SIZE_MASK (0x3f << 0)
1013 #define CP_MQD_BASE_ADDR 0xC914
1014 #define CP_MQD_BASE_ADDR_HI 0xC918
1015 #define CP_HQD_ACTIVE 0xC91C
1016 #define CP_HQD_VMID 0xC920
1018 #define CP_HQD_PQ_BASE 0xC934
1019 #define CP_HQD_PQ_BASE_HI 0xC938
1020 #define CP_HQD_PQ_RPTR 0xC93C
1021 #define CP_HQD_PQ_RPTR_REPORT_ADDR 0xC940
1022 #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI 0xC944
1023 #define CP_HQD_PQ_WPTR_POLL_ADDR 0xC948
1024 #define CP_HQD_PQ_WPTR_POLL_ADDR_HI 0xC94C
1025 #define CP_HQD_PQ_DOORBELL_CONTROL 0xC950
1026 #define DOORBELL_OFFSET(x) ((x) << 2)
1027 #define DOORBELL_OFFSET_MASK (0x1fffff << 2)
1028 #define DOORBELL_SOURCE (1 << 28)
1029 #define DOORBELL_SCHD_HIT (1 << 29)
1030 #define DOORBELL_EN (1 << 30)
1031 #define DOORBELL_HIT (1 << 31)
1032 #define CP_HQD_PQ_WPTR 0xC954
1033 #define CP_HQD_PQ_CONTROL 0xC958
1034 #define QUEUE_SIZE(x) ((x) << 0)
1035 #define QUEUE_SIZE_MASK (0x3f << 0)
1036 #define RPTR_BLOCK_SIZE(x) ((x) << 8)
1037 #define RPTR_BLOCK_SIZE_MASK (0x3f << 8)
1038 #define PQ_VOLATILE (1 << 26)
1039 #define NO_UPDATE_RPTR (1 << 27)
1040 #define UNORD_DISPATCH (1 << 28)
1041 #define ROQ_PQ_IB_FLIP (1 << 29)
1042 #define PRIV_STATE (1 << 30)
1043 #define KMD_QUEUE (1 << 31)
1045 #define CP_HQD_DEQUEUE_REQUEST 0xC974
1047 #define CP_MQD_CONTROL 0xC99C
1048 #define MQD_VMID(x) ((x) << 0)
1049 #define MQD_VMID_MASK (0xf << 0)
1051 #define DB_RENDER_CONTROL 0x28000
1053 #define PA_SC_RASTER_CONFIG 0x28350
1054 # define RASTER_CONFIG_RB_MAP_0 0
1055 # define RASTER_CONFIG_RB_MAP_1 1
1056 # define RASTER_CONFIG_RB_MAP_2 2
1057 # define RASTER_CONFIG_RB_MAP_3 3
1059 #define VGT_EVENT_INITIATOR 0x28a90
1060 # define SAMPLE_STREAMOUTSTATS1 (1 << 0)
1061 # define SAMPLE_STREAMOUTSTATS2 (2 << 0)
1062 # define SAMPLE_STREAMOUTSTATS3 (3 << 0)
1063 # define CACHE_FLUSH_TS (4 << 0)
1064 # define CACHE_FLUSH (6 << 0)
1065 # define CS_PARTIAL_FLUSH (7 << 0)
1066 # define VGT_STREAMOUT_RESET (10 << 0)
1067 # define END_OF_PIPE_INCR_DE (11 << 0)
1068 # define END_OF_PIPE_IB_END (12 << 0)
1069 # define RST_PIX_CNT (13 << 0)
1070 # define VS_PARTIAL_FLUSH (15 << 0)
1071 # define PS_PARTIAL_FLUSH (16 << 0)
1072 # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0)
1073 # define ZPASS_DONE (21 << 0)
1074 # define CACHE_FLUSH_AND_INV_EVENT (22 << 0)
1075 # define PERFCOUNTER_START (23 << 0)
1076 # define PERFCOUNTER_STOP (24 << 0)
1077 # define PIPELINESTAT_START (25 << 0)
1078 # define PIPELINESTAT_STOP (26 << 0)
1079 # define PERFCOUNTER_SAMPLE (27 << 0)
1080 # define SAMPLE_PIPELINESTAT (30 << 0)
1081 # define SO_VGT_STREAMOUT_FLUSH (31 << 0)
1082 # define SAMPLE_STREAMOUTSTATS (32 << 0)
1083 # define RESET_VTX_CNT (33 << 0)
1084 # define VGT_FLUSH (36 << 0)
1085 # define BOTTOM_OF_PIPE_TS (40 << 0)
1086 # define DB_CACHE_FLUSH_AND_INV (42 << 0)
1087 # define FLUSH_AND_INV_DB_DATA_TS (43 << 0)
1088 # define FLUSH_AND_INV_DB_META (44 << 0)
1089 # define FLUSH_AND_INV_CB_DATA_TS (45 << 0)
1090 # define FLUSH_AND_INV_CB_META (46 << 0)
1091 # define CS_DONE (47 << 0)
1092 # define PS_DONE (48 << 0)
1093 # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0)
1094 # define THREAD_TRACE_START (51 << 0)
1095 # define THREAD_TRACE_STOP (52 << 0)
1096 # define THREAD_TRACE_FLUSH (54 << 0)
1097 # define THREAD_TRACE_FINISH (55 << 0)
1098 # define PIXEL_PIPE_STAT_CONTROL (56 << 0)
1099 # define PIXEL_PIPE_STAT_DUMP (57 << 0)
1100 # define PIXEL_PIPE_STAT_RESET (58 << 0)
1102 #define SCRATCH_REG0 0x30100
1103 #define SCRATCH_REG1 0x30104
1104 #define SCRATCH_REG2 0x30108
1105 #define SCRATCH_REG3 0x3010C
1106 #define SCRATCH_REG4 0x30110
1107 #define SCRATCH_REG5 0x30114
1108 #define SCRATCH_REG6 0x30118
1109 #define SCRATCH_REG7 0x3011C
1111 #define SCRATCH_UMSK 0x30140
1112 #define SCRATCH_ADDR 0x30144
1114 #define CP_SEM_WAIT_TIMER 0x301BC
1116 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x301C8
1118 #define CP_WAIT_REG_MEM_TIMEOUT 0x301D0
1120 #define GRBM_GFX_INDEX 0x30800
1121 #define INSTANCE_INDEX(x) ((x) << 0)
1122 #define SH_INDEX(x) ((x) << 8)
1123 #define SE_INDEX(x) ((x) << 16)
1124 #define SH_BROADCAST_WRITES (1 << 29)
1125 #define INSTANCE_BROADCAST_WRITES (1 << 30)
1126 #define SE_BROADCAST_WRITES (1 << 31)
1128 #define VGT_ESGS_RING_SIZE 0x30900
1129 #define VGT_GSVS_RING_SIZE 0x30904
1130 #define VGT_PRIMITIVE_TYPE 0x30908
1131 #define VGT_INDEX_TYPE 0x3090C
1133 #define VGT_NUM_INDICES 0x30930
1134 #define VGT_NUM_INSTANCES 0x30934
1135 #define VGT_TF_RING_SIZE 0x30938
1136 #define VGT_HS_OFFCHIP_PARAM 0x3093C
1137 #define VGT_TF_MEMORY_BASE 0x30940
1139 #define PA_SU_LINE_STIPPLE_VALUE 0x30a00
1140 #define PA_SC_LINE_STIPPLE_STATE 0x30a04
1142 #define SQC_CACHES 0x30d20
1144 #define CP_PERFMON_CNTL 0x36020
1146 #define CGTS_SM_CTRL_REG 0x3c000
1147 #define SM_MODE(x) ((x) << 17)
1148 #define SM_MODE_MASK (0x7 << 17)
1149 #define SM_MODE_ENABLE (1 << 20)
1150 #define CGTS_OVERRIDE (1 << 21)
1151 #define CGTS_LS_OVERRIDE (1 << 22)
1152 #define ON_MONITOR_ADD_EN (1 << 23)
1153 #define ON_MONITOR_ADD(x) ((x) << 24)
1154 #define ON_MONITOR_ADD_MASK (0xff << 24)
1156 #define CGTS_TCC_DISABLE 0x3c00c
1157 #define CGTS_USER_TCC_DISABLE 0x3c010
1158 #define TCC_DISABLE_MASK 0xFFFF0000
1159 #define TCC_DISABLE_SHIFT 16
1161 #define CB_CGTT_SCLK_CTRL 0x3c2a0
1166 #define PACKET_TYPE0 0
1167 #define PACKET_TYPE1 1
1168 #define PACKET_TYPE2 2
1169 #define PACKET_TYPE3 3
1171 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
1172 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
1173 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
1174 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
1175 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
1176 (((reg) >> 2) & 0xFFFF) | \
1177 ((n) & 0x3FFF) << 16)
1178 #define CP_PACKET2 0x80000000
1179 #define PACKET2_PAD_SHIFT 0
1180 #define PACKET2_PAD_MASK (0x3fffffff << 0)
1182 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
1184 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
1185 (((op) & 0xFF) << 8) | \
1186 ((n) & 0x3FFF) << 16)
1188 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
1190 /* Packet 3 types */
1191 #define PACKET3_NOP 0x10
1192 #define PACKET3_SET_BASE 0x11
1193 #define PACKET3_BASE_INDEX(x) ((x) << 0)
1194 #define CE_PARTITION_BASE 3
1195 #define PACKET3_CLEAR_STATE 0x12
1196 #define PACKET3_INDEX_BUFFER_SIZE 0x13
1197 #define PACKET3_DISPATCH_DIRECT 0x15
1198 #define PACKET3_DISPATCH_INDIRECT 0x16
1199 #define PACKET3_ATOMIC_GDS 0x1D
1200 #define PACKET3_ATOMIC_MEM 0x1E
1201 #define PACKET3_OCCLUSION_QUERY 0x1F
1202 #define PACKET3_SET_PREDICATION 0x20
1203 #define PACKET3_REG_RMW 0x21
1204 #define PACKET3_COND_EXEC 0x22
1205 #define PACKET3_PRED_EXEC 0x23
1206 #define PACKET3_DRAW_INDIRECT 0x24
1207 #define PACKET3_DRAW_INDEX_INDIRECT 0x25
1208 #define PACKET3_INDEX_BASE 0x26
1209 #define PACKET3_DRAW_INDEX_2 0x27
1210 #define PACKET3_CONTEXT_CONTROL 0x28
1211 #define PACKET3_INDEX_TYPE 0x2A
1212 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C
1213 #define PACKET3_DRAW_INDEX_AUTO 0x2D
1214 #define PACKET3_NUM_INSTANCES 0x2F
1215 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
1216 #define PACKET3_INDIRECT_BUFFER_CONST 0x33
1217 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
1218 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
1219 #define PACKET3_DRAW_PREAMBLE 0x36
1220 #define PACKET3_WRITE_DATA 0x37
1221 #define WRITE_DATA_DST_SEL(x) ((x) << 8)
1223 * 1 - memory (sync - via GRBM)
1227 * 5 - memory (async - direct)
1229 #define WR_ONE_ADDR (1 << 16)
1230 #define WR_CONFIRM (1 << 20)
1231 #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)
1235 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
1240 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
1241 #define PACKET3_MEM_SEMAPHORE 0x39
1242 # define PACKET3_SEM_USE_MAILBOX (0x1 << 16)
1243 # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */
1244 # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */
1245 # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
1246 # define PACKET3_SEM_SEL_WAIT (0x7 << 29)
1247 #define PACKET3_COPY_DW 0x3B
1248 #define PACKET3_WAIT_REG_MEM 0x3C
1249 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
1258 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
1262 #define WAIT_REG_MEM_OPERATION(x) ((x) << 6)
1264 * 1 - wr_wait_wr_reg
1266 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
1270 #define PACKET3_INDIRECT_BUFFER 0x3F
1271 #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22)
1272 #define INDIRECT_BUFFER_VALID (1 << 23)
1273 #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28)
1278 #define PACKET3_COPY_DATA 0x40
1279 #define PACKET3_PFP_SYNC_ME 0x42
1280 #define PACKET3_SURFACE_SYNC 0x43
1281 # define PACKET3_DEST_BASE_0_ENA (1 << 0)
1282 # define PACKET3_DEST_BASE_1_ENA (1 << 1)
1283 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
1284 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
1285 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
1286 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
1287 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
1288 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
1289 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
1290 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
1291 # define PACKET3_DB_DEST_BASE_ENA (1 << 14)
1292 # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15)
1293 # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */
1294 # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */
1295 # define PACKET3_DEST_BASE_2_ENA (1 << 19)
1296 # define PACKET3_DEST_BASE_3_ENA (1 << 21)
1297 # define PACKET3_TCL1_ACTION_ENA (1 << 22)
1298 # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */
1299 # define PACKET3_CB_ACTION_ENA (1 << 25)
1300 # define PACKET3_DB_ACTION_ENA (1 << 26)
1301 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
1302 # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28)
1303 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
1304 #define PACKET3_COND_WRITE 0x45
1305 #define PACKET3_EVENT_WRITE 0x46
1306 #define EVENT_TYPE(x) ((x) << 0)
1307 #define EVENT_INDEX(x) ((x) << 8)
1308 /* 0 - any non-TS event
1309 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
1310 * 2 - SAMPLE_PIPELINESTAT
1311 * 3 - SAMPLE_STREAMOUTSTAT*
1312 * 4 - *S_PARTIAL_FLUSH
1316 #define PACKET3_EVENT_WRITE_EOP 0x47
1317 #define EOP_TCL1_VOL_ACTION_EN (1 << 12)
1318 #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */
1319 #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */
1320 #define EOP_TCL1_ACTION_EN (1 << 16)
1321 #define EOP_TC_ACTION_EN (1 << 17) /* L2 */
1322 #define EOP_CACHE_POLICY(x) ((x) << 25)
1327 #define EOP_TCL2_VOLATILE (1 << 27)
1328 #define DATA_SEL(x) ((x) << 29)
1330 * 1 - send low 32bit data
1331 * 2 - send 64bit data
1332 * 3 - send 64bit GPU counter value
1333 * 4 - send 64bit sys counter value
1335 #define INT_SEL(x) ((x) << 24)
1337 * 1 - interrupt only (DATA_SEL = 0)
1338 * 2 - interrupt when data write is confirmed
1340 #define DST_SEL(x) ((x) << 16)
1344 #define PACKET3_EVENT_WRITE_EOS 0x48
1345 #define PACKET3_RELEASE_MEM 0x49
1346 #define PACKET3_PREAMBLE_CNTL 0x4A
1347 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
1348 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
1349 #define PACKET3_DMA_DATA 0x50
1350 #define PACKET3_AQUIRE_MEM 0x58
1351 #define PACKET3_REWIND 0x59
1352 #define PACKET3_LOAD_UCONFIG_REG 0x5E
1353 #define PACKET3_LOAD_SH_REG 0x5F
1354 #define PACKET3_LOAD_CONFIG_REG 0x60
1355 #define PACKET3_LOAD_CONTEXT_REG 0x61
1356 #define PACKET3_SET_CONFIG_REG 0x68
1357 #define PACKET3_SET_CONFIG_REG_START 0x00008000
1358 #define PACKET3_SET_CONFIG_REG_END 0x0000b000
1359 #define PACKET3_SET_CONTEXT_REG 0x69
1360 #define PACKET3_SET_CONTEXT_REG_START 0x00028000
1361 #define PACKET3_SET_CONTEXT_REG_END 0x00029000
1362 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
1363 #define PACKET3_SET_SH_REG 0x76
1364 #define PACKET3_SET_SH_REG_START 0x0000b000
1365 #define PACKET3_SET_SH_REG_END 0x0000c000
1366 #define PACKET3_SET_SH_REG_OFFSET 0x77
1367 #define PACKET3_SET_QUEUE_REG 0x78
1368 #define PACKET3_SET_UCONFIG_REG 0x79
1369 #define PACKET3_SET_UCONFIG_REG_START 0x00030000
1370 #define PACKET3_SET_UCONFIG_REG_END 0x00031000
1371 #define PACKET3_SCRATCH_RAM_WRITE 0x7D
1372 #define PACKET3_SCRATCH_RAM_READ 0x7E
1373 #define PACKET3_LOAD_CONST_RAM 0x80
1374 #define PACKET3_WRITE_CONST_RAM 0x81
1375 #define PACKET3_DUMP_CONST_RAM 0x83
1376 #define PACKET3_INCREMENT_CE_COUNTER 0x84
1377 #define PACKET3_INCREMENT_DE_COUNTER 0x85
1378 #define PACKET3_WAIT_ON_CE_COUNTER 0x86
1379 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
1380 #define PACKET3_SWITCH_BUFFER 0x8B
1382 /* SDMA - first instance at 0xd000, second at 0xd800 */
1383 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */
1384 #define SDMA1_REGISTER_OFFSET 0x800 /* not a register */
1386 #define SDMA0_UCODE_ADDR 0xD000
1387 #define SDMA0_UCODE_DATA 0xD004
1388 #define SDMA0_POWER_CNTL 0xD008
1389 #define SDMA0_CLK_CTRL 0xD00C
1391 #define SDMA0_CNTL 0xD010
1392 # define TRAP_ENABLE (1 << 0)
1393 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
1394 # define SEM_WAIT_INT_ENABLE (1 << 2)
1395 # define DATA_SWAP_ENABLE (1 << 3)
1396 # define FENCE_SWAP_ENABLE (1 << 4)
1397 # define AUTO_CTXSW_ENABLE (1 << 18)
1398 # define CTXEMPTY_INT_ENABLE (1 << 28)
1400 #define SDMA0_TILING_CONFIG 0xD018
1402 #define SDMA0_SEM_INCOMPLETE_TIMER_CNTL 0xD020
1403 #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0xD024
1405 #define SDMA0_STATUS_REG 0xd034
1406 # define SDMA_IDLE (1 << 0)
1408 #define SDMA0_ME_CNTL 0xD048
1409 # define SDMA_HALT (1 << 0)
1411 #define SDMA0_GFX_RB_CNTL 0xD200
1412 # define SDMA_RB_ENABLE (1 << 0)
1413 # define SDMA_RB_SIZE(x) ((x) << 1) /* log2 */
1414 # define SDMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
1415 # define SDMA_RPTR_WRITEBACK_ENABLE (1 << 12)
1416 # define SDMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
1417 # define SDMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
1418 #define SDMA0_GFX_RB_BASE 0xD204
1419 #define SDMA0_GFX_RB_BASE_HI 0xD208
1420 #define SDMA0_GFX_RB_RPTR 0xD20C
1421 #define SDMA0_GFX_RB_WPTR 0xD210
1423 #define SDMA0_GFX_RB_RPTR_ADDR_HI 0xD220
1424 #define SDMA0_GFX_RB_RPTR_ADDR_LO 0xD224
1425 #define SDMA0_GFX_IB_CNTL 0xD228
1426 # define SDMA_IB_ENABLE (1 << 0)
1427 # define SDMA_IB_SWAP_ENABLE (1 << 4)
1428 # define SDMA_SWITCH_INSIDE_IB (1 << 8)
1429 # define SDMA_CMD_VMID(x) ((x) << 16)
1431 #define SDMA0_GFX_VIRTUAL_ADDR 0xD29C
1432 #define SDMA0_GFX_APE1_CNTL 0xD2A0
1434 #define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \
1435 (((sub_op) & 0xFF) << 8) | \
1436 (((op) & 0xFF) << 0))
1438 #define SDMA_OPCODE_NOP 0
1439 #define SDMA_OPCODE_COPY 1
1440 # define SDMA_COPY_SUB_OPCODE_LINEAR 0
1441 # define SDMA_COPY_SUB_OPCODE_TILED 1
1442 # define SDMA_COPY_SUB_OPCODE_SOA 3
1443 # define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4
1444 # define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5
1445 # define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6
1446 #define SDMA_OPCODE_WRITE 2
1447 # define SDMA_WRITE_SUB_OPCODE_LINEAR 0
1448 # define SDMA_WRTIE_SUB_OPCODE_TILED 1
1449 #define SDMA_OPCODE_INDIRECT_BUFFER 4
1450 #define SDMA_OPCODE_FENCE 5
1451 #define SDMA_OPCODE_TRAP 6
1452 #define SDMA_OPCODE_SEMAPHORE 7
1453 # define SDMA_SEMAPHORE_EXTRA_O (1 << 13)
1457 # define SDMA_SEMAPHORE_EXTRA_S (1 << 14)
1461 # define SDMA_SEMAPHORE_EXTRA_M (1 << 15)
1463 #define SDMA_OPCODE_POLL_REG_MEM 8
1464 # define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10)
1466 * 1 - wr_wait_wr_reg
1468 # define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12)
1477 # define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15)
1481 #define SDMA_OPCODE_COND_EXEC 9
1482 #define SDMA_OPCODE_CONSTANT_FILL 11
1483 # define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14)
1487 #define SDMA_OPCODE_GENERATE_PTE_PDE 12
1488 #define SDMA_OPCODE_TIMESTAMP 13
1489 # define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0
1490 # define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1
1491 # define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2
1492 #define SDMA_OPCODE_SRBM_WRITE 14
1493 # define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12)
1498 #define UVD_UDEC_ADDR_CONFIG 0xef4c
1499 #define UVD_UDEC_DB_ADDR_CONFIG 0xef50
1500 #define UVD_UDEC_DBW_ADDR_CONFIG 0xef54
1502 #define UVD_LMI_EXT40_ADDR 0xf498
1503 #define UVD_LMI_ADDR_EXT 0xf594
1504 #define UVD_VCPU_CACHE_OFFSET0 0xf608
1505 #define UVD_VCPU_CACHE_SIZE0 0xf60c
1506 #define UVD_VCPU_CACHE_OFFSET1 0xf610
1507 #define UVD_VCPU_CACHE_SIZE1 0xf614
1508 #define UVD_VCPU_CACHE_OFFSET2 0xf618
1509 #define UVD_VCPU_CACHE_SIZE2 0xf61c
1511 #define UVD_RBC_RB_RPTR 0xf690
1512 #define UVD_RBC_RB_WPTR 0xf694
1514 #define UVD_CGC_CTRL 0xF4B0
1515 # define DCM (1 << 0)
1516 # define CG_DT(x) ((x) << 2)
1517 # define CG_DT_MASK (0xf << 2)
1518 # define CLK_OD(x) ((x) << 6)
1519 # define CLK_OD_MASK (0x1f << 6)
1523 #define CG_DCLK_CNTL 0xC050009C
1524 # define DCLK_DIVIDER_MASK 0x7f
1525 # define DCLK_DIR_CNTL_EN (1 << 8)
1526 #define CG_DCLK_STATUS 0xC05000A0
1527 # define DCLK_STATUS (1 << 0)
1528 #define CG_VCLK_CNTL 0xC05000A4
1529 #define CG_VCLK_STATUS 0xC05000A8
1531 /* UVD CTX indirect */
1532 #define UVD_CGC_MEM_CTRL 0xC0
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