2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
27 #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001
29 #define CIK_RB_BITMAP_WIDTH_PER_SH 2
31 /* DIDT IND registers */
32 #define DIDT_SQ_CTRL0 0x0
33 # define DIDT_CTRL_EN (1 << 0)
34 #define DIDT_DB_CTRL0 0x20
35 #define DIDT_TD_CTRL0 0x40
36 #define DIDT_TCP_CTRL0 0x60
38 /* SMC IND registers */
39 #define DPM_TABLE_475 0x3F768
40 # define SamuBootLevel(x) ((x) << 0)
41 # define SamuBootLevel_MASK 0x000000ff
42 # define SamuBootLevel_SHIFT 0
43 # define AcpBootLevel(x) ((x) << 8)
44 # define AcpBootLevel_MASK 0x0000ff00
45 # define AcpBootLevel_SHIFT 8
46 # define VceBootLevel(x) ((x) << 16)
47 # define VceBootLevel_MASK 0x00ff0000
48 # define VceBootLevel_SHIFT 16
49 # define UvdBootLevel(x) ((x) << 24)
50 # define UvdBootLevel_MASK 0xff000000
51 # define UvdBootLevel_SHIFT 24
53 #define FIRMWARE_FLAGS 0x3F800
54 # define INTERRUPTS_ENABLED (1 << 0)
56 #define NB_DPM_CONFIG_1 0x3F9E8
57 # define Dpm0PgNbPsLo(x) ((x) << 0)
58 # define Dpm0PgNbPsLo_MASK 0x000000ff
59 # define Dpm0PgNbPsLo_SHIFT 0
60 # define Dpm0PgNbPsHi(x) ((x) << 8)
61 # define Dpm0PgNbPsHi_MASK 0x0000ff00
62 # define Dpm0PgNbPsHi_SHIFT 8
63 # define DpmXNbPsLo(x) ((x) << 16)
64 # define DpmXNbPsLo_MASK 0x00ff0000
65 # define DpmXNbPsLo_SHIFT 16
66 # define DpmXNbPsHi(x) ((x) << 24)
67 # define DpmXNbPsHi_MASK 0xff000000
68 # define DpmXNbPsHi_SHIFT 24
70 #define SMC_SYSCON_RESET_CNTL 0x80000000
71 # define RST_REG (1 << 0)
72 #define SMC_SYSCON_CLOCK_CNTL_0 0x80000004
73 # define CK_DISABLE (1 << 0)
74 # define CKEN (1 << 24)
76 #define SMC_SYSCON_MISC_CNTL 0x80000010
78 #define SMC_SYSCON_MSG_ARG_0 0x80000068
80 #define SMC_PC_C 0x80000370
82 #define SMC_SCRATCH9 0x80000424
84 #define RCU_UC_EVENTS 0xC0000004
85 # define BOOT_SEQ_DONE (1 << 7)
87 #define GENERAL_PWRMGT 0xC0200000
88 # define GLOBAL_PWRMGT_EN (1 << 0)
89 # define STATIC_PM_EN (1 << 1)
90 # define THERMAL_PROTECTION_DIS (1 << 2)
91 # define THERMAL_PROTECTION_TYPE (1 << 3)
92 # define SW_SMIO_INDEX(x) ((x) << 6)
93 # define SW_SMIO_INDEX_MASK (1 << 6)
94 # define SW_SMIO_INDEX_SHIFT 6
95 # define VOLT_PWRMGT_EN (1 << 10)
96 # define GPU_COUNTER_CLK (1 << 15)
97 # define DYN_SPREAD_SPECTRUM_EN (1 << 23)
99 #define CNB_PWRMGT_CNTL 0xC0200004
100 # define GNB_SLOW_MODE(x) ((x) << 0)
101 # define GNB_SLOW_MODE_MASK (3 << 0)
102 # define GNB_SLOW_MODE_SHIFT 0
103 # define GNB_SLOW (1 << 2)
104 # define FORCE_NB_PS1 (1 << 3)
105 # define DPM_ENABLED (1 << 4)
107 #define SCLK_PWRMGT_CNTL 0xC0200008
108 # define SCLK_PWRMGT_OFF (1 << 0)
109 # define RESET_BUSY_CNT (1 << 4)
110 # define RESET_SCLK_CNT (1 << 5)
111 # define DYNAMIC_PM_EN (1 << 21)
113 #define CG_SSP 0xC0200044
114 # define SST(x) ((x) << 0)
115 # define SST_MASK (0xffff << 0)
116 # define SSTU(x) ((x) << 16)
117 # define SSTU_MASK (0xf << 16)
119 #define CG_DISPLAY_GAP_CNTL 0xC0200060
120 # define DISP_GAP(x) ((x) << 0)
121 # define DISP_GAP_MASK (3 << 0)
122 # define VBI_TIMER_COUNT(x) ((x) << 4)
123 # define VBI_TIMER_COUNT_MASK (0x3fff << 4)
124 # define VBI_TIMER_UNIT(x) ((x) << 20)
125 # define VBI_TIMER_UNIT_MASK (7 << 20)
126 # define DISP_GAP_MCHG(x) ((x) << 24)
127 # define DISP_GAP_MCHG_MASK (3 << 24)
129 #define CG_ULV_PARAMETER 0xC0200158
131 #define CG_FTV_0 0xC02001A8
132 #define CG_FTV_1 0xC02001AC
133 #define CG_FTV_2 0xC02001B0
134 #define CG_FTV_3 0xC02001B4
135 #define CG_FTV_4 0xC02001B8
136 #define CG_FTV_5 0xC02001BC
137 #define CG_FTV_6 0xC02001C0
138 #define CG_FTV_7 0xC02001C4
140 #define CG_DISPLAY_GAP_CNTL2 0xC0200230
142 #define LCAC_SX0_OVR_SEL 0xC0400D04
143 #define LCAC_SX0_OVR_VAL 0xC0400D08
145 #define LCAC_MC0_CNTL 0xC0400D30
146 #define LCAC_MC0_OVR_SEL 0xC0400D34
147 #define LCAC_MC0_OVR_VAL 0xC0400D38
148 #define LCAC_MC1_CNTL 0xC0400D3C
149 #define LCAC_MC1_OVR_SEL 0xC0400D40
150 #define LCAC_MC1_OVR_VAL 0xC0400D44
152 #define LCAC_MC2_OVR_SEL 0xC0400D4C
153 #define LCAC_MC2_OVR_VAL 0xC0400D50
155 #define LCAC_MC3_OVR_SEL 0xC0400D58
156 #define LCAC_MC3_OVR_VAL 0xC0400D5C
158 #define LCAC_CPL_CNTL 0xC0400D80
159 #define LCAC_CPL_OVR_SEL 0xC0400D84
160 #define LCAC_CPL_OVR_VAL 0xC0400D88
163 #define CG_THERMAL_CTRL 0xC0300004
164 #define DPM_EVENT_SRC(x) ((x) << 0)
165 #define DPM_EVENT_SRC_MASK (7 << 0)
166 #define DIG_THERM_DPM(x) ((x) << 14)
167 #define DIG_THERM_DPM_MASK 0x003FC000
168 #define DIG_THERM_DPM_SHIFT 14
170 #define CG_THERMAL_INT 0xC030000C
171 #define CI_DIG_THERM_INTH(x) ((x) << 8)
172 #define CI_DIG_THERM_INTH_MASK 0x0000FF00
173 #define CI_DIG_THERM_INTH_SHIFT 8
174 #define CI_DIG_THERM_INTL(x) ((x) << 16)
175 #define CI_DIG_THERM_INTL_MASK 0x00FF0000
176 #define CI_DIG_THERM_INTL_SHIFT 16
177 #define THERM_INT_MASK_HIGH (1 << 24)
178 #define THERM_INT_MASK_LOW (1 << 25)
180 #define CG_MULT_THERMAL_STATUS 0xC0300014
181 #define ASIC_MAX_TEMP(x) ((x) << 0)
182 #define ASIC_MAX_TEMP_MASK 0x000001ff
183 #define ASIC_MAX_TEMP_SHIFT 0
184 #define CTF_TEMP(x) ((x) << 9)
185 #define CTF_TEMP_MASK 0x0003fe00
186 #define CTF_TEMP_SHIFT 9
188 #define CG_SPLL_FUNC_CNTL 0xC0500140
189 #define SPLL_RESET (1 << 0)
190 #define SPLL_PWRON (1 << 1)
191 #define SPLL_BYPASS_EN (1 << 3)
192 #define SPLL_REF_DIV(x) ((x) << 5)
193 #define SPLL_REF_DIV_MASK (0x3f << 5)
194 #define SPLL_PDIV_A(x) ((x) << 20)
195 #define SPLL_PDIV_A_MASK (0x7f << 20)
196 #define SPLL_PDIV_A_SHIFT 20
197 #define CG_SPLL_FUNC_CNTL_2 0xC0500144
198 #define SCLK_MUX_SEL(x) ((x) << 0)
199 #define SCLK_MUX_SEL_MASK (0x1ff << 0)
200 #define CG_SPLL_FUNC_CNTL_3 0xC0500148
201 #define SPLL_FB_DIV(x) ((x) << 0)
202 #define SPLL_FB_DIV_MASK (0x3ffffff << 0)
203 #define SPLL_FB_DIV_SHIFT 0
204 #define SPLL_DITHEN (1 << 28)
205 #define CG_SPLL_FUNC_CNTL_4 0xC050014C
207 #define CG_SPLL_SPREAD_SPECTRUM 0xC0500164
208 #define SSEN (1 << 0)
209 #define CLK_S(x) ((x) << 4)
210 #define CLK_S_MASK (0xfff << 4)
211 #define CLK_S_SHIFT 4
212 #define CG_SPLL_SPREAD_SPECTRUM_2 0xC0500168
213 #define CLK_V(x) ((x) << 0)
214 #define CLK_V_MASK (0x3ffffff << 0)
215 #define CLK_V_SHIFT 0
217 #define MPLL_BYPASSCLK_SEL 0xC050019C
218 # define MPLL_CLKOUT_SEL(x) ((x) << 8)
219 # define MPLL_CLKOUT_SEL_MASK 0xFF00
220 #define CG_CLKPIN_CNTL 0xC05001A0
221 # define XTALIN_DIVIDE (1 << 1)
222 # define BCLK_AS_XCLK (1 << 2)
223 #define CG_CLKPIN_CNTL_2 0xC05001A4
224 # define FORCE_BIF_REFCLK_EN (1 << 3)
225 # define MUX_TCLK_TO_XCLK (1 << 8)
226 #define THM_CLK_CNTL 0xC05001A8
227 # define CMON_CLK_SEL(x) ((x) << 0)
228 # define CMON_CLK_SEL_MASK 0xFF
229 # define TMON_CLK_SEL(x) ((x) << 8)
230 # define TMON_CLK_SEL_MASK 0xFF00
231 #define MISC_CLK_CTRL 0xC05001AC
232 # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0)
233 # define DEEP_SLEEP_CLK_SEL_MASK 0xFF
234 # define ZCLK_SEL(x) ((x) << 8)
235 # define ZCLK_SEL_MASK 0xFF00
238 #define CG_THERMAL_INT_CTRL 0xC2100028
239 #define DIG_THERM_INTH(x) ((x) << 0)
240 #define DIG_THERM_INTH_MASK 0x000000FF
241 #define DIG_THERM_INTH_SHIFT 0
242 #define DIG_THERM_INTL(x) ((x) << 8)
243 #define DIG_THERM_INTL_MASK 0x0000FF00
244 #define DIG_THERM_INTL_SHIFT 8
245 #define THERM_INTH_MASK (1 << 24)
246 #define THERM_INTL_MASK (1 << 25)
248 /* PCIE registers idx/data 0x38/0x3c */
249 #define PB0_PIF_PWRDOWN_0 0x1100012 /* PCIE */
250 # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7)
251 # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7)
252 # define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7
253 # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10)
254 # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10)
255 # define PLL_POWER_STATE_IN_OFF_0_SHIFT 10
256 # define PLL_RAMP_UP_TIME_0(x) ((x) << 24)
257 # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24)
258 # define PLL_RAMP_UP_TIME_0_SHIFT 24
259 #define PB0_PIF_PWRDOWN_1 0x1100013 /* PCIE */
260 # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7)
261 # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7)
262 # define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7
263 # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10)
264 # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10)
265 # define PLL_POWER_STATE_IN_OFF_1_SHIFT 10
266 # define PLL_RAMP_UP_TIME_1(x) ((x) << 24)
267 # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24)
268 # define PLL_RAMP_UP_TIME_1_SHIFT 24
270 #define PCIE_CNTL2 0x1001001c /* PCIE */
271 # define SLV_MEM_LS_EN (1 << 16)
272 # define MST_MEM_LS_EN (1 << 18)
273 # define REPLAY_MEM_LS_EN (1 << 19)
275 #define PCIE_LC_STATUS1 0x1400028 /* PCIE */
276 # define LC_REVERSE_RCVR (1 << 0)
277 # define LC_REVERSE_XMIT (1 << 1)
278 # define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2)
279 # define LC_OPERATING_LINK_WIDTH_SHIFT 2
280 # define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5)
281 # define LC_DETECTED_LINK_WIDTH_SHIFT 5
283 #define PCIE_P_CNTL 0x1400040 /* PCIE */
284 # define P_IGNORE_EDB_ERR (1 << 6)
286 #define PB1_PIF_PWRDOWN_0 0x2100012 /* PCIE */
287 #define PB1_PIF_PWRDOWN_1 0x2100013 /* PCIE */
289 #define PCIE_LC_CNTL 0x100100A0 /* PCIE */
290 # define LC_L0S_INACTIVITY(x) ((x) << 8)
291 # define LC_L0S_INACTIVITY_MASK (0xf << 8)
292 # define LC_L0S_INACTIVITY_SHIFT 8
293 # define LC_L1_INACTIVITY(x) ((x) << 12)
294 # define LC_L1_INACTIVITY_MASK (0xf << 12)
295 # define LC_L1_INACTIVITY_SHIFT 12
296 # define LC_PMI_TO_L1_DIS (1 << 16)
297 # define LC_ASPM_TO_L1_DIS (1 << 24)
299 #define PCIE_LC_LINK_WIDTH_CNTL 0x100100A2 /* PCIE */
300 # define LC_LINK_WIDTH_SHIFT 0
301 # define LC_LINK_WIDTH_MASK 0x7
302 # define LC_LINK_WIDTH_X0 0
303 # define LC_LINK_WIDTH_X1 1
304 # define LC_LINK_WIDTH_X2 2
305 # define LC_LINK_WIDTH_X4 3
306 # define LC_LINK_WIDTH_X8 4
307 # define LC_LINK_WIDTH_X16 6
308 # define LC_LINK_WIDTH_RD_SHIFT 4
309 # define LC_LINK_WIDTH_RD_MASK 0x70
310 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
311 # define LC_RECONFIG_NOW (1 << 8)
312 # define LC_RENEGOTIATION_SUPPORT (1 << 9)
313 # define LC_RENEGOTIATE_EN (1 << 10)
314 # define LC_SHORT_RECONFIG_EN (1 << 11)
315 # define LC_UPCONFIGURE_SUPPORT (1 << 12)
316 # define LC_UPCONFIGURE_DIS (1 << 13)
317 # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21)
318 # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21)
319 # define LC_DYN_LANES_PWR_STATE_SHIFT 21
320 #define PCIE_LC_N_FTS_CNTL 0x100100a3 /* PCIE */
321 # define LC_XMIT_N_FTS(x) ((x) << 0)
322 # define LC_XMIT_N_FTS_MASK (0xff << 0)
323 # define LC_XMIT_N_FTS_SHIFT 0
324 # define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8)
325 # define LC_N_FTS_MASK (0xff << 24)
326 #define PCIE_LC_SPEED_CNTL 0x100100A4 /* PCIE */
327 # define LC_GEN2_EN_STRAP (1 << 0)
328 # define LC_GEN3_EN_STRAP (1 << 1)
329 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2)
330 # define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3)
331 # define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3
332 # define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5)
333 # define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6)
334 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7)
335 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8)
336 # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9)
337 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10)
338 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10
339 # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */
340 # define LC_CURRENT_DATA_RATE_SHIFT 13
341 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16)
342 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18)
343 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19)
344 # define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20)
345 # define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21)
347 #define PCIE_LC_CNTL2 0x100100B1 /* PCIE */
348 # define LC_ALLOW_PDWN_IN_L1 (1 << 17)
349 # define LC_ALLOW_PDWN_IN_L23 (1 << 18)
351 #define PCIE_LC_CNTL3 0x100100B5 /* PCIE */
352 # define LC_GO_TO_RECOVERY (1 << 30)
353 #define PCIE_LC_CNTL4 0x100100B6 /* PCIE */
354 # define LC_REDO_EQ (1 << 5)
355 # define LC_SET_QUIESCE (1 << 13)
357 /* direct registers */
358 #define PCIE_INDEX 0x38
359 #define PCIE_DATA 0x3C
361 #define SMC_IND_INDEX_0 0x200
362 #define SMC_IND_DATA_0 0x204
364 #define SMC_IND_ACCESS_CNTL 0x240
365 #define AUTO_INCREMENT_IND_0 (1 << 0)
367 #define SMC_MESSAGE_0 0x250
368 #define SMC_MSG_MASK 0xffff
369 #define SMC_RESP_0 0x254
370 #define SMC_RESP_MASK 0xffff
372 #define SMC_MSG_ARG_0 0x290
374 #define VGA_HDP_CONTROL 0x328
375 #define VGA_MEMORY_DISABLE (1 << 4)
377 #define DMIF_ADDR_CALC 0xC00
379 #define SRBM_GFX_CNTL 0xE44
380 #define PIPEID(x) ((x) << 0)
381 #define MEID(x) ((x) << 2)
382 #define VMID(x) ((x) << 4)
383 #define QUEUEID(x) ((x) << 8)
385 #define SRBM_STATUS2 0xE4C
386 #define SDMA_BUSY (1 << 5)
387 #define SDMA1_BUSY (1 << 6)
388 #define SRBM_STATUS 0xE50
389 #define UVD_RQ_PENDING (1 << 1)
390 #define GRBM_RQ_PENDING (1 << 5)
391 #define VMC_BUSY (1 << 8)
392 #define MCB_BUSY (1 << 9)
393 #define MCB_NON_DISPLAY_BUSY (1 << 10)
394 #define MCC_BUSY (1 << 11)
395 #define MCD_BUSY (1 << 12)
396 #define SEM_BUSY (1 << 14)
397 #define IH_BUSY (1 << 17)
398 #define UVD_BUSY (1 << 19)
400 #define SRBM_SOFT_RESET 0xE60
401 #define SOFT_RESET_BIF (1 << 1)
402 #define SOFT_RESET_R0PLL (1 << 4)
403 #define SOFT_RESET_DC (1 << 5)
404 #define SOFT_RESET_SDMA1 (1 << 6)
405 #define SOFT_RESET_GRBM (1 << 8)
406 #define SOFT_RESET_HDP (1 << 9)
407 #define SOFT_RESET_IH (1 << 10)
408 #define SOFT_RESET_MC (1 << 11)
409 #define SOFT_RESET_ROM (1 << 14)
410 #define SOFT_RESET_SEM (1 << 15)
411 #define SOFT_RESET_VMC (1 << 17)
412 #define SOFT_RESET_SDMA (1 << 20)
413 #define SOFT_RESET_TST (1 << 21)
414 #define SOFT_RESET_REGBB (1 << 22)
415 #define SOFT_RESET_ORB (1 << 23)
416 #define SOFT_RESET_VCE (1 << 24)
418 #define VM_L2_CNTL 0x1400
419 #define ENABLE_L2_CACHE (1 << 0)
420 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
421 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2)
422 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4)
423 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
424 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
425 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15)
426 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19)
427 #define VM_L2_CNTL2 0x1404
428 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
429 #define INVALIDATE_L2_CACHE (1 << 1)
430 #define INVALIDATE_CACHE_MODE(x) ((x) << 26)
431 #define INVALIDATE_PTE_AND_PDE_CACHES 0
432 #define INVALIDATE_ONLY_PTE_CACHES 1
433 #define INVALIDATE_ONLY_PDE_CACHES 2
434 #define VM_L2_CNTL3 0x1408
435 #define BANK_SELECT(x) ((x) << 0)
436 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6)
437 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)
438 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
439 #define VM_L2_STATUS 0x140C
440 #define L2_BUSY (1 << 0)
441 #define VM_CONTEXT0_CNTL 0x1410
442 #define ENABLE_CONTEXT (1 << 0)
443 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
444 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)
445 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
446 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)
447 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)
448 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)
449 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)
450 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)
451 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)
452 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)
453 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)
454 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)
455 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)
456 #define VM_CONTEXT1_CNTL 0x1414
457 #define VM_CONTEXT0_CNTL2 0x1430
458 #define VM_CONTEXT1_CNTL2 0x1434
459 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438
460 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c
461 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440
462 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444
463 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448
464 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c
465 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450
466 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454
468 #define VM_INVALIDATE_REQUEST 0x1478
469 #define VM_INVALIDATE_RESPONSE 0x147c
471 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC
472 #define PROTECTIONS_MASK (0xf << 0)
473 #define PROTECTIONS_SHIFT 0
480 #define MEMORY_CLIENT_ID_MASK (0xff << 12)
481 #define MEMORY_CLIENT_ID_SHIFT 12
482 #define MEMORY_CLIENT_RW_MASK (1 << 24)
483 #define MEMORY_CLIENT_RW_SHIFT 24
484 #define FAULT_VMID_MASK (0xf << 25)
485 #define FAULT_VMID_SHIFT 25
487 #define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x14E4
489 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC
491 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
492 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
494 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
495 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540
496 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544
497 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548
498 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c
499 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550
500 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554
501 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558
502 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
503 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560
505 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
506 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580
508 #define VM_L2_CG 0x15c0
509 #define MC_CG_ENABLE (1 << 18)
510 #define MC_LS_ENABLE (1 << 19)
512 #define MC_SHARED_CHMAP 0x2004
513 #define NOOFCHAN_SHIFT 12
514 #define NOOFCHAN_MASK 0x0000f000
515 #define MC_SHARED_CHREMAP 0x2008
517 #define CHUB_CONTROL 0x1864
518 #define BYPASS_VM (1 << 0)
520 #define MC_VM_FB_LOCATION 0x2024
521 #define MC_VM_AGP_TOP 0x2028
522 #define MC_VM_AGP_BOT 0x202C
523 #define MC_VM_AGP_BASE 0x2030
524 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
525 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
526 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
528 #define MC_VM_MX_L1_TLB_CNTL 0x2064
529 #define ENABLE_L1_TLB (1 << 0)
530 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
531 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
532 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
533 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
534 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
535 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
536 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
537 #define MC_VM_FB_OFFSET 0x2068
539 #define MC_SHARED_BLACKOUT_CNTL 0x20ac
541 #define MC_HUB_MISC_HUB_CG 0x20b8
542 #define MC_HUB_MISC_VM_CG 0x20bc
544 #define MC_HUB_MISC_SIP_CG 0x20c0
546 #define MC_XPB_CLK_GAT 0x2478
548 #define MC_CITF_MISC_RD_CG 0x2648
549 #define MC_CITF_MISC_WR_CG 0x264c
550 #define MC_CITF_MISC_VM_CG 0x2650
552 #define MC_ARB_RAMCFG 0x2760
553 #define NOOFBANK_SHIFT 0
554 #define NOOFBANK_MASK 0x00000003
555 #define NOOFRANK_SHIFT 2
556 #define NOOFRANK_MASK 0x00000004
557 #define NOOFROWS_SHIFT 3
558 #define NOOFROWS_MASK 0x00000038
559 #define NOOFCOLS_SHIFT 6
560 #define NOOFCOLS_MASK 0x000000C0
561 #define CHANSIZE_SHIFT 8
562 #define CHANSIZE_MASK 0x00000100
563 #define NOOFGROUPS_SHIFT 12
564 #define NOOFGROUPS_MASK 0x00001000
566 #define MC_ARB_DRAM_TIMING 0x2774
567 #define MC_ARB_DRAM_TIMING2 0x2778
569 #define MC_ARB_BURST_TIME 0x2808
570 #define STATE0(x) ((x) << 0)
571 #define STATE0_MASK (0x1f << 0)
572 #define STATE0_SHIFT 0
573 #define STATE1(x) ((x) << 5)
574 #define STATE1_MASK (0x1f << 5)
575 #define STATE1_SHIFT 5
576 #define STATE2(x) ((x) << 10)
577 #define STATE2_MASK (0x1f << 10)
578 #define STATE2_SHIFT 10
579 #define STATE3(x) ((x) << 15)
580 #define STATE3_MASK (0x1f << 15)
581 #define STATE3_SHIFT 15
583 #define MC_SEQ_RAS_TIMING 0x28a0
584 #define MC_SEQ_CAS_TIMING 0x28a4
585 #define MC_SEQ_MISC_TIMING 0x28a8
586 #define MC_SEQ_MISC_TIMING2 0x28ac
587 #define MC_SEQ_PMG_TIMING 0x28b0
588 #define MC_SEQ_RD_CTL_D0 0x28b4
589 #define MC_SEQ_RD_CTL_D1 0x28b8
590 #define MC_SEQ_WR_CTL_D0 0x28bc
591 #define MC_SEQ_WR_CTL_D1 0x28c0
593 #define MC_SEQ_SUP_CNTL 0x28c8
594 #define RUN_MASK (1 << 0)
595 #define MC_SEQ_SUP_PGM 0x28cc
596 #define MC_PMG_AUTO_CMD 0x28d0
598 #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8
599 #define TRAIN_DONE_D0 (1 << 30)
600 #define TRAIN_DONE_D1 (1 << 31)
602 #define MC_IO_PAD_CNTL_D0 0x29d0
603 #define MEM_FALL_OUT_CMD (1 << 8)
605 #define MC_SEQ_MISC0 0x2a00
606 #define MC_SEQ_MISC0_VEN_ID_SHIFT 8
607 #define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00
608 #define MC_SEQ_MISC0_VEN_ID_VALUE 3
609 #define MC_SEQ_MISC0_REV_ID_SHIFT 12
610 #define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000
611 #define MC_SEQ_MISC0_REV_ID_VALUE 1
612 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
613 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
614 #define MC_SEQ_MISC0_GDDR5_VALUE 5
615 #define MC_SEQ_MISC1 0x2a04
616 #define MC_SEQ_RESERVE_M 0x2a08
617 #define MC_PMG_CMD_EMRS 0x2a0c
619 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44
620 #define MC_SEQ_IO_DEBUG_DATA 0x2a48
622 #define MC_SEQ_MISC5 0x2a54
623 #define MC_SEQ_MISC6 0x2a58
625 #define MC_SEQ_MISC7 0x2a64
627 #define MC_SEQ_RAS_TIMING_LP 0x2a6c
628 #define MC_SEQ_CAS_TIMING_LP 0x2a70
629 #define MC_SEQ_MISC_TIMING_LP 0x2a74
630 #define MC_SEQ_MISC_TIMING2_LP 0x2a78
631 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c
632 #define MC_SEQ_WR_CTL_D1_LP 0x2a80
633 #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84
634 #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88
636 #define MC_PMG_CMD_MRS 0x2aac
638 #define MC_SEQ_RD_CTL_D0_LP 0x2b1c
639 #define MC_SEQ_RD_CTL_D1_LP 0x2b20
641 #define MC_PMG_CMD_MRS1 0x2b44
642 #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48
643 #define MC_SEQ_PMG_TIMING_LP 0x2b4c
645 #define MC_SEQ_WR_CTL_2 0x2b54
646 #define MC_SEQ_WR_CTL_2_LP 0x2b58
647 #define MC_PMG_CMD_MRS2 0x2b5c
648 #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60
650 #define MCLK_PWRMGT_CNTL 0x2ba0
651 # define DLL_SPEED(x) ((x) << 0)
652 # define DLL_SPEED_MASK (0x1f << 0)
653 # define DLL_READY (1 << 6)
654 # define MC_INT_CNTL (1 << 7)
655 # define MRDCK0_PDNB (1 << 8)
656 # define MRDCK1_PDNB (1 << 9)
657 # define MRDCK0_RESET (1 << 16)
658 # define MRDCK1_RESET (1 << 17)
659 # define DLL_READY_READ (1 << 24)
660 #define DLL_CNTL 0x2ba4
661 # define MRDCK0_BYPASS (1 << 24)
662 # define MRDCK1_BYPASS (1 << 25)
664 #define MPLL_FUNC_CNTL 0x2bb4
665 #define BWCTRL(x) ((x) << 20)
666 #define BWCTRL_MASK (0xff << 20)
667 #define MPLL_FUNC_CNTL_1 0x2bb8
668 #define VCO_MODE(x) ((x) << 0)
669 #define VCO_MODE_MASK (3 << 0)
670 #define CLKFRAC(x) ((x) << 4)
671 #define CLKFRAC_MASK (0xfff << 4)
672 #define CLKF(x) ((x) << 16)
673 #define CLKF_MASK (0xfff << 16)
674 #define MPLL_FUNC_CNTL_2 0x2bbc
675 #define MPLL_AD_FUNC_CNTL 0x2bc0
676 #define YCLK_POST_DIV(x) ((x) << 0)
677 #define YCLK_POST_DIV_MASK (7 << 0)
678 #define MPLL_DQ_FUNC_CNTL 0x2bc4
679 #define YCLK_SEL(x) ((x) << 4)
680 #define YCLK_SEL_MASK (1 << 4)
682 #define MPLL_SS1 0x2bcc
683 #define CLKV(x) ((x) << 0)
684 #define CLKV_MASK (0x3ffffff << 0)
685 #define MPLL_SS2 0x2bd0
686 #define CLKS(x) ((x) << 0)
687 #define CLKS_MASK (0xfff << 0)
689 #define HDP_HOST_PATH_CNTL 0x2C00
690 #define CLOCK_GATING_DIS (1 << 23)
691 #define HDP_NONSURFACE_BASE 0x2C04
692 #define HDP_NONSURFACE_INFO 0x2C08
693 #define HDP_NONSURFACE_SIZE 0x2C0C
695 #define HDP_ADDR_CONFIG 0x2F48
696 #define HDP_MISC_CNTL 0x2F4C
697 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
698 #define HDP_MEM_POWER_LS 0x2F50
699 #define HDP_LS_ENABLE (1 << 0)
701 #define ATC_MISC_CG 0x3350
703 #define MC_SEQ_CNTL_3 0x3600
704 # define CAC_EN (1 << 31)
705 #define MC_SEQ_G5PDX_CTRL 0x3604
706 #define MC_SEQ_G5PDX_CTRL_LP 0x3608
707 #define MC_SEQ_G5PDX_CMD0 0x360c
708 #define MC_SEQ_G5PDX_CMD0_LP 0x3610
709 #define MC_SEQ_G5PDX_CMD1 0x3614
710 #define MC_SEQ_G5PDX_CMD1_LP 0x3618
712 #define MC_SEQ_PMG_DVS_CTL 0x3628
713 #define MC_SEQ_PMG_DVS_CTL_LP 0x362c
714 #define MC_SEQ_PMG_DVS_CMD 0x3630
715 #define MC_SEQ_PMG_DVS_CMD_LP 0x3634
716 #define MC_SEQ_DLL_STBY 0x3638
717 #define MC_SEQ_DLL_STBY_LP 0x363c
719 #define IH_RB_CNTL 0x3e00
720 # define IH_RB_ENABLE (1 << 0)
721 # define IH_RB_SIZE(x) ((x) << 1) /* log2 */
722 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
723 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
724 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
725 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
726 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
727 #define IH_RB_BASE 0x3e04
728 #define IH_RB_RPTR 0x3e08
729 #define IH_RB_WPTR 0x3e0c
730 # define RB_OVERFLOW (1 << 0)
731 # define WPTR_OFFSET_MASK 0x3fffc
732 #define IH_RB_WPTR_ADDR_HI 0x3e10
733 #define IH_RB_WPTR_ADDR_LO 0x3e14
734 #define IH_CNTL 0x3e18
735 # define ENABLE_INTR (1 << 0)
736 # define IH_MC_SWAP(x) ((x) << 1)
737 # define IH_MC_SWAP_NONE 0
738 # define IH_MC_SWAP_16BIT 1
739 # define IH_MC_SWAP_32BIT 2
740 # define IH_MC_SWAP_64BIT 3
741 # define RPTR_REARM (1 << 4)
742 # define MC_WRREQ_CREDIT(x) ((x) << 15)
743 # define MC_WR_CLEAN_CNT(x) ((x) << 20)
744 # define MC_VMID(x) ((x) << 25)
746 #define BIF_LNCNT_RESET 0x5220
747 # define RESET_LNCNT_EN (1 << 0)
749 #define CONFIG_MEMSIZE 0x5428
751 #define INTERRUPT_CNTL 0x5468
752 # define IH_DUMMY_RD_OVERRIDE (1 << 0)
753 # define IH_DUMMY_RD_EN (1 << 1)
754 # define IH_REQ_NONSNOOP_EN (1 << 3)
755 # define GEN_IH_INT_EN (1 << 8)
756 #define INTERRUPT_CNTL2 0x546c
758 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
760 #define BIF_FB_EN 0x5490
761 #define FB_READ_EN (1 << 0)
762 #define FB_WRITE_EN (1 << 1)
764 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
766 #define GPU_HDP_FLUSH_REQ 0x54DC
767 #define GPU_HDP_FLUSH_DONE 0x54E0
778 #define SDMA0 (1 << 10)
779 #define SDMA1 (1 << 11)
781 /* 0x6b04, 0x7704, 0x10304, 0x10f04, 0x11b04, 0x12704 */
782 #define LB_MEMORY_CTRL 0x6b04
783 #define LB_MEMORY_SIZE(x) ((x) << 0)
784 #define LB_MEMORY_CONFIG(x) ((x) << 20)
786 #define DPG_WATERMARK_MASK_CONTROL 0x6cc8
787 # define LATENCY_WATERMARK_MASK(x) ((x) << 8)
788 #define DPG_PIPE_LATENCY_CONTROL 0x6ccc
789 # define LATENCY_LOW_WATERMARK(x) ((x) << 0)
790 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
792 /* 0x6b24, 0x7724, 0x10324, 0x10f24, 0x11b24, 0x12724 */
793 #define LB_VLINE_STATUS 0x6b24
794 # define VLINE_OCCURRED (1 << 0)
795 # define VLINE_ACK (1 << 4)
796 # define VLINE_STAT (1 << 12)
797 # define VLINE_INTERRUPT (1 << 16)
798 # define VLINE_INTERRUPT_TYPE (1 << 17)
799 /* 0x6b2c, 0x772c, 0x1032c, 0x10f2c, 0x11b2c, 0x1272c */
800 #define LB_VBLANK_STATUS 0x6b2c
801 # define VBLANK_OCCURRED (1 << 0)
802 # define VBLANK_ACK (1 << 4)
803 # define VBLANK_STAT (1 << 12)
804 # define VBLANK_INTERRUPT (1 << 16)
805 # define VBLANK_INTERRUPT_TYPE (1 << 17)
807 /* 0x6b20, 0x7720, 0x10320, 0x10f20, 0x11b20, 0x12720 */
808 #define LB_INTERRUPT_MASK 0x6b20
809 # define VBLANK_INTERRUPT_MASK (1 << 0)
810 # define VLINE_INTERRUPT_MASK (1 << 4)
811 # define VLINE2_INTERRUPT_MASK (1 << 8)
813 #define DISP_INTERRUPT_STATUS 0x60f4
814 # define LB_D1_VLINE_INTERRUPT (1 << 2)
815 # define LB_D1_VBLANK_INTERRUPT (1 << 3)
816 # define DC_HPD1_INTERRUPT (1 << 17)
817 # define DC_HPD1_RX_INTERRUPT (1 << 18)
818 # define DACA_AUTODETECT_INTERRUPT (1 << 22)
819 # define DACB_AUTODETECT_INTERRUPT (1 << 23)
820 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
821 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
822 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
823 # define LB_D2_VLINE_INTERRUPT (1 << 2)
824 # define LB_D2_VBLANK_INTERRUPT (1 << 3)
825 # define DC_HPD2_INTERRUPT (1 << 17)
826 # define DC_HPD2_RX_INTERRUPT (1 << 18)
827 # define DISP_TIMER_INTERRUPT (1 << 24)
828 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
829 # define LB_D3_VLINE_INTERRUPT (1 << 2)
830 # define LB_D3_VBLANK_INTERRUPT (1 << 3)
831 # define DC_HPD3_INTERRUPT (1 << 17)
832 # define DC_HPD3_RX_INTERRUPT (1 << 18)
833 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
834 # define LB_D4_VLINE_INTERRUPT (1 << 2)
835 # define LB_D4_VBLANK_INTERRUPT (1 << 3)
836 # define DC_HPD4_INTERRUPT (1 << 17)
837 # define DC_HPD4_RX_INTERRUPT (1 << 18)
838 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
839 # define LB_D5_VLINE_INTERRUPT (1 << 2)
840 # define LB_D5_VBLANK_INTERRUPT (1 << 3)
841 # define DC_HPD5_INTERRUPT (1 << 17)
842 # define DC_HPD5_RX_INTERRUPT (1 << 18)
843 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150
844 # define LB_D6_VLINE_INTERRUPT (1 << 2)
845 # define LB_D6_VBLANK_INTERRUPT (1 << 3)
846 # define DC_HPD6_INTERRUPT (1 << 17)
847 # define DC_HPD6_RX_INTERRUPT (1 << 18)
848 #define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780
850 #define DAC_AUTODETECT_INT_CONTROL 0x67c8
852 #define DC_HPD1_INT_STATUS 0x601c
853 #define DC_HPD2_INT_STATUS 0x6028
854 #define DC_HPD3_INT_STATUS 0x6034
855 #define DC_HPD4_INT_STATUS 0x6040
856 #define DC_HPD5_INT_STATUS 0x604c
857 #define DC_HPD6_INT_STATUS 0x6058
858 # define DC_HPDx_INT_STATUS (1 << 0)
859 # define DC_HPDx_SENSE (1 << 1)
860 # define DC_HPDx_SENSE_DELAYED (1 << 4)
861 # define DC_HPDx_RX_INT_STATUS (1 << 8)
863 #define DC_HPD1_INT_CONTROL 0x6020
864 #define DC_HPD2_INT_CONTROL 0x602c
865 #define DC_HPD3_INT_CONTROL 0x6038
866 #define DC_HPD4_INT_CONTROL 0x6044
867 #define DC_HPD5_INT_CONTROL 0x6050
868 #define DC_HPD6_INT_CONTROL 0x605c
869 # define DC_HPDx_INT_ACK (1 << 0)
870 # define DC_HPDx_INT_POLARITY (1 << 8)
871 # define DC_HPDx_INT_EN (1 << 16)
872 # define DC_HPDx_RX_INT_ACK (1 << 20)
873 # define DC_HPDx_RX_INT_EN (1 << 24)
875 #define DC_HPD1_CONTROL 0x6024
876 #define DC_HPD2_CONTROL 0x6030
877 #define DC_HPD3_CONTROL 0x603c
878 #define DC_HPD4_CONTROL 0x6048
879 #define DC_HPD5_CONTROL 0x6054
880 #define DC_HPD6_CONTROL 0x6060
881 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
882 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
883 # define DC_HPDx_EN (1 << 28)
885 #define DPG_PIPE_STUTTER_CONTROL 0x6cd4
886 # define STUTTER_ENABLE (1 << 0)
888 #define GRBM_CNTL 0x8000
889 #define GRBM_READ_TIMEOUT(x) ((x) << 0)
891 #define GRBM_STATUS2 0x8008
892 #define ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000F
893 #define ME0PIPE1_CF_RQ_PENDING (1 << 4)
894 #define ME0PIPE1_PF_RQ_PENDING (1 << 5)
895 #define ME1PIPE0_RQ_PENDING (1 << 6)
896 #define ME1PIPE1_RQ_PENDING (1 << 7)
897 #define ME1PIPE2_RQ_PENDING (1 << 8)
898 #define ME1PIPE3_RQ_PENDING (1 << 9)
899 #define ME2PIPE0_RQ_PENDING (1 << 10)
900 #define ME2PIPE1_RQ_PENDING (1 << 11)
901 #define ME2PIPE2_RQ_PENDING (1 << 12)
902 #define ME2PIPE3_RQ_PENDING (1 << 13)
903 #define RLC_RQ_PENDING (1 << 14)
904 #define RLC_BUSY (1 << 24)
905 #define TC_BUSY (1 << 25)
906 #define CPF_BUSY (1 << 28)
907 #define CPC_BUSY (1 << 29)
908 #define CPG_BUSY (1 << 30)
910 #define GRBM_STATUS 0x8010
911 #define ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000F
912 #define SRBM_RQ_PENDING (1 << 5)
913 #define ME0PIPE0_CF_RQ_PENDING (1 << 7)
914 #define ME0PIPE0_PF_RQ_PENDING (1 << 8)
915 #define GDS_DMA_RQ_PENDING (1 << 9)
916 #define DB_CLEAN (1 << 12)
917 #define CB_CLEAN (1 << 13)
918 #define TA_BUSY (1 << 14)
919 #define GDS_BUSY (1 << 15)
920 #define WD_BUSY_NO_DMA (1 << 16)
921 #define VGT_BUSY (1 << 17)
922 #define IA_BUSY_NO_DMA (1 << 18)
923 #define IA_BUSY (1 << 19)
924 #define SX_BUSY (1 << 20)
925 #define WD_BUSY (1 << 21)
926 #define SPI_BUSY (1 << 22)
927 #define BCI_BUSY (1 << 23)
928 #define SC_BUSY (1 << 24)
929 #define PA_BUSY (1 << 25)
930 #define DB_BUSY (1 << 26)
931 #define CP_COHERENCY_BUSY (1 << 28)
932 #define CP_BUSY (1 << 29)
933 #define CB_BUSY (1 << 30)
934 #define GUI_ACTIVE (1 << 31)
935 #define GRBM_STATUS_SE0 0x8014
936 #define GRBM_STATUS_SE1 0x8018
937 #define GRBM_STATUS_SE2 0x8038
938 #define GRBM_STATUS_SE3 0x803C
939 #define SE_DB_CLEAN (1 << 1)
940 #define SE_CB_CLEAN (1 << 2)
941 #define SE_BCI_BUSY (1 << 22)
942 #define SE_VGT_BUSY (1 << 23)
943 #define SE_PA_BUSY (1 << 24)
944 #define SE_TA_BUSY (1 << 25)
945 #define SE_SX_BUSY (1 << 26)
946 #define SE_SPI_BUSY (1 << 27)
947 #define SE_SC_BUSY (1 << 29)
948 #define SE_DB_BUSY (1 << 30)
949 #define SE_CB_BUSY (1 << 31)
951 #define GRBM_SOFT_RESET 0x8020
952 #define SOFT_RESET_CP (1 << 0) /* All CP blocks */
953 #define SOFT_RESET_RLC (1 << 2) /* RLC */
954 #define SOFT_RESET_GFX (1 << 16) /* GFX */
955 #define SOFT_RESET_CPF (1 << 17) /* CP fetcher shared by gfx and compute */
956 #define SOFT_RESET_CPC (1 << 18) /* CP Compute (MEC1/2) */
957 #define SOFT_RESET_CPG (1 << 19) /* CP GFX (PFP, ME, CE) */
959 #define GRBM_INT_CNTL 0x8060
960 # define RDERR_INT_ENABLE (1 << 0)
961 # define GUI_IDLE_INT_ENABLE (1 << 19)
963 #define CP_CPC_STATUS 0x8210
964 #define CP_CPC_BUSY_STAT 0x8214
965 #define CP_CPC_STALLED_STAT1 0x8218
966 #define CP_CPF_STATUS 0x821c
967 #define CP_CPF_BUSY_STAT 0x8220
968 #define CP_CPF_STALLED_STAT1 0x8224
970 #define CP_MEC_CNTL 0x8234
971 #define MEC_ME2_HALT (1 << 28)
972 #define MEC_ME1_HALT (1 << 30)
974 #define CP_MEC_CNTL 0x8234
975 #define MEC_ME2_HALT (1 << 28)
976 #define MEC_ME1_HALT (1 << 30)
978 #define CP_STALLED_STAT3 0x8670
979 #define CP_STALLED_STAT1 0x8674
980 #define CP_STALLED_STAT2 0x8678
982 #define CP_STAT 0x8680
984 #define CP_ME_CNTL 0x86D8
985 #define CP_CE_HALT (1 << 24)
986 #define CP_PFP_HALT (1 << 26)
987 #define CP_ME_HALT (1 << 28)
989 #define CP_RB0_RPTR 0x8700
990 #define CP_RB_WPTR_DELAY 0x8704
991 #define CP_RB_WPTR_POLL_CNTL 0x8708
992 #define IDLE_POLL_COUNT(x) ((x) << 16)
993 #define IDLE_POLL_COUNT_MASK (0xffff << 16)
995 #define CP_MEQ_THRESHOLDS 0x8764
996 #define MEQ1_START(x) ((x) << 0)
997 #define MEQ2_START(x) ((x) << 8)
999 #define VGT_VTX_VECT_EJECT_REG 0x88B0
1001 #define VGT_CACHE_INVALIDATION 0x88C4
1002 #define CACHE_INVALIDATION(x) ((x) << 0)
1006 #define AUTO_INVLD_EN(x) ((x) << 6)
1010 #define ES_AND_GS_AUTO 3
1012 #define VGT_GS_VERTEX_REUSE 0x88D4
1014 #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc
1015 #define INACTIVE_CUS_MASK 0xFFFF0000
1016 #define INACTIVE_CUS_SHIFT 16
1017 #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0
1019 #define PA_CL_ENHANCE 0x8A14
1020 #define CLIP_VTX_REORDER_ENA (1 << 0)
1021 #define NUM_CLIP_SEQ(x) ((x) << 1)
1023 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
1024 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1025 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
1027 #define PA_SC_FIFO_SIZE 0x8BCC
1028 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0)
1029 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6)
1030 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15)
1031 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23)
1033 #define PA_SC_ENHANCE 0x8BF0
1034 #define ENABLE_PA_SC_OUT_OF_ORDER (1 << 0)
1035 #define DISABLE_PA_SC_GUIDANCE (1 << 13)
1037 #define SQ_CONFIG 0x8C00
1039 #define SH_MEM_BASES 0x8C28
1040 /* if PTR32, these are the bases for scratch and lds */
1041 #define PRIVATE_BASE(x) ((x) << 0) /* scratch */
1042 #define SHARED_BASE(x) ((x) << 16) /* LDS */
1043 #define SH_MEM_APE1_BASE 0x8C2C
1044 /* if PTR32, this is the base location of GPUVM */
1045 #define SH_MEM_APE1_LIMIT 0x8C30
1046 /* if PTR32, this is the upper limit of GPUVM */
1047 #define SH_MEM_CONFIG 0x8C34
1048 #define PTR32 (1 << 0)
1049 #define ALIGNMENT_MODE(x) ((x) << 2)
1050 #define SH_MEM_ALIGNMENT_MODE_DWORD 0
1051 #define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1
1052 #define SH_MEM_ALIGNMENT_MODE_STRICT 2
1053 #define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3
1054 #define DEFAULT_MTYPE(x) ((x) << 4)
1055 #define APE1_MTYPE(x) ((x) << 7)
1057 #define SX_DEBUG_1 0x9060
1059 #define SPI_CONFIG_CNTL 0x9100
1061 #define SPI_CONFIG_CNTL_1 0x913C
1062 #define VTX_DONE_DELAY(x) ((x) << 0)
1063 #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
1065 #define TA_CNTL_AUX 0x9508
1067 #define DB_DEBUG 0x9830
1068 #define DB_DEBUG2 0x9834
1069 #define DB_DEBUG3 0x9838
1071 #define CC_RB_BACKEND_DISABLE 0x98F4
1072 #define BACKEND_DISABLE(x) ((x) << 16)
1073 #define GB_ADDR_CONFIG 0x98F8
1074 #define NUM_PIPES(x) ((x) << 0)
1075 #define NUM_PIPES_MASK 0x00000007
1076 #define NUM_PIPES_SHIFT 0
1077 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
1078 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
1079 #define PIPE_INTERLEAVE_SIZE_SHIFT 4
1080 #define NUM_SHADER_ENGINES(x) ((x) << 12)
1081 #define NUM_SHADER_ENGINES_MASK 0x00003000
1082 #define NUM_SHADER_ENGINES_SHIFT 12
1083 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
1084 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
1085 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16
1086 #define ROW_SIZE(x) ((x) << 28)
1087 #define ROW_SIZE_MASK 0x30000000
1088 #define ROW_SIZE_SHIFT 28
1090 #define GB_TILE_MODE0 0x9910
1091 # define ARRAY_MODE(x) ((x) << 2)
1092 # define ARRAY_LINEAR_GENERAL 0
1093 # define ARRAY_LINEAR_ALIGNED 1
1094 # define ARRAY_1D_TILED_THIN1 2
1095 # define ARRAY_2D_TILED_THIN1 4
1096 # define ARRAY_PRT_TILED_THIN1 5
1097 # define ARRAY_PRT_2D_TILED_THIN1 6
1098 # define PIPE_CONFIG(x) ((x) << 6)
1099 # define ADDR_SURF_P2 0
1100 # define ADDR_SURF_P4_8x16 4
1101 # define ADDR_SURF_P4_16x16 5
1102 # define ADDR_SURF_P4_16x32 6
1103 # define ADDR_SURF_P4_32x32 7
1104 # define ADDR_SURF_P8_16x16_8x16 8
1105 # define ADDR_SURF_P8_16x32_8x16 9
1106 # define ADDR_SURF_P8_32x32_8x16 10
1107 # define ADDR_SURF_P8_16x32_16x16 11
1108 # define ADDR_SURF_P8_32x32_16x16 12
1109 # define ADDR_SURF_P8_32x32_16x32 13
1110 # define ADDR_SURF_P8_32x64_32x32 14
1111 # define TILE_SPLIT(x) ((x) << 11)
1112 # define ADDR_SURF_TILE_SPLIT_64B 0
1113 # define ADDR_SURF_TILE_SPLIT_128B 1
1114 # define ADDR_SURF_TILE_SPLIT_256B 2
1115 # define ADDR_SURF_TILE_SPLIT_512B 3
1116 # define ADDR_SURF_TILE_SPLIT_1KB 4
1117 # define ADDR_SURF_TILE_SPLIT_2KB 5
1118 # define ADDR_SURF_TILE_SPLIT_4KB 6
1119 # define MICRO_TILE_MODE_NEW(x) ((x) << 22)
1120 # define ADDR_SURF_DISPLAY_MICRO_TILING 0
1121 # define ADDR_SURF_THIN_MICRO_TILING 1
1122 # define ADDR_SURF_DEPTH_MICRO_TILING 2
1123 # define ADDR_SURF_ROTATED_MICRO_TILING 3
1124 # define SAMPLE_SPLIT(x) ((x) << 25)
1125 # define ADDR_SURF_SAMPLE_SPLIT_1 0
1126 # define ADDR_SURF_SAMPLE_SPLIT_2 1
1127 # define ADDR_SURF_SAMPLE_SPLIT_4 2
1128 # define ADDR_SURF_SAMPLE_SPLIT_8 3
1130 #define GB_MACROTILE_MODE0 0x9990
1131 # define BANK_WIDTH(x) ((x) << 0)
1132 # define ADDR_SURF_BANK_WIDTH_1 0
1133 # define ADDR_SURF_BANK_WIDTH_2 1
1134 # define ADDR_SURF_BANK_WIDTH_4 2
1135 # define ADDR_SURF_BANK_WIDTH_8 3
1136 # define BANK_HEIGHT(x) ((x) << 2)
1137 # define ADDR_SURF_BANK_HEIGHT_1 0
1138 # define ADDR_SURF_BANK_HEIGHT_2 1
1139 # define ADDR_SURF_BANK_HEIGHT_4 2
1140 # define ADDR_SURF_BANK_HEIGHT_8 3
1141 # define MACRO_TILE_ASPECT(x) ((x) << 4)
1142 # define ADDR_SURF_MACRO_ASPECT_1 0
1143 # define ADDR_SURF_MACRO_ASPECT_2 1
1144 # define ADDR_SURF_MACRO_ASPECT_4 2
1145 # define ADDR_SURF_MACRO_ASPECT_8 3
1146 # define NUM_BANKS(x) ((x) << 6)
1147 # define ADDR_SURF_2_BANK 0
1148 # define ADDR_SURF_4_BANK 1
1149 # define ADDR_SURF_8_BANK 2
1150 # define ADDR_SURF_16_BANK 3
1152 #define CB_HW_CONTROL 0x9A10
1154 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C
1155 #define BACKEND_DISABLE_MASK 0x00FF0000
1156 #define BACKEND_DISABLE_SHIFT 16
1158 #define TCP_CHAN_STEER_LO 0xac0c
1159 #define TCP_CHAN_STEER_HI 0xac10
1161 #define TC_CFG_L1_LOAD_POLICY0 0xAC68
1162 #define TC_CFG_L1_LOAD_POLICY1 0xAC6C
1163 #define TC_CFG_L1_STORE_POLICY 0xAC70
1164 #define TC_CFG_L2_LOAD_POLICY0 0xAC74
1165 #define TC_CFG_L2_LOAD_POLICY1 0xAC78
1166 #define TC_CFG_L2_STORE_POLICY0 0xAC7C
1167 #define TC_CFG_L2_STORE_POLICY1 0xAC80
1168 #define TC_CFG_L2_ATOMIC_POLICY 0xAC84
1169 #define TC_CFG_L1_VOLATILE 0xAC88
1170 #define TC_CFG_L2_VOLATILE 0xAC8C
1172 #define CP_RB0_BASE 0xC100
1173 #define CP_RB0_CNTL 0xC104
1174 #define RB_BUFSZ(x) ((x) << 0)
1175 #define RB_BLKSZ(x) ((x) << 8)
1176 #define BUF_SWAP_32BIT (2 << 16)
1177 #define RB_NO_UPDATE (1 << 27)
1178 #define RB_RPTR_WR_ENA (1 << 31)
1180 #define CP_RB0_RPTR_ADDR 0xC10C
1181 #define RB_RPTR_SWAP_32BIT (2 << 0)
1182 #define CP_RB0_RPTR_ADDR_HI 0xC110
1183 #define CP_RB0_WPTR 0xC114
1185 #define CP_DEVICE_ID 0xC12C
1186 #define CP_ENDIAN_SWAP 0xC140
1187 #define CP_RB_VMID 0xC144
1189 #define CP_PFP_UCODE_ADDR 0xC150
1190 #define CP_PFP_UCODE_DATA 0xC154
1191 #define CP_ME_RAM_RADDR 0xC158
1192 #define CP_ME_RAM_WADDR 0xC15C
1193 #define CP_ME_RAM_DATA 0xC160
1195 #define CP_CE_UCODE_ADDR 0xC168
1196 #define CP_CE_UCODE_DATA 0xC16C
1197 #define CP_MEC_ME1_UCODE_ADDR 0xC170
1198 #define CP_MEC_ME1_UCODE_DATA 0xC174
1199 #define CP_MEC_ME2_UCODE_ADDR 0xC178
1200 #define CP_MEC_ME2_UCODE_DATA 0xC17C
1202 #define CP_INT_CNTL_RING0 0xC1A8
1203 # define CNTX_BUSY_INT_ENABLE (1 << 19)
1204 # define CNTX_EMPTY_INT_ENABLE (1 << 20)
1205 # define PRIV_INSTR_INT_ENABLE (1 << 22)
1206 # define PRIV_REG_INT_ENABLE (1 << 23)
1207 # define TIME_STAMP_INT_ENABLE (1 << 26)
1208 # define CP_RINGID2_INT_ENABLE (1 << 29)
1209 # define CP_RINGID1_INT_ENABLE (1 << 30)
1210 # define CP_RINGID0_INT_ENABLE (1 << 31)
1212 #define CP_INT_STATUS_RING0 0xC1B4
1213 # define PRIV_INSTR_INT_STAT (1 << 22)
1214 # define PRIV_REG_INT_STAT (1 << 23)
1215 # define TIME_STAMP_INT_STAT (1 << 26)
1216 # define CP_RINGID2_INT_STAT (1 << 29)
1217 # define CP_RINGID1_INT_STAT (1 << 30)
1218 # define CP_RINGID0_INT_STAT (1 << 31)
1220 #define CP_MEM_SLP_CNTL 0xC1E4
1221 # define CP_MEM_LS_EN (1 << 0)
1223 #define CP_CPF_DEBUG 0xC200
1225 #define CP_PQ_WPTR_POLL_CNTL 0xC20C
1226 #define WPTR_POLL_EN (1 << 31)
1228 #define CP_ME1_PIPE0_INT_CNTL 0xC214
1229 #define CP_ME1_PIPE1_INT_CNTL 0xC218
1230 #define CP_ME1_PIPE2_INT_CNTL 0xC21C
1231 #define CP_ME1_PIPE3_INT_CNTL 0xC220
1232 #define CP_ME2_PIPE0_INT_CNTL 0xC224
1233 #define CP_ME2_PIPE1_INT_CNTL 0xC228
1234 #define CP_ME2_PIPE2_INT_CNTL 0xC22C
1235 #define CP_ME2_PIPE3_INT_CNTL 0xC230
1236 # define DEQUEUE_REQUEST_INT_ENABLE (1 << 13)
1237 # define WRM_POLL_TIMEOUT_INT_ENABLE (1 << 17)
1238 # define PRIV_REG_INT_ENABLE (1 << 23)
1239 # define TIME_STAMP_INT_ENABLE (1 << 26)
1240 # define GENERIC2_INT_ENABLE (1 << 29)
1241 # define GENERIC1_INT_ENABLE (1 << 30)
1242 # define GENERIC0_INT_ENABLE (1 << 31)
1243 #define CP_ME1_PIPE0_INT_STATUS 0xC214
1244 #define CP_ME1_PIPE1_INT_STATUS 0xC218
1245 #define CP_ME1_PIPE2_INT_STATUS 0xC21C
1246 #define CP_ME1_PIPE3_INT_STATUS 0xC220
1247 #define CP_ME2_PIPE0_INT_STATUS 0xC224
1248 #define CP_ME2_PIPE1_INT_STATUS 0xC228
1249 #define CP_ME2_PIPE2_INT_STATUS 0xC22C
1250 #define CP_ME2_PIPE3_INT_STATUS 0xC230
1251 # define DEQUEUE_REQUEST_INT_STATUS (1 << 13)
1252 # define WRM_POLL_TIMEOUT_INT_STATUS (1 << 17)
1253 # define PRIV_REG_INT_STATUS (1 << 23)
1254 # define TIME_STAMP_INT_STATUS (1 << 26)
1255 # define GENERIC2_INT_STATUS (1 << 29)
1256 # define GENERIC1_INT_STATUS (1 << 30)
1257 # define GENERIC0_INT_STATUS (1 << 31)
1259 #define CP_MAX_CONTEXT 0xC2B8
1261 #define CP_RB0_BASE_HI 0xC2C4
1263 #define RLC_CNTL 0xC300
1264 # define RLC_ENABLE (1 << 0)
1266 #define RLC_MC_CNTL 0xC30C
1268 #define RLC_MEM_SLP_CNTL 0xC318
1269 # define RLC_MEM_LS_EN (1 << 0)
1271 #define RLC_LB_CNTR_MAX 0xC348
1273 #define RLC_LB_CNTL 0xC364
1274 # define LOAD_BALANCE_ENABLE (1 << 0)
1276 #define RLC_LB_CNTR_INIT 0xC36C
1278 #define RLC_SAVE_AND_RESTORE_BASE 0xC374
1279 #define RLC_DRIVER_DMA_STATUS 0xC378 /* dGPU */
1280 #define RLC_CP_TABLE_RESTORE 0xC378 /* APU */
1281 #define RLC_PG_DELAY_2 0xC37C
1283 #define RLC_GPM_UCODE_ADDR 0xC388
1284 #define RLC_GPM_UCODE_DATA 0xC38C
1285 #define RLC_GPU_CLOCK_COUNT_LSB 0xC390
1286 #define RLC_GPU_CLOCK_COUNT_MSB 0xC394
1287 #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC398
1288 #define RLC_UCODE_CNTL 0xC39C
1290 #define RLC_GPM_STAT 0xC400
1291 # define RLC_GPM_BUSY (1 << 0)
1292 # define GFX_POWER_STATUS (1 << 1)
1293 # define GFX_CLOCK_STATUS (1 << 2)
1295 #define RLC_PG_CNTL 0xC40C
1296 # define GFX_PG_ENABLE (1 << 0)
1297 # define GFX_PG_SRC (1 << 1)
1298 # define DYN_PER_CU_PG_ENABLE (1 << 2)
1299 # define STATIC_PER_CU_PG_ENABLE (1 << 3)
1300 # define DISABLE_GDS_PG (1 << 13)
1301 # define DISABLE_CP_PG (1 << 15)
1302 # define SMU_CLK_SLOWDOWN_ON_PU_ENABLE (1 << 17)
1303 # define SMU_CLK_SLOWDOWN_ON_PD_ENABLE (1 << 18)
1305 #define RLC_CGTT_MGCG_OVERRIDE 0xC420
1306 #define RLC_CGCG_CGLS_CTRL 0xC424
1307 # define CGCG_EN (1 << 0)
1308 # define CGLS_EN (1 << 1)
1310 #define RLC_PG_DELAY 0xC434
1312 #define RLC_LB_INIT_CU_MASK 0xC43C
1314 #define RLC_LB_PARAMS 0xC444
1316 #define RLC_PG_AO_CU_MASK 0xC44C
1318 #define RLC_MAX_PG_CU 0xC450
1319 # define MAX_PU_CU(x) ((x) << 0)
1320 # define MAX_PU_CU_MASK (0xff << 0)
1321 #define RLC_AUTO_PG_CTRL 0xC454
1322 # define AUTO_PG_EN (1 << 0)
1323 # define GRBM_REG_SGIT(x) ((x) << 3)
1324 # define GRBM_REG_SGIT_MASK (0xffff << 3)
1326 #define RLC_SERDES_WR_CU_MASTER_MASK 0xC474
1327 #define RLC_SERDES_WR_NONCU_MASTER_MASK 0xC478
1328 #define RLC_SERDES_WR_CTRL 0xC47C
1329 #define BPM_ADDR(x) ((x) << 0)
1330 #define BPM_ADDR_MASK (0xff << 0)
1331 #define CGLS_ENABLE (1 << 16)
1332 #define CGCG_OVERRIDE_0 (1 << 20)
1333 #define MGCG_OVERRIDE_0 (1 << 22)
1334 #define MGCG_OVERRIDE_1 (1 << 23)
1336 #define RLC_SERDES_CU_MASTER_BUSY 0xC484
1337 #define RLC_SERDES_NONCU_MASTER_BUSY 0xC488
1338 # define SE_MASTER_BUSY_MASK 0x0000ffff
1339 # define GC_MASTER_BUSY (1 << 16)
1340 # define TC0_MASTER_BUSY (1 << 17)
1341 # define TC1_MASTER_BUSY (1 << 18)
1343 #define RLC_GPM_SCRATCH_ADDR 0xC4B0
1344 #define RLC_GPM_SCRATCH_DATA 0xC4B4
1346 #define RLC_GPR_REG2 0xC4E8
1347 #define REQ 0x00000001
1348 #define MESSAGE(x) ((x) << 1)
1349 #define MESSAGE_MASK 0x0000001e
1350 #define MSG_ENTER_RLC_SAFE_MODE 1
1351 #define MSG_EXIT_RLC_SAFE_MODE 0
1353 #define CP_HPD_EOP_BASE_ADDR 0xC904
1354 #define CP_HPD_EOP_BASE_ADDR_HI 0xC908
1355 #define CP_HPD_EOP_VMID 0xC90C
1356 #define CP_HPD_EOP_CONTROL 0xC910
1357 #define EOP_SIZE(x) ((x) << 0)
1358 #define EOP_SIZE_MASK (0x3f << 0)
1359 #define CP_MQD_BASE_ADDR 0xC914
1360 #define CP_MQD_BASE_ADDR_HI 0xC918
1361 #define CP_HQD_ACTIVE 0xC91C
1362 #define CP_HQD_VMID 0xC920
1364 #define CP_HQD_PQ_BASE 0xC934
1365 #define CP_HQD_PQ_BASE_HI 0xC938
1366 #define CP_HQD_PQ_RPTR 0xC93C
1367 #define CP_HQD_PQ_RPTR_REPORT_ADDR 0xC940
1368 #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI 0xC944
1369 #define CP_HQD_PQ_WPTR_POLL_ADDR 0xC948
1370 #define CP_HQD_PQ_WPTR_POLL_ADDR_HI 0xC94C
1371 #define CP_HQD_PQ_DOORBELL_CONTROL 0xC950
1372 #define DOORBELL_OFFSET(x) ((x) << 2)
1373 #define DOORBELL_OFFSET_MASK (0x1fffff << 2)
1374 #define DOORBELL_SOURCE (1 << 28)
1375 #define DOORBELL_SCHD_HIT (1 << 29)
1376 #define DOORBELL_EN (1 << 30)
1377 #define DOORBELL_HIT (1 << 31)
1378 #define CP_HQD_PQ_WPTR 0xC954
1379 #define CP_HQD_PQ_CONTROL 0xC958
1380 #define QUEUE_SIZE(x) ((x) << 0)
1381 #define QUEUE_SIZE_MASK (0x3f << 0)
1382 #define RPTR_BLOCK_SIZE(x) ((x) << 8)
1383 #define RPTR_BLOCK_SIZE_MASK (0x3f << 8)
1384 #define PQ_VOLATILE (1 << 26)
1385 #define NO_UPDATE_RPTR (1 << 27)
1386 #define UNORD_DISPATCH (1 << 28)
1387 #define ROQ_PQ_IB_FLIP (1 << 29)
1388 #define PRIV_STATE (1 << 30)
1389 #define KMD_QUEUE (1 << 31)
1391 #define CP_HQD_DEQUEUE_REQUEST 0xC974
1393 #define CP_MQD_CONTROL 0xC99C
1394 #define MQD_VMID(x) ((x) << 0)
1395 #define MQD_VMID_MASK (0xf << 0)
1397 #define DB_RENDER_CONTROL 0x28000
1399 #define PA_SC_RASTER_CONFIG 0x28350
1400 # define RASTER_CONFIG_RB_MAP_0 0
1401 # define RASTER_CONFIG_RB_MAP_1 1
1402 # define RASTER_CONFIG_RB_MAP_2 2
1403 # define RASTER_CONFIG_RB_MAP_3 3
1405 #define VGT_EVENT_INITIATOR 0x28a90
1406 # define SAMPLE_STREAMOUTSTATS1 (1 << 0)
1407 # define SAMPLE_STREAMOUTSTATS2 (2 << 0)
1408 # define SAMPLE_STREAMOUTSTATS3 (3 << 0)
1409 # define CACHE_FLUSH_TS (4 << 0)
1410 # define CACHE_FLUSH (6 << 0)
1411 # define CS_PARTIAL_FLUSH (7 << 0)
1412 # define VGT_STREAMOUT_RESET (10 << 0)
1413 # define END_OF_PIPE_INCR_DE (11 << 0)
1414 # define END_OF_PIPE_IB_END (12 << 0)
1415 # define RST_PIX_CNT (13 << 0)
1416 # define VS_PARTIAL_FLUSH (15 << 0)
1417 # define PS_PARTIAL_FLUSH (16 << 0)
1418 # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0)
1419 # define ZPASS_DONE (21 << 0)
1420 # define CACHE_FLUSH_AND_INV_EVENT (22 << 0)
1421 # define PERFCOUNTER_START (23 << 0)
1422 # define PERFCOUNTER_STOP (24 << 0)
1423 # define PIPELINESTAT_START (25 << 0)
1424 # define PIPELINESTAT_STOP (26 << 0)
1425 # define PERFCOUNTER_SAMPLE (27 << 0)
1426 # define SAMPLE_PIPELINESTAT (30 << 0)
1427 # define SO_VGT_STREAMOUT_FLUSH (31 << 0)
1428 # define SAMPLE_STREAMOUTSTATS (32 << 0)
1429 # define RESET_VTX_CNT (33 << 0)
1430 # define VGT_FLUSH (36 << 0)
1431 # define BOTTOM_OF_PIPE_TS (40 << 0)
1432 # define DB_CACHE_FLUSH_AND_INV (42 << 0)
1433 # define FLUSH_AND_INV_DB_DATA_TS (43 << 0)
1434 # define FLUSH_AND_INV_DB_META (44 << 0)
1435 # define FLUSH_AND_INV_CB_DATA_TS (45 << 0)
1436 # define FLUSH_AND_INV_CB_META (46 << 0)
1437 # define CS_DONE (47 << 0)
1438 # define PS_DONE (48 << 0)
1439 # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0)
1440 # define THREAD_TRACE_START (51 << 0)
1441 # define THREAD_TRACE_STOP (52 << 0)
1442 # define THREAD_TRACE_FLUSH (54 << 0)
1443 # define THREAD_TRACE_FINISH (55 << 0)
1444 # define PIXEL_PIPE_STAT_CONTROL (56 << 0)
1445 # define PIXEL_PIPE_STAT_DUMP (57 << 0)
1446 # define PIXEL_PIPE_STAT_RESET (58 << 0)
1448 #define SCRATCH_REG0 0x30100
1449 #define SCRATCH_REG1 0x30104
1450 #define SCRATCH_REG2 0x30108
1451 #define SCRATCH_REG3 0x3010C
1452 #define SCRATCH_REG4 0x30110
1453 #define SCRATCH_REG5 0x30114
1454 #define SCRATCH_REG6 0x30118
1455 #define SCRATCH_REG7 0x3011C
1457 #define SCRATCH_UMSK 0x30140
1458 #define SCRATCH_ADDR 0x30144
1460 #define CP_SEM_WAIT_TIMER 0x301BC
1462 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x301C8
1464 #define CP_WAIT_REG_MEM_TIMEOUT 0x301D0
1466 #define GRBM_GFX_INDEX 0x30800
1467 #define INSTANCE_INDEX(x) ((x) << 0)
1468 #define SH_INDEX(x) ((x) << 8)
1469 #define SE_INDEX(x) ((x) << 16)
1470 #define SH_BROADCAST_WRITES (1 << 29)
1471 #define INSTANCE_BROADCAST_WRITES (1 << 30)
1472 #define SE_BROADCAST_WRITES (1 << 31)
1474 #define VGT_ESGS_RING_SIZE 0x30900
1475 #define VGT_GSVS_RING_SIZE 0x30904
1476 #define VGT_PRIMITIVE_TYPE 0x30908
1477 #define VGT_INDEX_TYPE 0x3090C
1479 #define VGT_NUM_INDICES 0x30930
1480 #define VGT_NUM_INSTANCES 0x30934
1481 #define VGT_TF_RING_SIZE 0x30938
1482 #define VGT_HS_OFFCHIP_PARAM 0x3093C
1483 #define VGT_TF_MEMORY_BASE 0x30940
1485 #define PA_SU_LINE_STIPPLE_VALUE 0x30a00
1486 #define PA_SC_LINE_STIPPLE_STATE 0x30a04
1488 #define SQC_CACHES 0x30d20
1490 #define CP_PERFMON_CNTL 0x36020
1492 #define CGTS_SM_CTRL_REG 0x3c000
1493 #define SM_MODE(x) ((x) << 17)
1494 #define SM_MODE_MASK (0x7 << 17)
1495 #define SM_MODE_ENABLE (1 << 20)
1496 #define CGTS_OVERRIDE (1 << 21)
1497 #define CGTS_LS_OVERRIDE (1 << 22)
1498 #define ON_MONITOR_ADD_EN (1 << 23)
1499 #define ON_MONITOR_ADD(x) ((x) << 24)
1500 #define ON_MONITOR_ADD_MASK (0xff << 24)
1502 #define CGTS_TCC_DISABLE 0x3c00c
1503 #define CGTS_USER_TCC_DISABLE 0x3c010
1504 #define TCC_DISABLE_MASK 0xFFFF0000
1505 #define TCC_DISABLE_SHIFT 16
1507 #define CB_CGTT_SCLK_CTRL 0x3c2a0
1512 #define PACKET_TYPE0 0
1513 #define PACKET_TYPE1 1
1514 #define PACKET_TYPE2 2
1515 #define PACKET_TYPE3 3
1517 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
1518 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
1519 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
1520 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
1521 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
1522 (((reg) >> 2) & 0xFFFF) | \
1523 ((n) & 0x3FFF) << 16)
1524 #define CP_PACKET2 0x80000000
1525 #define PACKET2_PAD_SHIFT 0
1526 #define PACKET2_PAD_MASK (0x3fffffff << 0)
1528 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
1530 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
1531 (((op) & 0xFF) << 8) | \
1532 ((n) & 0x3FFF) << 16)
1534 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
1536 /* Packet 3 types */
1537 #define PACKET3_NOP 0x10
1538 #define PACKET3_SET_BASE 0x11
1539 #define PACKET3_BASE_INDEX(x) ((x) << 0)
1540 #define CE_PARTITION_BASE 3
1541 #define PACKET3_CLEAR_STATE 0x12
1542 #define PACKET3_INDEX_BUFFER_SIZE 0x13
1543 #define PACKET3_DISPATCH_DIRECT 0x15
1544 #define PACKET3_DISPATCH_INDIRECT 0x16
1545 #define PACKET3_ATOMIC_GDS 0x1D
1546 #define PACKET3_ATOMIC_MEM 0x1E
1547 #define PACKET3_OCCLUSION_QUERY 0x1F
1548 #define PACKET3_SET_PREDICATION 0x20
1549 #define PACKET3_REG_RMW 0x21
1550 #define PACKET3_COND_EXEC 0x22
1551 #define PACKET3_PRED_EXEC 0x23
1552 #define PACKET3_DRAW_INDIRECT 0x24
1553 #define PACKET3_DRAW_INDEX_INDIRECT 0x25
1554 #define PACKET3_INDEX_BASE 0x26
1555 #define PACKET3_DRAW_INDEX_2 0x27
1556 #define PACKET3_CONTEXT_CONTROL 0x28
1557 #define PACKET3_INDEX_TYPE 0x2A
1558 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C
1559 #define PACKET3_DRAW_INDEX_AUTO 0x2D
1560 #define PACKET3_NUM_INSTANCES 0x2F
1561 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
1562 #define PACKET3_INDIRECT_BUFFER_CONST 0x33
1563 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
1564 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
1565 #define PACKET3_DRAW_PREAMBLE 0x36
1566 #define PACKET3_WRITE_DATA 0x37
1567 #define WRITE_DATA_DST_SEL(x) ((x) << 8)
1569 * 1 - memory (sync - via GRBM)
1573 * 5 - memory (async - direct)
1575 #define WR_ONE_ADDR (1 << 16)
1576 #define WR_CONFIRM (1 << 20)
1577 #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)
1581 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
1586 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
1587 #define PACKET3_MEM_SEMAPHORE 0x39
1588 # define PACKET3_SEM_USE_MAILBOX (0x1 << 16)
1589 # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */
1590 # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */
1591 # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
1592 # define PACKET3_SEM_SEL_WAIT (0x7 << 29)
1593 #define PACKET3_COPY_DW 0x3B
1594 #define PACKET3_WAIT_REG_MEM 0x3C
1595 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
1604 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
1608 #define WAIT_REG_MEM_OPERATION(x) ((x) << 6)
1610 * 1 - wr_wait_wr_reg
1612 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
1616 #define PACKET3_INDIRECT_BUFFER 0x3F
1617 #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22)
1618 #define INDIRECT_BUFFER_VALID (1 << 23)
1619 #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28)
1624 #define PACKET3_COPY_DATA 0x40
1625 #define PACKET3_PFP_SYNC_ME 0x42
1626 #define PACKET3_SURFACE_SYNC 0x43
1627 # define PACKET3_DEST_BASE_0_ENA (1 << 0)
1628 # define PACKET3_DEST_BASE_1_ENA (1 << 1)
1629 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
1630 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
1631 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
1632 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
1633 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
1634 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
1635 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
1636 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
1637 # define PACKET3_DB_DEST_BASE_ENA (1 << 14)
1638 # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15)
1639 # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */
1640 # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */
1641 # define PACKET3_DEST_BASE_2_ENA (1 << 19)
1642 # define PACKET3_DEST_BASE_3_ENA (1 << 21)
1643 # define PACKET3_TCL1_ACTION_ENA (1 << 22)
1644 # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */
1645 # define PACKET3_CB_ACTION_ENA (1 << 25)
1646 # define PACKET3_DB_ACTION_ENA (1 << 26)
1647 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
1648 # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28)
1649 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
1650 #define PACKET3_COND_WRITE 0x45
1651 #define PACKET3_EVENT_WRITE 0x46
1652 #define EVENT_TYPE(x) ((x) << 0)
1653 #define EVENT_INDEX(x) ((x) << 8)
1654 /* 0 - any non-TS event
1655 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
1656 * 2 - SAMPLE_PIPELINESTAT
1657 * 3 - SAMPLE_STREAMOUTSTAT*
1658 * 4 - *S_PARTIAL_FLUSH
1662 #define PACKET3_EVENT_WRITE_EOP 0x47
1663 #define EOP_TCL1_VOL_ACTION_EN (1 << 12)
1664 #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */
1665 #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */
1666 #define EOP_TCL1_ACTION_EN (1 << 16)
1667 #define EOP_TC_ACTION_EN (1 << 17) /* L2 */
1668 #define EOP_CACHE_POLICY(x) ((x) << 25)
1673 #define EOP_TCL2_VOLATILE (1 << 27)
1674 #define DATA_SEL(x) ((x) << 29)
1676 * 1 - send low 32bit data
1677 * 2 - send 64bit data
1678 * 3 - send 64bit GPU counter value
1679 * 4 - send 64bit sys counter value
1681 #define INT_SEL(x) ((x) << 24)
1683 * 1 - interrupt only (DATA_SEL = 0)
1684 * 2 - interrupt when data write is confirmed
1686 #define DST_SEL(x) ((x) << 16)
1690 #define PACKET3_EVENT_WRITE_EOS 0x48
1691 #define PACKET3_RELEASE_MEM 0x49
1692 #define PACKET3_PREAMBLE_CNTL 0x4A
1693 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
1694 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
1695 #define PACKET3_DMA_DATA 0x50
1696 #define PACKET3_AQUIRE_MEM 0x58
1697 #define PACKET3_REWIND 0x59
1698 #define PACKET3_LOAD_UCONFIG_REG 0x5E
1699 #define PACKET3_LOAD_SH_REG 0x5F
1700 #define PACKET3_LOAD_CONFIG_REG 0x60
1701 #define PACKET3_LOAD_CONTEXT_REG 0x61
1702 #define PACKET3_SET_CONFIG_REG 0x68
1703 #define PACKET3_SET_CONFIG_REG_START 0x00008000
1704 #define PACKET3_SET_CONFIG_REG_END 0x0000b000
1705 #define PACKET3_SET_CONTEXT_REG 0x69
1706 #define PACKET3_SET_CONTEXT_REG_START 0x00028000
1707 #define PACKET3_SET_CONTEXT_REG_END 0x00029000
1708 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
1709 #define PACKET3_SET_SH_REG 0x76
1710 #define PACKET3_SET_SH_REG_START 0x0000b000
1711 #define PACKET3_SET_SH_REG_END 0x0000c000
1712 #define PACKET3_SET_SH_REG_OFFSET 0x77
1713 #define PACKET3_SET_QUEUE_REG 0x78
1714 #define PACKET3_SET_UCONFIG_REG 0x79
1715 #define PACKET3_SET_UCONFIG_REG_START 0x00030000
1716 #define PACKET3_SET_UCONFIG_REG_END 0x00031000
1717 #define PACKET3_SCRATCH_RAM_WRITE 0x7D
1718 #define PACKET3_SCRATCH_RAM_READ 0x7E
1719 #define PACKET3_LOAD_CONST_RAM 0x80
1720 #define PACKET3_WRITE_CONST_RAM 0x81
1721 #define PACKET3_DUMP_CONST_RAM 0x83
1722 #define PACKET3_INCREMENT_CE_COUNTER 0x84
1723 #define PACKET3_INCREMENT_DE_COUNTER 0x85
1724 #define PACKET3_WAIT_ON_CE_COUNTER 0x86
1725 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
1726 #define PACKET3_SWITCH_BUFFER 0x8B
1728 /* SDMA - first instance at 0xd000, second at 0xd800 */
1729 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */
1730 #define SDMA1_REGISTER_OFFSET 0x800 /* not a register */
1732 #define SDMA0_UCODE_ADDR 0xD000
1733 #define SDMA0_UCODE_DATA 0xD004
1734 #define SDMA0_POWER_CNTL 0xD008
1735 #define SDMA0_CLK_CTRL 0xD00C
1737 #define SDMA0_CNTL 0xD010
1738 # define TRAP_ENABLE (1 << 0)
1739 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
1740 # define SEM_WAIT_INT_ENABLE (1 << 2)
1741 # define DATA_SWAP_ENABLE (1 << 3)
1742 # define FENCE_SWAP_ENABLE (1 << 4)
1743 # define AUTO_CTXSW_ENABLE (1 << 18)
1744 # define CTXEMPTY_INT_ENABLE (1 << 28)
1746 #define SDMA0_TILING_CONFIG 0xD018
1748 #define SDMA0_SEM_INCOMPLETE_TIMER_CNTL 0xD020
1749 #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0xD024
1751 #define SDMA0_STATUS_REG 0xd034
1752 # define SDMA_IDLE (1 << 0)
1754 #define SDMA0_ME_CNTL 0xD048
1755 # define SDMA_HALT (1 << 0)
1757 #define SDMA0_GFX_RB_CNTL 0xD200
1758 # define SDMA_RB_ENABLE (1 << 0)
1759 # define SDMA_RB_SIZE(x) ((x) << 1) /* log2 */
1760 # define SDMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
1761 # define SDMA_RPTR_WRITEBACK_ENABLE (1 << 12)
1762 # define SDMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
1763 # define SDMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
1764 #define SDMA0_GFX_RB_BASE 0xD204
1765 #define SDMA0_GFX_RB_BASE_HI 0xD208
1766 #define SDMA0_GFX_RB_RPTR 0xD20C
1767 #define SDMA0_GFX_RB_WPTR 0xD210
1769 #define SDMA0_GFX_RB_RPTR_ADDR_HI 0xD220
1770 #define SDMA0_GFX_RB_RPTR_ADDR_LO 0xD224
1771 #define SDMA0_GFX_IB_CNTL 0xD228
1772 # define SDMA_IB_ENABLE (1 << 0)
1773 # define SDMA_IB_SWAP_ENABLE (1 << 4)
1774 # define SDMA_SWITCH_INSIDE_IB (1 << 8)
1775 # define SDMA_CMD_VMID(x) ((x) << 16)
1777 #define SDMA0_GFX_VIRTUAL_ADDR 0xD29C
1778 #define SDMA0_GFX_APE1_CNTL 0xD2A0
1780 #define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \
1781 (((sub_op) & 0xFF) << 8) | \
1782 (((op) & 0xFF) << 0))
1784 #define SDMA_OPCODE_NOP 0
1785 #define SDMA_OPCODE_COPY 1
1786 # define SDMA_COPY_SUB_OPCODE_LINEAR 0
1787 # define SDMA_COPY_SUB_OPCODE_TILED 1
1788 # define SDMA_COPY_SUB_OPCODE_SOA 3
1789 # define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4
1790 # define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5
1791 # define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6
1792 #define SDMA_OPCODE_WRITE 2
1793 # define SDMA_WRITE_SUB_OPCODE_LINEAR 0
1794 # define SDMA_WRTIE_SUB_OPCODE_TILED 1
1795 #define SDMA_OPCODE_INDIRECT_BUFFER 4
1796 #define SDMA_OPCODE_FENCE 5
1797 #define SDMA_OPCODE_TRAP 6
1798 #define SDMA_OPCODE_SEMAPHORE 7
1799 # define SDMA_SEMAPHORE_EXTRA_O (1 << 13)
1803 # define SDMA_SEMAPHORE_EXTRA_S (1 << 14)
1807 # define SDMA_SEMAPHORE_EXTRA_M (1 << 15)
1809 #define SDMA_OPCODE_POLL_REG_MEM 8
1810 # define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10)
1812 * 1 - wr_wait_wr_reg
1814 # define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12)
1823 # define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15)
1827 #define SDMA_OPCODE_COND_EXEC 9
1828 #define SDMA_OPCODE_CONSTANT_FILL 11
1829 # define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14)
1833 #define SDMA_OPCODE_GENERATE_PTE_PDE 12
1834 #define SDMA_OPCODE_TIMESTAMP 13
1835 # define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0
1836 # define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1
1837 # define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2
1838 #define SDMA_OPCODE_SRBM_WRITE 14
1839 # define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12)
1844 #define UVD_UDEC_ADDR_CONFIG 0xef4c
1845 #define UVD_UDEC_DB_ADDR_CONFIG 0xef50
1846 #define UVD_UDEC_DBW_ADDR_CONFIG 0xef54
1848 #define UVD_LMI_EXT40_ADDR 0xf498
1849 #define UVD_LMI_ADDR_EXT 0xf594
1850 #define UVD_VCPU_CACHE_OFFSET0 0xf608
1851 #define UVD_VCPU_CACHE_SIZE0 0xf60c
1852 #define UVD_VCPU_CACHE_OFFSET1 0xf610
1853 #define UVD_VCPU_CACHE_SIZE1 0xf614
1854 #define UVD_VCPU_CACHE_OFFSET2 0xf618
1855 #define UVD_VCPU_CACHE_SIZE2 0xf61c
1857 #define UVD_RBC_RB_RPTR 0xf690
1858 #define UVD_RBC_RB_WPTR 0xf694
1860 #define UVD_CGC_CTRL 0xF4B0
1861 # define DCM (1 << 0)
1862 # define CG_DT(x) ((x) << 2)
1863 # define CG_DT_MASK (0xf << 2)
1864 # define CLK_OD(x) ((x) << 6)
1865 # define CLK_OD_MASK (0x1f << 6)
1869 #define CG_DCLK_CNTL 0xC050009C
1870 # define DCLK_DIVIDER_MASK 0x7f
1871 # define DCLK_DIR_CNTL_EN (1 << 8)
1872 #define CG_DCLK_STATUS 0xC05000A0
1873 # define DCLK_STATUS (1 << 0)
1874 #define CG_VCLK_CNTL 0xC05000A4
1875 #define CG_VCLK_STATUS 0xC05000A8
1877 /* UVD CTX indirect */
1878 #define UVD_CGC_MEM_CTRL 0xC0
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