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drm/radeon/kms: add support for gui idle interrupts (v4)
[deliverable/linux.git] / drivers / gpu / drm / radeon / evergreen.c
1 /*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include "drmP.h"
28 #include "radeon.h"
29 #include "radeon_asic.h"
30 #include "radeon_drm.h"
31 #include "evergreend.h"
32 #include "atom.h"
33 #include "avivod.h"
34 #include "evergreen_reg.h"
35
36 #define EVERGREEN_PFP_UCODE_SIZE 1120
37 #define EVERGREEN_PM4_UCODE_SIZE 1376
38
39 static void evergreen_gpu_init(struct radeon_device *rdev);
40 void evergreen_fini(struct radeon_device *rdev);
41
42 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
43 {
44 bool connected = false;
45
46 switch (hpd) {
47 case RADEON_HPD_1:
48 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
49 connected = true;
50 break;
51 case RADEON_HPD_2:
52 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
53 connected = true;
54 break;
55 case RADEON_HPD_3:
56 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
57 connected = true;
58 break;
59 case RADEON_HPD_4:
60 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
61 connected = true;
62 break;
63 case RADEON_HPD_5:
64 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
65 connected = true;
66 break;
67 case RADEON_HPD_6:
68 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
69 connected = true;
70 break;
71 default:
72 break;
73 }
74
75 return connected;
76 }
77
78 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
79 enum radeon_hpd_id hpd)
80 {
81 u32 tmp;
82 bool connected = evergreen_hpd_sense(rdev, hpd);
83
84 switch (hpd) {
85 case RADEON_HPD_1:
86 tmp = RREG32(DC_HPD1_INT_CONTROL);
87 if (connected)
88 tmp &= ~DC_HPDx_INT_POLARITY;
89 else
90 tmp |= DC_HPDx_INT_POLARITY;
91 WREG32(DC_HPD1_INT_CONTROL, tmp);
92 break;
93 case RADEON_HPD_2:
94 tmp = RREG32(DC_HPD2_INT_CONTROL);
95 if (connected)
96 tmp &= ~DC_HPDx_INT_POLARITY;
97 else
98 tmp |= DC_HPDx_INT_POLARITY;
99 WREG32(DC_HPD2_INT_CONTROL, tmp);
100 break;
101 case RADEON_HPD_3:
102 tmp = RREG32(DC_HPD3_INT_CONTROL);
103 if (connected)
104 tmp &= ~DC_HPDx_INT_POLARITY;
105 else
106 tmp |= DC_HPDx_INT_POLARITY;
107 WREG32(DC_HPD3_INT_CONTROL, tmp);
108 break;
109 case RADEON_HPD_4:
110 tmp = RREG32(DC_HPD4_INT_CONTROL);
111 if (connected)
112 tmp &= ~DC_HPDx_INT_POLARITY;
113 else
114 tmp |= DC_HPDx_INT_POLARITY;
115 WREG32(DC_HPD4_INT_CONTROL, tmp);
116 break;
117 case RADEON_HPD_5:
118 tmp = RREG32(DC_HPD5_INT_CONTROL);
119 if (connected)
120 tmp &= ~DC_HPDx_INT_POLARITY;
121 else
122 tmp |= DC_HPDx_INT_POLARITY;
123 WREG32(DC_HPD5_INT_CONTROL, tmp);
124 break;
125 case RADEON_HPD_6:
126 tmp = RREG32(DC_HPD6_INT_CONTROL);
127 if (connected)
128 tmp &= ~DC_HPDx_INT_POLARITY;
129 else
130 tmp |= DC_HPDx_INT_POLARITY;
131 WREG32(DC_HPD6_INT_CONTROL, tmp);
132 break;
133 default:
134 break;
135 }
136 }
137
138 void evergreen_hpd_init(struct radeon_device *rdev)
139 {
140 struct drm_device *dev = rdev->ddev;
141 struct drm_connector *connector;
142 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
143 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
144
145 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
146 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
147 switch (radeon_connector->hpd.hpd) {
148 case RADEON_HPD_1:
149 WREG32(DC_HPD1_CONTROL, tmp);
150 rdev->irq.hpd[0] = true;
151 break;
152 case RADEON_HPD_2:
153 WREG32(DC_HPD2_CONTROL, tmp);
154 rdev->irq.hpd[1] = true;
155 break;
156 case RADEON_HPD_3:
157 WREG32(DC_HPD3_CONTROL, tmp);
158 rdev->irq.hpd[2] = true;
159 break;
160 case RADEON_HPD_4:
161 WREG32(DC_HPD4_CONTROL, tmp);
162 rdev->irq.hpd[3] = true;
163 break;
164 case RADEON_HPD_5:
165 WREG32(DC_HPD5_CONTROL, tmp);
166 rdev->irq.hpd[4] = true;
167 break;
168 case RADEON_HPD_6:
169 WREG32(DC_HPD6_CONTROL, tmp);
170 rdev->irq.hpd[5] = true;
171 break;
172 default:
173 break;
174 }
175 }
176 if (rdev->irq.installed)
177 evergreen_irq_set(rdev);
178 }
179
180 void evergreen_hpd_fini(struct radeon_device *rdev)
181 {
182 struct drm_device *dev = rdev->ddev;
183 struct drm_connector *connector;
184
185 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
186 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
187 switch (radeon_connector->hpd.hpd) {
188 case RADEON_HPD_1:
189 WREG32(DC_HPD1_CONTROL, 0);
190 rdev->irq.hpd[0] = false;
191 break;
192 case RADEON_HPD_2:
193 WREG32(DC_HPD2_CONTROL, 0);
194 rdev->irq.hpd[1] = false;
195 break;
196 case RADEON_HPD_3:
197 WREG32(DC_HPD3_CONTROL, 0);
198 rdev->irq.hpd[2] = false;
199 break;
200 case RADEON_HPD_4:
201 WREG32(DC_HPD4_CONTROL, 0);
202 rdev->irq.hpd[3] = false;
203 break;
204 case RADEON_HPD_5:
205 WREG32(DC_HPD5_CONTROL, 0);
206 rdev->irq.hpd[4] = false;
207 break;
208 case RADEON_HPD_6:
209 WREG32(DC_HPD6_CONTROL, 0);
210 rdev->irq.hpd[5] = false;
211 break;
212 default:
213 break;
214 }
215 }
216 }
217
218 void evergreen_bandwidth_update(struct radeon_device *rdev)
219 {
220 /* XXX */
221 }
222
223 static int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
224 {
225 unsigned i;
226 u32 tmp;
227
228 for (i = 0; i < rdev->usec_timeout; i++) {
229 /* read MC_STATUS */
230 tmp = RREG32(SRBM_STATUS) & 0x1F00;
231 if (!tmp)
232 return 0;
233 udelay(1);
234 }
235 return -1;
236 }
237
238 /*
239 * GART
240 */
241 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
242 {
243 unsigned i;
244 u32 tmp;
245
246 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
247 for (i = 0; i < rdev->usec_timeout; i++) {
248 /* read MC_STATUS */
249 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
250 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
251 if (tmp == 2) {
252 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
253 return;
254 }
255 if (tmp) {
256 return;
257 }
258 udelay(1);
259 }
260 }
261
262 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
263 {
264 u32 tmp;
265 int r;
266
267 if (rdev->gart.table.vram.robj == NULL) {
268 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
269 return -EINVAL;
270 }
271 r = radeon_gart_table_vram_pin(rdev);
272 if (r)
273 return r;
274 radeon_gart_restore(rdev);
275 /* Setup L2 cache */
276 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
277 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
278 EFFECTIVE_L2_QUEUE_SIZE(7));
279 WREG32(VM_L2_CNTL2, 0);
280 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
281 /* Setup TLB control */
282 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
283 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
284 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
285 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
286 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
287 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
288 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
289 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
290 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
291 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
292 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
293 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
294 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
295 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
296 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
297 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
298 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
299 (u32)(rdev->dummy_page.addr >> 12));
300 WREG32(VM_CONTEXT1_CNTL, 0);
301
302 evergreen_pcie_gart_tlb_flush(rdev);
303 rdev->gart.ready = true;
304 return 0;
305 }
306
307 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
308 {
309 u32 tmp;
310 int r;
311
312 /* Disable all tables */
313 WREG32(VM_CONTEXT0_CNTL, 0);
314 WREG32(VM_CONTEXT1_CNTL, 0);
315
316 /* Setup L2 cache */
317 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
318 EFFECTIVE_L2_QUEUE_SIZE(7));
319 WREG32(VM_L2_CNTL2, 0);
320 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
321 /* Setup TLB control */
322 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
323 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
324 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
325 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
326 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
327 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
328 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
329 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
330 if (rdev->gart.table.vram.robj) {
331 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
332 if (likely(r == 0)) {
333 radeon_bo_kunmap(rdev->gart.table.vram.robj);
334 radeon_bo_unpin(rdev->gart.table.vram.robj);
335 radeon_bo_unreserve(rdev->gart.table.vram.robj);
336 }
337 }
338 }
339
340 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
341 {
342 evergreen_pcie_gart_disable(rdev);
343 radeon_gart_table_vram_free(rdev);
344 radeon_gart_fini(rdev);
345 }
346
347
348 void evergreen_agp_enable(struct radeon_device *rdev)
349 {
350 u32 tmp;
351
352 /* Setup L2 cache */
353 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
354 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
355 EFFECTIVE_L2_QUEUE_SIZE(7));
356 WREG32(VM_L2_CNTL2, 0);
357 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
358 /* Setup TLB control */
359 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
360 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
361 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
362 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
363 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
364 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
365 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
366 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
367 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
368 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
369 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
370 WREG32(VM_CONTEXT0_CNTL, 0);
371 WREG32(VM_CONTEXT1_CNTL, 0);
372 }
373
374 static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
375 {
376 save->vga_control[0] = RREG32(D1VGA_CONTROL);
377 save->vga_control[1] = RREG32(D2VGA_CONTROL);
378 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
379 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
380 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
381 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
382 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
383 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
384 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
385 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
386 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
387 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
388 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
389 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
390
391 /* Stop all video */
392 WREG32(VGA_RENDER_CONTROL, 0);
393 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
394 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
395 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
396 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
397 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
398 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
399 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
400 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
401 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
402 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
403 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
404 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
405 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
406 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
407 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
408 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
409 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
410 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
411
412 WREG32(D1VGA_CONTROL, 0);
413 WREG32(D2VGA_CONTROL, 0);
414 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
415 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
416 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
417 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
418 }
419
420 static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
421 {
422 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
423 upper_32_bits(rdev->mc.vram_start));
424 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
425 upper_32_bits(rdev->mc.vram_start));
426 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
427 (u32)rdev->mc.vram_start);
428 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
429 (u32)rdev->mc.vram_start);
430
431 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
432 upper_32_bits(rdev->mc.vram_start));
433 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
434 upper_32_bits(rdev->mc.vram_start));
435 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
436 (u32)rdev->mc.vram_start);
437 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
438 (u32)rdev->mc.vram_start);
439
440 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
441 upper_32_bits(rdev->mc.vram_start));
442 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
443 upper_32_bits(rdev->mc.vram_start));
444 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
445 (u32)rdev->mc.vram_start);
446 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
447 (u32)rdev->mc.vram_start);
448
449 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
450 upper_32_bits(rdev->mc.vram_start));
451 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
452 upper_32_bits(rdev->mc.vram_start));
453 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
454 (u32)rdev->mc.vram_start);
455 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
456 (u32)rdev->mc.vram_start);
457
458 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
459 upper_32_bits(rdev->mc.vram_start));
460 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
461 upper_32_bits(rdev->mc.vram_start));
462 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
463 (u32)rdev->mc.vram_start);
464 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
465 (u32)rdev->mc.vram_start);
466
467 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
468 upper_32_bits(rdev->mc.vram_start));
469 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
470 upper_32_bits(rdev->mc.vram_start));
471 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
472 (u32)rdev->mc.vram_start);
473 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
474 (u32)rdev->mc.vram_start);
475
476 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
477 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
478 /* Unlock host access */
479 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
480 mdelay(1);
481 /* Restore video state */
482 WREG32(D1VGA_CONTROL, save->vga_control[0]);
483 WREG32(D2VGA_CONTROL, save->vga_control[1]);
484 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
485 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
486 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
487 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
488 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
489 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
490 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
491 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
492 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
493 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
494 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
495 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
496 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
497 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
498 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
499 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
500 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
501 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
502 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
503 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
504 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
505 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
506 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
507 }
508
509 static void evergreen_mc_program(struct radeon_device *rdev)
510 {
511 struct evergreen_mc_save save;
512 u32 tmp;
513 int i, j;
514
515 /* Initialize HDP */
516 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
517 WREG32((0x2c14 + j), 0x00000000);
518 WREG32((0x2c18 + j), 0x00000000);
519 WREG32((0x2c1c + j), 0x00000000);
520 WREG32((0x2c20 + j), 0x00000000);
521 WREG32((0x2c24 + j), 0x00000000);
522 }
523 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
524
525 evergreen_mc_stop(rdev, &save);
526 if (evergreen_mc_wait_for_idle(rdev)) {
527 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
528 }
529 /* Lockout access through VGA aperture*/
530 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
531 /* Update configuration */
532 if (rdev->flags & RADEON_IS_AGP) {
533 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
534 /* VRAM before AGP */
535 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
536 rdev->mc.vram_start >> 12);
537 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
538 rdev->mc.gtt_end >> 12);
539 } else {
540 /* VRAM after AGP */
541 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
542 rdev->mc.gtt_start >> 12);
543 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
544 rdev->mc.vram_end >> 12);
545 }
546 } else {
547 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
548 rdev->mc.vram_start >> 12);
549 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
550 rdev->mc.vram_end >> 12);
551 }
552 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
553 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
554 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
555 WREG32(MC_VM_FB_LOCATION, tmp);
556 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
557 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
558 WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
559 if (rdev->flags & RADEON_IS_AGP) {
560 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
561 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
562 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
563 } else {
564 WREG32(MC_VM_AGP_BASE, 0);
565 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
566 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
567 }
568 if (evergreen_mc_wait_for_idle(rdev)) {
569 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
570 }
571 evergreen_mc_resume(rdev, &save);
572 /* we need to own VRAM, so turn off the VGA renderer here
573 * to stop it overwriting our objects */
574 rv515_vga_render_disable(rdev);
575 }
576
577 /*
578 * CP.
579 */
580
581 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
582 {
583 const __be32 *fw_data;
584 int i;
585
586 if (!rdev->me_fw || !rdev->pfp_fw)
587 return -EINVAL;
588
589 r700_cp_stop(rdev);
590 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
591
592 fw_data = (const __be32 *)rdev->pfp_fw->data;
593 WREG32(CP_PFP_UCODE_ADDR, 0);
594 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
595 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
596 WREG32(CP_PFP_UCODE_ADDR, 0);
597
598 fw_data = (const __be32 *)rdev->me_fw->data;
599 WREG32(CP_ME_RAM_WADDR, 0);
600 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
601 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
602
603 WREG32(CP_PFP_UCODE_ADDR, 0);
604 WREG32(CP_ME_RAM_WADDR, 0);
605 WREG32(CP_ME_RAM_RADDR, 0);
606 return 0;
607 }
608
609 int evergreen_cp_resume(struct radeon_device *rdev)
610 {
611 u32 tmp;
612 u32 rb_bufsz;
613 int r;
614
615 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
616 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
617 SOFT_RESET_PA |
618 SOFT_RESET_SH |
619 SOFT_RESET_VGT |
620 SOFT_RESET_SX));
621 RREG32(GRBM_SOFT_RESET);
622 mdelay(15);
623 WREG32(GRBM_SOFT_RESET, 0);
624 RREG32(GRBM_SOFT_RESET);
625
626 /* Set ring buffer size */
627 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
628 tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
629 #ifdef __BIG_ENDIAN
630 tmp |= BUF_SWAP_32BIT;
631 #endif
632 WREG32(CP_RB_CNTL, tmp);
633 WREG32(CP_SEM_WAIT_TIMER, 0x4);
634
635 /* Set the write pointer delay */
636 WREG32(CP_RB_WPTR_DELAY, 0);
637
638 /* Initialize the ring buffer's read and write pointers */
639 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
640 WREG32(CP_RB_RPTR_WR, 0);
641 WREG32(CP_RB_WPTR, 0);
642 WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
643 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
644 mdelay(1);
645 WREG32(CP_RB_CNTL, tmp);
646
647 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
648 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
649
650 rdev->cp.rptr = RREG32(CP_RB_RPTR);
651 rdev->cp.wptr = RREG32(CP_RB_WPTR);
652
653 r600_cp_start(rdev);
654 rdev->cp.ready = true;
655 r = radeon_ring_test(rdev);
656 if (r) {
657 rdev->cp.ready = false;
658 return r;
659 }
660 return 0;
661 }
662
663 /*
664 * Core functions
665 */
666 static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
667 u32 num_tile_pipes,
668 u32 num_backends,
669 u32 backend_disable_mask)
670 {
671 u32 backend_map = 0;
672 u32 enabled_backends_mask = 0;
673 u32 enabled_backends_count = 0;
674 u32 cur_pipe;
675 u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
676 u32 cur_backend = 0;
677 u32 i;
678 bool force_no_swizzle;
679
680 if (num_tile_pipes > EVERGREEN_MAX_PIPES)
681 num_tile_pipes = EVERGREEN_MAX_PIPES;
682 if (num_tile_pipes < 1)
683 num_tile_pipes = 1;
684 if (num_backends > EVERGREEN_MAX_BACKENDS)
685 num_backends = EVERGREEN_MAX_BACKENDS;
686 if (num_backends < 1)
687 num_backends = 1;
688
689 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
690 if (((backend_disable_mask >> i) & 1) == 0) {
691 enabled_backends_mask |= (1 << i);
692 ++enabled_backends_count;
693 }
694 if (enabled_backends_count == num_backends)
695 break;
696 }
697
698 if (enabled_backends_count == 0) {
699 enabled_backends_mask = 1;
700 enabled_backends_count = 1;
701 }
702
703 if (enabled_backends_count != num_backends)
704 num_backends = enabled_backends_count;
705
706 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
707 switch (rdev->family) {
708 case CHIP_CEDAR:
709 case CHIP_REDWOOD:
710 force_no_swizzle = false;
711 break;
712 case CHIP_CYPRESS:
713 case CHIP_HEMLOCK:
714 case CHIP_JUNIPER:
715 default:
716 force_no_swizzle = true;
717 break;
718 }
719 if (force_no_swizzle) {
720 bool last_backend_enabled = false;
721
722 force_no_swizzle = false;
723 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
724 if (((enabled_backends_mask >> i) & 1) == 1) {
725 if (last_backend_enabled)
726 force_no_swizzle = true;
727 last_backend_enabled = true;
728 } else
729 last_backend_enabled = false;
730 }
731 }
732
733 switch (num_tile_pipes) {
734 case 1:
735 case 3:
736 case 5:
737 case 7:
738 DRM_ERROR("odd number of pipes!\n");
739 break;
740 case 2:
741 swizzle_pipe[0] = 0;
742 swizzle_pipe[1] = 1;
743 break;
744 case 4:
745 if (force_no_swizzle) {
746 swizzle_pipe[0] = 0;
747 swizzle_pipe[1] = 1;
748 swizzle_pipe[2] = 2;
749 swizzle_pipe[3] = 3;
750 } else {
751 swizzle_pipe[0] = 0;
752 swizzle_pipe[1] = 2;
753 swizzle_pipe[2] = 1;
754 swizzle_pipe[3] = 3;
755 }
756 break;
757 case 6:
758 if (force_no_swizzle) {
759 swizzle_pipe[0] = 0;
760 swizzle_pipe[1] = 1;
761 swizzle_pipe[2] = 2;
762 swizzle_pipe[3] = 3;
763 swizzle_pipe[4] = 4;
764 swizzle_pipe[5] = 5;
765 } else {
766 swizzle_pipe[0] = 0;
767 swizzle_pipe[1] = 2;
768 swizzle_pipe[2] = 4;
769 swizzle_pipe[3] = 1;
770 swizzle_pipe[4] = 3;
771 swizzle_pipe[5] = 5;
772 }
773 break;
774 case 8:
775 if (force_no_swizzle) {
776 swizzle_pipe[0] = 0;
777 swizzle_pipe[1] = 1;
778 swizzle_pipe[2] = 2;
779 swizzle_pipe[3] = 3;
780 swizzle_pipe[4] = 4;
781 swizzle_pipe[5] = 5;
782 swizzle_pipe[6] = 6;
783 swizzle_pipe[7] = 7;
784 } else {
785 swizzle_pipe[0] = 0;
786 swizzle_pipe[1] = 2;
787 swizzle_pipe[2] = 4;
788 swizzle_pipe[3] = 6;
789 swizzle_pipe[4] = 1;
790 swizzle_pipe[5] = 3;
791 swizzle_pipe[6] = 5;
792 swizzle_pipe[7] = 7;
793 }
794 break;
795 }
796
797 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
798 while (((1 << cur_backend) & enabled_backends_mask) == 0)
799 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
800
801 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
802
803 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
804 }
805
806 return backend_map;
807 }
808
809 static void evergreen_gpu_init(struct radeon_device *rdev)
810 {
811 u32 cc_rb_backend_disable = 0;
812 u32 cc_gc_shader_pipe_config;
813 u32 gb_addr_config = 0;
814 u32 mc_shared_chmap, mc_arb_ramcfg;
815 u32 gb_backend_map;
816 u32 grbm_gfx_index;
817 u32 sx_debug_1;
818 u32 smx_dc_ctl0;
819 u32 sq_config;
820 u32 sq_lds_resource_mgmt;
821 u32 sq_gpr_resource_mgmt_1;
822 u32 sq_gpr_resource_mgmt_2;
823 u32 sq_gpr_resource_mgmt_3;
824 u32 sq_thread_resource_mgmt;
825 u32 sq_thread_resource_mgmt_2;
826 u32 sq_stack_resource_mgmt_1;
827 u32 sq_stack_resource_mgmt_2;
828 u32 sq_stack_resource_mgmt_3;
829 u32 vgt_cache_invalidation;
830 u32 hdp_host_path_cntl;
831 int i, j, num_shader_engines, ps_thread_count;
832
833 switch (rdev->family) {
834 case CHIP_CYPRESS:
835 case CHIP_HEMLOCK:
836 rdev->config.evergreen.num_ses = 2;
837 rdev->config.evergreen.max_pipes = 4;
838 rdev->config.evergreen.max_tile_pipes = 8;
839 rdev->config.evergreen.max_simds = 10;
840 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
841 rdev->config.evergreen.max_gprs = 256;
842 rdev->config.evergreen.max_threads = 248;
843 rdev->config.evergreen.max_gs_threads = 32;
844 rdev->config.evergreen.max_stack_entries = 512;
845 rdev->config.evergreen.sx_num_of_sets = 4;
846 rdev->config.evergreen.sx_max_export_size = 256;
847 rdev->config.evergreen.sx_max_export_pos_size = 64;
848 rdev->config.evergreen.sx_max_export_smx_size = 192;
849 rdev->config.evergreen.max_hw_contexts = 8;
850 rdev->config.evergreen.sq_num_cf_insts = 2;
851
852 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
853 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
854 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
855 break;
856 case CHIP_JUNIPER:
857 rdev->config.evergreen.num_ses = 1;
858 rdev->config.evergreen.max_pipes = 4;
859 rdev->config.evergreen.max_tile_pipes = 4;
860 rdev->config.evergreen.max_simds = 10;
861 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
862 rdev->config.evergreen.max_gprs = 256;
863 rdev->config.evergreen.max_threads = 248;
864 rdev->config.evergreen.max_gs_threads = 32;
865 rdev->config.evergreen.max_stack_entries = 512;
866 rdev->config.evergreen.sx_num_of_sets = 4;
867 rdev->config.evergreen.sx_max_export_size = 256;
868 rdev->config.evergreen.sx_max_export_pos_size = 64;
869 rdev->config.evergreen.sx_max_export_smx_size = 192;
870 rdev->config.evergreen.max_hw_contexts = 8;
871 rdev->config.evergreen.sq_num_cf_insts = 2;
872
873 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
874 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
875 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
876 break;
877 case CHIP_REDWOOD:
878 rdev->config.evergreen.num_ses = 1;
879 rdev->config.evergreen.max_pipes = 4;
880 rdev->config.evergreen.max_tile_pipes = 4;
881 rdev->config.evergreen.max_simds = 5;
882 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
883 rdev->config.evergreen.max_gprs = 256;
884 rdev->config.evergreen.max_threads = 248;
885 rdev->config.evergreen.max_gs_threads = 32;
886 rdev->config.evergreen.max_stack_entries = 256;
887 rdev->config.evergreen.sx_num_of_sets = 4;
888 rdev->config.evergreen.sx_max_export_size = 256;
889 rdev->config.evergreen.sx_max_export_pos_size = 64;
890 rdev->config.evergreen.sx_max_export_smx_size = 192;
891 rdev->config.evergreen.max_hw_contexts = 8;
892 rdev->config.evergreen.sq_num_cf_insts = 2;
893
894 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
895 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
896 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
897 break;
898 case CHIP_CEDAR:
899 default:
900 rdev->config.evergreen.num_ses = 1;
901 rdev->config.evergreen.max_pipes = 2;
902 rdev->config.evergreen.max_tile_pipes = 2;
903 rdev->config.evergreen.max_simds = 2;
904 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
905 rdev->config.evergreen.max_gprs = 256;
906 rdev->config.evergreen.max_threads = 192;
907 rdev->config.evergreen.max_gs_threads = 16;
908 rdev->config.evergreen.max_stack_entries = 256;
909 rdev->config.evergreen.sx_num_of_sets = 4;
910 rdev->config.evergreen.sx_max_export_size = 128;
911 rdev->config.evergreen.sx_max_export_pos_size = 32;
912 rdev->config.evergreen.sx_max_export_smx_size = 96;
913 rdev->config.evergreen.max_hw_contexts = 4;
914 rdev->config.evergreen.sq_num_cf_insts = 1;
915
916 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
917 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
918 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
919 break;
920 }
921
922 /* Initialize HDP */
923 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
924 WREG32((0x2c14 + j), 0x00000000);
925 WREG32((0x2c18 + j), 0x00000000);
926 WREG32((0x2c1c + j), 0x00000000);
927 WREG32((0x2c20 + j), 0x00000000);
928 WREG32((0x2c24 + j), 0x00000000);
929 }
930
931 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
932
933 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
934
935 cc_gc_shader_pipe_config |=
936 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
937 & EVERGREEN_MAX_PIPES_MASK);
938 cc_gc_shader_pipe_config |=
939 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
940 & EVERGREEN_MAX_SIMDS_MASK);
941
942 cc_rb_backend_disable =
943 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
944 & EVERGREEN_MAX_BACKENDS_MASK);
945
946
947 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
948 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
949
950 switch (rdev->config.evergreen.max_tile_pipes) {
951 case 1:
952 default:
953 gb_addr_config |= NUM_PIPES(0);
954 break;
955 case 2:
956 gb_addr_config |= NUM_PIPES(1);
957 break;
958 case 4:
959 gb_addr_config |= NUM_PIPES(2);
960 break;
961 case 8:
962 gb_addr_config |= NUM_PIPES(3);
963 break;
964 }
965
966 gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
967 gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
968 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
969 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
970 gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
971 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
972
973 if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
974 gb_addr_config |= ROW_SIZE(2);
975 else
976 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
977
978 if (rdev->ddev->pdev->device == 0x689e) {
979 u32 efuse_straps_4;
980 u32 efuse_straps_3;
981 u8 efuse_box_bit_131_124;
982
983 WREG32(RCU_IND_INDEX, 0x204);
984 efuse_straps_4 = RREG32(RCU_IND_DATA);
985 WREG32(RCU_IND_INDEX, 0x203);
986 efuse_straps_3 = RREG32(RCU_IND_DATA);
987 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
988
989 switch(efuse_box_bit_131_124) {
990 case 0x00:
991 gb_backend_map = 0x76543210;
992 break;
993 case 0x55:
994 gb_backend_map = 0x77553311;
995 break;
996 case 0x56:
997 gb_backend_map = 0x77553300;
998 break;
999 case 0x59:
1000 gb_backend_map = 0x77552211;
1001 break;
1002 case 0x66:
1003 gb_backend_map = 0x77443300;
1004 break;
1005 case 0x99:
1006 gb_backend_map = 0x66552211;
1007 break;
1008 case 0x5a:
1009 gb_backend_map = 0x77552200;
1010 break;
1011 case 0xaa:
1012 gb_backend_map = 0x66442200;
1013 break;
1014 case 0x95:
1015 gb_backend_map = 0x66553311;
1016 break;
1017 default:
1018 DRM_ERROR("bad backend map, using default\n");
1019 gb_backend_map =
1020 evergreen_get_tile_pipe_to_backend_map(rdev,
1021 rdev->config.evergreen.max_tile_pipes,
1022 rdev->config.evergreen.max_backends,
1023 ((EVERGREEN_MAX_BACKENDS_MASK <<
1024 rdev->config.evergreen.max_backends) &
1025 EVERGREEN_MAX_BACKENDS_MASK));
1026 break;
1027 }
1028 } else if (rdev->ddev->pdev->device == 0x68b9) {
1029 u32 efuse_straps_3;
1030 u8 efuse_box_bit_127_124;
1031
1032 WREG32(RCU_IND_INDEX, 0x203);
1033 efuse_straps_3 = RREG32(RCU_IND_DATA);
1034 efuse_box_bit_127_124 = (u8)(efuse_straps_3 & 0xF0000000) >> 28;
1035
1036 switch(efuse_box_bit_127_124) {
1037 case 0x0:
1038 gb_backend_map = 0x00003210;
1039 break;
1040 case 0x5:
1041 case 0x6:
1042 case 0x9:
1043 case 0xa:
1044 gb_backend_map = 0x00003311;
1045 break;
1046 default:
1047 DRM_ERROR("bad backend map, using default\n");
1048 gb_backend_map =
1049 evergreen_get_tile_pipe_to_backend_map(rdev,
1050 rdev->config.evergreen.max_tile_pipes,
1051 rdev->config.evergreen.max_backends,
1052 ((EVERGREEN_MAX_BACKENDS_MASK <<
1053 rdev->config.evergreen.max_backends) &
1054 EVERGREEN_MAX_BACKENDS_MASK));
1055 break;
1056 }
1057 } else
1058 gb_backend_map =
1059 evergreen_get_tile_pipe_to_backend_map(rdev,
1060 rdev->config.evergreen.max_tile_pipes,
1061 rdev->config.evergreen.max_backends,
1062 ((EVERGREEN_MAX_BACKENDS_MASK <<
1063 rdev->config.evergreen.max_backends) &
1064 EVERGREEN_MAX_BACKENDS_MASK));
1065
1066 WREG32(GB_BACKEND_MAP, gb_backend_map);
1067 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1068 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1069 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1070
1071 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
1072 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
1073
1074 for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
1075 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
1076 u32 sp = cc_gc_shader_pipe_config;
1077 u32 gfx = grbm_gfx_index | SE_INDEX(i);
1078
1079 if (i == num_shader_engines) {
1080 rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
1081 sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
1082 }
1083
1084 WREG32(GRBM_GFX_INDEX, gfx);
1085 WREG32(RLC_GFX_INDEX, gfx);
1086
1087 WREG32(CC_RB_BACKEND_DISABLE, rb);
1088 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
1089 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
1090 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
1091 }
1092
1093 grbm_gfx_index |= SE_BROADCAST_WRITES;
1094 WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
1095 WREG32(RLC_GFX_INDEX, grbm_gfx_index);
1096
1097 WREG32(CGTS_SYS_TCC_DISABLE, 0);
1098 WREG32(CGTS_TCC_DISABLE, 0);
1099 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1100 WREG32(CGTS_USER_TCC_DISABLE, 0);
1101
1102 /* set HW defaults for 3D engine */
1103 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1104 ROQ_IB2_START(0x2b)));
1105
1106 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1107
1108 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
1109 SYNC_GRADIENT |
1110 SYNC_WALKER |
1111 SYNC_ALIGNER));
1112
1113 sx_debug_1 = RREG32(SX_DEBUG_1);
1114 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1115 WREG32(SX_DEBUG_1, sx_debug_1);
1116
1117
1118 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1119 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1120 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
1121 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1122
1123 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
1124 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
1125 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
1126
1127 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
1128 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
1129 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
1130
1131 WREG32(VGT_NUM_INSTANCES, 1);
1132 WREG32(SPI_CONFIG_CNTL, 0);
1133 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1134 WREG32(CP_PERFMON_CNTL, 0);
1135
1136 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
1137 FETCH_FIFO_HIWATER(0x4) |
1138 DONE_FIFO_HIWATER(0xe0) |
1139 ALU_UPDATE_FIFO_HIWATER(0x8)));
1140
1141 sq_config = RREG32(SQ_CONFIG);
1142 sq_config &= ~(PS_PRIO(3) |
1143 VS_PRIO(3) |
1144 GS_PRIO(3) |
1145 ES_PRIO(3));
1146 sq_config |= (VC_ENABLE |
1147 EXPORT_SRC_C |
1148 PS_PRIO(0) |
1149 VS_PRIO(1) |
1150 GS_PRIO(2) |
1151 ES_PRIO(3));
1152
1153 if (rdev->family == CHIP_CEDAR)
1154 /* no vertex cache */
1155 sq_config &= ~VC_ENABLE;
1156
1157 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
1158
1159 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
1160 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
1161 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
1162 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1163 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1164 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1165 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1166
1167 if (rdev->family == CHIP_CEDAR)
1168 ps_thread_count = 96;
1169 else
1170 ps_thread_count = 128;
1171
1172 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
1173 sq_thread_resource_mgmt |= NUM_VS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
1174 sq_thread_resource_mgmt |= NUM_GS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
1175 sq_thread_resource_mgmt |= NUM_ES_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
1176 sq_thread_resource_mgmt_2 = NUM_HS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
1177 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
1178
1179 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1180 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1181 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1182 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1183 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1184 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1185
1186 WREG32(SQ_CONFIG, sq_config);
1187 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1188 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1189 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
1190 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1191 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
1192 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1193 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1194 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
1195 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
1196 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
1197
1198 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1199 FORCE_EOV_MAX_REZ_CNT(255)));
1200
1201 if (rdev->family == CHIP_CEDAR)
1202 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
1203 else
1204 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
1205 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
1206 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
1207
1208 WREG32(VGT_GS_VERTEX_REUSE, 16);
1209 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1210
1211 WREG32(CB_PERF_CTR0_SEL_0, 0);
1212 WREG32(CB_PERF_CTR0_SEL_1, 0);
1213 WREG32(CB_PERF_CTR1_SEL_0, 0);
1214 WREG32(CB_PERF_CTR1_SEL_1, 0);
1215 WREG32(CB_PERF_CTR2_SEL_0, 0);
1216 WREG32(CB_PERF_CTR2_SEL_1, 0);
1217 WREG32(CB_PERF_CTR3_SEL_0, 0);
1218 WREG32(CB_PERF_CTR3_SEL_1, 0);
1219
1220 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1221 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1222
1223 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1224
1225 udelay(50);
1226
1227 }
1228
1229 int evergreen_mc_init(struct radeon_device *rdev)
1230 {
1231 u32 tmp;
1232 int chansize, numchan;
1233
1234 /* Get VRAM informations */
1235 rdev->mc.vram_is_ddr = true;
1236 tmp = RREG32(MC_ARB_RAMCFG);
1237 if (tmp & CHANSIZE_OVERRIDE) {
1238 chansize = 16;
1239 } else if (tmp & CHANSIZE_MASK) {
1240 chansize = 64;
1241 } else {
1242 chansize = 32;
1243 }
1244 tmp = RREG32(MC_SHARED_CHMAP);
1245 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1246 case 0:
1247 default:
1248 numchan = 1;
1249 break;
1250 case 1:
1251 numchan = 2;
1252 break;
1253 case 2:
1254 numchan = 4;
1255 break;
1256 case 3:
1257 numchan = 8;
1258 break;
1259 }
1260 rdev->mc.vram_width = numchan * chansize;
1261 /* Could aper size report 0 ? */
1262 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1263 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1264 /* Setup GPU memory space */
1265 /* size in MB on evergreen */
1266 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
1267 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
1268 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1269 r600_vram_gtt_location(rdev, &rdev->mc);
1270 radeon_update_bandwidth_info(rdev);
1271
1272 return 0;
1273 }
1274
1275 bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
1276 {
1277 /* FIXME: implement for evergreen */
1278 return false;
1279 }
1280
1281 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
1282 {
1283 struct evergreen_mc_save save;
1284 u32 srbm_reset = 0;
1285 u32 grbm_reset = 0;
1286
1287 dev_info(rdev->dev, "GPU softreset \n");
1288 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1289 RREG32(GRBM_STATUS));
1290 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1291 RREG32(GRBM_STATUS_SE0));
1292 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1293 RREG32(GRBM_STATUS_SE1));
1294 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1295 RREG32(SRBM_STATUS));
1296 evergreen_mc_stop(rdev, &save);
1297 if (evergreen_mc_wait_for_idle(rdev)) {
1298 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1299 }
1300 /* Disable CP parsing/prefetching */
1301 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1302
1303 /* reset all the gfx blocks */
1304 grbm_reset = (SOFT_RESET_CP |
1305 SOFT_RESET_CB |
1306 SOFT_RESET_DB |
1307 SOFT_RESET_PA |
1308 SOFT_RESET_SC |
1309 SOFT_RESET_SPI |
1310 SOFT_RESET_SH |
1311 SOFT_RESET_SX |
1312 SOFT_RESET_TC |
1313 SOFT_RESET_TA |
1314 SOFT_RESET_VC |
1315 SOFT_RESET_VGT);
1316
1317 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
1318 WREG32(GRBM_SOFT_RESET, grbm_reset);
1319 (void)RREG32(GRBM_SOFT_RESET);
1320 udelay(50);
1321 WREG32(GRBM_SOFT_RESET, 0);
1322 (void)RREG32(GRBM_SOFT_RESET);
1323
1324 /* reset all the system blocks */
1325 srbm_reset = SRBM_SOFT_RESET_ALL_MASK;
1326
1327 dev_info(rdev->dev, " SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
1328 WREG32(SRBM_SOFT_RESET, srbm_reset);
1329 (void)RREG32(SRBM_SOFT_RESET);
1330 udelay(50);
1331 WREG32(SRBM_SOFT_RESET, 0);
1332 (void)RREG32(SRBM_SOFT_RESET);
1333 /* Wait a little for things to settle down */
1334 udelay(50);
1335 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1336 RREG32(GRBM_STATUS));
1337 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1338 RREG32(GRBM_STATUS_SE0));
1339 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1340 RREG32(GRBM_STATUS_SE1));
1341 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1342 RREG32(SRBM_STATUS));
1343 /* After reset we need to reinit the asic as GPU often endup in an
1344 * incoherent state.
1345 */
1346 atom_asic_init(rdev->mode_info.atom_context);
1347 evergreen_mc_resume(rdev, &save);
1348 return 0;
1349 }
1350
1351 int evergreen_asic_reset(struct radeon_device *rdev)
1352 {
1353 return evergreen_gpu_soft_reset(rdev);
1354 }
1355
1356 /* Interrupts */
1357
1358 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
1359 {
1360 switch (crtc) {
1361 case 0:
1362 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
1363 case 1:
1364 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
1365 case 2:
1366 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
1367 case 3:
1368 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
1369 case 4:
1370 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
1371 case 5:
1372 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
1373 default:
1374 return 0;
1375 }
1376 }
1377
1378 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
1379 {
1380 u32 tmp;
1381
1382 WREG32(CP_INT_CNTL, 0);
1383 WREG32(GRBM_INT_CNTL, 0);
1384 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1385 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1386 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1387 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1388 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1389 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1390
1391 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1392 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1393 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1394 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1395 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1396 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1397
1398 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
1399 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
1400
1401 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1402 WREG32(DC_HPD1_INT_CONTROL, tmp);
1403 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1404 WREG32(DC_HPD2_INT_CONTROL, tmp);
1405 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1406 WREG32(DC_HPD3_INT_CONTROL, tmp);
1407 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1408 WREG32(DC_HPD4_INT_CONTROL, tmp);
1409 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1410 WREG32(DC_HPD5_INT_CONTROL, tmp);
1411 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1412 WREG32(DC_HPD6_INT_CONTROL, tmp);
1413
1414 }
1415
1416 int evergreen_irq_set(struct radeon_device *rdev)
1417 {
1418 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
1419 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
1420 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
1421 u32 grbm_int_cntl = 0;
1422
1423 if (!rdev->irq.installed) {
1424 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
1425 return -EINVAL;
1426 }
1427 /* don't enable anything if the ih is disabled */
1428 if (!rdev->ih.enabled) {
1429 r600_disable_interrupts(rdev);
1430 /* force the active interrupt state to all disabled */
1431 evergreen_disable_interrupt_state(rdev);
1432 return 0;
1433 }
1434
1435 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
1436 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
1437 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
1438 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
1439 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
1440 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
1441
1442 if (rdev->irq.sw_int) {
1443 DRM_DEBUG("evergreen_irq_set: sw int\n");
1444 cp_int_cntl |= RB_INT_ENABLE;
1445 }
1446 if (rdev->irq.crtc_vblank_int[0]) {
1447 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
1448 crtc1 |= VBLANK_INT_MASK;
1449 }
1450 if (rdev->irq.crtc_vblank_int[1]) {
1451 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
1452 crtc2 |= VBLANK_INT_MASK;
1453 }
1454 if (rdev->irq.crtc_vblank_int[2]) {
1455 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
1456 crtc3 |= VBLANK_INT_MASK;
1457 }
1458 if (rdev->irq.crtc_vblank_int[3]) {
1459 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
1460 crtc4 |= VBLANK_INT_MASK;
1461 }
1462 if (rdev->irq.crtc_vblank_int[4]) {
1463 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
1464 crtc5 |= VBLANK_INT_MASK;
1465 }
1466 if (rdev->irq.crtc_vblank_int[5]) {
1467 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
1468 crtc6 |= VBLANK_INT_MASK;
1469 }
1470 if (rdev->irq.hpd[0]) {
1471 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
1472 hpd1 |= DC_HPDx_INT_EN;
1473 }
1474 if (rdev->irq.hpd[1]) {
1475 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
1476 hpd2 |= DC_HPDx_INT_EN;
1477 }
1478 if (rdev->irq.hpd[2]) {
1479 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
1480 hpd3 |= DC_HPDx_INT_EN;
1481 }
1482 if (rdev->irq.hpd[3]) {
1483 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
1484 hpd4 |= DC_HPDx_INT_EN;
1485 }
1486 if (rdev->irq.hpd[4]) {
1487 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
1488 hpd5 |= DC_HPDx_INT_EN;
1489 }
1490 if (rdev->irq.hpd[5]) {
1491 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
1492 hpd6 |= DC_HPDx_INT_EN;
1493 }
1494 if (rdev->irq.gui_idle) {
1495 DRM_DEBUG("gui idle\n");
1496 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
1497 }
1498
1499 WREG32(CP_INT_CNTL, cp_int_cntl);
1500 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
1501
1502 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
1503 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
1504 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
1505 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
1506 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
1507 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
1508
1509 WREG32(DC_HPD1_INT_CONTROL, hpd1);
1510 WREG32(DC_HPD2_INT_CONTROL, hpd2);
1511 WREG32(DC_HPD3_INT_CONTROL, hpd3);
1512 WREG32(DC_HPD4_INT_CONTROL, hpd4);
1513 WREG32(DC_HPD5_INT_CONTROL, hpd5);
1514 WREG32(DC_HPD6_INT_CONTROL, hpd6);
1515
1516 return 0;
1517 }
1518
1519 static inline void evergreen_irq_ack(struct radeon_device *rdev,
1520 u32 *disp_int,
1521 u32 *disp_int_cont,
1522 u32 *disp_int_cont2,
1523 u32 *disp_int_cont3,
1524 u32 *disp_int_cont4,
1525 u32 *disp_int_cont5)
1526 {
1527 u32 tmp;
1528
1529 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
1530 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
1531 *disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
1532 *disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
1533 *disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
1534 *disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
1535
1536 if (*disp_int & LB_D1_VBLANK_INTERRUPT)
1537 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
1538 if (*disp_int & LB_D1_VLINE_INTERRUPT)
1539 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
1540
1541 if (*disp_int_cont & LB_D2_VBLANK_INTERRUPT)
1542 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
1543 if (*disp_int_cont & LB_D2_VLINE_INTERRUPT)
1544 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
1545
1546 if (*disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
1547 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
1548 if (*disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
1549 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
1550
1551 if (*disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
1552 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
1553 if (*disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
1554 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
1555
1556 if (*disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
1557 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
1558 if (*disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
1559 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
1560
1561 if (*disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
1562 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
1563 if (*disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
1564 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
1565
1566 if (*disp_int & DC_HPD1_INTERRUPT) {
1567 tmp = RREG32(DC_HPD1_INT_CONTROL);
1568 tmp |= DC_HPDx_INT_ACK;
1569 WREG32(DC_HPD1_INT_CONTROL, tmp);
1570 }
1571 if (*disp_int_cont & DC_HPD2_INTERRUPT) {
1572 tmp = RREG32(DC_HPD2_INT_CONTROL);
1573 tmp |= DC_HPDx_INT_ACK;
1574 WREG32(DC_HPD2_INT_CONTROL, tmp);
1575 }
1576 if (*disp_int_cont2 & DC_HPD3_INTERRUPT) {
1577 tmp = RREG32(DC_HPD3_INT_CONTROL);
1578 tmp |= DC_HPDx_INT_ACK;
1579 WREG32(DC_HPD3_INT_CONTROL, tmp);
1580 }
1581 if (*disp_int_cont3 & DC_HPD4_INTERRUPT) {
1582 tmp = RREG32(DC_HPD4_INT_CONTROL);
1583 tmp |= DC_HPDx_INT_ACK;
1584 WREG32(DC_HPD4_INT_CONTROL, tmp);
1585 }
1586 if (*disp_int_cont4 & DC_HPD5_INTERRUPT) {
1587 tmp = RREG32(DC_HPD5_INT_CONTROL);
1588 tmp |= DC_HPDx_INT_ACK;
1589 WREG32(DC_HPD5_INT_CONTROL, tmp);
1590 }
1591 if (*disp_int_cont5 & DC_HPD6_INTERRUPT) {
1592 tmp = RREG32(DC_HPD5_INT_CONTROL);
1593 tmp |= DC_HPDx_INT_ACK;
1594 WREG32(DC_HPD6_INT_CONTROL, tmp);
1595 }
1596 }
1597
1598 void evergreen_irq_disable(struct radeon_device *rdev)
1599 {
1600 u32 disp_int, disp_int_cont, disp_int_cont2;
1601 u32 disp_int_cont3, disp_int_cont4, disp_int_cont5;
1602
1603 r600_disable_interrupts(rdev);
1604 /* Wait and acknowledge irq */
1605 mdelay(1);
1606 evergreen_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2,
1607 &disp_int_cont3, &disp_int_cont4, &disp_int_cont5);
1608 evergreen_disable_interrupt_state(rdev);
1609 }
1610
1611 static void evergreen_irq_suspend(struct radeon_device *rdev)
1612 {
1613 evergreen_irq_disable(rdev);
1614 r600_rlc_stop(rdev);
1615 }
1616
1617 static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
1618 {
1619 u32 wptr, tmp;
1620
1621 /* XXX use writeback */
1622 wptr = RREG32(IH_RB_WPTR);
1623
1624 if (wptr & RB_OVERFLOW) {
1625 /* When a ring buffer overflow happen start parsing interrupt
1626 * from the last not overwritten vector (wptr + 16). Hopefully
1627 * this should allow us to catchup.
1628 */
1629 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
1630 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
1631 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
1632 tmp = RREG32(IH_RB_CNTL);
1633 tmp |= IH_WPTR_OVERFLOW_CLEAR;
1634 WREG32(IH_RB_CNTL, tmp);
1635 }
1636 return (wptr & rdev->ih.ptr_mask);
1637 }
1638
1639 int evergreen_irq_process(struct radeon_device *rdev)
1640 {
1641 u32 wptr = evergreen_get_ih_wptr(rdev);
1642 u32 rptr = rdev->ih.rptr;
1643 u32 src_id, src_data;
1644 u32 ring_index;
1645 u32 disp_int, disp_int_cont, disp_int_cont2;
1646 u32 disp_int_cont3, disp_int_cont4, disp_int_cont5;
1647 unsigned long flags;
1648 bool queue_hotplug = false;
1649
1650 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
1651 if (!rdev->ih.enabled)
1652 return IRQ_NONE;
1653
1654 spin_lock_irqsave(&rdev->ih.lock, flags);
1655
1656 if (rptr == wptr) {
1657 spin_unlock_irqrestore(&rdev->ih.lock, flags);
1658 return IRQ_NONE;
1659 }
1660 if (rdev->shutdown) {
1661 spin_unlock_irqrestore(&rdev->ih.lock, flags);
1662 return IRQ_NONE;
1663 }
1664
1665 restart_ih:
1666 /* display interrupts */
1667 evergreen_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2,
1668 &disp_int_cont3, &disp_int_cont4, &disp_int_cont5);
1669
1670 rdev->ih.wptr = wptr;
1671 while (rptr != wptr) {
1672 /* wptr/rptr are in bytes! */
1673 ring_index = rptr / 4;
1674 src_id = rdev->ih.ring[ring_index] & 0xff;
1675 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
1676
1677 switch (src_id) {
1678 case 1: /* D1 vblank/vline */
1679 switch (src_data) {
1680 case 0: /* D1 vblank */
1681 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
1682 drm_handle_vblank(rdev->ddev, 0);
1683 wake_up(&rdev->irq.vblank_queue);
1684 disp_int &= ~LB_D1_VBLANK_INTERRUPT;
1685 DRM_DEBUG("IH: D1 vblank\n");
1686 }
1687 break;
1688 case 1: /* D1 vline */
1689 if (disp_int & LB_D1_VLINE_INTERRUPT) {
1690 disp_int &= ~LB_D1_VLINE_INTERRUPT;
1691 DRM_DEBUG("IH: D1 vline\n");
1692 }
1693 break;
1694 default:
1695 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1696 break;
1697 }
1698 break;
1699 case 2: /* D2 vblank/vline */
1700 switch (src_data) {
1701 case 0: /* D2 vblank */
1702 if (disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
1703 drm_handle_vblank(rdev->ddev, 1);
1704 wake_up(&rdev->irq.vblank_queue);
1705 disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
1706 DRM_DEBUG("IH: D2 vblank\n");
1707 }
1708 break;
1709 case 1: /* D2 vline */
1710 if (disp_int_cont & LB_D2_VLINE_INTERRUPT) {
1711 disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
1712 DRM_DEBUG("IH: D2 vline\n");
1713 }
1714 break;
1715 default:
1716 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1717 break;
1718 }
1719 break;
1720 case 3: /* D3 vblank/vline */
1721 switch (src_data) {
1722 case 0: /* D3 vblank */
1723 if (disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
1724 drm_handle_vblank(rdev->ddev, 2);
1725 wake_up(&rdev->irq.vblank_queue);
1726 disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
1727 DRM_DEBUG("IH: D3 vblank\n");
1728 }
1729 break;
1730 case 1: /* D3 vline */
1731 if (disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
1732 disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
1733 DRM_DEBUG("IH: D3 vline\n");
1734 }
1735 break;
1736 default:
1737 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1738 break;
1739 }
1740 break;
1741 case 4: /* D4 vblank/vline */
1742 switch (src_data) {
1743 case 0: /* D4 vblank */
1744 if (disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
1745 drm_handle_vblank(rdev->ddev, 3);
1746 wake_up(&rdev->irq.vblank_queue);
1747 disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
1748 DRM_DEBUG("IH: D4 vblank\n");
1749 }
1750 break;
1751 case 1: /* D4 vline */
1752 if (disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
1753 disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
1754 DRM_DEBUG("IH: D4 vline\n");
1755 }
1756 break;
1757 default:
1758 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1759 break;
1760 }
1761 break;
1762 case 5: /* D5 vblank/vline */
1763 switch (src_data) {
1764 case 0: /* D5 vblank */
1765 if (disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
1766 drm_handle_vblank(rdev->ddev, 4);
1767 wake_up(&rdev->irq.vblank_queue);
1768 disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
1769 DRM_DEBUG("IH: D5 vblank\n");
1770 }
1771 break;
1772 case 1: /* D5 vline */
1773 if (disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
1774 disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
1775 DRM_DEBUG("IH: D5 vline\n");
1776 }
1777 break;
1778 default:
1779 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1780 break;
1781 }
1782 break;
1783 case 6: /* D6 vblank/vline */
1784 switch (src_data) {
1785 case 0: /* D6 vblank */
1786 if (disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
1787 drm_handle_vblank(rdev->ddev, 5);
1788 wake_up(&rdev->irq.vblank_queue);
1789 disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
1790 DRM_DEBUG("IH: D6 vblank\n");
1791 }
1792 break;
1793 case 1: /* D6 vline */
1794 if (disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
1795 disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
1796 DRM_DEBUG("IH: D6 vline\n");
1797 }
1798 break;
1799 default:
1800 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1801 break;
1802 }
1803 break;
1804 case 42: /* HPD hotplug */
1805 switch (src_data) {
1806 case 0:
1807 if (disp_int & DC_HPD1_INTERRUPT) {
1808 disp_int &= ~DC_HPD1_INTERRUPT;
1809 queue_hotplug = true;
1810 DRM_DEBUG("IH: HPD1\n");
1811 }
1812 break;
1813 case 1:
1814 if (disp_int_cont & DC_HPD2_INTERRUPT) {
1815 disp_int_cont &= ~DC_HPD2_INTERRUPT;
1816 queue_hotplug = true;
1817 DRM_DEBUG("IH: HPD2\n");
1818 }
1819 break;
1820 case 2:
1821 if (disp_int_cont2 & DC_HPD3_INTERRUPT) {
1822 disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
1823 queue_hotplug = true;
1824 DRM_DEBUG("IH: HPD3\n");
1825 }
1826 break;
1827 case 3:
1828 if (disp_int_cont3 & DC_HPD4_INTERRUPT) {
1829 disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
1830 queue_hotplug = true;
1831 DRM_DEBUG("IH: HPD4\n");
1832 }
1833 break;
1834 case 4:
1835 if (disp_int_cont4 & DC_HPD5_INTERRUPT) {
1836 disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
1837 queue_hotplug = true;
1838 DRM_DEBUG("IH: HPD5\n");
1839 }
1840 break;
1841 case 5:
1842 if (disp_int_cont5 & DC_HPD6_INTERRUPT) {
1843 disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
1844 queue_hotplug = true;
1845 DRM_DEBUG("IH: HPD6\n");
1846 }
1847 break;
1848 default:
1849 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1850 break;
1851 }
1852 break;
1853 case 176: /* CP_INT in ring buffer */
1854 case 177: /* CP_INT in IB1 */
1855 case 178: /* CP_INT in IB2 */
1856 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
1857 radeon_fence_process(rdev);
1858 break;
1859 case 181: /* CP EOP event */
1860 DRM_DEBUG("IH: CP EOP\n");
1861 break;
1862 case 233: /* GUI IDLE */
1863 DRM_DEBUG("IH: CP EOP\n");
1864 rdev->pm.gui_idle = true;
1865 wake_up(&rdev->irq.idle_queue);
1866 break;
1867 default:
1868 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1869 break;
1870 }
1871
1872 /* wptr/rptr are in bytes! */
1873 rptr += 16;
1874 rptr &= rdev->ih.ptr_mask;
1875 }
1876 /* make sure wptr hasn't changed while processing */
1877 wptr = evergreen_get_ih_wptr(rdev);
1878 if (wptr != rdev->ih.wptr)
1879 goto restart_ih;
1880 if (queue_hotplug)
1881 queue_work(rdev->wq, &rdev->hotplug_work);
1882 rdev->ih.rptr = rptr;
1883 WREG32(IH_RB_RPTR, rdev->ih.rptr);
1884 spin_unlock_irqrestore(&rdev->ih.lock, flags);
1885 return IRQ_HANDLED;
1886 }
1887
1888 static int evergreen_startup(struct radeon_device *rdev)
1889 {
1890 int r;
1891
1892 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1893 r = r600_init_microcode(rdev);
1894 if (r) {
1895 DRM_ERROR("Failed to load firmware!\n");
1896 return r;
1897 }
1898 }
1899
1900 evergreen_mc_program(rdev);
1901 if (rdev->flags & RADEON_IS_AGP) {
1902 evergreen_agp_enable(rdev);
1903 } else {
1904 r = evergreen_pcie_gart_enable(rdev);
1905 if (r)
1906 return r;
1907 }
1908 evergreen_gpu_init(rdev);
1909 #if 0
1910 if (!rdev->r600_blit.shader_obj) {
1911 r = r600_blit_init(rdev);
1912 if (r) {
1913 DRM_ERROR("radeon: failed blitter (%d).\n", r);
1914 return r;
1915 }
1916 }
1917
1918 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1919 if (unlikely(r != 0))
1920 return r;
1921 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1922 &rdev->r600_blit.shader_gpu_addr);
1923 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1924 if (r) {
1925 DRM_ERROR("failed to pin blit object %d\n", r);
1926 return r;
1927 }
1928 #endif
1929
1930 /* Enable IRQ */
1931 r = r600_irq_init(rdev);
1932 if (r) {
1933 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1934 radeon_irq_kms_fini(rdev);
1935 return r;
1936 }
1937 evergreen_irq_set(rdev);
1938
1939 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1940 if (r)
1941 return r;
1942 r = evergreen_cp_load_microcode(rdev);
1943 if (r)
1944 return r;
1945 r = evergreen_cp_resume(rdev);
1946 if (r)
1947 return r;
1948 /* write back buffer are not vital so don't worry about failure */
1949 r600_wb_enable(rdev);
1950
1951 return 0;
1952 }
1953
1954 int evergreen_resume(struct radeon_device *rdev)
1955 {
1956 int r;
1957
1958 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1959 * posting will perform necessary task to bring back GPU into good
1960 * shape.
1961 */
1962 /* post card */
1963 atom_asic_init(rdev->mode_info.atom_context);
1964 /* Initialize clocks */
1965 r = radeon_clocks_init(rdev);
1966 if (r) {
1967 return r;
1968 }
1969
1970 r = evergreen_startup(rdev);
1971 if (r) {
1972 DRM_ERROR("r600 startup failed on resume\n");
1973 return r;
1974 }
1975
1976 r = r600_ib_test(rdev);
1977 if (r) {
1978 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1979 return r;
1980 }
1981
1982 return r;
1983
1984 }
1985
1986 int evergreen_suspend(struct radeon_device *rdev)
1987 {
1988 #if 0
1989 int r;
1990 #endif
1991 /* FIXME: we should wait for ring to be empty */
1992 r700_cp_stop(rdev);
1993 rdev->cp.ready = false;
1994 evergreen_irq_suspend(rdev);
1995 r600_wb_disable(rdev);
1996 evergreen_pcie_gart_disable(rdev);
1997 #if 0
1998 /* unpin shaders bo */
1999 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2000 if (likely(r == 0)) {
2001 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2002 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2003 }
2004 #endif
2005 return 0;
2006 }
2007
2008 static bool evergreen_card_posted(struct radeon_device *rdev)
2009 {
2010 u32 reg;
2011
2012 /* first check CRTCs */
2013 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
2014 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
2015 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
2016 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
2017 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
2018 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
2019 if (reg & EVERGREEN_CRTC_MASTER_EN)
2020 return true;
2021
2022 /* then check MEM_SIZE, in case the crtcs are off */
2023 if (RREG32(CONFIG_MEMSIZE))
2024 return true;
2025
2026 return false;
2027 }
2028
2029 /* Plan is to move initialization in that function and use
2030 * helper function so that radeon_device_init pretty much
2031 * do nothing more than calling asic specific function. This
2032 * should also allow to remove a bunch of callback function
2033 * like vram_info.
2034 */
2035 int evergreen_init(struct radeon_device *rdev)
2036 {
2037 int r;
2038
2039 r = radeon_dummy_page_init(rdev);
2040 if (r)
2041 return r;
2042 /* This don't do much */
2043 r = radeon_gem_init(rdev);
2044 if (r)
2045 return r;
2046 /* Read BIOS */
2047 if (!radeon_get_bios(rdev)) {
2048 if (ASIC_IS_AVIVO(rdev))
2049 return -EINVAL;
2050 }
2051 /* Must be an ATOMBIOS */
2052 if (!rdev->is_atom_bios) {
2053 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2054 return -EINVAL;
2055 }
2056 r = radeon_atombios_init(rdev);
2057 if (r)
2058 return r;
2059 /* Post card if necessary */
2060 if (!evergreen_card_posted(rdev)) {
2061 if (!rdev->bios) {
2062 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2063 return -EINVAL;
2064 }
2065 DRM_INFO("GPU not posted. posting now...\n");
2066 atom_asic_init(rdev->mode_info.atom_context);
2067 }
2068 /* Initialize scratch registers */
2069 r600_scratch_init(rdev);
2070 /* Initialize surface registers */
2071 radeon_surface_init(rdev);
2072 /* Initialize clocks */
2073 radeon_get_clock_info(rdev->ddev);
2074 r = radeon_clocks_init(rdev);
2075 if (r)
2076 return r;
2077 /* Initialize power management */
2078 radeon_pm_init(rdev);
2079 /* Fence driver */
2080 r = radeon_fence_driver_init(rdev);
2081 if (r)
2082 return r;
2083 /* initialize AGP */
2084 if (rdev->flags & RADEON_IS_AGP) {
2085 r = radeon_agp_init(rdev);
2086 if (r)
2087 radeon_agp_disable(rdev);
2088 }
2089 /* initialize memory controller */
2090 r = evergreen_mc_init(rdev);
2091 if (r)
2092 return r;
2093 /* Memory manager */
2094 r = radeon_bo_init(rdev);
2095 if (r)
2096 return r;
2097
2098 r = radeon_irq_kms_init(rdev);
2099 if (r)
2100 return r;
2101
2102 rdev->cp.ring_obj = NULL;
2103 r600_ring_init(rdev, 1024 * 1024);
2104
2105 rdev->ih.ring_obj = NULL;
2106 r600_ih_ring_init(rdev, 64 * 1024);
2107
2108 r = r600_pcie_gart_init(rdev);
2109 if (r)
2110 return r;
2111
2112 rdev->accel_working = false;
2113 r = evergreen_startup(rdev);
2114 if (r) {
2115 dev_err(rdev->dev, "disabling GPU acceleration\n");
2116 r700_cp_fini(rdev);
2117 r600_wb_fini(rdev);
2118 r600_irq_fini(rdev);
2119 radeon_irq_kms_fini(rdev);
2120 evergreen_pcie_gart_fini(rdev);
2121 rdev->accel_working = false;
2122 }
2123 if (rdev->accel_working) {
2124 r = radeon_ib_pool_init(rdev);
2125 if (r) {
2126 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
2127 rdev->accel_working = false;
2128 }
2129 r = r600_ib_test(rdev);
2130 if (r) {
2131 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
2132 rdev->accel_working = false;
2133 }
2134 }
2135 return 0;
2136 }
2137
2138 void evergreen_fini(struct radeon_device *rdev)
2139 {
2140 radeon_pm_fini(rdev);
2141 /*r600_blit_fini(rdev);*/
2142 r700_cp_fini(rdev);
2143 r600_wb_fini(rdev);
2144 r600_irq_fini(rdev);
2145 radeon_irq_kms_fini(rdev);
2146 evergreen_pcie_gart_fini(rdev);
2147 radeon_gem_fini(rdev);
2148 radeon_fence_driver_fini(rdev);
2149 radeon_clocks_fini(rdev);
2150 radeon_agp_fini(rdev);
2151 radeon_bo_fini(rdev);
2152 radeon_atombios_fini(rdev);
2153 kfree(rdev->bios);
2154 rdev->bios = NULL;
2155 radeon_dummy_page_fini(rdev);
2156 }
Linux kernel - Deliverables
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