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drm/radeon/kms: implement gpu lockup check for evergreen
[deliverable/linux.git] / drivers / gpu / drm / radeon / evergreen.c
1 /*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include "drmP.h"
28 #include "radeon.h"
29 #include "radeon_asic.h"
30 #include "radeon_drm.h"
31 #include "evergreend.h"
32 #include "atom.h"
33 #include "avivod.h"
34 #include "evergreen_reg.h"
35 #include "evergreen_blit_shaders.h"
36
37 #define EVERGREEN_PFP_UCODE_SIZE 1120
38 #define EVERGREEN_PM4_UCODE_SIZE 1376
39
40 static void evergreen_gpu_init(struct radeon_device *rdev);
41 void evergreen_fini(struct radeon_device *rdev);
42
43 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
44 {
45 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
46 u32 tmp;
47
48 /* make sure flip is at vb rather than hb */
49 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
50 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
51 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
52
53 /* set pageflip to happen anywhere in vblank interval */
54 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
55
56 /* enable the pflip int */
57 radeon_irq_kms_pflip_irq_get(rdev, crtc);
58 }
59
60 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
61 {
62 /* disable the pflip int */
63 radeon_irq_kms_pflip_irq_put(rdev, crtc);
64 }
65
66 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
67 {
68 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
69 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
70
71 /* Lock the graphics update lock */
72 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
73 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
74
75 /* update the scanout addresses */
76 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
77 upper_32_bits(crtc_base));
78 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
79 (u32)crtc_base);
80
81 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
82 upper_32_bits(crtc_base));
83 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
84 (u32)crtc_base);
85
86 /* Wait for update_pending to go high. */
87 while (!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING));
88 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
89
90 /* Unlock the lock, so double-buffering can take place inside vblank */
91 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
92 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
93
94 /* Return current update_pending status: */
95 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
96 }
97
98 /* get temperature in millidegrees */
99 u32 evergreen_get_temp(struct radeon_device *rdev)
100 {
101 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
102 ASIC_T_SHIFT;
103 u32 actual_temp = 0;
104
105 if ((temp >> 10) & 1)
106 actual_temp = 0;
107 else if ((temp >> 9) & 1)
108 actual_temp = 255;
109 else
110 actual_temp = (temp >> 1) & 0xff;
111
112 return actual_temp * 1000;
113 }
114
115 u32 sumo_get_temp(struct radeon_device *rdev)
116 {
117 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
118 u32 actual_temp = (temp >> 1) & 0xff;
119
120 return actual_temp * 1000;
121 }
122
123 void evergreen_pm_misc(struct radeon_device *rdev)
124 {
125 int req_ps_idx = rdev->pm.requested_power_state_index;
126 int req_cm_idx = rdev->pm.requested_clock_mode_index;
127 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
128 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
129
130 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
131 if (voltage->voltage != rdev->pm.current_vddc) {
132 radeon_atom_set_voltage(rdev, voltage->voltage);
133 rdev->pm.current_vddc = voltage->voltage;
134 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
135 }
136 }
137 }
138
139 void evergreen_pm_prepare(struct radeon_device *rdev)
140 {
141 struct drm_device *ddev = rdev->ddev;
142 struct drm_crtc *crtc;
143 struct radeon_crtc *radeon_crtc;
144 u32 tmp;
145
146 /* disable any active CRTCs */
147 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
148 radeon_crtc = to_radeon_crtc(crtc);
149 if (radeon_crtc->enabled) {
150 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
151 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
152 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
153 }
154 }
155 }
156
157 void evergreen_pm_finish(struct radeon_device *rdev)
158 {
159 struct drm_device *ddev = rdev->ddev;
160 struct drm_crtc *crtc;
161 struct radeon_crtc *radeon_crtc;
162 u32 tmp;
163
164 /* enable any active CRTCs */
165 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
166 radeon_crtc = to_radeon_crtc(crtc);
167 if (radeon_crtc->enabled) {
168 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
169 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
170 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
171 }
172 }
173 }
174
175 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
176 {
177 bool connected = false;
178
179 switch (hpd) {
180 case RADEON_HPD_1:
181 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
182 connected = true;
183 break;
184 case RADEON_HPD_2:
185 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
186 connected = true;
187 break;
188 case RADEON_HPD_3:
189 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
190 connected = true;
191 break;
192 case RADEON_HPD_4:
193 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
194 connected = true;
195 break;
196 case RADEON_HPD_5:
197 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
198 connected = true;
199 break;
200 case RADEON_HPD_6:
201 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
202 connected = true;
203 break;
204 default:
205 break;
206 }
207
208 return connected;
209 }
210
211 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
212 enum radeon_hpd_id hpd)
213 {
214 u32 tmp;
215 bool connected = evergreen_hpd_sense(rdev, hpd);
216
217 switch (hpd) {
218 case RADEON_HPD_1:
219 tmp = RREG32(DC_HPD1_INT_CONTROL);
220 if (connected)
221 tmp &= ~DC_HPDx_INT_POLARITY;
222 else
223 tmp |= DC_HPDx_INT_POLARITY;
224 WREG32(DC_HPD1_INT_CONTROL, tmp);
225 break;
226 case RADEON_HPD_2:
227 tmp = RREG32(DC_HPD2_INT_CONTROL);
228 if (connected)
229 tmp &= ~DC_HPDx_INT_POLARITY;
230 else
231 tmp |= DC_HPDx_INT_POLARITY;
232 WREG32(DC_HPD2_INT_CONTROL, tmp);
233 break;
234 case RADEON_HPD_3:
235 tmp = RREG32(DC_HPD3_INT_CONTROL);
236 if (connected)
237 tmp &= ~DC_HPDx_INT_POLARITY;
238 else
239 tmp |= DC_HPDx_INT_POLARITY;
240 WREG32(DC_HPD3_INT_CONTROL, tmp);
241 break;
242 case RADEON_HPD_4:
243 tmp = RREG32(DC_HPD4_INT_CONTROL);
244 if (connected)
245 tmp &= ~DC_HPDx_INT_POLARITY;
246 else
247 tmp |= DC_HPDx_INT_POLARITY;
248 WREG32(DC_HPD4_INT_CONTROL, tmp);
249 break;
250 case RADEON_HPD_5:
251 tmp = RREG32(DC_HPD5_INT_CONTROL);
252 if (connected)
253 tmp &= ~DC_HPDx_INT_POLARITY;
254 else
255 tmp |= DC_HPDx_INT_POLARITY;
256 WREG32(DC_HPD5_INT_CONTROL, tmp);
257 break;
258 case RADEON_HPD_6:
259 tmp = RREG32(DC_HPD6_INT_CONTROL);
260 if (connected)
261 tmp &= ~DC_HPDx_INT_POLARITY;
262 else
263 tmp |= DC_HPDx_INT_POLARITY;
264 WREG32(DC_HPD6_INT_CONTROL, tmp);
265 break;
266 default:
267 break;
268 }
269 }
270
271 void evergreen_hpd_init(struct radeon_device *rdev)
272 {
273 struct drm_device *dev = rdev->ddev;
274 struct drm_connector *connector;
275 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
276 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
277
278 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
279 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
280 switch (radeon_connector->hpd.hpd) {
281 case RADEON_HPD_1:
282 WREG32(DC_HPD1_CONTROL, tmp);
283 rdev->irq.hpd[0] = true;
284 break;
285 case RADEON_HPD_2:
286 WREG32(DC_HPD2_CONTROL, tmp);
287 rdev->irq.hpd[1] = true;
288 break;
289 case RADEON_HPD_3:
290 WREG32(DC_HPD3_CONTROL, tmp);
291 rdev->irq.hpd[2] = true;
292 break;
293 case RADEON_HPD_4:
294 WREG32(DC_HPD4_CONTROL, tmp);
295 rdev->irq.hpd[3] = true;
296 break;
297 case RADEON_HPD_5:
298 WREG32(DC_HPD5_CONTROL, tmp);
299 rdev->irq.hpd[4] = true;
300 break;
301 case RADEON_HPD_6:
302 WREG32(DC_HPD6_CONTROL, tmp);
303 rdev->irq.hpd[5] = true;
304 break;
305 default:
306 break;
307 }
308 }
309 if (rdev->irq.installed)
310 evergreen_irq_set(rdev);
311 }
312
313 void evergreen_hpd_fini(struct radeon_device *rdev)
314 {
315 struct drm_device *dev = rdev->ddev;
316 struct drm_connector *connector;
317
318 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
319 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
320 switch (radeon_connector->hpd.hpd) {
321 case RADEON_HPD_1:
322 WREG32(DC_HPD1_CONTROL, 0);
323 rdev->irq.hpd[0] = false;
324 break;
325 case RADEON_HPD_2:
326 WREG32(DC_HPD2_CONTROL, 0);
327 rdev->irq.hpd[1] = false;
328 break;
329 case RADEON_HPD_3:
330 WREG32(DC_HPD3_CONTROL, 0);
331 rdev->irq.hpd[2] = false;
332 break;
333 case RADEON_HPD_4:
334 WREG32(DC_HPD4_CONTROL, 0);
335 rdev->irq.hpd[3] = false;
336 break;
337 case RADEON_HPD_5:
338 WREG32(DC_HPD5_CONTROL, 0);
339 rdev->irq.hpd[4] = false;
340 break;
341 case RADEON_HPD_6:
342 WREG32(DC_HPD6_CONTROL, 0);
343 rdev->irq.hpd[5] = false;
344 break;
345 default:
346 break;
347 }
348 }
349 }
350
351 /* watermark setup */
352
353 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
354 struct radeon_crtc *radeon_crtc,
355 struct drm_display_mode *mode,
356 struct drm_display_mode *other_mode)
357 {
358 u32 tmp = 0;
359 /*
360 * Line Buffer Setup
361 * There are 3 line buffers, each one shared by 2 display controllers.
362 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
363 * the display controllers. The paritioning is done via one of four
364 * preset allocations specified in bits 2:0:
365 * first display controller
366 * 0 - first half of lb (3840 * 2)
367 * 1 - first 3/4 of lb (5760 * 2)
368 * 2 - whole lb (7680 * 2)
369 * 3 - first 1/4 of lb (1920 * 2)
370 * second display controller
371 * 4 - second half of lb (3840 * 2)
372 * 5 - second 3/4 of lb (5760 * 2)
373 * 6 - whole lb (7680 * 2)
374 * 7 - last 1/4 of lb (1920 * 2)
375 */
376 if (mode && other_mode) {
377 if (mode->hdisplay > other_mode->hdisplay) {
378 if (mode->hdisplay > 2560)
379 tmp = 1; /* 3/4 */
380 else
381 tmp = 0; /* 1/2 */
382 } else if (other_mode->hdisplay > mode->hdisplay) {
383 if (other_mode->hdisplay > 2560)
384 tmp = 3; /* 1/4 */
385 else
386 tmp = 0; /* 1/2 */
387 } else
388 tmp = 0; /* 1/2 */
389 } else if (mode)
390 tmp = 2; /* whole */
391 else if (other_mode)
392 tmp = 3; /* 1/4 */
393
394 /* second controller of the pair uses second half of the lb */
395 if (radeon_crtc->crtc_id % 2)
396 tmp += 4;
397 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
398
399 switch (tmp) {
400 case 0:
401 case 4:
402 default:
403 return 3840 * 2;
404 case 1:
405 case 5:
406 return 5760 * 2;
407 case 2:
408 case 6:
409 return 7680 * 2;
410 case 3:
411 case 7:
412 return 1920 * 2;
413 }
414 }
415
416 static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
417 {
418 u32 tmp = RREG32(MC_SHARED_CHMAP);
419
420 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
421 case 0:
422 default:
423 return 1;
424 case 1:
425 return 2;
426 case 2:
427 return 4;
428 case 3:
429 return 8;
430 }
431 }
432
433 struct evergreen_wm_params {
434 u32 dram_channels; /* number of dram channels */
435 u32 yclk; /* bandwidth per dram data pin in kHz */
436 u32 sclk; /* engine clock in kHz */
437 u32 disp_clk; /* display clock in kHz */
438 u32 src_width; /* viewport width */
439 u32 active_time; /* active display time in ns */
440 u32 blank_time; /* blank time in ns */
441 bool interlaced; /* mode is interlaced */
442 fixed20_12 vsc; /* vertical scale ratio */
443 u32 num_heads; /* number of active crtcs */
444 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
445 u32 lb_size; /* line buffer allocated to pipe */
446 u32 vtaps; /* vertical scaler taps */
447 };
448
449 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
450 {
451 /* Calculate DRAM Bandwidth and the part allocated to display. */
452 fixed20_12 dram_efficiency; /* 0.7 */
453 fixed20_12 yclk, dram_channels, bandwidth;
454 fixed20_12 a;
455
456 a.full = dfixed_const(1000);
457 yclk.full = dfixed_const(wm->yclk);
458 yclk.full = dfixed_div(yclk, a);
459 dram_channels.full = dfixed_const(wm->dram_channels * 4);
460 a.full = dfixed_const(10);
461 dram_efficiency.full = dfixed_const(7);
462 dram_efficiency.full = dfixed_div(dram_efficiency, a);
463 bandwidth.full = dfixed_mul(dram_channels, yclk);
464 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
465
466 return dfixed_trunc(bandwidth);
467 }
468
469 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
470 {
471 /* Calculate DRAM Bandwidth and the part allocated to display. */
472 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
473 fixed20_12 yclk, dram_channels, bandwidth;
474 fixed20_12 a;
475
476 a.full = dfixed_const(1000);
477 yclk.full = dfixed_const(wm->yclk);
478 yclk.full = dfixed_div(yclk, a);
479 dram_channels.full = dfixed_const(wm->dram_channels * 4);
480 a.full = dfixed_const(10);
481 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
482 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
483 bandwidth.full = dfixed_mul(dram_channels, yclk);
484 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
485
486 return dfixed_trunc(bandwidth);
487 }
488
489 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
490 {
491 /* Calculate the display Data return Bandwidth */
492 fixed20_12 return_efficiency; /* 0.8 */
493 fixed20_12 sclk, bandwidth;
494 fixed20_12 a;
495
496 a.full = dfixed_const(1000);
497 sclk.full = dfixed_const(wm->sclk);
498 sclk.full = dfixed_div(sclk, a);
499 a.full = dfixed_const(10);
500 return_efficiency.full = dfixed_const(8);
501 return_efficiency.full = dfixed_div(return_efficiency, a);
502 a.full = dfixed_const(32);
503 bandwidth.full = dfixed_mul(a, sclk);
504 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
505
506 return dfixed_trunc(bandwidth);
507 }
508
509 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
510 {
511 /* Calculate the DMIF Request Bandwidth */
512 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
513 fixed20_12 disp_clk, bandwidth;
514 fixed20_12 a;
515
516 a.full = dfixed_const(1000);
517 disp_clk.full = dfixed_const(wm->disp_clk);
518 disp_clk.full = dfixed_div(disp_clk, a);
519 a.full = dfixed_const(10);
520 disp_clk_request_efficiency.full = dfixed_const(8);
521 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
522 a.full = dfixed_const(32);
523 bandwidth.full = dfixed_mul(a, disp_clk);
524 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
525
526 return dfixed_trunc(bandwidth);
527 }
528
529 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
530 {
531 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
532 u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
533 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
534 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
535
536 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
537 }
538
539 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
540 {
541 /* Calculate the display mode Average Bandwidth
542 * DisplayMode should contain the source and destination dimensions,
543 * timing, etc.
544 */
545 fixed20_12 bpp;
546 fixed20_12 line_time;
547 fixed20_12 src_width;
548 fixed20_12 bandwidth;
549 fixed20_12 a;
550
551 a.full = dfixed_const(1000);
552 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
553 line_time.full = dfixed_div(line_time, a);
554 bpp.full = dfixed_const(wm->bytes_per_pixel);
555 src_width.full = dfixed_const(wm->src_width);
556 bandwidth.full = dfixed_mul(src_width, bpp);
557 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
558 bandwidth.full = dfixed_div(bandwidth, line_time);
559
560 return dfixed_trunc(bandwidth);
561 }
562
563 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
564 {
565 /* First calcualte the latency in ns */
566 u32 mc_latency = 2000; /* 2000 ns. */
567 u32 available_bandwidth = evergreen_available_bandwidth(wm);
568 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
569 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
570 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
571 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
572 (wm->num_heads * cursor_line_pair_return_time);
573 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
574 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
575 fixed20_12 a, b, c;
576
577 if (wm->num_heads == 0)
578 return 0;
579
580 a.full = dfixed_const(2);
581 b.full = dfixed_const(1);
582 if ((wm->vsc.full > a.full) ||
583 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
584 (wm->vtaps >= 5) ||
585 ((wm->vsc.full >= a.full) && wm->interlaced))
586 max_src_lines_per_dst_line = 4;
587 else
588 max_src_lines_per_dst_line = 2;
589
590 a.full = dfixed_const(available_bandwidth);
591 b.full = dfixed_const(wm->num_heads);
592 a.full = dfixed_div(a, b);
593
594 b.full = dfixed_const(1000);
595 c.full = dfixed_const(wm->disp_clk);
596 b.full = dfixed_div(c, b);
597 c.full = dfixed_const(wm->bytes_per_pixel);
598 b.full = dfixed_mul(b, c);
599
600 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
601
602 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
603 b.full = dfixed_const(1000);
604 c.full = dfixed_const(lb_fill_bw);
605 b.full = dfixed_div(c, b);
606 a.full = dfixed_div(a, b);
607 line_fill_time = dfixed_trunc(a);
608
609 if (line_fill_time < wm->active_time)
610 return latency;
611 else
612 return latency + (line_fill_time - wm->active_time);
613
614 }
615
616 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
617 {
618 if (evergreen_average_bandwidth(wm) <=
619 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
620 return true;
621 else
622 return false;
623 };
624
625 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
626 {
627 if (evergreen_average_bandwidth(wm) <=
628 (evergreen_available_bandwidth(wm) / wm->num_heads))
629 return true;
630 else
631 return false;
632 };
633
634 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
635 {
636 u32 lb_partitions = wm->lb_size / wm->src_width;
637 u32 line_time = wm->active_time + wm->blank_time;
638 u32 latency_tolerant_lines;
639 u32 latency_hiding;
640 fixed20_12 a;
641
642 a.full = dfixed_const(1);
643 if (wm->vsc.full > a.full)
644 latency_tolerant_lines = 1;
645 else {
646 if (lb_partitions <= (wm->vtaps + 1))
647 latency_tolerant_lines = 1;
648 else
649 latency_tolerant_lines = 2;
650 }
651
652 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
653
654 if (evergreen_latency_watermark(wm) <= latency_hiding)
655 return true;
656 else
657 return false;
658 }
659
660 static void evergreen_program_watermarks(struct radeon_device *rdev,
661 struct radeon_crtc *radeon_crtc,
662 u32 lb_size, u32 num_heads)
663 {
664 struct drm_display_mode *mode = &radeon_crtc->base.mode;
665 struct evergreen_wm_params wm;
666 u32 pixel_period;
667 u32 line_time = 0;
668 u32 latency_watermark_a = 0, latency_watermark_b = 0;
669 u32 priority_a_mark = 0, priority_b_mark = 0;
670 u32 priority_a_cnt = PRIORITY_OFF;
671 u32 priority_b_cnt = PRIORITY_OFF;
672 u32 pipe_offset = radeon_crtc->crtc_id * 16;
673 u32 tmp, arb_control3;
674 fixed20_12 a, b, c;
675
676 if (radeon_crtc->base.enabled && num_heads && mode) {
677 pixel_period = 1000000 / (u32)mode->clock;
678 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
679 priority_a_cnt = 0;
680 priority_b_cnt = 0;
681
682 wm.yclk = rdev->pm.current_mclk * 10;
683 wm.sclk = rdev->pm.current_sclk * 10;
684 wm.disp_clk = mode->clock;
685 wm.src_width = mode->crtc_hdisplay;
686 wm.active_time = mode->crtc_hdisplay * pixel_period;
687 wm.blank_time = line_time - wm.active_time;
688 wm.interlaced = false;
689 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
690 wm.interlaced = true;
691 wm.vsc = radeon_crtc->vsc;
692 wm.vtaps = 1;
693 if (radeon_crtc->rmx_type != RMX_OFF)
694 wm.vtaps = 2;
695 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
696 wm.lb_size = lb_size;
697 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
698 wm.num_heads = num_heads;
699
700 /* set for high clocks */
701 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
702 /* set for low clocks */
703 /* wm.yclk = low clk; wm.sclk = low clk */
704 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
705
706 /* possibly force display priority to high */
707 /* should really do this at mode validation time... */
708 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
709 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
710 !evergreen_check_latency_hiding(&wm) ||
711 (rdev->disp_priority == 2)) {
712 DRM_INFO("force priority to high\n");
713 priority_a_cnt |= PRIORITY_ALWAYS_ON;
714 priority_b_cnt |= PRIORITY_ALWAYS_ON;
715 }
716
717 a.full = dfixed_const(1000);
718 b.full = dfixed_const(mode->clock);
719 b.full = dfixed_div(b, a);
720 c.full = dfixed_const(latency_watermark_a);
721 c.full = dfixed_mul(c, b);
722 c.full = dfixed_mul(c, radeon_crtc->hsc);
723 c.full = dfixed_div(c, a);
724 a.full = dfixed_const(16);
725 c.full = dfixed_div(c, a);
726 priority_a_mark = dfixed_trunc(c);
727 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
728
729 a.full = dfixed_const(1000);
730 b.full = dfixed_const(mode->clock);
731 b.full = dfixed_div(b, a);
732 c.full = dfixed_const(latency_watermark_b);
733 c.full = dfixed_mul(c, b);
734 c.full = dfixed_mul(c, radeon_crtc->hsc);
735 c.full = dfixed_div(c, a);
736 a.full = dfixed_const(16);
737 c.full = dfixed_div(c, a);
738 priority_b_mark = dfixed_trunc(c);
739 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
740 }
741
742 /* select wm A */
743 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
744 tmp = arb_control3;
745 tmp &= ~LATENCY_WATERMARK_MASK(3);
746 tmp |= LATENCY_WATERMARK_MASK(1);
747 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
748 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
749 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
750 LATENCY_HIGH_WATERMARK(line_time)));
751 /* select wm B */
752 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
753 tmp &= ~LATENCY_WATERMARK_MASK(3);
754 tmp |= LATENCY_WATERMARK_MASK(2);
755 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
756 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
757 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
758 LATENCY_HIGH_WATERMARK(line_time)));
759 /* restore original selection */
760 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
761
762 /* write the priority marks */
763 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
764 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
765
766 }
767
768 void evergreen_bandwidth_update(struct radeon_device *rdev)
769 {
770 struct drm_display_mode *mode0 = NULL;
771 struct drm_display_mode *mode1 = NULL;
772 u32 num_heads = 0, lb_size;
773 int i;
774
775 radeon_update_display_priority(rdev);
776
777 for (i = 0; i < rdev->num_crtc; i++) {
778 if (rdev->mode_info.crtcs[i]->base.enabled)
779 num_heads++;
780 }
781 for (i = 0; i < rdev->num_crtc; i += 2) {
782 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
783 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
784 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
785 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
786 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
787 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
788 }
789 }
790
791 static int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
792 {
793 unsigned i;
794 u32 tmp;
795
796 for (i = 0; i < rdev->usec_timeout; i++) {
797 /* read MC_STATUS */
798 tmp = RREG32(SRBM_STATUS) & 0x1F00;
799 if (!tmp)
800 return 0;
801 udelay(1);
802 }
803 return -1;
804 }
805
806 /*
807 * GART
808 */
809 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
810 {
811 unsigned i;
812 u32 tmp;
813
814 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
815
816 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
817 for (i = 0; i < rdev->usec_timeout; i++) {
818 /* read MC_STATUS */
819 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
820 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
821 if (tmp == 2) {
822 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
823 return;
824 }
825 if (tmp) {
826 return;
827 }
828 udelay(1);
829 }
830 }
831
832 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
833 {
834 u32 tmp;
835 int r;
836
837 if (rdev->gart.table.vram.robj == NULL) {
838 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
839 return -EINVAL;
840 }
841 r = radeon_gart_table_vram_pin(rdev);
842 if (r)
843 return r;
844 radeon_gart_restore(rdev);
845 /* Setup L2 cache */
846 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
847 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
848 EFFECTIVE_L2_QUEUE_SIZE(7));
849 WREG32(VM_L2_CNTL2, 0);
850 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
851 /* Setup TLB control */
852 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
853 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
854 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
855 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
856 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
857 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
858 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
859 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
860 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
861 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
862 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
863 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
864 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
865 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
866 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
867 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
868 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
869 (u32)(rdev->dummy_page.addr >> 12));
870 WREG32(VM_CONTEXT1_CNTL, 0);
871
872 evergreen_pcie_gart_tlb_flush(rdev);
873 rdev->gart.ready = true;
874 return 0;
875 }
876
877 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
878 {
879 u32 tmp;
880 int r;
881
882 /* Disable all tables */
883 WREG32(VM_CONTEXT0_CNTL, 0);
884 WREG32(VM_CONTEXT1_CNTL, 0);
885
886 /* Setup L2 cache */
887 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
888 EFFECTIVE_L2_QUEUE_SIZE(7));
889 WREG32(VM_L2_CNTL2, 0);
890 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
891 /* Setup TLB control */
892 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
893 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
894 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
895 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
896 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
897 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
898 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
899 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
900 if (rdev->gart.table.vram.robj) {
901 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
902 if (likely(r == 0)) {
903 radeon_bo_kunmap(rdev->gart.table.vram.robj);
904 radeon_bo_unpin(rdev->gart.table.vram.robj);
905 radeon_bo_unreserve(rdev->gart.table.vram.robj);
906 }
907 }
908 }
909
910 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
911 {
912 evergreen_pcie_gart_disable(rdev);
913 radeon_gart_table_vram_free(rdev);
914 radeon_gart_fini(rdev);
915 }
916
917
918 void evergreen_agp_enable(struct radeon_device *rdev)
919 {
920 u32 tmp;
921
922 /* Setup L2 cache */
923 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
924 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
925 EFFECTIVE_L2_QUEUE_SIZE(7));
926 WREG32(VM_L2_CNTL2, 0);
927 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
928 /* Setup TLB control */
929 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
930 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
931 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
932 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
933 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
934 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
935 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
936 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
937 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
938 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
939 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
940 WREG32(VM_CONTEXT0_CNTL, 0);
941 WREG32(VM_CONTEXT1_CNTL, 0);
942 }
943
944 static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
945 {
946 save->vga_control[0] = RREG32(D1VGA_CONTROL);
947 save->vga_control[1] = RREG32(D2VGA_CONTROL);
948 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
949 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
950 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
951 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
952 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
953 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
954 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
955 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
956 if (!(rdev->flags & RADEON_IS_IGP)) {
957 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
958 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
959 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
960 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
961 }
962
963 /* Stop all video */
964 WREG32(VGA_RENDER_CONTROL, 0);
965 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
966 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
967 if (!(rdev->flags & RADEON_IS_IGP)) {
968 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
969 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
970 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
971 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
972 }
973 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
974 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
975 if (!(rdev->flags & RADEON_IS_IGP)) {
976 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
977 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
978 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
979 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
980 }
981 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
982 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
983 if (!(rdev->flags & RADEON_IS_IGP)) {
984 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
985 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
986 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
987 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
988 }
989
990 WREG32(D1VGA_CONTROL, 0);
991 WREG32(D2VGA_CONTROL, 0);
992 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
993 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
994 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
995 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
996 }
997
998 static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
999 {
1000 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1001 upper_32_bits(rdev->mc.vram_start));
1002 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1003 upper_32_bits(rdev->mc.vram_start));
1004 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1005 (u32)rdev->mc.vram_start);
1006 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1007 (u32)rdev->mc.vram_start);
1008
1009 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1010 upper_32_bits(rdev->mc.vram_start));
1011 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1012 upper_32_bits(rdev->mc.vram_start));
1013 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1014 (u32)rdev->mc.vram_start);
1015 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1016 (u32)rdev->mc.vram_start);
1017
1018 if (!(rdev->flags & RADEON_IS_IGP)) {
1019 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1020 upper_32_bits(rdev->mc.vram_start));
1021 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1022 upper_32_bits(rdev->mc.vram_start));
1023 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1024 (u32)rdev->mc.vram_start);
1025 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1026 (u32)rdev->mc.vram_start);
1027
1028 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1029 upper_32_bits(rdev->mc.vram_start));
1030 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1031 upper_32_bits(rdev->mc.vram_start));
1032 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1033 (u32)rdev->mc.vram_start);
1034 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1035 (u32)rdev->mc.vram_start);
1036
1037 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1038 upper_32_bits(rdev->mc.vram_start));
1039 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1040 upper_32_bits(rdev->mc.vram_start));
1041 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1042 (u32)rdev->mc.vram_start);
1043 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1044 (u32)rdev->mc.vram_start);
1045
1046 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1047 upper_32_bits(rdev->mc.vram_start));
1048 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1049 upper_32_bits(rdev->mc.vram_start));
1050 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1051 (u32)rdev->mc.vram_start);
1052 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1053 (u32)rdev->mc.vram_start);
1054 }
1055
1056 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1057 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1058 /* Unlock host access */
1059 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1060 mdelay(1);
1061 /* Restore video state */
1062 WREG32(D1VGA_CONTROL, save->vga_control[0]);
1063 WREG32(D2VGA_CONTROL, save->vga_control[1]);
1064 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1065 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1066 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1067 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1068 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1069 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1070 if (!(rdev->flags & RADEON_IS_IGP)) {
1071 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1072 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1073 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1074 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1075 }
1076 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1077 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1078 if (!(rdev->flags & RADEON_IS_IGP)) {
1079 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1080 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1081 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1082 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1083 }
1084 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1085 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1086 if (!(rdev->flags & RADEON_IS_IGP)) {
1087 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1088 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1089 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1090 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1091 }
1092 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1093 }
1094
1095 static void evergreen_mc_program(struct radeon_device *rdev)
1096 {
1097 struct evergreen_mc_save save;
1098 u32 tmp;
1099 int i, j;
1100
1101 /* Initialize HDP */
1102 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1103 WREG32((0x2c14 + j), 0x00000000);
1104 WREG32((0x2c18 + j), 0x00000000);
1105 WREG32((0x2c1c + j), 0x00000000);
1106 WREG32((0x2c20 + j), 0x00000000);
1107 WREG32((0x2c24 + j), 0x00000000);
1108 }
1109 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1110
1111 evergreen_mc_stop(rdev, &save);
1112 if (evergreen_mc_wait_for_idle(rdev)) {
1113 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1114 }
1115 /* Lockout access through VGA aperture*/
1116 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1117 /* Update configuration */
1118 if (rdev->flags & RADEON_IS_AGP) {
1119 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1120 /* VRAM before AGP */
1121 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1122 rdev->mc.vram_start >> 12);
1123 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1124 rdev->mc.gtt_end >> 12);
1125 } else {
1126 /* VRAM after AGP */
1127 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1128 rdev->mc.gtt_start >> 12);
1129 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1130 rdev->mc.vram_end >> 12);
1131 }
1132 } else {
1133 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1134 rdev->mc.vram_start >> 12);
1135 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1136 rdev->mc.vram_end >> 12);
1137 }
1138 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1139 if (rdev->flags & RADEON_IS_IGP) {
1140 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1141 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1142 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1143 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1144 }
1145 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1146 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1147 WREG32(MC_VM_FB_LOCATION, tmp);
1148 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1149 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1150 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1151 if (rdev->flags & RADEON_IS_AGP) {
1152 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1153 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1154 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1155 } else {
1156 WREG32(MC_VM_AGP_BASE, 0);
1157 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1158 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1159 }
1160 if (evergreen_mc_wait_for_idle(rdev)) {
1161 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1162 }
1163 evergreen_mc_resume(rdev, &save);
1164 /* we need to own VRAM, so turn off the VGA renderer here
1165 * to stop it overwriting our objects */
1166 rv515_vga_render_disable(rdev);
1167 }
1168
1169 /*
1170 * CP.
1171 */
1172
1173 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1174 {
1175 const __be32 *fw_data;
1176 int i;
1177
1178 if (!rdev->me_fw || !rdev->pfp_fw)
1179 return -EINVAL;
1180
1181 r700_cp_stop(rdev);
1182 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
1183
1184 fw_data = (const __be32 *)rdev->pfp_fw->data;
1185 WREG32(CP_PFP_UCODE_ADDR, 0);
1186 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1187 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1188 WREG32(CP_PFP_UCODE_ADDR, 0);
1189
1190 fw_data = (const __be32 *)rdev->me_fw->data;
1191 WREG32(CP_ME_RAM_WADDR, 0);
1192 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1193 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1194
1195 WREG32(CP_PFP_UCODE_ADDR, 0);
1196 WREG32(CP_ME_RAM_WADDR, 0);
1197 WREG32(CP_ME_RAM_RADDR, 0);
1198 return 0;
1199 }
1200
1201 static int evergreen_cp_start(struct radeon_device *rdev)
1202 {
1203 int r, i;
1204 uint32_t cp_me;
1205
1206 r = radeon_ring_lock(rdev, 7);
1207 if (r) {
1208 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1209 return r;
1210 }
1211 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1212 radeon_ring_write(rdev, 0x1);
1213 radeon_ring_write(rdev, 0x0);
1214 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1215 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1216 radeon_ring_write(rdev, 0);
1217 radeon_ring_write(rdev, 0);
1218 radeon_ring_unlock_commit(rdev);
1219
1220 cp_me = 0xff;
1221 WREG32(CP_ME_CNTL, cp_me);
1222
1223 r = radeon_ring_lock(rdev, evergreen_default_size + 15);
1224 if (r) {
1225 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1226 return r;
1227 }
1228
1229 /* setup clear context state */
1230 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1231 radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1232
1233 for (i = 0; i < evergreen_default_size; i++)
1234 radeon_ring_write(rdev, evergreen_default_state[i]);
1235
1236 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1237 radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1238
1239 /* set clear context state */
1240 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1241 radeon_ring_write(rdev, 0);
1242
1243 /* SQ_VTX_BASE_VTX_LOC */
1244 radeon_ring_write(rdev, 0xc0026f00);
1245 radeon_ring_write(rdev, 0x00000000);
1246 radeon_ring_write(rdev, 0x00000000);
1247 radeon_ring_write(rdev, 0x00000000);
1248
1249 /* Clear consts */
1250 radeon_ring_write(rdev, 0xc0036f00);
1251 radeon_ring_write(rdev, 0x00000bc4);
1252 radeon_ring_write(rdev, 0xffffffff);
1253 radeon_ring_write(rdev, 0xffffffff);
1254 radeon_ring_write(rdev, 0xffffffff);
1255
1256 radeon_ring_unlock_commit(rdev);
1257
1258 return 0;
1259 }
1260
1261 int evergreen_cp_resume(struct radeon_device *rdev)
1262 {
1263 u32 tmp;
1264 u32 rb_bufsz;
1265 int r;
1266
1267 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1268 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1269 SOFT_RESET_PA |
1270 SOFT_RESET_SH |
1271 SOFT_RESET_VGT |
1272 SOFT_RESET_SX));
1273 RREG32(GRBM_SOFT_RESET);
1274 mdelay(15);
1275 WREG32(GRBM_SOFT_RESET, 0);
1276 RREG32(GRBM_SOFT_RESET);
1277
1278 /* Set ring buffer size */
1279 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1280 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1281 #ifdef __BIG_ENDIAN
1282 tmp |= BUF_SWAP_32BIT;
1283 #endif
1284 WREG32(CP_RB_CNTL, tmp);
1285 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1286
1287 /* Set the write pointer delay */
1288 WREG32(CP_RB_WPTR_DELAY, 0);
1289
1290 /* Initialize the ring buffer's read and write pointers */
1291 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1292 WREG32(CP_RB_RPTR_WR, 0);
1293 WREG32(CP_RB_WPTR, 0);
1294
1295 /* set the wb address wether it's enabled or not */
1296 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
1297 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1298 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1299
1300 if (rdev->wb.enabled)
1301 WREG32(SCRATCH_UMSK, 0xff);
1302 else {
1303 tmp |= RB_NO_UPDATE;
1304 WREG32(SCRATCH_UMSK, 0);
1305 }
1306
1307 mdelay(1);
1308 WREG32(CP_RB_CNTL, tmp);
1309
1310 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1311 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1312
1313 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1314 rdev->cp.wptr = RREG32(CP_RB_WPTR);
1315
1316 evergreen_cp_start(rdev);
1317 rdev->cp.ready = true;
1318 r = radeon_ring_test(rdev);
1319 if (r) {
1320 rdev->cp.ready = false;
1321 return r;
1322 }
1323 return 0;
1324 }
1325
1326 /*
1327 * Core functions
1328 */
1329 static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1330 u32 num_tile_pipes,
1331 u32 num_backends,
1332 u32 backend_disable_mask)
1333 {
1334 u32 backend_map = 0;
1335 u32 enabled_backends_mask = 0;
1336 u32 enabled_backends_count = 0;
1337 u32 cur_pipe;
1338 u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1339 u32 cur_backend = 0;
1340 u32 i;
1341 bool force_no_swizzle;
1342
1343 if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1344 num_tile_pipes = EVERGREEN_MAX_PIPES;
1345 if (num_tile_pipes < 1)
1346 num_tile_pipes = 1;
1347 if (num_backends > EVERGREEN_MAX_BACKENDS)
1348 num_backends = EVERGREEN_MAX_BACKENDS;
1349 if (num_backends < 1)
1350 num_backends = 1;
1351
1352 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1353 if (((backend_disable_mask >> i) & 1) == 0) {
1354 enabled_backends_mask |= (1 << i);
1355 ++enabled_backends_count;
1356 }
1357 if (enabled_backends_count == num_backends)
1358 break;
1359 }
1360
1361 if (enabled_backends_count == 0) {
1362 enabled_backends_mask = 1;
1363 enabled_backends_count = 1;
1364 }
1365
1366 if (enabled_backends_count != num_backends)
1367 num_backends = enabled_backends_count;
1368
1369 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1370 switch (rdev->family) {
1371 case CHIP_CEDAR:
1372 case CHIP_REDWOOD:
1373 case CHIP_PALM:
1374 force_no_swizzle = false;
1375 break;
1376 case CHIP_CYPRESS:
1377 case CHIP_HEMLOCK:
1378 case CHIP_JUNIPER:
1379 default:
1380 force_no_swizzle = true;
1381 break;
1382 }
1383 if (force_no_swizzle) {
1384 bool last_backend_enabled = false;
1385
1386 force_no_swizzle = false;
1387 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1388 if (((enabled_backends_mask >> i) & 1) == 1) {
1389 if (last_backend_enabled)
1390 force_no_swizzle = true;
1391 last_backend_enabled = true;
1392 } else
1393 last_backend_enabled = false;
1394 }
1395 }
1396
1397 switch (num_tile_pipes) {
1398 case 1:
1399 case 3:
1400 case 5:
1401 case 7:
1402 DRM_ERROR("odd number of pipes!\n");
1403 break;
1404 case 2:
1405 swizzle_pipe[0] = 0;
1406 swizzle_pipe[1] = 1;
1407 break;
1408 case 4:
1409 if (force_no_swizzle) {
1410 swizzle_pipe[0] = 0;
1411 swizzle_pipe[1] = 1;
1412 swizzle_pipe[2] = 2;
1413 swizzle_pipe[3] = 3;
1414 } else {
1415 swizzle_pipe[0] = 0;
1416 swizzle_pipe[1] = 2;
1417 swizzle_pipe[2] = 1;
1418 swizzle_pipe[3] = 3;
1419 }
1420 break;
1421 case 6:
1422 if (force_no_swizzle) {
1423 swizzle_pipe[0] = 0;
1424 swizzle_pipe[1] = 1;
1425 swizzle_pipe[2] = 2;
1426 swizzle_pipe[3] = 3;
1427 swizzle_pipe[4] = 4;
1428 swizzle_pipe[5] = 5;
1429 } else {
1430 swizzle_pipe[0] = 0;
1431 swizzle_pipe[1] = 2;
1432 swizzle_pipe[2] = 4;
1433 swizzle_pipe[3] = 1;
1434 swizzle_pipe[4] = 3;
1435 swizzle_pipe[5] = 5;
1436 }
1437 break;
1438 case 8:
1439 if (force_no_swizzle) {
1440 swizzle_pipe[0] = 0;
1441 swizzle_pipe[1] = 1;
1442 swizzle_pipe[2] = 2;
1443 swizzle_pipe[3] = 3;
1444 swizzle_pipe[4] = 4;
1445 swizzle_pipe[5] = 5;
1446 swizzle_pipe[6] = 6;
1447 swizzle_pipe[7] = 7;
1448 } else {
1449 swizzle_pipe[0] = 0;
1450 swizzle_pipe[1] = 2;
1451 swizzle_pipe[2] = 4;
1452 swizzle_pipe[3] = 6;
1453 swizzle_pipe[4] = 1;
1454 swizzle_pipe[5] = 3;
1455 swizzle_pipe[6] = 5;
1456 swizzle_pipe[7] = 7;
1457 }
1458 break;
1459 }
1460
1461 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1462 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1463 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1464
1465 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1466
1467 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1468 }
1469
1470 return backend_map;
1471 }
1472
1473 static void evergreen_program_channel_remap(struct radeon_device *rdev)
1474 {
1475 u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
1476
1477 tmp = RREG32(MC_SHARED_CHMAP);
1478 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1479 case 0:
1480 case 1:
1481 case 2:
1482 case 3:
1483 default:
1484 /* default mapping */
1485 mc_shared_chremap = 0x00fac688;
1486 break;
1487 }
1488
1489 switch (rdev->family) {
1490 case CHIP_HEMLOCK:
1491 case CHIP_CYPRESS:
1492 tcp_chan_steer_lo = 0x54763210;
1493 tcp_chan_steer_hi = 0x0000ba98;
1494 break;
1495 case CHIP_JUNIPER:
1496 case CHIP_REDWOOD:
1497 case CHIP_CEDAR:
1498 case CHIP_PALM:
1499 default:
1500 tcp_chan_steer_lo = 0x76543210;
1501 tcp_chan_steer_hi = 0x0000ba98;
1502 break;
1503 }
1504
1505 WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
1506 WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
1507 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
1508 }
1509
1510 static void evergreen_gpu_init(struct radeon_device *rdev)
1511 {
1512 u32 cc_rb_backend_disable = 0;
1513 u32 cc_gc_shader_pipe_config;
1514 u32 gb_addr_config = 0;
1515 u32 mc_shared_chmap, mc_arb_ramcfg;
1516 u32 gb_backend_map;
1517 u32 grbm_gfx_index;
1518 u32 sx_debug_1;
1519 u32 smx_dc_ctl0;
1520 u32 sq_config;
1521 u32 sq_lds_resource_mgmt;
1522 u32 sq_gpr_resource_mgmt_1;
1523 u32 sq_gpr_resource_mgmt_2;
1524 u32 sq_gpr_resource_mgmt_3;
1525 u32 sq_thread_resource_mgmt;
1526 u32 sq_thread_resource_mgmt_2;
1527 u32 sq_stack_resource_mgmt_1;
1528 u32 sq_stack_resource_mgmt_2;
1529 u32 sq_stack_resource_mgmt_3;
1530 u32 vgt_cache_invalidation;
1531 u32 hdp_host_path_cntl;
1532 int i, j, num_shader_engines, ps_thread_count;
1533
1534 switch (rdev->family) {
1535 case CHIP_CYPRESS:
1536 case CHIP_HEMLOCK:
1537 rdev->config.evergreen.num_ses = 2;
1538 rdev->config.evergreen.max_pipes = 4;
1539 rdev->config.evergreen.max_tile_pipes = 8;
1540 rdev->config.evergreen.max_simds = 10;
1541 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1542 rdev->config.evergreen.max_gprs = 256;
1543 rdev->config.evergreen.max_threads = 248;
1544 rdev->config.evergreen.max_gs_threads = 32;
1545 rdev->config.evergreen.max_stack_entries = 512;
1546 rdev->config.evergreen.sx_num_of_sets = 4;
1547 rdev->config.evergreen.sx_max_export_size = 256;
1548 rdev->config.evergreen.sx_max_export_pos_size = 64;
1549 rdev->config.evergreen.sx_max_export_smx_size = 192;
1550 rdev->config.evergreen.max_hw_contexts = 8;
1551 rdev->config.evergreen.sq_num_cf_insts = 2;
1552
1553 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1554 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1555 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1556 break;
1557 case CHIP_JUNIPER:
1558 rdev->config.evergreen.num_ses = 1;
1559 rdev->config.evergreen.max_pipes = 4;
1560 rdev->config.evergreen.max_tile_pipes = 4;
1561 rdev->config.evergreen.max_simds = 10;
1562 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1563 rdev->config.evergreen.max_gprs = 256;
1564 rdev->config.evergreen.max_threads = 248;
1565 rdev->config.evergreen.max_gs_threads = 32;
1566 rdev->config.evergreen.max_stack_entries = 512;
1567 rdev->config.evergreen.sx_num_of_sets = 4;
1568 rdev->config.evergreen.sx_max_export_size = 256;
1569 rdev->config.evergreen.sx_max_export_pos_size = 64;
1570 rdev->config.evergreen.sx_max_export_smx_size = 192;
1571 rdev->config.evergreen.max_hw_contexts = 8;
1572 rdev->config.evergreen.sq_num_cf_insts = 2;
1573
1574 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1575 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1576 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1577 break;
1578 case CHIP_REDWOOD:
1579 rdev->config.evergreen.num_ses = 1;
1580 rdev->config.evergreen.max_pipes = 4;
1581 rdev->config.evergreen.max_tile_pipes = 4;
1582 rdev->config.evergreen.max_simds = 5;
1583 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1584 rdev->config.evergreen.max_gprs = 256;
1585 rdev->config.evergreen.max_threads = 248;
1586 rdev->config.evergreen.max_gs_threads = 32;
1587 rdev->config.evergreen.max_stack_entries = 256;
1588 rdev->config.evergreen.sx_num_of_sets = 4;
1589 rdev->config.evergreen.sx_max_export_size = 256;
1590 rdev->config.evergreen.sx_max_export_pos_size = 64;
1591 rdev->config.evergreen.sx_max_export_smx_size = 192;
1592 rdev->config.evergreen.max_hw_contexts = 8;
1593 rdev->config.evergreen.sq_num_cf_insts = 2;
1594
1595 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1596 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1597 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1598 break;
1599 case CHIP_CEDAR:
1600 default:
1601 rdev->config.evergreen.num_ses = 1;
1602 rdev->config.evergreen.max_pipes = 2;
1603 rdev->config.evergreen.max_tile_pipes = 2;
1604 rdev->config.evergreen.max_simds = 2;
1605 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1606 rdev->config.evergreen.max_gprs = 256;
1607 rdev->config.evergreen.max_threads = 192;
1608 rdev->config.evergreen.max_gs_threads = 16;
1609 rdev->config.evergreen.max_stack_entries = 256;
1610 rdev->config.evergreen.sx_num_of_sets = 4;
1611 rdev->config.evergreen.sx_max_export_size = 128;
1612 rdev->config.evergreen.sx_max_export_pos_size = 32;
1613 rdev->config.evergreen.sx_max_export_smx_size = 96;
1614 rdev->config.evergreen.max_hw_contexts = 4;
1615 rdev->config.evergreen.sq_num_cf_insts = 1;
1616
1617 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1618 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1619 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1620 break;
1621 case CHIP_PALM:
1622 rdev->config.evergreen.num_ses = 1;
1623 rdev->config.evergreen.max_pipes = 2;
1624 rdev->config.evergreen.max_tile_pipes = 2;
1625 rdev->config.evergreen.max_simds = 2;
1626 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1627 rdev->config.evergreen.max_gprs = 256;
1628 rdev->config.evergreen.max_threads = 192;
1629 rdev->config.evergreen.max_gs_threads = 16;
1630 rdev->config.evergreen.max_stack_entries = 256;
1631 rdev->config.evergreen.sx_num_of_sets = 4;
1632 rdev->config.evergreen.sx_max_export_size = 128;
1633 rdev->config.evergreen.sx_max_export_pos_size = 32;
1634 rdev->config.evergreen.sx_max_export_smx_size = 96;
1635 rdev->config.evergreen.max_hw_contexts = 4;
1636 rdev->config.evergreen.sq_num_cf_insts = 1;
1637
1638 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1639 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1640 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1641 break;
1642 }
1643
1644 /* Initialize HDP */
1645 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1646 WREG32((0x2c14 + j), 0x00000000);
1647 WREG32((0x2c18 + j), 0x00000000);
1648 WREG32((0x2c1c + j), 0x00000000);
1649 WREG32((0x2c20 + j), 0x00000000);
1650 WREG32((0x2c24 + j), 0x00000000);
1651 }
1652
1653 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1654
1655 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1656
1657 cc_gc_shader_pipe_config |=
1658 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1659 & EVERGREEN_MAX_PIPES_MASK);
1660 cc_gc_shader_pipe_config |=
1661 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1662 & EVERGREEN_MAX_SIMDS_MASK);
1663
1664 cc_rb_backend_disable =
1665 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1666 & EVERGREEN_MAX_BACKENDS_MASK);
1667
1668
1669 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1670 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1671
1672 switch (rdev->config.evergreen.max_tile_pipes) {
1673 case 1:
1674 default:
1675 gb_addr_config |= NUM_PIPES(0);
1676 break;
1677 case 2:
1678 gb_addr_config |= NUM_PIPES(1);
1679 break;
1680 case 4:
1681 gb_addr_config |= NUM_PIPES(2);
1682 break;
1683 case 8:
1684 gb_addr_config |= NUM_PIPES(3);
1685 break;
1686 }
1687
1688 gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1689 gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1690 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1691 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1692 gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1693 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1694
1695 if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1696 gb_addr_config |= ROW_SIZE(2);
1697 else
1698 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1699
1700 if (rdev->ddev->pdev->device == 0x689e) {
1701 u32 efuse_straps_4;
1702 u32 efuse_straps_3;
1703 u8 efuse_box_bit_131_124;
1704
1705 WREG32(RCU_IND_INDEX, 0x204);
1706 efuse_straps_4 = RREG32(RCU_IND_DATA);
1707 WREG32(RCU_IND_INDEX, 0x203);
1708 efuse_straps_3 = RREG32(RCU_IND_DATA);
1709 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1710
1711 switch(efuse_box_bit_131_124) {
1712 case 0x00:
1713 gb_backend_map = 0x76543210;
1714 break;
1715 case 0x55:
1716 gb_backend_map = 0x77553311;
1717 break;
1718 case 0x56:
1719 gb_backend_map = 0x77553300;
1720 break;
1721 case 0x59:
1722 gb_backend_map = 0x77552211;
1723 break;
1724 case 0x66:
1725 gb_backend_map = 0x77443300;
1726 break;
1727 case 0x99:
1728 gb_backend_map = 0x66552211;
1729 break;
1730 case 0x5a:
1731 gb_backend_map = 0x77552200;
1732 break;
1733 case 0xaa:
1734 gb_backend_map = 0x66442200;
1735 break;
1736 case 0x95:
1737 gb_backend_map = 0x66553311;
1738 break;
1739 default:
1740 DRM_ERROR("bad backend map, using default\n");
1741 gb_backend_map =
1742 evergreen_get_tile_pipe_to_backend_map(rdev,
1743 rdev->config.evergreen.max_tile_pipes,
1744 rdev->config.evergreen.max_backends,
1745 ((EVERGREEN_MAX_BACKENDS_MASK <<
1746 rdev->config.evergreen.max_backends) &
1747 EVERGREEN_MAX_BACKENDS_MASK));
1748 break;
1749 }
1750 } else if (rdev->ddev->pdev->device == 0x68b9) {
1751 u32 efuse_straps_3;
1752 u8 efuse_box_bit_127_124;
1753
1754 WREG32(RCU_IND_INDEX, 0x203);
1755 efuse_straps_3 = RREG32(RCU_IND_DATA);
1756 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
1757
1758 switch(efuse_box_bit_127_124) {
1759 case 0x0:
1760 gb_backend_map = 0x00003210;
1761 break;
1762 case 0x5:
1763 case 0x6:
1764 case 0x9:
1765 case 0xa:
1766 gb_backend_map = 0x00003311;
1767 break;
1768 default:
1769 DRM_ERROR("bad backend map, using default\n");
1770 gb_backend_map =
1771 evergreen_get_tile_pipe_to_backend_map(rdev,
1772 rdev->config.evergreen.max_tile_pipes,
1773 rdev->config.evergreen.max_backends,
1774 ((EVERGREEN_MAX_BACKENDS_MASK <<
1775 rdev->config.evergreen.max_backends) &
1776 EVERGREEN_MAX_BACKENDS_MASK));
1777 break;
1778 }
1779 } else {
1780 switch (rdev->family) {
1781 case CHIP_CYPRESS:
1782 case CHIP_HEMLOCK:
1783 gb_backend_map = 0x66442200;
1784 break;
1785 case CHIP_JUNIPER:
1786 gb_backend_map = 0x00006420;
1787 break;
1788 default:
1789 gb_backend_map =
1790 evergreen_get_tile_pipe_to_backend_map(rdev,
1791 rdev->config.evergreen.max_tile_pipes,
1792 rdev->config.evergreen.max_backends,
1793 ((EVERGREEN_MAX_BACKENDS_MASK <<
1794 rdev->config.evergreen.max_backends) &
1795 EVERGREEN_MAX_BACKENDS_MASK));
1796 }
1797 }
1798
1799 /* setup tiling info dword. gb_addr_config is not adequate since it does
1800 * not have bank info, so create a custom tiling dword.
1801 * bits 3:0 num_pipes
1802 * bits 7:4 num_banks
1803 * bits 11:8 group_size
1804 * bits 15:12 row_size
1805 */
1806 rdev->config.evergreen.tile_config = 0;
1807 switch (rdev->config.evergreen.max_tile_pipes) {
1808 case 1:
1809 default:
1810 rdev->config.evergreen.tile_config |= (0 << 0);
1811 break;
1812 case 2:
1813 rdev->config.evergreen.tile_config |= (1 << 0);
1814 break;
1815 case 4:
1816 rdev->config.evergreen.tile_config |= (2 << 0);
1817 break;
1818 case 8:
1819 rdev->config.evergreen.tile_config |= (3 << 0);
1820 break;
1821 }
1822 rdev->config.evergreen.tile_config |=
1823 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
1824 rdev->config.evergreen.tile_config |=
1825 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
1826 rdev->config.evergreen.tile_config |=
1827 ((gb_addr_config & 0x30000000) >> 28) << 12;
1828
1829 WREG32(GB_BACKEND_MAP, gb_backend_map);
1830 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1831 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1832 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1833
1834 evergreen_program_channel_remap(rdev);
1835
1836 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
1837 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
1838
1839 for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
1840 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
1841 u32 sp = cc_gc_shader_pipe_config;
1842 u32 gfx = grbm_gfx_index | SE_INDEX(i);
1843
1844 if (i == num_shader_engines) {
1845 rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
1846 sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
1847 }
1848
1849 WREG32(GRBM_GFX_INDEX, gfx);
1850 WREG32(RLC_GFX_INDEX, gfx);
1851
1852 WREG32(CC_RB_BACKEND_DISABLE, rb);
1853 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
1854 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
1855 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
1856 }
1857
1858 grbm_gfx_index |= SE_BROADCAST_WRITES;
1859 WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
1860 WREG32(RLC_GFX_INDEX, grbm_gfx_index);
1861
1862 WREG32(CGTS_SYS_TCC_DISABLE, 0);
1863 WREG32(CGTS_TCC_DISABLE, 0);
1864 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1865 WREG32(CGTS_USER_TCC_DISABLE, 0);
1866
1867 /* set HW defaults for 3D engine */
1868 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1869 ROQ_IB2_START(0x2b)));
1870
1871 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1872
1873 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
1874 SYNC_GRADIENT |
1875 SYNC_WALKER |
1876 SYNC_ALIGNER));
1877
1878 sx_debug_1 = RREG32(SX_DEBUG_1);
1879 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1880 WREG32(SX_DEBUG_1, sx_debug_1);
1881
1882
1883 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1884 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1885 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
1886 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1887
1888 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
1889 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
1890 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
1891
1892 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
1893 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
1894 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
1895
1896 WREG32(VGT_NUM_INSTANCES, 1);
1897 WREG32(SPI_CONFIG_CNTL, 0);
1898 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1899 WREG32(CP_PERFMON_CNTL, 0);
1900
1901 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
1902 FETCH_FIFO_HIWATER(0x4) |
1903 DONE_FIFO_HIWATER(0xe0) |
1904 ALU_UPDATE_FIFO_HIWATER(0x8)));
1905
1906 sq_config = RREG32(SQ_CONFIG);
1907 sq_config &= ~(PS_PRIO(3) |
1908 VS_PRIO(3) |
1909 GS_PRIO(3) |
1910 ES_PRIO(3));
1911 sq_config |= (VC_ENABLE |
1912 EXPORT_SRC_C |
1913 PS_PRIO(0) |
1914 VS_PRIO(1) |
1915 GS_PRIO(2) |
1916 ES_PRIO(3));
1917
1918 switch (rdev->family) {
1919 case CHIP_CEDAR:
1920 case CHIP_PALM:
1921 /* no vertex cache */
1922 sq_config &= ~VC_ENABLE;
1923 break;
1924 default:
1925 break;
1926 }
1927
1928 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
1929
1930 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
1931 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
1932 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
1933 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1934 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1935 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1936 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1937
1938 switch (rdev->family) {
1939 case CHIP_CEDAR:
1940 case CHIP_PALM:
1941 ps_thread_count = 96;
1942 break;
1943 default:
1944 ps_thread_count = 128;
1945 break;
1946 }
1947
1948 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
1949 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1950 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1951 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1952 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1953 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1954
1955 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1956 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1957 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1958 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1959 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1960 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1961
1962 WREG32(SQ_CONFIG, sq_config);
1963 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1964 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1965 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
1966 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1967 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
1968 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1969 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1970 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
1971 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
1972 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
1973
1974 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1975 FORCE_EOV_MAX_REZ_CNT(255)));
1976
1977 switch (rdev->family) {
1978 case CHIP_CEDAR:
1979 case CHIP_PALM:
1980 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
1981 break;
1982 default:
1983 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
1984 break;
1985 }
1986 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
1987 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
1988
1989 WREG32(VGT_GS_VERTEX_REUSE, 16);
1990 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1991
1992 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
1993 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
1994
1995 WREG32(CB_PERF_CTR0_SEL_0, 0);
1996 WREG32(CB_PERF_CTR0_SEL_1, 0);
1997 WREG32(CB_PERF_CTR1_SEL_0, 0);
1998 WREG32(CB_PERF_CTR1_SEL_1, 0);
1999 WREG32(CB_PERF_CTR2_SEL_0, 0);
2000 WREG32(CB_PERF_CTR2_SEL_1, 0);
2001 WREG32(CB_PERF_CTR3_SEL_0, 0);
2002 WREG32(CB_PERF_CTR3_SEL_1, 0);
2003
2004 /* clear render buffer base addresses */
2005 WREG32(CB_COLOR0_BASE, 0);
2006 WREG32(CB_COLOR1_BASE, 0);
2007 WREG32(CB_COLOR2_BASE, 0);
2008 WREG32(CB_COLOR3_BASE, 0);
2009 WREG32(CB_COLOR4_BASE, 0);
2010 WREG32(CB_COLOR5_BASE, 0);
2011 WREG32(CB_COLOR6_BASE, 0);
2012 WREG32(CB_COLOR7_BASE, 0);
2013 WREG32(CB_COLOR8_BASE, 0);
2014 WREG32(CB_COLOR9_BASE, 0);
2015 WREG32(CB_COLOR10_BASE, 0);
2016 WREG32(CB_COLOR11_BASE, 0);
2017
2018 /* set the shader const cache sizes to 0 */
2019 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2020 WREG32(i, 0);
2021 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2022 WREG32(i, 0);
2023
2024 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2025 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2026
2027 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2028
2029 udelay(50);
2030
2031 }
2032
2033 int evergreen_mc_init(struct radeon_device *rdev)
2034 {
2035 u32 tmp;
2036 int chansize, numchan;
2037
2038 /* Get VRAM informations */
2039 rdev->mc.vram_is_ddr = true;
2040 tmp = RREG32(MC_ARB_RAMCFG);
2041 if (tmp & CHANSIZE_OVERRIDE) {
2042 chansize = 16;
2043 } else if (tmp & CHANSIZE_MASK) {
2044 chansize = 64;
2045 } else {
2046 chansize = 32;
2047 }
2048 tmp = RREG32(MC_SHARED_CHMAP);
2049 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2050 case 0:
2051 default:
2052 numchan = 1;
2053 break;
2054 case 1:
2055 numchan = 2;
2056 break;
2057 case 2:
2058 numchan = 4;
2059 break;
2060 case 3:
2061 numchan = 8;
2062 break;
2063 }
2064 rdev->mc.vram_width = numchan * chansize;
2065 /* Could aper size report 0 ? */
2066 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2067 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2068 /* Setup GPU memory space */
2069 if (rdev->flags & RADEON_IS_IGP) {
2070 /* size in bytes on fusion */
2071 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2072 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2073 } else {
2074 /* size in MB on evergreen */
2075 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2076 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2077 }
2078 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2079 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
2080 r700_vram_gtt_location(rdev, &rdev->mc);
2081 radeon_update_bandwidth_info(rdev);
2082
2083 return 0;
2084 }
2085
2086 bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
2087 {
2088 u32 srbm_status;
2089 u32 grbm_status;
2090 u32 grbm_status_se0, grbm_status_se1;
2091 struct r100_gpu_lockup *lockup = &rdev->config.evergreen.lockup;
2092 int r;
2093
2094 srbm_status = RREG32(SRBM_STATUS);
2095 grbm_status = RREG32(GRBM_STATUS);
2096 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2097 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2098 if (!(grbm_status & GUI_ACTIVE)) {
2099 r100_gpu_lockup_update(lockup, &rdev->cp);
2100 return false;
2101 }
2102 /* force CP activities */
2103 r = radeon_ring_lock(rdev, 2);
2104 if (!r) {
2105 /* PACKET2 NOP */
2106 radeon_ring_write(rdev, 0x80000000);
2107 radeon_ring_write(rdev, 0x80000000);
2108 radeon_ring_unlock_commit(rdev);
2109 }
2110 rdev->cp.rptr = RREG32(CP_RB_RPTR);
2111 return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
2112 }
2113
2114 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2115 {
2116 struct evergreen_mc_save save;
2117 u32 grbm_reset = 0;
2118
2119 dev_info(rdev->dev, "GPU softreset \n");
2120 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2121 RREG32(GRBM_STATUS));
2122 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2123 RREG32(GRBM_STATUS_SE0));
2124 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2125 RREG32(GRBM_STATUS_SE1));
2126 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2127 RREG32(SRBM_STATUS));
2128 evergreen_mc_stop(rdev, &save);
2129 if (evergreen_mc_wait_for_idle(rdev)) {
2130 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2131 }
2132 /* Disable CP parsing/prefetching */
2133 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2134
2135 /* reset all the gfx blocks */
2136 grbm_reset = (SOFT_RESET_CP |
2137 SOFT_RESET_CB |
2138 SOFT_RESET_DB |
2139 SOFT_RESET_PA |
2140 SOFT_RESET_SC |
2141 SOFT_RESET_SPI |
2142 SOFT_RESET_SH |
2143 SOFT_RESET_SX |
2144 SOFT_RESET_TC |
2145 SOFT_RESET_TA |
2146 SOFT_RESET_VC |
2147 SOFT_RESET_VGT);
2148
2149 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2150 WREG32(GRBM_SOFT_RESET, grbm_reset);
2151 (void)RREG32(GRBM_SOFT_RESET);
2152 udelay(50);
2153 WREG32(GRBM_SOFT_RESET, 0);
2154 (void)RREG32(GRBM_SOFT_RESET);
2155 /* Wait a little for things to settle down */
2156 udelay(50);
2157 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2158 RREG32(GRBM_STATUS));
2159 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2160 RREG32(GRBM_STATUS_SE0));
2161 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2162 RREG32(GRBM_STATUS_SE1));
2163 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2164 RREG32(SRBM_STATUS));
2165 evergreen_mc_resume(rdev, &save);
2166 return 0;
2167 }
2168
2169 int evergreen_asic_reset(struct radeon_device *rdev)
2170 {
2171 return evergreen_gpu_soft_reset(rdev);
2172 }
2173
2174 /* Interrupts */
2175
2176 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2177 {
2178 switch (crtc) {
2179 case 0:
2180 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2181 case 1:
2182 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2183 case 2:
2184 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2185 case 3:
2186 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2187 case 4:
2188 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2189 case 5:
2190 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2191 default:
2192 return 0;
2193 }
2194 }
2195
2196 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2197 {
2198 u32 tmp;
2199
2200 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2201 WREG32(GRBM_INT_CNTL, 0);
2202 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2203 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2204 if (!(rdev->flags & RADEON_IS_IGP)) {
2205 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2206 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2207 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2208 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2209 }
2210
2211 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2212 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2213 if (!(rdev->flags & RADEON_IS_IGP)) {
2214 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2215 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2216 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2217 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2218 }
2219
2220 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2221 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2222
2223 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2224 WREG32(DC_HPD1_INT_CONTROL, tmp);
2225 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2226 WREG32(DC_HPD2_INT_CONTROL, tmp);
2227 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2228 WREG32(DC_HPD3_INT_CONTROL, tmp);
2229 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2230 WREG32(DC_HPD4_INT_CONTROL, tmp);
2231 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2232 WREG32(DC_HPD5_INT_CONTROL, tmp);
2233 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2234 WREG32(DC_HPD6_INT_CONTROL, tmp);
2235
2236 }
2237
2238 int evergreen_irq_set(struct radeon_device *rdev)
2239 {
2240 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2241 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2242 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2243 u32 grbm_int_cntl = 0;
2244 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2245
2246 if (!rdev->irq.installed) {
2247 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2248 return -EINVAL;
2249 }
2250 /* don't enable anything if the ih is disabled */
2251 if (!rdev->ih.enabled) {
2252 r600_disable_interrupts(rdev);
2253 /* force the active interrupt state to all disabled */
2254 evergreen_disable_interrupt_state(rdev);
2255 return 0;
2256 }
2257
2258 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2259 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2260 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2261 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2262 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2263 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2264
2265 if (rdev->irq.sw_int) {
2266 DRM_DEBUG("evergreen_irq_set: sw int\n");
2267 cp_int_cntl |= RB_INT_ENABLE;
2268 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2269 }
2270 if (rdev->irq.crtc_vblank_int[0] ||
2271 rdev->irq.pflip[0]) {
2272 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2273 crtc1 |= VBLANK_INT_MASK;
2274 }
2275 if (rdev->irq.crtc_vblank_int[1] ||
2276 rdev->irq.pflip[1]) {
2277 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2278 crtc2 |= VBLANK_INT_MASK;
2279 }
2280 if (rdev->irq.crtc_vblank_int[2] ||
2281 rdev->irq.pflip[2]) {
2282 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2283 crtc3 |= VBLANK_INT_MASK;
2284 }
2285 if (rdev->irq.crtc_vblank_int[3] ||
2286 rdev->irq.pflip[3]) {
2287 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2288 crtc4 |= VBLANK_INT_MASK;
2289 }
2290 if (rdev->irq.crtc_vblank_int[4] ||
2291 rdev->irq.pflip[4]) {
2292 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2293 crtc5 |= VBLANK_INT_MASK;
2294 }
2295 if (rdev->irq.crtc_vblank_int[5] ||
2296 rdev->irq.pflip[5]) {
2297 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2298 crtc6 |= VBLANK_INT_MASK;
2299 }
2300 if (rdev->irq.hpd[0]) {
2301 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2302 hpd1 |= DC_HPDx_INT_EN;
2303 }
2304 if (rdev->irq.hpd[1]) {
2305 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2306 hpd2 |= DC_HPDx_INT_EN;
2307 }
2308 if (rdev->irq.hpd[2]) {
2309 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2310 hpd3 |= DC_HPDx_INT_EN;
2311 }
2312 if (rdev->irq.hpd[3]) {
2313 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2314 hpd4 |= DC_HPDx_INT_EN;
2315 }
2316 if (rdev->irq.hpd[4]) {
2317 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2318 hpd5 |= DC_HPDx_INT_EN;
2319 }
2320 if (rdev->irq.hpd[5]) {
2321 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2322 hpd6 |= DC_HPDx_INT_EN;
2323 }
2324 if (rdev->irq.gui_idle) {
2325 DRM_DEBUG("gui idle\n");
2326 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2327 }
2328
2329 WREG32(CP_INT_CNTL, cp_int_cntl);
2330 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2331
2332 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2333 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2334 if (!(rdev->flags & RADEON_IS_IGP)) {
2335 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2336 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2337 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2338 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2339 }
2340
2341 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2342 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2343 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2344 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2345 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2346 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2347
2348 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2349 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2350 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2351 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2352 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2353 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2354
2355 return 0;
2356 }
2357
2358 static inline void evergreen_irq_ack(struct radeon_device *rdev)
2359 {
2360 u32 tmp;
2361
2362 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2363 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2364 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2365 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2366 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2367 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2368 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2369 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2370 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2371 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2372 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2373 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2374
2375 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2376 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2377 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2378 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2379 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2380 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2381 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2382 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2383 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2384 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2385 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2386 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2387
2388 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2389 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2390 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2391 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2392
2393 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2394 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2395 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2396 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2397
2398 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2399 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2400 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2401 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2402
2403 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2404 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2405 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2406 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2407
2408 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2409 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2410 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2411 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2412
2413 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2414 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2415 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2416 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2417
2418 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2419 tmp = RREG32(DC_HPD1_INT_CONTROL);
2420 tmp |= DC_HPDx_INT_ACK;
2421 WREG32(DC_HPD1_INT_CONTROL, tmp);
2422 }
2423 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2424 tmp = RREG32(DC_HPD2_INT_CONTROL);
2425 tmp |= DC_HPDx_INT_ACK;
2426 WREG32(DC_HPD2_INT_CONTROL, tmp);
2427 }
2428 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2429 tmp = RREG32(DC_HPD3_INT_CONTROL);
2430 tmp |= DC_HPDx_INT_ACK;
2431 WREG32(DC_HPD3_INT_CONTROL, tmp);
2432 }
2433 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2434 tmp = RREG32(DC_HPD4_INT_CONTROL);
2435 tmp |= DC_HPDx_INT_ACK;
2436 WREG32(DC_HPD4_INT_CONTROL, tmp);
2437 }
2438 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2439 tmp = RREG32(DC_HPD5_INT_CONTROL);
2440 tmp |= DC_HPDx_INT_ACK;
2441 WREG32(DC_HPD5_INT_CONTROL, tmp);
2442 }
2443 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2444 tmp = RREG32(DC_HPD5_INT_CONTROL);
2445 tmp |= DC_HPDx_INT_ACK;
2446 WREG32(DC_HPD6_INT_CONTROL, tmp);
2447 }
2448 }
2449
2450 void evergreen_irq_disable(struct radeon_device *rdev)
2451 {
2452 r600_disable_interrupts(rdev);
2453 /* Wait and acknowledge irq */
2454 mdelay(1);
2455 evergreen_irq_ack(rdev);
2456 evergreen_disable_interrupt_state(rdev);
2457 }
2458
2459 static void evergreen_irq_suspend(struct radeon_device *rdev)
2460 {
2461 evergreen_irq_disable(rdev);
2462 r600_rlc_stop(rdev);
2463 }
2464
2465 static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2466 {
2467 u32 wptr, tmp;
2468
2469 if (rdev->wb.enabled)
2470 wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
2471 else
2472 wptr = RREG32(IH_RB_WPTR);
2473
2474 if (wptr & RB_OVERFLOW) {
2475 /* When a ring buffer overflow happen start parsing interrupt
2476 * from the last not overwritten vector (wptr + 16). Hopefully
2477 * this should allow us to catchup.
2478 */
2479 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2480 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2481 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2482 tmp = RREG32(IH_RB_CNTL);
2483 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2484 WREG32(IH_RB_CNTL, tmp);
2485 }
2486 return (wptr & rdev->ih.ptr_mask);
2487 }
2488
2489 int evergreen_irq_process(struct radeon_device *rdev)
2490 {
2491 u32 wptr = evergreen_get_ih_wptr(rdev);
2492 u32 rptr = rdev->ih.rptr;
2493 u32 src_id, src_data;
2494 u32 ring_index;
2495 unsigned long flags;
2496 bool queue_hotplug = false;
2497
2498 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2499 if (!rdev->ih.enabled)
2500 return IRQ_NONE;
2501
2502 spin_lock_irqsave(&rdev->ih.lock, flags);
2503
2504 if (rptr == wptr) {
2505 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2506 return IRQ_NONE;
2507 }
2508 if (rdev->shutdown) {
2509 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2510 return IRQ_NONE;
2511 }
2512
2513 restart_ih:
2514 /* display interrupts */
2515 evergreen_irq_ack(rdev);
2516
2517 rdev->ih.wptr = wptr;
2518 while (rptr != wptr) {
2519 /* wptr/rptr are in bytes! */
2520 ring_index = rptr / 4;
2521 src_id = rdev->ih.ring[ring_index] & 0xff;
2522 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2523
2524 switch (src_id) {
2525 case 1: /* D1 vblank/vline */
2526 switch (src_data) {
2527 case 0: /* D1 vblank */
2528 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2529 if (rdev->irq.crtc_vblank_int[0]) {
2530 drm_handle_vblank(rdev->ddev, 0);
2531 rdev->pm.vblank_sync = true;
2532 wake_up(&rdev->irq.vblank_queue);
2533 }
2534 if (rdev->irq.pflip[0])
2535 radeon_crtc_handle_flip(rdev, 0);
2536 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2537 DRM_DEBUG("IH: D1 vblank\n");
2538 }
2539 break;
2540 case 1: /* D1 vline */
2541 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2542 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2543 DRM_DEBUG("IH: D1 vline\n");
2544 }
2545 break;
2546 default:
2547 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2548 break;
2549 }
2550 break;
2551 case 2: /* D2 vblank/vline */
2552 switch (src_data) {
2553 case 0: /* D2 vblank */
2554 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2555 if (rdev->irq.crtc_vblank_int[1]) {
2556 drm_handle_vblank(rdev->ddev, 1);
2557 rdev->pm.vblank_sync = true;
2558 wake_up(&rdev->irq.vblank_queue);
2559 }
2560 if (rdev->irq.pflip[1])
2561 radeon_crtc_handle_flip(rdev, 1);
2562 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2563 DRM_DEBUG("IH: D2 vblank\n");
2564 }
2565 break;
2566 case 1: /* D2 vline */
2567 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2568 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2569 DRM_DEBUG("IH: D2 vline\n");
2570 }
2571 break;
2572 default:
2573 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2574 break;
2575 }
2576 break;
2577 case 3: /* D3 vblank/vline */
2578 switch (src_data) {
2579 case 0: /* D3 vblank */
2580 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2581 if (rdev->irq.crtc_vblank_int[2]) {
2582 drm_handle_vblank(rdev->ddev, 2);
2583 rdev->pm.vblank_sync = true;
2584 wake_up(&rdev->irq.vblank_queue);
2585 }
2586 if (rdev->irq.pflip[2])
2587 radeon_crtc_handle_flip(rdev, 2);
2588 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2589 DRM_DEBUG("IH: D3 vblank\n");
2590 }
2591 break;
2592 case 1: /* D3 vline */
2593 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2594 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2595 DRM_DEBUG("IH: D3 vline\n");
2596 }
2597 break;
2598 default:
2599 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2600 break;
2601 }
2602 break;
2603 case 4: /* D4 vblank/vline */
2604 switch (src_data) {
2605 case 0: /* D4 vblank */
2606 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2607 if (rdev->irq.crtc_vblank_int[3]) {
2608 drm_handle_vblank(rdev->ddev, 3);
2609 rdev->pm.vblank_sync = true;
2610 wake_up(&rdev->irq.vblank_queue);
2611 }
2612 if (rdev->irq.pflip[3])
2613 radeon_crtc_handle_flip(rdev, 3);
2614 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2615 DRM_DEBUG("IH: D4 vblank\n");
2616 }
2617 break;
2618 case 1: /* D4 vline */
2619 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2620 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2621 DRM_DEBUG("IH: D4 vline\n");
2622 }
2623 break;
2624 default:
2625 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2626 break;
2627 }
2628 break;
2629 case 5: /* D5 vblank/vline */
2630 switch (src_data) {
2631 case 0: /* D5 vblank */
2632 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2633 if (rdev->irq.crtc_vblank_int[4]) {
2634 drm_handle_vblank(rdev->ddev, 4);
2635 rdev->pm.vblank_sync = true;
2636 wake_up(&rdev->irq.vblank_queue);
2637 }
2638 if (rdev->irq.pflip[4])
2639 radeon_crtc_handle_flip(rdev, 4);
2640 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2641 DRM_DEBUG("IH: D5 vblank\n");
2642 }
2643 break;
2644 case 1: /* D5 vline */
2645 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2646 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2647 DRM_DEBUG("IH: D5 vline\n");
2648 }
2649 break;
2650 default:
2651 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2652 break;
2653 }
2654 break;
2655 case 6: /* D6 vblank/vline */
2656 switch (src_data) {
2657 case 0: /* D6 vblank */
2658 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2659 if (rdev->irq.crtc_vblank_int[5]) {
2660 drm_handle_vblank(rdev->ddev, 5);
2661 rdev->pm.vblank_sync = true;
2662 wake_up(&rdev->irq.vblank_queue);
2663 }
2664 if (rdev->irq.pflip[5])
2665 radeon_crtc_handle_flip(rdev, 5);
2666 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
2667 DRM_DEBUG("IH: D6 vblank\n");
2668 }
2669 break;
2670 case 1: /* D6 vline */
2671 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2672 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
2673 DRM_DEBUG("IH: D6 vline\n");
2674 }
2675 break;
2676 default:
2677 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2678 break;
2679 }
2680 break;
2681 case 42: /* HPD hotplug */
2682 switch (src_data) {
2683 case 0:
2684 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2685 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
2686 queue_hotplug = true;
2687 DRM_DEBUG("IH: HPD1\n");
2688 }
2689 break;
2690 case 1:
2691 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2692 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
2693 queue_hotplug = true;
2694 DRM_DEBUG("IH: HPD2\n");
2695 }
2696 break;
2697 case 2:
2698 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2699 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
2700 queue_hotplug = true;
2701 DRM_DEBUG("IH: HPD3\n");
2702 }
2703 break;
2704 case 3:
2705 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2706 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
2707 queue_hotplug = true;
2708 DRM_DEBUG("IH: HPD4\n");
2709 }
2710 break;
2711 case 4:
2712 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2713 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
2714 queue_hotplug = true;
2715 DRM_DEBUG("IH: HPD5\n");
2716 }
2717 break;
2718 case 5:
2719 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2720 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
2721 queue_hotplug = true;
2722 DRM_DEBUG("IH: HPD6\n");
2723 }
2724 break;
2725 default:
2726 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2727 break;
2728 }
2729 break;
2730 case 176: /* CP_INT in ring buffer */
2731 case 177: /* CP_INT in IB1 */
2732 case 178: /* CP_INT in IB2 */
2733 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2734 radeon_fence_process(rdev);
2735 break;
2736 case 181: /* CP EOP event */
2737 DRM_DEBUG("IH: CP EOP\n");
2738 radeon_fence_process(rdev);
2739 break;
2740 case 233: /* GUI IDLE */
2741 DRM_DEBUG("IH: CP EOP\n");
2742 rdev->pm.gui_idle = true;
2743 wake_up(&rdev->irq.idle_queue);
2744 break;
2745 default:
2746 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2747 break;
2748 }
2749
2750 /* wptr/rptr are in bytes! */
2751 rptr += 16;
2752 rptr &= rdev->ih.ptr_mask;
2753 }
2754 /* make sure wptr hasn't changed while processing */
2755 wptr = evergreen_get_ih_wptr(rdev);
2756 if (wptr != rdev->ih.wptr)
2757 goto restart_ih;
2758 if (queue_hotplug)
2759 queue_work(rdev->wq, &rdev->hotplug_work);
2760 rdev->ih.rptr = rptr;
2761 WREG32(IH_RB_RPTR, rdev->ih.rptr);
2762 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2763 return IRQ_HANDLED;
2764 }
2765
2766 static int evergreen_startup(struct radeon_device *rdev)
2767 {
2768 int r;
2769
2770 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2771 r = r600_init_microcode(rdev);
2772 if (r) {
2773 DRM_ERROR("Failed to load firmware!\n");
2774 return r;
2775 }
2776 }
2777
2778 evergreen_mc_program(rdev);
2779 if (rdev->flags & RADEON_IS_AGP) {
2780 evergreen_agp_enable(rdev);
2781 } else {
2782 r = evergreen_pcie_gart_enable(rdev);
2783 if (r)
2784 return r;
2785 }
2786 evergreen_gpu_init(rdev);
2787
2788 r = evergreen_blit_init(rdev);
2789 if (r) {
2790 evergreen_blit_fini(rdev);
2791 rdev->asic->copy = NULL;
2792 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2793 }
2794 /* XXX: ontario has problems blitting to gart at the moment */
2795 if (rdev->family == CHIP_PALM) {
2796 rdev->asic->copy = NULL;
2797 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
2798 }
2799
2800 /* allocate wb buffer */
2801 r = radeon_wb_init(rdev);
2802 if (r)
2803 return r;
2804
2805 /* Enable IRQ */
2806 r = r600_irq_init(rdev);
2807 if (r) {
2808 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2809 radeon_irq_kms_fini(rdev);
2810 return r;
2811 }
2812 evergreen_irq_set(rdev);
2813
2814 r = radeon_ring_init(rdev, rdev->cp.ring_size);
2815 if (r)
2816 return r;
2817 r = evergreen_cp_load_microcode(rdev);
2818 if (r)
2819 return r;
2820 r = evergreen_cp_resume(rdev);
2821 if (r)
2822 return r;
2823
2824 return 0;
2825 }
2826
2827 int evergreen_resume(struct radeon_device *rdev)
2828 {
2829 int r;
2830
2831 /* reset the asic, the gfx blocks are often in a bad state
2832 * after the driver is unloaded or after a resume
2833 */
2834 if (radeon_asic_reset(rdev))
2835 dev_warn(rdev->dev, "GPU reset failed !\n");
2836 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2837 * posting will perform necessary task to bring back GPU into good
2838 * shape.
2839 */
2840 /* post card */
2841 atom_asic_init(rdev->mode_info.atom_context);
2842
2843 r = evergreen_startup(rdev);
2844 if (r) {
2845 DRM_ERROR("r600 startup failed on resume\n");
2846 return r;
2847 }
2848
2849 r = r600_ib_test(rdev);
2850 if (r) {
2851 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2852 return r;
2853 }
2854
2855 return r;
2856
2857 }
2858
2859 int evergreen_suspend(struct radeon_device *rdev)
2860 {
2861 int r;
2862
2863 /* FIXME: we should wait for ring to be empty */
2864 r700_cp_stop(rdev);
2865 rdev->cp.ready = false;
2866 evergreen_irq_suspend(rdev);
2867 radeon_wb_disable(rdev);
2868 evergreen_pcie_gart_disable(rdev);
2869
2870 /* unpin shaders bo */
2871 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2872 if (likely(r == 0)) {
2873 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2874 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2875 }
2876
2877 return 0;
2878 }
2879
2880 int evergreen_copy_blit(struct radeon_device *rdev,
2881 uint64_t src_offset, uint64_t dst_offset,
2882 unsigned num_pages, struct radeon_fence *fence)
2883 {
2884 int r;
2885
2886 mutex_lock(&rdev->r600_blit.mutex);
2887 rdev->r600_blit.vb_ib = NULL;
2888 r = evergreen_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2889 if (r) {
2890 if (rdev->r600_blit.vb_ib)
2891 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2892 mutex_unlock(&rdev->r600_blit.mutex);
2893 return r;
2894 }
2895 evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2896 evergreen_blit_done_copy(rdev, fence);
2897 mutex_unlock(&rdev->r600_blit.mutex);
2898 return 0;
2899 }
2900
2901 static bool evergreen_card_posted(struct radeon_device *rdev)
2902 {
2903 u32 reg;
2904
2905 /* first check CRTCs */
2906 if (rdev->flags & RADEON_IS_IGP)
2907 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
2908 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
2909 else
2910 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
2911 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
2912 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
2913 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
2914 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
2915 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
2916 if (reg & EVERGREEN_CRTC_MASTER_EN)
2917 return true;
2918
2919 /* then check MEM_SIZE, in case the crtcs are off */
2920 if (RREG32(CONFIG_MEMSIZE))
2921 return true;
2922
2923 return false;
2924 }
2925
2926 /* Plan is to move initialization in that function and use
2927 * helper function so that radeon_device_init pretty much
2928 * do nothing more than calling asic specific function. This
2929 * should also allow to remove a bunch of callback function
2930 * like vram_info.
2931 */
2932 int evergreen_init(struct radeon_device *rdev)
2933 {
2934 int r;
2935
2936 r = radeon_dummy_page_init(rdev);
2937 if (r)
2938 return r;
2939 /* This don't do much */
2940 r = radeon_gem_init(rdev);
2941 if (r)
2942 return r;
2943 /* Read BIOS */
2944 if (!radeon_get_bios(rdev)) {
2945 if (ASIC_IS_AVIVO(rdev))
2946 return -EINVAL;
2947 }
2948 /* Must be an ATOMBIOS */
2949 if (!rdev->is_atom_bios) {
2950 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2951 return -EINVAL;
2952 }
2953 r = radeon_atombios_init(rdev);
2954 if (r)
2955 return r;
2956 /* reset the asic, the gfx blocks are often in a bad state
2957 * after the driver is unloaded or after a resume
2958 */
2959 if (radeon_asic_reset(rdev))
2960 dev_warn(rdev->dev, "GPU reset failed !\n");
2961 /* Post card if necessary */
2962 if (!evergreen_card_posted(rdev)) {
2963 if (!rdev->bios) {
2964 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2965 return -EINVAL;
2966 }
2967 DRM_INFO("GPU not posted. posting now...\n");
2968 atom_asic_init(rdev->mode_info.atom_context);
2969 }
2970 /* Initialize scratch registers */
2971 r600_scratch_init(rdev);
2972 /* Initialize surface registers */
2973 radeon_surface_init(rdev);
2974 /* Initialize clocks */
2975 radeon_get_clock_info(rdev->ddev);
2976 /* Fence driver */
2977 r = radeon_fence_driver_init(rdev);
2978 if (r)
2979 return r;
2980 /* initialize AGP */
2981 if (rdev->flags & RADEON_IS_AGP) {
2982 r = radeon_agp_init(rdev);
2983 if (r)
2984 radeon_agp_disable(rdev);
2985 }
2986 /* initialize memory controller */
2987 r = evergreen_mc_init(rdev);
2988 if (r)
2989 return r;
2990 /* Memory manager */
2991 r = radeon_bo_init(rdev);
2992 if (r)
2993 return r;
2994
2995 r = radeon_irq_kms_init(rdev);
2996 if (r)
2997 return r;
2998
2999 rdev->cp.ring_obj = NULL;
3000 r600_ring_init(rdev, 1024 * 1024);
3001
3002 rdev->ih.ring_obj = NULL;
3003 r600_ih_ring_init(rdev, 64 * 1024);
3004
3005 r = r600_pcie_gart_init(rdev);
3006 if (r)
3007 return r;
3008
3009 rdev->accel_working = true;
3010 r = evergreen_startup(rdev);
3011 if (r) {
3012 dev_err(rdev->dev, "disabling GPU acceleration\n");
3013 r700_cp_fini(rdev);
3014 r600_irq_fini(rdev);
3015 radeon_wb_fini(rdev);
3016 radeon_irq_kms_fini(rdev);
3017 evergreen_pcie_gart_fini(rdev);
3018 rdev->accel_working = false;
3019 }
3020 if (rdev->accel_working) {
3021 r = radeon_ib_pool_init(rdev);
3022 if (r) {
3023 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
3024 rdev->accel_working = false;
3025 }
3026 r = r600_ib_test(rdev);
3027 if (r) {
3028 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3029 rdev->accel_working = false;
3030 }
3031 }
3032 return 0;
3033 }
3034
3035 void evergreen_fini(struct radeon_device *rdev)
3036 {
3037 evergreen_blit_fini(rdev);
3038 r700_cp_fini(rdev);
3039 r600_irq_fini(rdev);
3040 radeon_wb_fini(rdev);
3041 radeon_irq_kms_fini(rdev);
3042 evergreen_pcie_gart_fini(rdev);
3043 radeon_gem_fini(rdev);
3044 radeon_fence_driver_fini(rdev);
3045 radeon_agp_fini(rdev);
3046 radeon_bo_fini(rdev);
3047 radeon_atombios_fini(rdev);
3048 kfree(rdev->bios);
3049 rdev->bios = NULL;
3050 radeon_dummy_page_fini(rdev);
3051 }
Linux kernel - Deliverables
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