2 * Copyright 2010 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
29 #include "radeon_asic.h"
30 #include "radeon_drm.h"
31 #include "evergreend.h"
34 #include "evergreen_reg.h"
35 #include "evergreen_blit_shaders.h"
37 #define EVERGREEN_PFP_UCODE_SIZE 1120
38 #define EVERGREEN_PM4_UCODE_SIZE 1376
40 static void evergreen_gpu_init(struct radeon_device
*rdev
);
41 void evergreen_fini(struct radeon_device
*rdev
);
42 void evergreen_pcie_gen2_enable(struct radeon_device
*rdev
);
43 extern void cayman_cp_int_cntl_setup(struct radeon_device
*rdev
,
44 int ring
, u32 cp_int_cntl
);
46 void evergreen_tiling_fields(unsigned tiling_flags
, unsigned *bankw
,
47 unsigned *bankh
, unsigned *mtaspect
,
50 *bankw
= (tiling_flags
>> RADEON_TILING_EG_BANKW_SHIFT
) & RADEON_TILING_EG_BANKW_MASK
;
51 *bankh
= (tiling_flags
>> RADEON_TILING_EG_BANKH_SHIFT
) & RADEON_TILING_EG_BANKH_MASK
;
52 *mtaspect
= (tiling_flags
>> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT
) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK
;
53 *tile_split
= (tiling_flags
>> RADEON_TILING_EG_TILE_SPLIT_SHIFT
) & RADEON_TILING_EG_TILE_SPLIT_MASK
;
56 case 1: *bankw
= EVERGREEN_ADDR_SURF_BANK_WIDTH_1
; break;
57 case 2: *bankw
= EVERGREEN_ADDR_SURF_BANK_WIDTH_2
; break;
58 case 4: *bankw
= EVERGREEN_ADDR_SURF_BANK_WIDTH_4
; break;
59 case 8: *bankw
= EVERGREEN_ADDR_SURF_BANK_WIDTH_8
; break;
63 case 1: *bankh
= EVERGREEN_ADDR_SURF_BANK_HEIGHT_1
; break;
64 case 2: *bankh
= EVERGREEN_ADDR_SURF_BANK_HEIGHT_2
; break;
65 case 4: *bankh
= EVERGREEN_ADDR_SURF_BANK_HEIGHT_4
; break;
66 case 8: *bankh
= EVERGREEN_ADDR_SURF_BANK_HEIGHT_8
; break;
70 case 1: *mtaspect
= EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1
; break;
71 case 2: *mtaspect
= EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2
; break;
72 case 4: *mtaspect
= EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4
; break;
73 case 8: *mtaspect
= EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8
; break;
77 void evergreen_fix_pci_max_read_req_size(struct radeon_device
*rdev
)
82 cap
= pci_pcie_cap(rdev
->pdev
);
86 err
= pci_read_config_word(rdev
->pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
90 v
= (ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12;
92 /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
93 * to avoid hangs or perfomance issues
95 if ((v
== 0) || (v
== 6) || (v
== 7)) {
96 ctl
&= ~PCI_EXP_DEVCTL_READRQ
;
98 pci_write_config_word(rdev
->pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
102 void dce4_wait_for_vblank(struct radeon_device
*rdev
, int crtc
)
104 struct radeon_crtc
*radeon_crtc
= rdev
->mode_info
.crtcs
[crtc
];
107 if (RREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
) & EVERGREEN_CRTC_MASTER_EN
) {
108 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
109 if (!(RREG32(EVERGREEN_CRTC_STATUS
+ radeon_crtc
->crtc_offset
) & EVERGREEN_CRTC_V_BLANK
))
113 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
114 if (RREG32(EVERGREEN_CRTC_STATUS
+ radeon_crtc
->crtc_offset
) & EVERGREEN_CRTC_V_BLANK
)
121 void evergreen_pre_page_flip(struct radeon_device
*rdev
, int crtc
)
123 /* enable the pflip int */
124 radeon_irq_kms_pflip_irq_get(rdev
, crtc
);
127 void evergreen_post_page_flip(struct radeon_device
*rdev
, int crtc
)
129 /* disable the pflip int */
130 radeon_irq_kms_pflip_irq_put(rdev
, crtc
);
133 u32
evergreen_page_flip(struct radeon_device
*rdev
, int crtc_id
, u64 crtc_base
)
135 struct radeon_crtc
*radeon_crtc
= rdev
->mode_info
.crtcs
[crtc_id
];
136 u32 tmp
= RREG32(EVERGREEN_GRPH_UPDATE
+ radeon_crtc
->crtc_offset
);
139 /* Lock the graphics update lock */
140 tmp
|= EVERGREEN_GRPH_UPDATE_LOCK
;
141 WREG32(EVERGREEN_GRPH_UPDATE
+ radeon_crtc
->crtc_offset
, tmp
);
143 /* update the scanout addresses */
144 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ radeon_crtc
->crtc_offset
,
145 upper_32_bits(crtc_base
));
146 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ radeon_crtc
->crtc_offset
,
149 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ radeon_crtc
->crtc_offset
,
150 upper_32_bits(crtc_base
));
151 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ radeon_crtc
->crtc_offset
,
154 /* Wait for update_pending to go high. */
155 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
156 if (RREG32(EVERGREEN_GRPH_UPDATE
+ radeon_crtc
->crtc_offset
) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING
)
160 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
162 /* Unlock the lock, so double-buffering can take place inside vblank */
163 tmp
&= ~EVERGREEN_GRPH_UPDATE_LOCK
;
164 WREG32(EVERGREEN_GRPH_UPDATE
+ radeon_crtc
->crtc_offset
, tmp
);
166 /* Return current update_pending status: */
167 return RREG32(EVERGREEN_GRPH_UPDATE
+ radeon_crtc
->crtc_offset
) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING
;
170 /* get temperature in millidegrees */
171 int evergreen_get_temp(struct radeon_device
*rdev
)
176 if (rdev
->family
== CHIP_JUNIPER
) {
177 toffset
= (RREG32(CG_THERMAL_CTRL
) & TOFFSET_MASK
) >>
179 temp
= (RREG32(CG_TS0_STATUS
) & TS0_ADC_DOUT_MASK
) >>
183 actual_temp
= temp
/ 2 - (0x200 - toffset
);
185 actual_temp
= temp
/ 2 + toffset
;
187 actual_temp
= actual_temp
* 1000;
190 temp
= (RREG32(CG_MULT_THERMAL_STATUS
) & ASIC_T_MASK
) >>
195 else if (temp
& 0x200)
197 else if (temp
& 0x100) {
198 actual_temp
= temp
& 0x1ff;
199 actual_temp
|= ~0x1ff;
201 actual_temp
= temp
& 0xff;
203 actual_temp
= (actual_temp
* 1000) / 2;
209 int sumo_get_temp(struct radeon_device
*rdev
)
211 u32 temp
= RREG32(CG_THERMAL_STATUS
) & 0xff;
212 int actual_temp
= temp
- 49;
214 return actual_temp
* 1000;
217 void sumo_pm_init_profile(struct radeon_device
*rdev
)
222 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
223 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
224 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
225 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 0;
228 if (rdev
->flags
& RADEON_IS_MOBILITY
)
229 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_BATTERY
, 0);
231 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 0);
233 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= idx
;
234 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= idx
;
235 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
236 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
238 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= idx
;
239 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= idx
;
240 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
241 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
243 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= idx
;
244 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= idx
;
245 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
246 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 0;
248 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= idx
;
249 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= idx
;
250 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
251 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 0;
254 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 0);
255 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= idx
;
256 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= idx
;
257 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
258 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
=
259 rdev
->pm
.power_state
[idx
].num_clock_modes
- 1;
261 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= idx
;
262 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= idx
;
263 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
264 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
=
265 rdev
->pm
.power_state
[idx
].num_clock_modes
- 1;
268 void evergreen_pm_misc(struct radeon_device
*rdev
)
270 int req_ps_idx
= rdev
->pm
.requested_power_state_index
;
271 int req_cm_idx
= rdev
->pm
.requested_clock_mode_index
;
272 struct radeon_power_state
*ps
= &rdev
->pm
.power_state
[req_ps_idx
];
273 struct radeon_voltage
*voltage
= &ps
->clock_info
[req_cm_idx
].voltage
;
275 if (voltage
->type
== VOLTAGE_SW
) {
276 /* 0xff01 is a flag rather then an actual voltage */
277 if (voltage
->voltage
== 0xff01)
279 if (voltage
->voltage
&& (voltage
->voltage
!= rdev
->pm
.current_vddc
)) {
280 radeon_atom_set_voltage(rdev
, voltage
->voltage
, SET_VOLTAGE_TYPE_ASIC_VDDC
);
281 rdev
->pm
.current_vddc
= voltage
->voltage
;
282 DRM_DEBUG("Setting: vddc: %d\n", voltage
->voltage
);
284 /* 0xff01 is a flag rather then an actual voltage */
285 if (voltage
->vddci
== 0xff01)
287 if (voltage
->vddci
&& (voltage
->vddci
!= rdev
->pm
.current_vddci
)) {
288 radeon_atom_set_voltage(rdev
, voltage
->vddci
, SET_VOLTAGE_TYPE_ASIC_VDDCI
);
289 rdev
->pm
.current_vddci
= voltage
->vddci
;
290 DRM_DEBUG("Setting: vddci: %d\n", voltage
->vddci
);
295 void evergreen_pm_prepare(struct radeon_device
*rdev
)
297 struct drm_device
*ddev
= rdev
->ddev
;
298 struct drm_crtc
*crtc
;
299 struct radeon_crtc
*radeon_crtc
;
302 /* disable any active CRTCs */
303 list_for_each_entry(crtc
, &ddev
->mode_config
.crtc_list
, head
) {
304 radeon_crtc
= to_radeon_crtc(crtc
);
305 if (radeon_crtc
->enabled
) {
306 tmp
= RREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
);
307 tmp
|= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE
;
308 WREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
, tmp
);
313 void evergreen_pm_finish(struct radeon_device
*rdev
)
315 struct drm_device
*ddev
= rdev
->ddev
;
316 struct drm_crtc
*crtc
;
317 struct radeon_crtc
*radeon_crtc
;
320 /* enable any active CRTCs */
321 list_for_each_entry(crtc
, &ddev
->mode_config
.crtc_list
, head
) {
322 radeon_crtc
= to_radeon_crtc(crtc
);
323 if (radeon_crtc
->enabled
) {
324 tmp
= RREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
);
325 tmp
&= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE
;
326 WREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
, tmp
);
331 bool evergreen_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
)
333 bool connected
= false;
337 if (RREG32(DC_HPD1_INT_STATUS
) & DC_HPDx_SENSE
)
341 if (RREG32(DC_HPD2_INT_STATUS
) & DC_HPDx_SENSE
)
345 if (RREG32(DC_HPD3_INT_STATUS
) & DC_HPDx_SENSE
)
349 if (RREG32(DC_HPD4_INT_STATUS
) & DC_HPDx_SENSE
)
353 if (RREG32(DC_HPD5_INT_STATUS
) & DC_HPDx_SENSE
)
357 if (RREG32(DC_HPD6_INT_STATUS
) & DC_HPDx_SENSE
)
367 void evergreen_hpd_set_polarity(struct radeon_device
*rdev
,
368 enum radeon_hpd_id hpd
)
371 bool connected
= evergreen_hpd_sense(rdev
, hpd
);
375 tmp
= RREG32(DC_HPD1_INT_CONTROL
);
377 tmp
&= ~DC_HPDx_INT_POLARITY
;
379 tmp
|= DC_HPDx_INT_POLARITY
;
380 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
383 tmp
= RREG32(DC_HPD2_INT_CONTROL
);
385 tmp
&= ~DC_HPDx_INT_POLARITY
;
387 tmp
|= DC_HPDx_INT_POLARITY
;
388 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
391 tmp
= RREG32(DC_HPD3_INT_CONTROL
);
393 tmp
&= ~DC_HPDx_INT_POLARITY
;
395 tmp
|= DC_HPDx_INT_POLARITY
;
396 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
399 tmp
= RREG32(DC_HPD4_INT_CONTROL
);
401 tmp
&= ~DC_HPDx_INT_POLARITY
;
403 tmp
|= DC_HPDx_INT_POLARITY
;
404 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
407 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
409 tmp
&= ~DC_HPDx_INT_POLARITY
;
411 tmp
|= DC_HPDx_INT_POLARITY
;
412 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
415 tmp
= RREG32(DC_HPD6_INT_CONTROL
);
417 tmp
&= ~DC_HPDx_INT_POLARITY
;
419 tmp
|= DC_HPDx_INT_POLARITY
;
420 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
427 void evergreen_hpd_init(struct radeon_device
*rdev
)
429 struct drm_device
*dev
= rdev
->ddev
;
430 struct drm_connector
*connector
;
431 u32 tmp
= DC_HPDx_CONNECTION_TIMER(0x9c4) |
432 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN
;
434 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
435 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
436 switch (radeon_connector
->hpd
.hpd
) {
438 WREG32(DC_HPD1_CONTROL
, tmp
);
439 rdev
->irq
.hpd
[0] = true;
442 WREG32(DC_HPD2_CONTROL
, tmp
);
443 rdev
->irq
.hpd
[1] = true;
446 WREG32(DC_HPD3_CONTROL
, tmp
);
447 rdev
->irq
.hpd
[2] = true;
450 WREG32(DC_HPD4_CONTROL
, tmp
);
451 rdev
->irq
.hpd
[3] = true;
454 WREG32(DC_HPD5_CONTROL
, tmp
);
455 rdev
->irq
.hpd
[4] = true;
458 WREG32(DC_HPD6_CONTROL
, tmp
);
459 rdev
->irq
.hpd
[5] = true;
464 radeon_hpd_set_polarity(rdev
, radeon_connector
->hpd
.hpd
);
466 if (rdev
->irq
.installed
)
467 evergreen_irq_set(rdev
);
470 void evergreen_hpd_fini(struct radeon_device
*rdev
)
472 struct drm_device
*dev
= rdev
->ddev
;
473 struct drm_connector
*connector
;
475 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
476 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
477 switch (radeon_connector
->hpd
.hpd
) {
479 WREG32(DC_HPD1_CONTROL
, 0);
480 rdev
->irq
.hpd
[0] = false;
483 WREG32(DC_HPD2_CONTROL
, 0);
484 rdev
->irq
.hpd
[1] = false;
487 WREG32(DC_HPD3_CONTROL
, 0);
488 rdev
->irq
.hpd
[2] = false;
491 WREG32(DC_HPD4_CONTROL
, 0);
492 rdev
->irq
.hpd
[3] = false;
495 WREG32(DC_HPD5_CONTROL
, 0);
496 rdev
->irq
.hpd
[4] = false;
499 WREG32(DC_HPD6_CONTROL
, 0);
500 rdev
->irq
.hpd
[5] = false;
508 /* watermark setup */
510 static u32
evergreen_line_buffer_adjust(struct radeon_device
*rdev
,
511 struct radeon_crtc
*radeon_crtc
,
512 struct drm_display_mode
*mode
,
513 struct drm_display_mode
*other_mode
)
518 * There are 3 line buffers, each one shared by 2 display controllers.
519 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
520 * the display controllers. The paritioning is done via one of four
521 * preset allocations specified in bits 2:0:
522 * first display controller
523 * 0 - first half of lb (3840 * 2)
524 * 1 - first 3/4 of lb (5760 * 2)
525 * 2 - whole lb (7680 * 2), other crtc must be disabled
526 * 3 - first 1/4 of lb (1920 * 2)
527 * second display controller
528 * 4 - second half of lb (3840 * 2)
529 * 5 - second 3/4 of lb (5760 * 2)
530 * 6 - whole lb (7680 * 2), other crtc must be disabled
531 * 7 - last 1/4 of lb (1920 * 2)
533 /* this can get tricky if we have two large displays on a paired group
534 * of crtcs. Ideally for multiple large displays we'd assign them to
535 * non-linked crtcs for maximum line buffer allocation.
537 if (radeon_crtc
->base
.enabled
&& mode
) {
545 /* second controller of the pair uses second half of the lb */
546 if (radeon_crtc
->crtc_id
% 2)
548 WREG32(DC_LB_MEMORY_SPLIT
+ radeon_crtc
->crtc_offset
, tmp
);
550 if (radeon_crtc
->base
.enabled
&& mode
) {
555 if (ASIC_IS_DCE5(rdev
))
561 if (ASIC_IS_DCE5(rdev
))
567 if (ASIC_IS_DCE5(rdev
))
573 if (ASIC_IS_DCE5(rdev
))
580 /* controller not enabled, so no lb used */
584 u32
evergreen_get_number_of_dram_channels(struct radeon_device
*rdev
)
586 u32 tmp
= RREG32(MC_SHARED_CHMAP
);
588 switch ((tmp
& NOOFCHAN_MASK
) >> NOOFCHAN_SHIFT
) {
601 struct evergreen_wm_params
{
602 u32 dram_channels
; /* number of dram channels */
603 u32 yclk
; /* bandwidth per dram data pin in kHz */
604 u32 sclk
; /* engine clock in kHz */
605 u32 disp_clk
; /* display clock in kHz */
606 u32 src_width
; /* viewport width */
607 u32 active_time
; /* active display time in ns */
608 u32 blank_time
; /* blank time in ns */
609 bool interlaced
; /* mode is interlaced */
610 fixed20_12 vsc
; /* vertical scale ratio */
611 u32 num_heads
; /* number of active crtcs */
612 u32 bytes_per_pixel
; /* bytes per pixel display + overlay */
613 u32 lb_size
; /* line buffer allocated to pipe */
614 u32 vtaps
; /* vertical scaler taps */
617 static u32
evergreen_dram_bandwidth(struct evergreen_wm_params
*wm
)
619 /* Calculate DRAM Bandwidth and the part allocated to display. */
620 fixed20_12 dram_efficiency
; /* 0.7 */
621 fixed20_12 yclk
, dram_channels
, bandwidth
;
624 a
.full
= dfixed_const(1000);
625 yclk
.full
= dfixed_const(wm
->yclk
);
626 yclk
.full
= dfixed_div(yclk
, a
);
627 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
628 a
.full
= dfixed_const(10);
629 dram_efficiency
.full
= dfixed_const(7);
630 dram_efficiency
.full
= dfixed_div(dram_efficiency
, a
);
631 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
632 bandwidth
.full
= dfixed_mul(bandwidth
, dram_efficiency
);
634 return dfixed_trunc(bandwidth
);
637 static u32
evergreen_dram_bandwidth_for_display(struct evergreen_wm_params
*wm
)
639 /* Calculate DRAM Bandwidth and the part allocated to display. */
640 fixed20_12 disp_dram_allocation
; /* 0.3 to 0.7 */
641 fixed20_12 yclk
, dram_channels
, bandwidth
;
644 a
.full
= dfixed_const(1000);
645 yclk
.full
= dfixed_const(wm
->yclk
);
646 yclk
.full
= dfixed_div(yclk
, a
);
647 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
648 a
.full
= dfixed_const(10);
649 disp_dram_allocation
.full
= dfixed_const(3); /* XXX worse case value 0.3 */
650 disp_dram_allocation
.full
= dfixed_div(disp_dram_allocation
, a
);
651 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
652 bandwidth
.full
= dfixed_mul(bandwidth
, disp_dram_allocation
);
654 return dfixed_trunc(bandwidth
);
657 static u32
evergreen_data_return_bandwidth(struct evergreen_wm_params
*wm
)
659 /* Calculate the display Data return Bandwidth */
660 fixed20_12 return_efficiency
; /* 0.8 */
661 fixed20_12 sclk
, bandwidth
;
664 a
.full
= dfixed_const(1000);
665 sclk
.full
= dfixed_const(wm
->sclk
);
666 sclk
.full
= dfixed_div(sclk
, a
);
667 a
.full
= dfixed_const(10);
668 return_efficiency
.full
= dfixed_const(8);
669 return_efficiency
.full
= dfixed_div(return_efficiency
, a
);
670 a
.full
= dfixed_const(32);
671 bandwidth
.full
= dfixed_mul(a
, sclk
);
672 bandwidth
.full
= dfixed_mul(bandwidth
, return_efficiency
);
674 return dfixed_trunc(bandwidth
);
677 static u32
evergreen_dmif_request_bandwidth(struct evergreen_wm_params
*wm
)
679 /* Calculate the DMIF Request Bandwidth */
680 fixed20_12 disp_clk_request_efficiency
; /* 0.8 */
681 fixed20_12 disp_clk
, bandwidth
;
684 a
.full
= dfixed_const(1000);
685 disp_clk
.full
= dfixed_const(wm
->disp_clk
);
686 disp_clk
.full
= dfixed_div(disp_clk
, a
);
687 a
.full
= dfixed_const(10);
688 disp_clk_request_efficiency
.full
= dfixed_const(8);
689 disp_clk_request_efficiency
.full
= dfixed_div(disp_clk_request_efficiency
, a
);
690 a
.full
= dfixed_const(32);
691 bandwidth
.full
= dfixed_mul(a
, disp_clk
);
692 bandwidth
.full
= dfixed_mul(bandwidth
, disp_clk_request_efficiency
);
694 return dfixed_trunc(bandwidth
);
697 static u32
evergreen_available_bandwidth(struct evergreen_wm_params
*wm
)
699 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
700 u32 dram_bandwidth
= evergreen_dram_bandwidth(wm
);
701 u32 data_return_bandwidth
= evergreen_data_return_bandwidth(wm
);
702 u32 dmif_req_bandwidth
= evergreen_dmif_request_bandwidth(wm
);
704 return min(dram_bandwidth
, min(data_return_bandwidth
, dmif_req_bandwidth
));
707 static u32
evergreen_average_bandwidth(struct evergreen_wm_params
*wm
)
709 /* Calculate the display mode Average Bandwidth
710 * DisplayMode should contain the source and destination dimensions,
714 fixed20_12 line_time
;
715 fixed20_12 src_width
;
716 fixed20_12 bandwidth
;
719 a
.full
= dfixed_const(1000);
720 line_time
.full
= dfixed_const(wm
->active_time
+ wm
->blank_time
);
721 line_time
.full
= dfixed_div(line_time
, a
);
722 bpp
.full
= dfixed_const(wm
->bytes_per_pixel
);
723 src_width
.full
= dfixed_const(wm
->src_width
);
724 bandwidth
.full
= dfixed_mul(src_width
, bpp
);
725 bandwidth
.full
= dfixed_mul(bandwidth
, wm
->vsc
);
726 bandwidth
.full
= dfixed_div(bandwidth
, line_time
);
728 return dfixed_trunc(bandwidth
);
731 static u32
evergreen_latency_watermark(struct evergreen_wm_params
*wm
)
733 /* First calcualte the latency in ns */
734 u32 mc_latency
= 2000; /* 2000 ns. */
735 u32 available_bandwidth
= evergreen_available_bandwidth(wm
);
736 u32 worst_chunk_return_time
= (512 * 8 * 1000) / available_bandwidth
;
737 u32 cursor_line_pair_return_time
= (128 * 4 * 1000) / available_bandwidth
;
738 u32 dc_latency
= 40000000 / wm
->disp_clk
; /* dc pipe latency */
739 u32 other_heads_data_return_time
= ((wm
->num_heads
+ 1) * worst_chunk_return_time
) +
740 (wm
->num_heads
* cursor_line_pair_return_time
);
741 u32 latency
= mc_latency
+ other_heads_data_return_time
+ dc_latency
;
742 u32 max_src_lines_per_dst_line
, lb_fill_bw
, line_fill_time
;
745 if (wm
->num_heads
== 0)
748 a
.full
= dfixed_const(2);
749 b
.full
= dfixed_const(1);
750 if ((wm
->vsc
.full
> a
.full
) ||
751 ((wm
->vsc
.full
> b
.full
) && (wm
->vtaps
>= 3)) ||
753 ((wm
->vsc
.full
>= a
.full
) && wm
->interlaced
))
754 max_src_lines_per_dst_line
= 4;
756 max_src_lines_per_dst_line
= 2;
758 a
.full
= dfixed_const(available_bandwidth
);
759 b
.full
= dfixed_const(wm
->num_heads
);
760 a
.full
= dfixed_div(a
, b
);
762 b
.full
= dfixed_const(1000);
763 c
.full
= dfixed_const(wm
->disp_clk
);
764 b
.full
= dfixed_div(c
, b
);
765 c
.full
= dfixed_const(wm
->bytes_per_pixel
);
766 b
.full
= dfixed_mul(b
, c
);
768 lb_fill_bw
= min(dfixed_trunc(a
), dfixed_trunc(b
));
770 a
.full
= dfixed_const(max_src_lines_per_dst_line
* wm
->src_width
* wm
->bytes_per_pixel
);
771 b
.full
= dfixed_const(1000);
772 c
.full
= dfixed_const(lb_fill_bw
);
773 b
.full
= dfixed_div(c
, b
);
774 a
.full
= dfixed_div(a
, b
);
775 line_fill_time
= dfixed_trunc(a
);
777 if (line_fill_time
< wm
->active_time
)
780 return latency
+ (line_fill_time
- wm
->active_time
);
784 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params
*wm
)
786 if (evergreen_average_bandwidth(wm
) <=
787 (evergreen_dram_bandwidth_for_display(wm
) / wm
->num_heads
))
793 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params
*wm
)
795 if (evergreen_average_bandwidth(wm
) <=
796 (evergreen_available_bandwidth(wm
) / wm
->num_heads
))
802 static bool evergreen_check_latency_hiding(struct evergreen_wm_params
*wm
)
804 u32 lb_partitions
= wm
->lb_size
/ wm
->src_width
;
805 u32 line_time
= wm
->active_time
+ wm
->blank_time
;
806 u32 latency_tolerant_lines
;
810 a
.full
= dfixed_const(1);
811 if (wm
->vsc
.full
> a
.full
)
812 latency_tolerant_lines
= 1;
814 if (lb_partitions
<= (wm
->vtaps
+ 1))
815 latency_tolerant_lines
= 1;
817 latency_tolerant_lines
= 2;
820 latency_hiding
= (latency_tolerant_lines
* line_time
+ wm
->blank_time
);
822 if (evergreen_latency_watermark(wm
) <= latency_hiding
)
828 static void evergreen_program_watermarks(struct radeon_device
*rdev
,
829 struct radeon_crtc
*radeon_crtc
,
830 u32 lb_size
, u32 num_heads
)
832 struct drm_display_mode
*mode
= &radeon_crtc
->base
.mode
;
833 struct evergreen_wm_params wm
;
836 u32 latency_watermark_a
= 0, latency_watermark_b
= 0;
837 u32 priority_a_mark
= 0, priority_b_mark
= 0;
838 u32 priority_a_cnt
= PRIORITY_OFF
;
839 u32 priority_b_cnt
= PRIORITY_OFF
;
840 u32 pipe_offset
= radeon_crtc
->crtc_id
* 16;
841 u32 tmp
, arb_control3
;
844 if (radeon_crtc
->base
.enabled
&& num_heads
&& mode
) {
845 pixel_period
= 1000000 / (u32
)mode
->clock
;
846 line_time
= min((u32
)mode
->crtc_htotal
* pixel_period
, (u32
)65535);
850 wm
.yclk
= rdev
->pm
.current_mclk
* 10;
851 wm
.sclk
= rdev
->pm
.current_sclk
* 10;
852 wm
.disp_clk
= mode
->clock
;
853 wm
.src_width
= mode
->crtc_hdisplay
;
854 wm
.active_time
= mode
->crtc_hdisplay
* pixel_period
;
855 wm
.blank_time
= line_time
- wm
.active_time
;
856 wm
.interlaced
= false;
857 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
858 wm
.interlaced
= true;
859 wm
.vsc
= radeon_crtc
->vsc
;
861 if (radeon_crtc
->rmx_type
!= RMX_OFF
)
863 wm
.bytes_per_pixel
= 4; /* XXX: get this from fb config */
864 wm
.lb_size
= lb_size
;
865 wm
.dram_channels
= evergreen_get_number_of_dram_channels(rdev
);
866 wm
.num_heads
= num_heads
;
868 /* set for high clocks */
869 latency_watermark_a
= min(evergreen_latency_watermark(&wm
), (u32
)65535);
870 /* set for low clocks */
871 /* wm.yclk = low clk; wm.sclk = low clk */
872 latency_watermark_b
= min(evergreen_latency_watermark(&wm
), (u32
)65535);
874 /* possibly force display priority to high */
875 /* should really do this at mode validation time... */
876 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm
) ||
877 !evergreen_average_bandwidth_vs_available_bandwidth(&wm
) ||
878 !evergreen_check_latency_hiding(&wm
) ||
879 (rdev
->disp_priority
== 2)) {
880 DRM_DEBUG_KMS("force priority to high\n");
881 priority_a_cnt
|= PRIORITY_ALWAYS_ON
;
882 priority_b_cnt
|= PRIORITY_ALWAYS_ON
;
885 a
.full
= dfixed_const(1000);
886 b
.full
= dfixed_const(mode
->clock
);
887 b
.full
= dfixed_div(b
, a
);
888 c
.full
= dfixed_const(latency_watermark_a
);
889 c
.full
= dfixed_mul(c
, b
);
890 c
.full
= dfixed_mul(c
, radeon_crtc
->hsc
);
891 c
.full
= dfixed_div(c
, a
);
892 a
.full
= dfixed_const(16);
893 c
.full
= dfixed_div(c
, a
);
894 priority_a_mark
= dfixed_trunc(c
);
895 priority_a_cnt
|= priority_a_mark
& PRIORITY_MARK_MASK
;
897 a
.full
= dfixed_const(1000);
898 b
.full
= dfixed_const(mode
->clock
);
899 b
.full
= dfixed_div(b
, a
);
900 c
.full
= dfixed_const(latency_watermark_b
);
901 c
.full
= dfixed_mul(c
, b
);
902 c
.full
= dfixed_mul(c
, radeon_crtc
->hsc
);
903 c
.full
= dfixed_div(c
, a
);
904 a
.full
= dfixed_const(16);
905 c
.full
= dfixed_div(c
, a
);
906 priority_b_mark
= dfixed_trunc(c
);
907 priority_b_cnt
|= priority_b_mark
& PRIORITY_MARK_MASK
;
911 arb_control3
= RREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
);
913 tmp
&= ~LATENCY_WATERMARK_MASK(3);
914 tmp
|= LATENCY_WATERMARK_MASK(1);
915 WREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
, tmp
);
916 WREG32(PIPE0_LATENCY_CONTROL
+ pipe_offset
,
917 (LATENCY_LOW_WATERMARK(latency_watermark_a
) |
918 LATENCY_HIGH_WATERMARK(line_time
)));
920 tmp
= RREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
);
921 tmp
&= ~LATENCY_WATERMARK_MASK(3);
922 tmp
|= LATENCY_WATERMARK_MASK(2);
923 WREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
, tmp
);
924 WREG32(PIPE0_LATENCY_CONTROL
+ pipe_offset
,
925 (LATENCY_LOW_WATERMARK(latency_watermark_b
) |
926 LATENCY_HIGH_WATERMARK(line_time
)));
927 /* restore original selection */
928 WREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
, arb_control3
);
930 /* write the priority marks */
931 WREG32(PRIORITY_A_CNT
+ radeon_crtc
->crtc_offset
, priority_a_cnt
);
932 WREG32(PRIORITY_B_CNT
+ radeon_crtc
->crtc_offset
, priority_b_cnt
);
936 void evergreen_bandwidth_update(struct radeon_device
*rdev
)
938 struct drm_display_mode
*mode0
= NULL
;
939 struct drm_display_mode
*mode1
= NULL
;
940 u32 num_heads
= 0, lb_size
;
943 radeon_update_display_priority(rdev
);
945 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
946 if (rdev
->mode_info
.crtcs
[i
]->base
.enabled
)
949 for (i
= 0; i
< rdev
->num_crtc
; i
+= 2) {
950 mode0
= &rdev
->mode_info
.crtcs
[i
]->base
.mode
;
951 mode1
= &rdev
->mode_info
.crtcs
[i
+1]->base
.mode
;
952 lb_size
= evergreen_line_buffer_adjust(rdev
, rdev
->mode_info
.crtcs
[i
], mode0
, mode1
);
953 evergreen_program_watermarks(rdev
, rdev
->mode_info
.crtcs
[i
], lb_size
, num_heads
);
954 lb_size
= evergreen_line_buffer_adjust(rdev
, rdev
->mode_info
.crtcs
[i
+1], mode1
, mode0
);
955 evergreen_program_watermarks(rdev
, rdev
->mode_info
.crtcs
[i
+1], lb_size
, num_heads
);
959 int evergreen_mc_wait_for_idle(struct radeon_device
*rdev
)
964 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
966 tmp
= RREG32(SRBM_STATUS
) & 0x1F00;
977 void evergreen_pcie_gart_tlb_flush(struct radeon_device
*rdev
)
982 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL
, 0x1);
984 WREG32(VM_CONTEXT0_REQUEST_RESPONSE
, REQUEST_TYPE(1));
985 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
987 tmp
= RREG32(VM_CONTEXT0_REQUEST_RESPONSE
);
988 tmp
= (tmp
& RESPONSE_TYPE_MASK
) >> RESPONSE_TYPE_SHIFT
;
990 printk(KERN_WARNING
"[drm] r600 flush TLB failed\n");
1000 int evergreen_pcie_gart_enable(struct radeon_device
*rdev
)
1005 if (rdev
->gart
.robj
== NULL
) {
1006 dev_err(rdev
->dev
, "No VRAM object for PCIE GART.\n");
1009 r
= radeon_gart_table_vram_pin(rdev
);
1012 radeon_gart_restore(rdev
);
1013 /* Setup L2 cache */
1014 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
1015 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
1016 EFFECTIVE_L2_QUEUE_SIZE(7));
1017 WREG32(VM_L2_CNTL2
, 0);
1018 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1019 /* Setup TLB control */
1020 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
1021 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
1022 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
|
1023 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1024 if (rdev
->flags
& RADEON_IS_IGP
) {
1025 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL
, tmp
);
1026 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL
, tmp
);
1027 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL
, tmp
);
1029 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
1030 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
1031 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
1032 if ((rdev
->family
== CHIP_JUNIPER
) ||
1033 (rdev
->family
== CHIP_CYPRESS
) ||
1034 (rdev
->family
== CHIP_HEMLOCK
) ||
1035 (rdev
->family
== CHIP_BARTS
))
1036 WREG32(MC_VM_MD_L1_TLB3_CNTL
, tmp
);
1038 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
1039 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
1040 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
1041 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
1042 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR
, rdev
->mc
.gtt_start
>> 12);
1043 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR
, rdev
->mc
.gtt_end
>> 12);
1044 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, rdev
->gart
.table_addr
>> 12);
1045 WREG32(VM_CONTEXT0_CNTL
, ENABLE_CONTEXT
| PAGE_TABLE_DEPTH(0) |
1046 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
);
1047 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
,
1048 (u32
)(rdev
->dummy_page
.addr
>> 12));
1049 WREG32(VM_CONTEXT1_CNTL
, 0);
1051 evergreen_pcie_gart_tlb_flush(rdev
);
1052 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1053 (unsigned)(rdev
->mc
.gtt_size
>> 20),
1054 (unsigned long long)rdev
->gart
.table_addr
);
1055 rdev
->gart
.ready
= true;
1059 void evergreen_pcie_gart_disable(struct radeon_device
*rdev
)
1063 /* Disable all tables */
1064 WREG32(VM_CONTEXT0_CNTL
, 0);
1065 WREG32(VM_CONTEXT1_CNTL
, 0);
1067 /* Setup L2 cache */
1068 WREG32(VM_L2_CNTL
, ENABLE_L2_FRAGMENT_PROCESSING
|
1069 EFFECTIVE_L2_QUEUE_SIZE(7));
1070 WREG32(VM_L2_CNTL2
, 0);
1071 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1072 /* Setup TLB control */
1073 tmp
= EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1074 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
1075 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
1076 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
1077 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
1078 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
1079 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
1080 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
1081 radeon_gart_table_vram_unpin(rdev
);
1084 void evergreen_pcie_gart_fini(struct radeon_device
*rdev
)
1086 evergreen_pcie_gart_disable(rdev
);
1087 radeon_gart_table_vram_free(rdev
);
1088 radeon_gart_fini(rdev
);
1092 void evergreen_agp_enable(struct radeon_device
*rdev
)
1096 /* Setup L2 cache */
1097 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
1098 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
1099 EFFECTIVE_L2_QUEUE_SIZE(7));
1100 WREG32(VM_L2_CNTL2
, 0);
1101 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1102 /* Setup TLB control */
1103 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
1104 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
1105 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
|
1106 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1107 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
1108 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
1109 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
1110 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
1111 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
1112 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
1113 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
1114 WREG32(VM_CONTEXT0_CNTL
, 0);
1115 WREG32(VM_CONTEXT1_CNTL
, 0);
1118 void evergreen_mc_stop(struct radeon_device
*rdev
, struct evergreen_mc_save
*save
)
1120 save
->vga_control
[0] = RREG32(D1VGA_CONTROL
);
1121 save
->vga_control
[1] = RREG32(D2VGA_CONTROL
);
1122 save
->vga_render_control
= RREG32(VGA_RENDER_CONTROL
);
1123 save
->vga_hdp_control
= RREG32(VGA_HDP_CONTROL
);
1124 save
->crtc_control
[0] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
);
1125 save
->crtc_control
[1] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
1126 if (rdev
->num_crtc
>= 4) {
1127 save
->vga_control
[2] = RREG32(EVERGREEN_D3VGA_CONTROL
);
1128 save
->vga_control
[3] = RREG32(EVERGREEN_D4VGA_CONTROL
);
1129 save
->crtc_control
[2] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
);
1130 save
->crtc_control
[3] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
1132 if (rdev
->num_crtc
>= 6) {
1133 save
->vga_control
[4] = RREG32(EVERGREEN_D5VGA_CONTROL
);
1134 save
->vga_control
[5] = RREG32(EVERGREEN_D6VGA_CONTROL
);
1135 save
->crtc_control
[4] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
);
1136 save
->crtc_control
[5] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
1139 /* Stop all video */
1140 WREG32(VGA_RENDER_CONTROL
, 0);
1141 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 1);
1142 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 1);
1143 if (rdev
->num_crtc
>= 4) {
1144 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 1);
1145 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 1);
1147 if (rdev
->num_crtc
>= 6) {
1148 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 1);
1149 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 1);
1151 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
1152 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
1153 if (rdev
->num_crtc
>= 4) {
1154 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
1155 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
1157 if (rdev
->num_crtc
>= 6) {
1158 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
1159 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
1161 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
1162 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
1163 if (rdev
->num_crtc
>= 4) {
1164 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
1165 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
1167 if (rdev
->num_crtc
>= 6) {
1168 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
1169 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
1172 WREG32(D1VGA_CONTROL
, 0);
1173 WREG32(D2VGA_CONTROL
, 0);
1174 if (rdev
->num_crtc
>= 4) {
1175 WREG32(EVERGREEN_D3VGA_CONTROL
, 0);
1176 WREG32(EVERGREEN_D4VGA_CONTROL
, 0);
1178 if (rdev
->num_crtc
>= 6) {
1179 WREG32(EVERGREEN_D5VGA_CONTROL
, 0);
1180 WREG32(EVERGREEN_D6VGA_CONTROL
, 0);
1184 void evergreen_mc_resume(struct radeon_device
*rdev
, struct evergreen_mc_save
*save
)
1186 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC0_REGISTER_OFFSET
,
1187 upper_32_bits(rdev
->mc
.vram_start
));
1188 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC0_REGISTER_OFFSET
,
1189 upper_32_bits(rdev
->mc
.vram_start
));
1190 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
,
1191 (u32
)rdev
->mc
.vram_start
);
1192 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
,
1193 (u32
)rdev
->mc
.vram_start
);
1195 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC1_REGISTER_OFFSET
,
1196 upper_32_bits(rdev
->mc
.vram_start
));
1197 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC1_REGISTER_OFFSET
,
1198 upper_32_bits(rdev
->mc
.vram_start
));
1199 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
,
1200 (u32
)rdev
->mc
.vram_start
);
1201 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
,
1202 (u32
)rdev
->mc
.vram_start
);
1204 if (rdev
->num_crtc
>= 4) {
1205 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC2_REGISTER_OFFSET
,
1206 upper_32_bits(rdev
->mc
.vram_start
));
1207 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC2_REGISTER_OFFSET
,
1208 upper_32_bits(rdev
->mc
.vram_start
));
1209 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
,
1210 (u32
)rdev
->mc
.vram_start
);
1211 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
,
1212 (u32
)rdev
->mc
.vram_start
);
1214 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC3_REGISTER_OFFSET
,
1215 upper_32_bits(rdev
->mc
.vram_start
));
1216 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC3_REGISTER_OFFSET
,
1217 upper_32_bits(rdev
->mc
.vram_start
));
1218 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
,
1219 (u32
)rdev
->mc
.vram_start
);
1220 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
,
1221 (u32
)rdev
->mc
.vram_start
);
1223 if (rdev
->num_crtc
>= 6) {
1224 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC4_REGISTER_OFFSET
,
1225 upper_32_bits(rdev
->mc
.vram_start
));
1226 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC4_REGISTER_OFFSET
,
1227 upper_32_bits(rdev
->mc
.vram_start
));
1228 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
,
1229 (u32
)rdev
->mc
.vram_start
);
1230 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
,
1231 (u32
)rdev
->mc
.vram_start
);
1233 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC5_REGISTER_OFFSET
,
1234 upper_32_bits(rdev
->mc
.vram_start
));
1235 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC5_REGISTER_OFFSET
,
1236 upper_32_bits(rdev
->mc
.vram_start
));
1237 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
,
1238 (u32
)rdev
->mc
.vram_start
);
1239 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
,
1240 (u32
)rdev
->mc
.vram_start
);
1243 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH
, upper_32_bits(rdev
->mc
.vram_start
));
1244 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS
, (u32
)rdev
->mc
.vram_start
);
1245 /* Unlock host access */
1246 WREG32(VGA_HDP_CONTROL
, save
->vga_hdp_control
);
1248 /* Restore video state */
1249 WREG32(D1VGA_CONTROL
, save
->vga_control
[0]);
1250 WREG32(D2VGA_CONTROL
, save
->vga_control
[1]);
1251 if (rdev
->num_crtc
>= 4) {
1252 WREG32(EVERGREEN_D3VGA_CONTROL
, save
->vga_control
[2]);
1253 WREG32(EVERGREEN_D4VGA_CONTROL
, save
->vga_control
[3]);
1255 if (rdev
->num_crtc
>= 6) {
1256 WREG32(EVERGREEN_D5VGA_CONTROL
, save
->vga_control
[4]);
1257 WREG32(EVERGREEN_D6VGA_CONTROL
, save
->vga_control
[5]);
1259 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 1);
1260 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 1);
1261 if (rdev
->num_crtc
>= 4) {
1262 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 1);
1263 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 1);
1265 if (rdev
->num_crtc
>= 6) {
1266 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 1);
1267 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 1);
1269 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, save
->crtc_control
[0]);
1270 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, save
->crtc_control
[1]);
1271 if (rdev
->num_crtc
>= 4) {
1272 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, save
->crtc_control
[2]);
1273 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, save
->crtc_control
[3]);
1275 if (rdev
->num_crtc
>= 6) {
1276 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, save
->crtc_control
[4]);
1277 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, save
->crtc_control
[5]);
1279 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
1280 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
1281 if (rdev
->num_crtc
>= 4) {
1282 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
1283 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
1285 if (rdev
->num_crtc
>= 6) {
1286 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
1287 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
1289 WREG32(VGA_RENDER_CONTROL
, save
->vga_render_control
);
1292 void evergreen_mc_program(struct radeon_device
*rdev
)
1294 struct evergreen_mc_save save
;
1298 /* Initialize HDP */
1299 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
1300 WREG32((0x2c14 + j
), 0x00000000);
1301 WREG32((0x2c18 + j
), 0x00000000);
1302 WREG32((0x2c1c + j
), 0x00000000);
1303 WREG32((0x2c20 + j
), 0x00000000);
1304 WREG32((0x2c24 + j
), 0x00000000);
1306 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL
, 0);
1308 evergreen_mc_stop(rdev
, &save
);
1309 if (evergreen_mc_wait_for_idle(rdev
)) {
1310 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1312 /* Lockout access through VGA aperture*/
1313 WREG32(VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
);
1314 /* Update configuration */
1315 if (rdev
->flags
& RADEON_IS_AGP
) {
1316 if (rdev
->mc
.vram_start
< rdev
->mc
.gtt_start
) {
1317 /* VRAM before AGP */
1318 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
1319 rdev
->mc
.vram_start
>> 12);
1320 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
1321 rdev
->mc
.gtt_end
>> 12);
1323 /* VRAM after AGP */
1324 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
1325 rdev
->mc
.gtt_start
>> 12);
1326 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
1327 rdev
->mc
.vram_end
>> 12);
1330 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
1331 rdev
->mc
.vram_start
>> 12);
1332 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
1333 rdev
->mc
.vram_end
>> 12);
1335 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
, rdev
->vram_scratch
.gpu_addr
>> 12);
1336 /* llano/ontario only */
1337 if ((rdev
->family
== CHIP_PALM
) ||
1338 (rdev
->family
== CHIP_SUMO
) ||
1339 (rdev
->family
== CHIP_SUMO2
)) {
1340 tmp
= RREG32(MC_FUS_VM_FB_OFFSET
) & 0x000FFFFF;
1341 tmp
|= ((rdev
->mc
.vram_end
>> 20) & 0xF) << 24;
1342 tmp
|= ((rdev
->mc
.vram_start
>> 20) & 0xF) << 20;
1343 WREG32(MC_FUS_VM_FB_OFFSET
, tmp
);
1345 tmp
= ((rdev
->mc
.vram_end
>> 24) & 0xFFFF) << 16;
1346 tmp
|= ((rdev
->mc
.vram_start
>> 24) & 0xFFFF);
1347 WREG32(MC_VM_FB_LOCATION
, tmp
);
1348 WREG32(HDP_NONSURFACE_BASE
, (rdev
->mc
.vram_start
>> 8));
1349 WREG32(HDP_NONSURFACE_INFO
, (2 << 7) | (1 << 30));
1350 WREG32(HDP_NONSURFACE_SIZE
, 0x3FFFFFFF);
1351 if (rdev
->flags
& RADEON_IS_AGP
) {
1352 WREG32(MC_VM_AGP_TOP
, rdev
->mc
.gtt_end
>> 16);
1353 WREG32(MC_VM_AGP_BOT
, rdev
->mc
.gtt_start
>> 16);
1354 WREG32(MC_VM_AGP_BASE
, rdev
->mc
.agp_base
>> 22);
1356 WREG32(MC_VM_AGP_BASE
, 0);
1357 WREG32(MC_VM_AGP_TOP
, 0x0FFFFFFF);
1358 WREG32(MC_VM_AGP_BOT
, 0x0FFFFFFF);
1360 if (evergreen_mc_wait_for_idle(rdev
)) {
1361 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1363 evergreen_mc_resume(rdev
, &save
);
1364 /* we need to own VRAM, so turn off the VGA renderer here
1365 * to stop it overwriting our objects */
1366 rv515_vga_render_disable(rdev
);
1372 void evergreen_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
1374 struct radeon_ring
*ring
= &rdev
->ring
[ib
->fence
->ring
];
1376 /* set to DX10/11 mode */
1377 radeon_ring_write(ring
, PACKET3(PACKET3_MODE_CONTROL
, 0));
1378 radeon_ring_write(ring
, 1);
1379 /* FIXME: implement */
1380 radeon_ring_write(ring
, PACKET3(PACKET3_INDIRECT_BUFFER
, 2));
1381 radeon_ring_write(ring
,
1385 (ib
->gpu_addr
& 0xFFFFFFFC));
1386 radeon_ring_write(ring
, upper_32_bits(ib
->gpu_addr
) & 0xFF);
1387 radeon_ring_write(ring
, ib
->length_dw
);
1391 static int evergreen_cp_load_microcode(struct radeon_device
*rdev
)
1393 const __be32
*fw_data
;
1396 if (!rdev
->me_fw
|| !rdev
->pfp_fw
)
1404 RB_NO_UPDATE
| RB_BLKSZ(15) | RB_BUFSZ(3));
1406 fw_data
= (const __be32
*)rdev
->pfp_fw
->data
;
1407 WREG32(CP_PFP_UCODE_ADDR
, 0);
1408 for (i
= 0; i
< EVERGREEN_PFP_UCODE_SIZE
; i
++)
1409 WREG32(CP_PFP_UCODE_DATA
, be32_to_cpup(fw_data
++));
1410 WREG32(CP_PFP_UCODE_ADDR
, 0);
1412 fw_data
= (const __be32
*)rdev
->me_fw
->data
;
1413 WREG32(CP_ME_RAM_WADDR
, 0);
1414 for (i
= 0; i
< EVERGREEN_PM4_UCODE_SIZE
; i
++)
1415 WREG32(CP_ME_RAM_DATA
, be32_to_cpup(fw_data
++));
1417 WREG32(CP_PFP_UCODE_ADDR
, 0);
1418 WREG32(CP_ME_RAM_WADDR
, 0);
1419 WREG32(CP_ME_RAM_RADDR
, 0);
1423 static int evergreen_cp_start(struct radeon_device
*rdev
)
1425 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
1429 r
= radeon_ring_lock(rdev
, ring
, 7);
1431 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
1434 radeon_ring_write(ring
, PACKET3(PACKET3_ME_INITIALIZE
, 5));
1435 radeon_ring_write(ring
, 0x1);
1436 radeon_ring_write(ring
, 0x0);
1437 radeon_ring_write(ring
, rdev
->config
.evergreen
.max_hw_contexts
- 1);
1438 radeon_ring_write(ring
, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1439 radeon_ring_write(ring
, 0);
1440 radeon_ring_write(ring
, 0);
1441 radeon_ring_unlock_commit(rdev
, ring
);
1444 WREG32(CP_ME_CNTL
, cp_me
);
1446 r
= radeon_ring_lock(rdev
, ring
, evergreen_default_size
+ 19);
1448 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
1452 /* setup clear context state */
1453 radeon_ring_write(ring
, PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
1454 radeon_ring_write(ring
, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE
);
1456 for (i
= 0; i
< evergreen_default_size
; i
++)
1457 radeon_ring_write(ring
, evergreen_default_state
[i
]);
1459 radeon_ring_write(ring
, PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
1460 radeon_ring_write(ring
, PACKET3_PREAMBLE_END_CLEAR_STATE
);
1462 /* set clear context state */
1463 radeon_ring_write(ring
, PACKET3(PACKET3_CLEAR_STATE
, 0));
1464 radeon_ring_write(ring
, 0);
1466 /* SQ_VTX_BASE_VTX_LOC */
1467 radeon_ring_write(ring
, 0xc0026f00);
1468 radeon_ring_write(ring
, 0x00000000);
1469 radeon_ring_write(ring
, 0x00000000);
1470 radeon_ring_write(ring
, 0x00000000);
1473 radeon_ring_write(ring
, 0xc0036f00);
1474 radeon_ring_write(ring
, 0x00000bc4);
1475 radeon_ring_write(ring
, 0xffffffff);
1476 radeon_ring_write(ring
, 0xffffffff);
1477 radeon_ring_write(ring
, 0xffffffff);
1479 radeon_ring_write(ring
, 0xc0026900);
1480 radeon_ring_write(ring
, 0x00000316);
1481 radeon_ring_write(ring
, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1482 radeon_ring_write(ring
, 0x00000010); /* */
1484 radeon_ring_unlock_commit(rdev
, ring
);
1489 int evergreen_cp_resume(struct radeon_device
*rdev
)
1491 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
1496 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1497 WREG32(GRBM_SOFT_RESET
, (SOFT_RESET_CP
|
1503 RREG32(GRBM_SOFT_RESET
);
1505 WREG32(GRBM_SOFT_RESET
, 0);
1506 RREG32(GRBM_SOFT_RESET
);
1508 /* Set ring buffer size */
1509 rb_bufsz
= drm_order(ring
->ring_size
/ 8);
1510 tmp
= (drm_order(RADEON_GPU_PAGE_SIZE
/8) << 8) | rb_bufsz
;
1512 tmp
|= BUF_SWAP_32BIT
;
1514 WREG32(CP_RB_CNTL
, tmp
);
1515 WREG32(CP_SEM_WAIT_TIMER
, 0x0);
1516 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL
, 0x0);
1518 /* Set the write pointer delay */
1519 WREG32(CP_RB_WPTR_DELAY
, 0);
1521 /* Initialize the ring buffer's read and write pointers */
1522 WREG32(CP_RB_CNTL
, tmp
| RB_RPTR_WR_ENA
);
1523 WREG32(CP_RB_RPTR_WR
, 0);
1525 WREG32(CP_RB_WPTR
, ring
->wptr
);
1527 /* set the wb address wether it's enabled or not */
1528 WREG32(CP_RB_RPTR_ADDR
,
1529 ((rdev
->wb
.gpu_addr
+ RADEON_WB_CP_RPTR_OFFSET
) & 0xFFFFFFFC));
1530 WREG32(CP_RB_RPTR_ADDR_HI
, upper_32_bits(rdev
->wb
.gpu_addr
+ RADEON_WB_CP_RPTR_OFFSET
) & 0xFF);
1531 WREG32(SCRATCH_ADDR
, ((rdev
->wb
.gpu_addr
+ RADEON_WB_SCRATCH_OFFSET
) >> 8) & 0xFFFFFFFF);
1533 if (rdev
->wb
.enabled
)
1534 WREG32(SCRATCH_UMSK
, 0xff);
1536 tmp
|= RB_NO_UPDATE
;
1537 WREG32(SCRATCH_UMSK
, 0);
1541 WREG32(CP_RB_CNTL
, tmp
);
1543 WREG32(CP_RB_BASE
, ring
->gpu_addr
>> 8);
1544 WREG32(CP_DEBUG
, (1 << 27) | (1 << 28));
1546 ring
->rptr
= RREG32(CP_RB_RPTR
);
1548 evergreen_cp_start(rdev
);
1550 r
= radeon_ring_test(rdev
, RADEON_RING_TYPE_GFX_INDEX
, ring
);
1552 ring
->ready
= false;
1561 static void evergreen_gpu_init(struct radeon_device
*rdev
)
1564 u32 mc_shared_chmap
, mc_arb_ramcfg
;
1568 u32 sq_lds_resource_mgmt
;
1569 u32 sq_gpr_resource_mgmt_1
;
1570 u32 sq_gpr_resource_mgmt_2
;
1571 u32 sq_gpr_resource_mgmt_3
;
1572 u32 sq_thread_resource_mgmt
;
1573 u32 sq_thread_resource_mgmt_2
;
1574 u32 sq_stack_resource_mgmt_1
;
1575 u32 sq_stack_resource_mgmt_2
;
1576 u32 sq_stack_resource_mgmt_3
;
1577 u32 vgt_cache_invalidation
;
1578 u32 hdp_host_path_cntl
, tmp
;
1579 u32 disabled_rb_mask
;
1580 int i
, j
, num_shader_engines
, ps_thread_count
;
1582 switch (rdev
->family
) {
1585 rdev
->config
.evergreen
.num_ses
= 2;
1586 rdev
->config
.evergreen
.max_pipes
= 4;
1587 rdev
->config
.evergreen
.max_tile_pipes
= 8;
1588 rdev
->config
.evergreen
.max_simds
= 10;
1589 rdev
->config
.evergreen
.max_backends
= 4 * rdev
->config
.evergreen
.num_ses
;
1590 rdev
->config
.evergreen
.max_gprs
= 256;
1591 rdev
->config
.evergreen
.max_threads
= 248;
1592 rdev
->config
.evergreen
.max_gs_threads
= 32;
1593 rdev
->config
.evergreen
.max_stack_entries
= 512;
1594 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1595 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1596 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1597 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1598 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1599 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1601 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
1602 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1603 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1604 gb_addr_config
= CYPRESS_GB_ADDR_CONFIG_GOLDEN
;
1607 rdev
->config
.evergreen
.num_ses
= 1;
1608 rdev
->config
.evergreen
.max_pipes
= 4;
1609 rdev
->config
.evergreen
.max_tile_pipes
= 4;
1610 rdev
->config
.evergreen
.max_simds
= 10;
1611 rdev
->config
.evergreen
.max_backends
= 4 * rdev
->config
.evergreen
.num_ses
;
1612 rdev
->config
.evergreen
.max_gprs
= 256;
1613 rdev
->config
.evergreen
.max_threads
= 248;
1614 rdev
->config
.evergreen
.max_gs_threads
= 32;
1615 rdev
->config
.evergreen
.max_stack_entries
= 512;
1616 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1617 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1618 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1619 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1620 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1621 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1623 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
1624 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1625 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1626 gb_addr_config
= JUNIPER_GB_ADDR_CONFIG_GOLDEN
;
1629 rdev
->config
.evergreen
.num_ses
= 1;
1630 rdev
->config
.evergreen
.max_pipes
= 4;
1631 rdev
->config
.evergreen
.max_tile_pipes
= 4;
1632 rdev
->config
.evergreen
.max_simds
= 5;
1633 rdev
->config
.evergreen
.max_backends
= 2 * rdev
->config
.evergreen
.num_ses
;
1634 rdev
->config
.evergreen
.max_gprs
= 256;
1635 rdev
->config
.evergreen
.max_threads
= 248;
1636 rdev
->config
.evergreen
.max_gs_threads
= 32;
1637 rdev
->config
.evergreen
.max_stack_entries
= 256;
1638 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1639 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1640 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1641 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1642 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1643 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1645 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
1646 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1647 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1648 gb_addr_config
= REDWOOD_GB_ADDR_CONFIG_GOLDEN
;
1652 rdev
->config
.evergreen
.num_ses
= 1;
1653 rdev
->config
.evergreen
.max_pipes
= 2;
1654 rdev
->config
.evergreen
.max_tile_pipes
= 2;
1655 rdev
->config
.evergreen
.max_simds
= 2;
1656 rdev
->config
.evergreen
.max_backends
= 1 * rdev
->config
.evergreen
.num_ses
;
1657 rdev
->config
.evergreen
.max_gprs
= 256;
1658 rdev
->config
.evergreen
.max_threads
= 192;
1659 rdev
->config
.evergreen
.max_gs_threads
= 16;
1660 rdev
->config
.evergreen
.max_stack_entries
= 256;
1661 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1662 rdev
->config
.evergreen
.sx_max_export_size
= 128;
1663 rdev
->config
.evergreen
.sx_max_export_pos_size
= 32;
1664 rdev
->config
.evergreen
.sx_max_export_smx_size
= 96;
1665 rdev
->config
.evergreen
.max_hw_contexts
= 4;
1666 rdev
->config
.evergreen
.sq_num_cf_insts
= 1;
1668 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x40;
1669 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1670 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1671 gb_addr_config
= CEDAR_GB_ADDR_CONFIG_GOLDEN
;
1674 rdev
->config
.evergreen
.num_ses
= 1;
1675 rdev
->config
.evergreen
.max_pipes
= 2;
1676 rdev
->config
.evergreen
.max_tile_pipes
= 2;
1677 rdev
->config
.evergreen
.max_simds
= 2;
1678 rdev
->config
.evergreen
.max_backends
= 1 * rdev
->config
.evergreen
.num_ses
;
1679 rdev
->config
.evergreen
.max_gprs
= 256;
1680 rdev
->config
.evergreen
.max_threads
= 192;
1681 rdev
->config
.evergreen
.max_gs_threads
= 16;
1682 rdev
->config
.evergreen
.max_stack_entries
= 256;
1683 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1684 rdev
->config
.evergreen
.sx_max_export_size
= 128;
1685 rdev
->config
.evergreen
.sx_max_export_pos_size
= 32;
1686 rdev
->config
.evergreen
.sx_max_export_smx_size
= 96;
1687 rdev
->config
.evergreen
.max_hw_contexts
= 4;
1688 rdev
->config
.evergreen
.sq_num_cf_insts
= 1;
1690 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x40;
1691 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1692 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1693 gb_addr_config
= CEDAR_GB_ADDR_CONFIG_GOLDEN
;
1696 rdev
->config
.evergreen
.num_ses
= 1;
1697 rdev
->config
.evergreen
.max_pipes
= 4;
1698 rdev
->config
.evergreen
.max_tile_pipes
= 2;
1699 if (rdev
->pdev
->device
== 0x9648)
1700 rdev
->config
.evergreen
.max_simds
= 3;
1701 else if ((rdev
->pdev
->device
== 0x9647) ||
1702 (rdev
->pdev
->device
== 0x964a))
1703 rdev
->config
.evergreen
.max_simds
= 4;
1705 rdev
->config
.evergreen
.max_simds
= 5;
1706 rdev
->config
.evergreen
.max_backends
= 2 * rdev
->config
.evergreen
.num_ses
;
1707 rdev
->config
.evergreen
.max_gprs
= 256;
1708 rdev
->config
.evergreen
.max_threads
= 248;
1709 rdev
->config
.evergreen
.max_gs_threads
= 32;
1710 rdev
->config
.evergreen
.max_stack_entries
= 256;
1711 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1712 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1713 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1714 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1715 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1716 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1718 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x40;
1719 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1720 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1721 gb_addr_config
= REDWOOD_GB_ADDR_CONFIG_GOLDEN
;
1724 rdev
->config
.evergreen
.num_ses
= 1;
1725 rdev
->config
.evergreen
.max_pipes
= 4;
1726 rdev
->config
.evergreen
.max_tile_pipes
= 4;
1727 rdev
->config
.evergreen
.max_simds
= 2;
1728 rdev
->config
.evergreen
.max_backends
= 1 * rdev
->config
.evergreen
.num_ses
;
1729 rdev
->config
.evergreen
.max_gprs
= 256;
1730 rdev
->config
.evergreen
.max_threads
= 248;
1731 rdev
->config
.evergreen
.max_gs_threads
= 32;
1732 rdev
->config
.evergreen
.max_stack_entries
= 512;
1733 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1734 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1735 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1736 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1737 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1738 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1740 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x40;
1741 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1742 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1743 gb_addr_config
= REDWOOD_GB_ADDR_CONFIG_GOLDEN
;
1746 rdev
->config
.evergreen
.num_ses
= 2;
1747 rdev
->config
.evergreen
.max_pipes
= 4;
1748 rdev
->config
.evergreen
.max_tile_pipes
= 8;
1749 rdev
->config
.evergreen
.max_simds
= 7;
1750 rdev
->config
.evergreen
.max_backends
= 4 * rdev
->config
.evergreen
.num_ses
;
1751 rdev
->config
.evergreen
.max_gprs
= 256;
1752 rdev
->config
.evergreen
.max_threads
= 248;
1753 rdev
->config
.evergreen
.max_gs_threads
= 32;
1754 rdev
->config
.evergreen
.max_stack_entries
= 512;
1755 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1756 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1757 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1758 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1759 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1760 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1762 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
1763 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1764 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1765 gb_addr_config
= BARTS_GB_ADDR_CONFIG_GOLDEN
;
1768 rdev
->config
.evergreen
.num_ses
= 1;
1769 rdev
->config
.evergreen
.max_pipes
= 4;
1770 rdev
->config
.evergreen
.max_tile_pipes
= 4;
1771 rdev
->config
.evergreen
.max_simds
= 6;
1772 rdev
->config
.evergreen
.max_backends
= 2 * rdev
->config
.evergreen
.num_ses
;
1773 rdev
->config
.evergreen
.max_gprs
= 256;
1774 rdev
->config
.evergreen
.max_threads
= 248;
1775 rdev
->config
.evergreen
.max_gs_threads
= 32;
1776 rdev
->config
.evergreen
.max_stack_entries
= 256;
1777 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1778 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1779 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1780 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1781 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1782 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1784 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
1785 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1786 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1787 gb_addr_config
= TURKS_GB_ADDR_CONFIG_GOLDEN
;
1790 rdev
->config
.evergreen
.num_ses
= 1;
1791 rdev
->config
.evergreen
.max_pipes
= 4;
1792 rdev
->config
.evergreen
.max_tile_pipes
= 2;
1793 rdev
->config
.evergreen
.max_simds
= 2;
1794 rdev
->config
.evergreen
.max_backends
= 1 * rdev
->config
.evergreen
.num_ses
;
1795 rdev
->config
.evergreen
.max_gprs
= 256;
1796 rdev
->config
.evergreen
.max_threads
= 192;
1797 rdev
->config
.evergreen
.max_gs_threads
= 16;
1798 rdev
->config
.evergreen
.max_stack_entries
= 256;
1799 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1800 rdev
->config
.evergreen
.sx_max_export_size
= 128;
1801 rdev
->config
.evergreen
.sx_max_export_pos_size
= 32;
1802 rdev
->config
.evergreen
.sx_max_export_smx_size
= 96;
1803 rdev
->config
.evergreen
.max_hw_contexts
= 4;
1804 rdev
->config
.evergreen
.sq_num_cf_insts
= 1;
1806 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x40;
1807 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1808 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1809 gb_addr_config
= CAICOS_GB_ADDR_CONFIG_GOLDEN
;
1813 /* Initialize HDP */
1814 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
1815 WREG32((0x2c14 + j
), 0x00000000);
1816 WREG32((0x2c18 + j
), 0x00000000);
1817 WREG32((0x2c1c + j
), 0x00000000);
1818 WREG32((0x2c20 + j
), 0x00000000);
1819 WREG32((0x2c24 + j
), 0x00000000);
1822 WREG32(GRBM_CNTL
, GRBM_READ_TIMEOUT(0xff));
1824 evergreen_fix_pci_max_read_req_size(rdev
);
1826 mc_shared_chmap
= RREG32(MC_SHARED_CHMAP
);
1827 if ((rdev
->family
== CHIP_PALM
) ||
1828 (rdev
->family
== CHIP_SUMO
) ||
1829 (rdev
->family
== CHIP_SUMO2
))
1830 mc_arb_ramcfg
= RREG32(FUS_MC_ARB_RAMCFG
);
1832 mc_arb_ramcfg
= RREG32(MC_ARB_RAMCFG
);
1834 /* setup tiling info dword. gb_addr_config is not adequate since it does
1835 * not have bank info, so create a custom tiling dword.
1836 * bits 3:0 num_pipes
1837 * bits 7:4 num_banks
1838 * bits 11:8 group_size
1839 * bits 15:12 row_size
1841 rdev
->config
.evergreen
.tile_config
= 0;
1842 switch (rdev
->config
.evergreen
.max_tile_pipes
) {
1845 rdev
->config
.evergreen
.tile_config
|= (0 << 0);
1848 rdev
->config
.evergreen
.tile_config
|= (1 << 0);
1851 rdev
->config
.evergreen
.tile_config
|= (2 << 0);
1854 rdev
->config
.evergreen
.tile_config
|= (3 << 0);
1857 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
1858 if (rdev
->flags
& RADEON_IS_IGP
)
1859 rdev
->config
.evergreen
.tile_config
|= 1 << 4;
1861 if ((mc_arb_ramcfg
& NOOFBANK_MASK
) >> NOOFBANK_SHIFT
)
1862 rdev
->config
.evergreen
.tile_config
|= 1 << 4;
1864 rdev
->config
.evergreen
.tile_config
|= 0 << 4;
1866 rdev
->config
.evergreen
.tile_config
|= 0 << 8;
1867 rdev
->config
.evergreen
.tile_config
|=
1868 ((gb_addr_config
& 0x30000000) >> 28) << 12;
1870 num_shader_engines
= (gb_addr_config
& NUM_SHADER_ENGINES(3) >> 12) + 1;
1872 if ((rdev
->family
>= CHIP_CEDAR
) && (rdev
->family
<= CHIP_HEMLOCK
)) {
1876 WREG32(RCU_IND_INDEX
, 0x204);
1877 efuse_straps_4
= RREG32(RCU_IND_DATA
);
1878 WREG32(RCU_IND_INDEX
, 0x203);
1879 efuse_straps_3
= RREG32(RCU_IND_DATA
);
1880 tmp
= (((efuse_straps_4
& 0xf) << 4) |
1881 ((efuse_straps_3
& 0xf0000000) >> 28));
1884 for (i
= (rdev
->config
.evergreen
.num_ses
- 1); i
>= 0; i
--) {
1885 u32 rb_disable_bitmap
;
1887 WREG32(GRBM_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
| SE_INDEX(i
));
1888 WREG32(RLC_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
| SE_INDEX(i
));
1889 rb_disable_bitmap
= (RREG32(CC_RB_BACKEND_DISABLE
) & 0x00ff0000) >> 16;
1891 tmp
|= rb_disable_bitmap
;
1894 /* enabled rb are just the one not disabled :) */
1895 disabled_rb_mask
= tmp
;
1897 WREG32(GRBM_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
| SE_BROADCAST_WRITES
);
1898 WREG32(RLC_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
| SE_BROADCAST_WRITES
);
1900 WREG32(GB_ADDR_CONFIG
, gb_addr_config
);
1901 WREG32(DMIF_ADDR_CONFIG
, gb_addr_config
);
1902 WREG32(HDP_ADDR_CONFIG
, gb_addr_config
);
1904 tmp
= gb_addr_config
& NUM_PIPES_MASK
;
1905 tmp
= r6xx_remap_render_backend(rdev
, tmp
, rdev
->config
.evergreen
.max_backends
,
1906 EVERGREEN_MAX_BACKENDS
, disabled_rb_mask
);
1907 WREG32(GB_BACKEND_MAP
, tmp
);
1909 WREG32(CGTS_SYS_TCC_DISABLE
, 0);
1910 WREG32(CGTS_TCC_DISABLE
, 0);
1911 WREG32(CGTS_USER_SYS_TCC_DISABLE
, 0);
1912 WREG32(CGTS_USER_TCC_DISABLE
, 0);
1914 /* set HW defaults for 3D engine */
1915 WREG32(CP_QUEUE_THRESHOLDS
, (ROQ_IB1_START(0x16) |
1916 ROQ_IB2_START(0x2b)));
1918 WREG32(CP_MEQ_THRESHOLDS
, STQ_SPLIT(0x30));
1920 WREG32(TA_CNTL_AUX
, (DISABLE_CUBE_ANISO
|
1925 sx_debug_1
= RREG32(SX_DEBUG_1
);
1926 sx_debug_1
|= ENABLE_NEW_SMX_ADDRESS
;
1927 WREG32(SX_DEBUG_1
, sx_debug_1
);
1930 smx_dc_ctl0
= RREG32(SMX_DC_CTL0
);
1931 smx_dc_ctl0
&= ~NUMBER_OF_SETS(0x1ff);
1932 smx_dc_ctl0
|= NUMBER_OF_SETS(rdev
->config
.evergreen
.sx_num_of_sets
);
1933 WREG32(SMX_DC_CTL0
, smx_dc_ctl0
);
1935 if (rdev
->family
<= CHIP_SUMO2
)
1936 WREG32(SMX_SAR_CTL0
, 0x00010000);
1938 WREG32(SX_EXPORT_BUFFER_SIZES
, (COLOR_BUFFER_SIZE((rdev
->config
.evergreen
.sx_max_export_size
/ 4) - 1) |
1939 POSITION_BUFFER_SIZE((rdev
->config
.evergreen
.sx_max_export_pos_size
/ 4) - 1) |
1940 SMX_BUFFER_SIZE((rdev
->config
.evergreen
.sx_max_export_smx_size
/ 4) - 1)));
1942 WREG32(PA_SC_FIFO_SIZE
, (SC_PRIM_FIFO_SIZE(rdev
->config
.evergreen
.sc_prim_fifo_size
) |
1943 SC_HIZ_TILE_FIFO_SIZE(rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
) |
1944 SC_EARLYZ_TILE_FIFO_SIZE(rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
)));
1946 WREG32(VGT_NUM_INSTANCES
, 1);
1947 WREG32(SPI_CONFIG_CNTL
, 0);
1948 WREG32(SPI_CONFIG_CNTL_1
, VTX_DONE_DELAY(4));
1949 WREG32(CP_PERFMON_CNTL
, 0);
1951 WREG32(SQ_MS_FIFO_SIZES
, (CACHE_FIFO_SIZE(16 * rdev
->config
.evergreen
.sq_num_cf_insts
) |
1952 FETCH_FIFO_HIWATER(0x4) |
1953 DONE_FIFO_HIWATER(0xe0) |
1954 ALU_UPDATE_FIFO_HIWATER(0x8)));
1956 sq_config
= RREG32(SQ_CONFIG
);
1957 sq_config
&= ~(PS_PRIO(3) |
1961 sq_config
|= (VC_ENABLE
|
1968 switch (rdev
->family
) {
1974 /* no vertex cache */
1975 sq_config
&= ~VC_ENABLE
;
1981 sq_lds_resource_mgmt
= RREG32(SQ_LDS_RESOURCE_MGMT
);
1983 sq_gpr_resource_mgmt_1
= NUM_PS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2))* 12 / 32);
1984 sq_gpr_resource_mgmt_1
|= NUM_VS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 6 / 32);
1985 sq_gpr_resource_mgmt_1
|= NUM_CLAUSE_TEMP_GPRS(4);
1986 sq_gpr_resource_mgmt_2
= NUM_GS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 4 / 32);
1987 sq_gpr_resource_mgmt_2
|= NUM_ES_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 4 / 32);
1988 sq_gpr_resource_mgmt_3
= NUM_HS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 3 / 32);
1989 sq_gpr_resource_mgmt_3
|= NUM_LS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 3 / 32);
1991 switch (rdev
->family
) {
1996 ps_thread_count
= 96;
1999 ps_thread_count
= 128;
2003 sq_thread_resource_mgmt
= NUM_PS_THREADS(ps_thread_count
);
2004 sq_thread_resource_mgmt
|= NUM_VS_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
2005 sq_thread_resource_mgmt
|= NUM_GS_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
2006 sq_thread_resource_mgmt
|= NUM_ES_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
2007 sq_thread_resource_mgmt_2
= NUM_HS_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
2008 sq_thread_resource_mgmt_2
|= NUM_LS_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
2010 sq_stack_resource_mgmt_1
= NUM_PS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2011 sq_stack_resource_mgmt_1
|= NUM_VS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2012 sq_stack_resource_mgmt_2
= NUM_GS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2013 sq_stack_resource_mgmt_2
|= NUM_ES_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2014 sq_stack_resource_mgmt_3
= NUM_HS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2015 sq_stack_resource_mgmt_3
|= NUM_LS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2017 WREG32(SQ_CONFIG
, sq_config
);
2018 WREG32(SQ_GPR_RESOURCE_MGMT_1
, sq_gpr_resource_mgmt_1
);
2019 WREG32(SQ_GPR_RESOURCE_MGMT_2
, sq_gpr_resource_mgmt_2
);
2020 WREG32(SQ_GPR_RESOURCE_MGMT_3
, sq_gpr_resource_mgmt_3
);
2021 WREG32(SQ_THREAD_RESOURCE_MGMT
, sq_thread_resource_mgmt
);
2022 WREG32(SQ_THREAD_RESOURCE_MGMT_2
, sq_thread_resource_mgmt_2
);
2023 WREG32(SQ_STACK_RESOURCE_MGMT_1
, sq_stack_resource_mgmt_1
);
2024 WREG32(SQ_STACK_RESOURCE_MGMT_2
, sq_stack_resource_mgmt_2
);
2025 WREG32(SQ_STACK_RESOURCE_MGMT_3
, sq_stack_resource_mgmt_3
);
2026 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0);
2027 WREG32(SQ_LDS_RESOURCE_MGMT
, sq_lds_resource_mgmt
);
2029 WREG32(PA_SC_FORCE_EOV_MAX_CNTS
, (FORCE_EOV_MAX_CLK_CNT(4095) |
2030 FORCE_EOV_MAX_REZ_CNT(255)));
2032 switch (rdev
->family
) {
2038 vgt_cache_invalidation
= CACHE_INVALIDATION(TC_ONLY
);
2041 vgt_cache_invalidation
= CACHE_INVALIDATION(VC_AND_TC
);
2044 vgt_cache_invalidation
|= AUTO_INVLD_EN(ES_AND_GS_AUTO
);
2045 WREG32(VGT_CACHE_INVALIDATION
, vgt_cache_invalidation
);
2047 WREG32(VGT_GS_VERTEX_REUSE
, 16);
2048 WREG32(PA_SU_LINE_STIPPLE_VALUE
, 0);
2049 WREG32(PA_SC_LINE_STIPPLE_STATE
, 0);
2051 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
2052 WREG32(VGT_OUT_DEALLOC_CNTL
, 16);
2054 WREG32(CB_PERF_CTR0_SEL_0
, 0);
2055 WREG32(CB_PERF_CTR0_SEL_1
, 0);
2056 WREG32(CB_PERF_CTR1_SEL_0
, 0);
2057 WREG32(CB_PERF_CTR1_SEL_1
, 0);
2058 WREG32(CB_PERF_CTR2_SEL_0
, 0);
2059 WREG32(CB_PERF_CTR2_SEL_1
, 0);
2060 WREG32(CB_PERF_CTR3_SEL_0
, 0);
2061 WREG32(CB_PERF_CTR3_SEL_1
, 0);
2063 /* clear render buffer base addresses */
2064 WREG32(CB_COLOR0_BASE
, 0);
2065 WREG32(CB_COLOR1_BASE
, 0);
2066 WREG32(CB_COLOR2_BASE
, 0);
2067 WREG32(CB_COLOR3_BASE
, 0);
2068 WREG32(CB_COLOR4_BASE
, 0);
2069 WREG32(CB_COLOR5_BASE
, 0);
2070 WREG32(CB_COLOR6_BASE
, 0);
2071 WREG32(CB_COLOR7_BASE
, 0);
2072 WREG32(CB_COLOR8_BASE
, 0);
2073 WREG32(CB_COLOR9_BASE
, 0);
2074 WREG32(CB_COLOR10_BASE
, 0);
2075 WREG32(CB_COLOR11_BASE
, 0);
2077 /* set the shader const cache sizes to 0 */
2078 for (i
= SQ_ALU_CONST_BUFFER_SIZE_PS_0
; i
< 0x28200; i
+= 4)
2080 for (i
= SQ_ALU_CONST_BUFFER_SIZE_HS_0
; i
< 0x29000; i
+= 4)
2083 tmp
= RREG32(HDP_MISC_CNTL
);
2084 tmp
|= HDP_FLUSH_INVALIDATE_CACHE
;
2085 WREG32(HDP_MISC_CNTL
, tmp
);
2087 hdp_host_path_cntl
= RREG32(HDP_HOST_PATH_CNTL
);
2088 WREG32(HDP_HOST_PATH_CNTL
, hdp_host_path_cntl
);
2090 WREG32(PA_CL_ENHANCE
, CLIP_VTX_REORDER_ENA
| NUM_CLIP_SEQ(3));
2096 int evergreen_mc_init(struct radeon_device
*rdev
)
2099 int chansize
, numchan
;
2101 /* Get VRAM informations */
2102 rdev
->mc
.vram_is_ddr
= true;
2103 if ((rdev
->family
== CHIP_PALM
) ||
2104 (rdev
->family
== CHIP_SUMO
) ||
2105 (rdev
->family
== CHIP_SUMO2
))
2106 tmp
= RREG32(FUS_MC_ARB_RAMCFG
);
2108 tmp
= RREG32(MC_ARB_RAMCFG
);
2109 if (tmp
& CHANSIZE_OVERRIDE
) {
2111 } else if (tmp
& CHANSIZE_MASK
) {
2116 tmp
= RREG32(MC_SHARED_CHMAP
);
2117 switch ((tmp
& NOOFCHAN_MASK
) >> NOOFCHAN_SHIFT
) {
2132 rdev
->mc
.vram_width
= numchan
* chansize
;
2133 /* Could aper size report 0 ? */
2134 rdev
->mc
.aper_base
= pci_resource_start(rdev
->pdev
, 0);
2135 rdev
->mc
.aper_size
= pci_resource_len(rdev
->pdev
, 0);
2136 /* Setup GPU memory space */
2137 if ((rdev
->family
== CHIP_PALM
) ||
2138 (rdev
->family
== CHIP_SUMO
) ||
2139 (rdev
->family
== CHIP_SUMO2
)) {
2140 /* size in bytes on fusion */
2141 rdev
->mc
.mc_vram_size
= RREG32(CONFIG_MEMSIZE
);
2142 rdev
->mc
.real_vram_size
= RREG32(CONFIG_MEMSIZE
);
2144 /* size in MB on evergreen/cayman/tn */
2145 rdev
->mc
.mc_vram_size
= RREG32(CONFIG_MEMSIZE
) * 1024 * 1024;
2146 rdev
->mc
.real_vram_size
= RREG32(CONFIG_MEMSIZE
) * 1024 * 1024;
2148 rdev
->mc
.visible_vram_size
= rdev
->mc
.aper_size
;
2149 r700_vram_gtt_location(rdev
, &rdev
->mc
);
2150 radeon_update_bandwidth_info(rdev
);
2155 bool evergreen_gpu_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
2159 u32 grbm_status_se0
, grbm_status_se1
;
2161 srbm_status
= RREG32(SRBM_STATUS
);
2162 grbm_status
= RREG32(GRBM_STATUS
);
2163 grbm_status_se0
= RREG32(GRBM_STATUS_SE0
);
2164 grbm_status_se1
= RREG32(GRBM_STATUS_SE1
);
2165 if (!(grbm_status
& GUI_ACTIVE
)) {
2166 radeon_ring_lockup_update(ring
);
2169 /* force CP activities */
2170 radeon_ring_force_activity(rdev
, ring
);
2171 return radeon_ring_test_lockup(rdev
, ring
);
2174 static int evergreen_gpu_soft_reset(struct radeon_device
*rdev
)
2176 struct evergreen_mc_save save
;
2179 if (!(RREG32(GRBM_STATUS
) & GUI_ACTIVE
))
2182 dev_info(rdev
->dev
, "GPU softreset \n");
2183 dev_info(rdev
->dev
, " GRBM_STATUS=0x%08X\n",
2184 RREG32(GRBM_STATUS
));
2185 dev_info(rdev
->dev
, " GRBM_STATUS_SE0=0x%08X\n",
2186 RREG32(GRBM_STATUS_SE0
));
2187 dev_info(rdev
->dev
, " GRBM_STATUS_SE1=0x%08X\n",
2188 RREG32(GRBM_STATUS_SE1
));
2189 dev_info(rdev
->dev
, " SRBM_STATUS=0x%08X\n",
2190 RREG32(SRBM_STATUS
));
2191 evergreen_mc_stop(rdev
, &save
);
2192 if (evergreen_mc_wait_for_idle(rdev
)) {
2193 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
2195 /* Disable CP parsing/prefetching */
2196 WREG32(CP_ME_CNTL
, CP_ME_HALT
| CP_PFP_HALT
);
2198 /* reset all the gfx blocks */
2199 grbm_reset
= (SOFT_RESET_CP
|
2212 dev_info(rdev
->dev
, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset
);
2213 WREG32(GRBM_SOFT_RESET
, grbm_reset
);
2214 (void)RREG32(GRBM_SOFT_RESET
);
2216 WREG32(GRBM_SOFT_RESET
, 0);
2217 (void)RREG32(GRBM_SOFT_RESET
);
2218 /* Wait a little for things to settle down */
2220 dev_info(rdev
->dev
, " GRBM_STATUS=0x%08X\n",
2221 RREG32(GRBM_STATUS
));
2222 dev_info(rdev
->dev
, " GRBM_STATUS_SE0=0x%08X\n",
2223 RREG32(GRBM_STATUS_SE0
));
2224 dev_info(rdev
->dev
, " GRBM_STATUS_SE1=0x%08X\n",
2225 RREG32(GRBM_STATUS_SE1
));
2226 dev_info(rdev
->dev
, " SRBM_STATUS=0x%08X\n",
2227 RREG32(SRBM_STATUS
));
2228 evergreen_mc_resume(rdev
, &save
);
2232 int evergreen_asic_reset(struct radeon_device
*rdev
)
2234 return evergreen_gpu_soft_reset(rdev
);
2239 u32
evergreen_get_vblank_counter(struct radeon_device
*rdev
, int crtc
)
2243 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC0_REGISTER_OFFSET
);
2245 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
2247 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC2_REGISTER_OFFSET
);
2249 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
2251 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC4_REGISTER_OFFSET
);
2253 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
2259 void evergreen_disable_interrupt_state(struct radeon_device
*rdev
)
2263 if (rdev
->family
>= CHIP_CAYMAN
) {
2264 cayman_cp_int_cntl_setup(rdev
, 0,
2265 CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
);
2266 cayman_cp_int_cntl_setup(rdev
, 1, 0);
2267 cayman_cp_int_cntl_setup(rdev
, 2, 0);
2269 WREG32(CP_INT_CNTL
, CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
);
2270 WREG32(GRBM_INT_CNTL
, 0);
2271 WREG32(INT_MASK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
2272 WREG32(INT_MASK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
2273 if (rdev
->num_crtc
>= 4) {
2274 WREG32(INT_MASK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
2275 WREG32(INT_MASK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
2277 if (rdev
->num_crtc
>= 6) {
2278 WREG32(INT_MASK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
2279 WREG32(INT_MASK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
2282 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
2283 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
2284 if (rdev
->num_crtc
>= 4) {
2285 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
2286 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
2288 if (rdev
->num_crtc
>= 6) {
2289 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
2290 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
2293 /* only one DAC on DCE6 */
2294 if (!ASIC_IS_DCE6(rdev
))
2295 WREG32(DACA_AUTODETECT_INT_CONTROL
, 0);
2296 WREG32(DACB_AUTODETECT_INT_CONTROL
, 0);
2298 tmp
= RREG32(DC_HPD1_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2299 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
2300 tmp
= RREG32(DC_HPD2_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2301 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
2302 tmp
= RREG32(DC_HPD3_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2303 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
2304 tmp
= RREG32(DC_HPD4_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2305 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
2306 tmp
= RREG32(DC_HPD5_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2307 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
2308 tmp
= RREG32(DC_HPD6_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2309 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
2313 int evergreen_irq_set(struct radeon_device
*rdev
)
2315 u32 cp_int_cntl
= CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
;
2316 u32 cp_int_cntl1
= 0, cp_int_cntl2
= 0;
2317 u32 crtc1
= 0, crtc2
= 0, crtc3
= 0, crtc4
= 0, crtc5
= 0, crtc6
= 0;
2318 u32 hpd1
, hpd2
, hpd3
, hpd4
, hpd5
, hpd6
;
2319 u32 grbm_int_cntl
= 0;
2320 u32 grph1
= 0, grph2
= 0, grph3
= 0, grph4
= 0, grph5
= 0, grph6
= 0;
2321 u32 afmt1
= 0, afmt2
= 0, afmt3
= 0, afmt4
= 0, afmt5
= 0, afmt6
= 0;
2323 if (!rdev
->irq
.installed
) {
2324 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2327 /* don't enable anything if the ih is disabled */
2328 if (!rdev
->ih
.enabled
) {
2329 r600_disable_interrupts(rdev
);
2330 /* force the active interrupt state to all disabled */
2331 evergreen_disable_interrupt_state(rdev
);
2335 hpd1
= RREG32(DC_HPD1_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2336 hpd2
= RREG32(DC_HPD2_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2337 hpd3
= RREG32(DC_HPD3_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2338 hpd4
= RREG32(DC_HPD4_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2339 hpd5
= RREG32(DC_HPD5_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2340 hpd6
= RREG32(DC_HPD6_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2342 afmt1
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
2343 afmt2
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
2344 afmt3
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
2345 afmt4
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
2346 afmt5
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
2347 afmt6
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
2349 if (rdev
->family
>= CHIP_CAYMAN
) {
2350 /* enable CP interrupts on all rings */
2351 if (rdev
->irq
.sw_int
[RADEON_RING_TYPE_GFX_INDEX
]) {
2352 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2353 cp_int_cntl
|= TIME_STAMP_INT_ENABLE
;
2355 if (rdev
->irq
.sw_int
[CAYMAN_RING_TYPE_CP1_INDEX
]) {
2356 DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
2357 cp_int_cntl1
|= TIME_STAMP_INT_ENABLE
;
2359 if (rdev
->irq
.sw_int
[CAYMAN_RING_TYPE_CP2_INDEX
]) {
2360 DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
2361 cp_int_cntl2
|= TIME_STAMP_INT_ENABLE
;
2364 if (rdev
->irq
.sw_int
[RADEON_RING_TYPE_GFX_INDEX
]) {
2365 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2366 cp_int_cntl
|= RB_INT_ENABLE
;
2367 cp_int_cntl
|= TIME_STAMP_INT_ENABLE
;
2371 if (rdev
->irq
.crtc_vblank_int
[0] ||
2372 rdev
->irq
.pflip
[0]) {
2373 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2374 crtc1
|= VBLANK_INT_MASK
;
2376 if (rdev
->irq
.crtc_vblank_int
[1] ||
2377 rdev
->irq
.pflip
[1]) {
2378 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2379 crtc2
|= VBLANK_INT_MASK
;
2381 if (rdev
->irq
.crtc_vblank_int
[2] ||
2382 rdev
->irq
.pflip
[2]) {
2383 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2384 crtc3
|= VBLANK_INT_MASK
;
2386 if (rdev
->irq
.crtc_vblank_int
[3] ||
2387 rdev
->irq
.pflip
[3]) {
2388 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2389 crtc4
|= VBLANK_INT_MASK
;
2391 if (rdev
->irq
.crtc_vblank_int
[4] ||
2392 rdev
->irq
.pflip
[4]) {
2393 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2394 crtc5
|= VBLANK_INT_MASK
;
2396 if (rdev
->irq
.crtc_vblank_int
[5] ||
2397 rdev
->irq
.pflip
[5]) {
2398 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2399 crtc6
|= VBLANK_INT_MASK
;
2401 if (rdev
->irq
.hpd
[0]) {
2402 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2403 hpd1
|= DC_HPDx_INT_EN
;
2405 if (rdev
->irq
.hpd
[1]) {
2406 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2407 hpd2
|= DC_HPDx_INT_EN
;
2409 if (rdev
->irq
.hpd
[2]) {
2410 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2411 hpd3
|= DC_HPDx_INT_EN
;
2413 if (rdev
->irq
.hpd
[3]) {
2414 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2415 hpd4
|= DC_HPDx_INT_EN
;
2417 if (rdev
->irq
.hpd
[4]) {
2418 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2419 hpd5
|= DC_HPDx_INT_EN
;
2421 if (rdev
->irq
.hpd
[5]) {
2422 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2423 hpd6
|= DC_HPDx_INT_EN
;
2425 if (rdev
->irq
.afmt
[0]) {
2426 DRM_DEBUG("evergreen_irq_set: hdmi 0\n");
2427 afmt1
|= AFMT_AZ_FORMAT_WTRIG_MASK
;
2429 if (rdev
->irq
.afmt
[1]) {
2430 DRM_DEBUG("evergreen_irq_set: hdmi 1\n");
2431 afmt2
|= AFMT_AZ_FORMAT_WTRIG_MASK
;
2433 if (rdev
->irq
.afmt
[2]) {
2434 DRM_DEBUG("evergreen_irq_set: hdmi 2\n");
2435 afmt3
|= AFMT_AZ_FORMAT_WTRIG_MASK
;
2437 if (rdev
->irq
.afmt
[3]) {
2438 DRM_DEBUG("evergreen_irq_set: hdmi 3\n");
2439 afmt4
|= AFMT_AZ_FORMAT_WTRIG_MASK
;
2441 if (rdev
->irq
.afmt
[4]) {
2442 DRM_DEBUG("evergreen_irq_set: hdmi 4\n");
2443 afmt5
|= AFMT_AZ_FORMAT_WTRIG_MASK
;
2445 if (rdev
->irq
.afmt
[5]) {
2446 DRM_DEBUG("evergreen_irq_set: hdmi 5\n");
2447 afmt6
|= AFMT_AZ_FORMAT_WTRIG_MASK
;
2449 if (rdev
->irq
.gui_idle
) {
2450 DRM_DEBUG("gui idle\n");
2451 grbm_int_cntl
|= GUI_IDLE_INT_ENABLE
;
2454 if (rdev
->family
>= CHIP_CAYMAN
) {
2455 cayman_cp_int_cntl_setup(rdev
, 0, cp_int_cntl
);
2456 cayman_cp_int_cntl_setup(rdev
, 1, cp_int_cntl1
);
2457 cayman_cp_int_cntl_setup(rdev
, 2, cp_int_cntl2
);
2459 WREG32(CP_INT_CNTL
, cp_int_cntl
);
2460 WREG32(GRBM_INT_CNTL
, grbm_int_cntl
);
2462 WREG32(INT_MASK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, crtc1
);
2463 WREG32(INT_MASK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, crtc2
);
2464 if (rdev
->num_crtc
>= 4) {
2465 WREG32(INT_MASK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, crtc3
);
2466 WREG32(INT_MASK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, crtc4
);
2468 if (rdev
->num_crtc
>= 6) {
2469 WREG32(INT_MASK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, crtc5
);
2470 WREG32(INT_MASK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, crtc6
);
2473 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, grph1
);
2474 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, grph2
);
2475 if (rdev
->num_crtc
>= 4) {
2476 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, grph3
);
2477 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, grph4
);
2479 if (rdev
->num_crtc
>= 6) {
2480 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, grph5
);
2481 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, grph6
);
2484 WREG32(DC_HPD1_INT_CONTROL
, hpd1
);
2485 WREG32(DC_HPD2_INT_CONTROL
, hpd2
);
2486 WREG32(DC_HPD3_INT_CONTROL
, hpd3
);
2487 WREG32(DC_HPD4_INT_CONTROL
, hpd4
);
2488 WREG32(DC_HPD5_INT_CONTROL
, hpd5
);
2489 WREG32(DC_HPD6_INT_CONTROL
, hpd6
);
2491 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, afmt1
);
2492 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, afmt2
);
2493 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, afmt3
);
2494 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, afmt4
);
2495 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, afmt5
);
2496 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, afmt6
);
2501 static void evergreen_irq_ack(struct radeon_device
*rdev
)
2505 rdev
->irq
.stat_regs
.evergreen
.disp_int
= RREG32(DISP_INTERRUPT_STATUS
);
2506 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE
);
2507 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE2
);
2508 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE3
);
2509 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE4
);
2510 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE5
);
2511 rdev
->irq
.stat_regs
.evergreen
.d1grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
);
2512 rdev
->irq
.stat_regs
.evergreen
.d2grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
2513 if (rdev
->num_crtc
>= 4) {
2514 rdev
->irq
.stat_regs
.evergreen
.d3grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
);
2515 rdev
->irq
.stat_regs
.evergreen
.d4grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
2517 if (rdev
->num_crtc
>= 6) {
2518 rdev
->irq
.stat_regs
.evergreen
.d5grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
);
2519 rdev
->irq
.stat_regs
.evergreen
.d6grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
2522 rdev
->irq
.stat_regs
.evergreen
.afmt_status1
= RREG32(AFMT_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
);
2523 rdev
->irq
.stat_regs
.evergreen
.afmt_status2
= RREG32(AFMT_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
2524 rdev
->irq
.stat_regs
.evergreen
.afmt_status3
= RREG32(AFMT_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
);
2525 rdev
->irq
.stat_regs
.evergreen
.afmt_status4
= RREG32(AFMT_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
2526 rdev
->irq
.stat_regs
.evergreen
.afmt_status5
= RREG32(AFMT_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
);
2527 rdev
->irq
.stat_regs
.evergreen
.afmt_status6
= RREG32(AFMT_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
2529 if (rdev
->irq
.stat_regs
.evergreen
.d1grph_int
& GRPH_PFLIP_INT_OCCURRED
)
2530 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
2531 if (rdev
->irq
.stat_regs
.evergreen
.d2grph_int
& GRPH_PFLIP_INT_OCCURRED
)
2532 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
2533 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& LB_D1_VBLANK_INTERRUPT
)
2534 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, VBLANK_ACK
);
2535 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& LB_D1_VLINE_INTERRUPT
)
2536 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, VLINE_ACK
);
2537 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& LB_D2_VBLANK_INTERRUPT
)
2538 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, VBLANK_ACK
);
2539 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& LB_D2_VLINE_INTERRUPT
)
2540 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, VLINE_ACK
);
2542 if (rdev
->num_crtc
>= 4) {
2543 if (rdev
->irq
.stat_regs
.evergreen
.d3grph_int
& GRPH_PFLIP_INT_OCCURRED
)
2544 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
2545 if (rdev
->irq
.stat_regs
.evergreen
.d4grph_int
& GRPH_PFLIP_INT_OCCURRED
)
2546 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
2547 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& LB_D3_VBLANK_INTERRUPT
)
2548 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, VBLANK_ACK
);
2549 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& LB_D3_VLINE_INTERRUPT
)
2550 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, VLINE_ACK
);
2551 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& LB_D4_VBLANK_INTERRUPT
)
2552 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, VBLANK_ACK
);
2553 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& LB_D4_VLINE_INTERRUPT
)
2554 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, VLINE_ACK
);
2557 if (rdev
->num_crtc
>= 6) {
2558 if (rdev
->irq
.stat_regs
.evergreen
.d5grph_int
& GRPH_PFLIP_INT_OCCURRED
)
2559 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
2560 if (rdev
->irq
.stat_regs
.evergreen
.d6grph_int
& GRPH_PFLIP_INT_OCCURRED
)
2561 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
2562 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& LB_D5_VBLANK_INTERRUPT
)
2563 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, VBLANK_ACK
);
2564 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& LB_D5_VLINE_INTERRUPT
)
2565 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, VLINE_ACK
);
2566 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& LB_D6_VBLANK_INTERRUPT
)
2567 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, VBLANK_ACK
);
2568 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& LB_D6_VLINE_INTERRUPT
)
2569 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, VLINE_ACK
);
2572 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& DC_HPD1_INTERRUPT
) {
2573 tmp
= RREG32(DC_HPD1_INT_CONTROL
);
2574 tmp
|= DC_HPDx_INT_ACK
;
2575 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
2577 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& DC_HPD2_INTERRUPT
) {
2578 tmp
= RREG32(DC_HPD2_INT_CONTROL
);
2579 tmp
|= DC_HPDx_INT_ACK
;
2580 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
2582 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& DC_HPD3_INTERRUPT
) {
2583 tmp
= RREG32(DC_HPD3_INT_CONTROL
);
2584 tmp
|= DC_HPDx_INT_ACK
;
2585 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
2587 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& DC_HPD4_INTERRUPT
) {
2588 tmp
= RREG32(DC_HPD4_INT_CONTROL
);
2589 tmp
|= DC_HPDx_INT_ACK
;
2590 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
2592 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& DC_HPD5_INTERRUPT
) {
2593 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
2594 tmp
|= DC_HPDx_INT_ACK
;
2595 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
2597 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& DC_HPD6_INTERRUPT
) {
2598 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
2599 tmp
|= DC_HPDx_INT_ACK
;
2600 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
2602 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status1
& AFMT_AZ_FORMAT_WTRIG
) {
2603 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
);
2604 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
2605 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, tmp
);
2607 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status2
& AFMT_AZ_FORMAT_WTRIG
) {
2608 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
2609 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
2610 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, tmp
);
2612 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status3
& AFMT_AZ_FORMAT_WTRIG
) {
2613 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
);
2614 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
2615 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, tmp
);
2617 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status4
& AFMT_AZ_FORMAT_WTRIG
) {
2618 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
2619 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
2620 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, tmp
);
2622 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status5
& AFMT_AZ_FORMAT_WTRIG
) {
2623 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
);
2624 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
2625 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, tmp
);
2627 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status6
& AFMT_AZ_FORMAT_WTRIG
) {
2628 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
2629 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
2630 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, tmp
);
2634 void evergreen_irq_disable(struct radeon_device
*rdev
)
2636 r600_disable_interrupts(rdev
);
2637 /* Wait and acknowledge irq */
2639 evergreen_irq_ack(rdev
);
2640 evergreen_disable_interrupt_state(rdev
);
2643 void evergreen_irq_suspend(struct radeon_device
*rdev
)
2645 evergreen_irq_disable(rdev
);
2646 r600_rlc_stop(rdev
);
2649 static u32
evergreen_get_ih_wptr(struct radeon_device
*rdev
)
2653 if (rdev
->wb
.enabled
)
2654 wptr
= le32_to_cpu(rdev
->wb
.wb
[R600_WB_IH_WPTR_OFFSET
/4]);
2656 wptr
= RREG32(IH_RB_WPTR
);
2658 if (wptr
& RB_OVERFLOW
) {
2659 /* When a ring buffer overflow happen start parsing interrupt
2660 * from the last not overwritten vector (wptr + 16). Hopefully
2661 * this should allow us to catchup.
2663 dev_warn(rdev
->dev
, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2664 wptr
, rdev
->ih
.rptr
, (wptr
+ 16) + rdev
->ih
.ptr_mask
);
2665 rdev
->ih
.rptr
= (wptr
+ 16) & rdev
->ih
.ptr_mask
;
2666 tmp
= RREG32(IH_RB_CNTL
);
2667 tmp
|= IH_WPTR_OVERFLOW_CLEAR
;
2668 WREG32(IH_RB_CNTL
, tmp
);
2670 return (wptr
& rdev
->ih
.ptr_mask
);
2673 int evergreen_irq_process(struct radeon_device
*rdev
)
2677 u32 src_id
, src_data
;
2679 unsigned long flags
;
2680 bool queue_hotplug
= false;
2681 bool queue_hdmi
= false;
2683 if (!rdev
->ih
.enabled
|| rdev
->shutdown
)
2686 wptr
= evergreen_get_ih_wptr(rdev
);
2687 rptr
= rdev
->ih
.rptr
;
2688 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr
, wptr
);
2690 spin_lock_irqsave(&rdev
->ih
.lock
, flags
);
2692 spin_unlock_irqrestore(&rdev
->ih
.lock
, flags
);
2696 /* Order reading of wptr vs. reading of IH ring data */
2699 /* display interrupts */
2700 evergreen_irq_ack(rdev
);
2702 rdev
->ih
.wptr
= wptr
;
2703 while (rptr
!= wptr
) {
2704 /* wptr/rptr are in bytes! */
2705 ring_index
= rptr
/ 4;
2706 src_id
= le32_to_cpu(rdev
->ih
.ring
[ring_index
]) & 0xff;
2707 src_data
= le32_to_cpu(rdev
->ih
.ring
[ring_index
+ 1]) & 0xfffffff;
2710 case 1: /* D1 vblank/vline */
2712 case 0: /* D1 vblank */
2713 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& LB_D1_VBLANK_INTERRUPT
) {
2714 if (rdev
->irq
.crtc_vblank_int
[0]) {
2715 drm_handle_vblank(rdev
->ddev
, 0);
2716 rdev
->pm
.vblank_sync
= true;
2717 wake_up(&rdev
->irq
.vblank_queue
);
2719 if (rdev
->irq
.pflip
[0])
2720 radeon_crtc_handle_flip(rdev
, 0);
2721 rdev
->irq
.stat_regs
.evergreen
.disp_int
&= ~LB_D1_VBLANK_INTERRUPT
;
2722 DRM_DEBUG("IH: D1 vblank\n");
2725 case 1: /* D1 vline */
2726 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& LB_D1_VLINE_INTERRUPT
) {
2727 rdev
->irq
.stat_regs
.evergreen
.disp_int
&= ~LB_D1_VLINE_INTERRUPT
;
2728 DRM_DEBUG("IH: D1 vline\n");
2732 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2736 case 2: /* D2 vblank/vline */
2738 case 0: /* D2 vblank */
2739 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& LB_D2_VBLANK_INTERRUPT
) {
2740 if (rdev
->irq
.crtc_vblank_int
[1]) {
2741 drm_handle_vblank(rdev
->ddev
, 1);
2742 rdev
->pm
.vblank_sync
= true;
2743 wake_up(&rdev
->irq
.vblank_queue
);
2745 if (rdev
->irq
.pflip
[1])
2746 radeon_crtc_handle_flip(rdev
, 1);
2747 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
&= ~LB_D2_VBLANK_INTERRUPT
;
2748 DRM_DEBUG("IH: D2 vblank\n");
2751 case 1: /* D2 vline */
2752 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& LB_D2_VLINE_INTERRUPT
) {
2753 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
&= ~LB_D2_VLINE_INTERRUPT
;
2754 DRM_DEBUG("IH: D2 vline\n");
2758 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2762 case 3: /* D3 vblank/vline */
2764 case 0: /* D3 vblank */
2765 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& LB_D3_VBLANK_INTERRUPT
) {
2766 if (rdev
->irq
.crtc_vblank_int
[2]) {
2767 drm_handle_vblank(rdev
->ddev
, 2);
2768 rdev
->pm
.vblank_sync
= true;
2769 wake_up(&rdev
->irq
.vblank_queue
);
2771 if (rdev
->irq
.pflip
[2])
2772 radeon_crtc_handle_flip(rdev
, 2);
2773 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
&= ~LB_D3_VBLANK_INTERRUPT
;
2774 DRM_DEBUG("IH: D3 vblank\n");
2777 case 1: /* D3 vline */
2778 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& LB_D3_VLINE_INTERRUPT
) {
2779 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
&= ~LB_D3_VLINE_INTERRUPT
;
2780 DRM_DEBUG("IH: D3 vline\n");
2784 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2788 case 4: /* D4 vblank/vline */
2790 case 0: /* D4 vblank */
2791 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& LB_D4_VBLANK_INTERRUPT
) {
2792 if (rdev
->irq
.crtc_vblank_int
[3]) {
2793 drm_handle_vblank(rdev
->ddev
, 3);
2794 rdev
->pm
.vblank_sync
= true;
2795 wake_up(&rdev
->irq
.vblank_queue
);
2797 if (rdev
->irq
.pflip
[3])
2798 radeon_crtc_handle_flip(rdev
, 3);
2799 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
&= ~LB_D4_VBLANK_INTERRUPT
;
2800 DRM_DEBUG("IH: D4 vblank\n");
2803 case 1: /* D4 vline */
2804 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& LB_D4_VLINE_INTERRUPT
) {
2805 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
&= ~LB_D4_VLINE_INTERRUPT
;
2806 DRM_DEBUG("IH: D4 vline\n");
2810 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2814 case 5: /* D5 vblank/vline */
2816 case 0: /* D5 vblank */
2817 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& LB_D5_VBLANK_INTERRUPT
) {
2818 if (rdev
->irq
.crtc_vblank_int
[4]) {
2819 drm_handle_vblank(rdev
->ddev
, 4);
2820 rdev
->pm
.vblank_sync
= true;
2821 wake_up(&rdev
->irq
.vblank_queue
);
2823 if (rdev
->irq
.pflip
[4])
2824 radeon_crtc_handle_flip(rdev
, 4);
2825 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
&= ~LB_D5_VBLANK_INTERRUPT
;
2826 DRM_DEBUG("IH: D5 vblank\n");
2829 case 1: /* D5 vline */
2830 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& LB_D5_VLINE_INTERRUPT
) {
2831 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
&= ~LB_D5_VLINE_INTERRUPT
;
2832 DRM_DEBUG("IH: D5 vline\n");
2836 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2840 case 6: /* D6 vblank/vline */
2842 case 0: /* D6 vblank */
2843 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& LB_D6_VBLANK_INTERRUPT
) {
2844 if (rdev
->irq
.crtc_vblank_int
[5]) {
2845 drm_handle_vblank(rdev
->ddev
, 5);
2846 rdev
->pm
.vblank_sync
= true;
2847 wake_up(&rdev
->irq
.vblank_queue
);
2849 if (rdev
->irq
.pflip
[5])
2850 radeon_crtc_handle_flip(rdev
, 5);
2851 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
&= ~LB_D6_VBLANK_INTERRUPT
;
2852 DRM_DEBUG("IH: D6 vblank\n");
2855 case 1: /* D6 vline */
2856 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& LB_D6_VLINE_INTERRUPT
) {
2857 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
&= ~LB_D6_VLINE_INTERRUPT
;
2858 DRM_DEBUG("IH: D6 vline\n");
2862 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2866 case 42: /* HPD hotplug */
2869 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& DC_HPD1_INTERRUPT
) {
2870 rdev
->irq
.stat_regs
.evergreen
.disp_int
&= ~DC_HPD1_INTERRUPT
;
2871 queue_hotplug
= true;
2872 DRM_DEBUG("IH: HPD1\n");
2876 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& DC_HPD2_INTERRUPT
) {
2877 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
&= ~DC_HPD2_INTERRUPT
;
2878 queue_hotplug
= true;
2879 DRM_DEBUG("IH: HPD2\n");
2883 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& DC_HPD3_INTERRUPT
) {
2884 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
&= ~DC_HPD3_INTERRUPT
;
2885 queue_hotplug
= true;
2886 DRM_DEBUG("IH: HPD3\n");
2890 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& DC_HPD4_INTERRUPT
) {
2891 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
&= ~DC_HPD4_INTERRUPT
;
2892 queue_hotplug
= true;
2893 DRM_DEBUG("IH: HPD4\n");
2897 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& DC_HPD5_INTERRUPT
) {
2898 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
&= ~DC_HPD5_INTERRUPT
;
2899 queue_hotplug
= true;
2900 DRM_DEBUG("IH: HPD5\n");
2904 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& DC_HPD6_INTERRUPT
) {
2905 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
&= ~DC_HPD6_INTERRUPT
;
2906 queue_hotplug
= true;
2907 DRM_DEBUG("IH: HPD6\n");
2911 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2918 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status1
& AFMT_AZ_FORMAT_WTRIG
) {
2919 rdev
->irq
.stat_regs
.evergreen
.afmt_status1
&= ~AFMT_AZ_FORMAT_WTRIG
;
2921 DRM_DEBUG("IH: HDMI0\n");
2925 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status2
& AFMT_AZ_FORMAT_WTRIG
) {
2926 rdev
->irq
.stat_regs
.evergreen
.afmt_status2
&= ~AFMT_AZ_FORMAT_WTRIG
;
2928 DRM_DEBUG("IH: HDMI1\n");
2932 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status3
& AFMT_AZ_FORMAT_WTRIG
) {
2933 rdev
->irq
.stat_regs
.evergreen
.afmt_status3
&= ~AFMT_AZ_FORMAT_WTRIG
;
2935 DRM_DEBUG("IH: HDMI2\n");
2939 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status4
& AFMT_AZ_FORMAT_WTRIG
) {
2940 rdev
->irq
.stat_regs
.evergreen
.afmt_status4
&= ~AFMT_AZ_FORMAT_WTRIG
;
2942 DRM_DEBUG("IH: HDMI3\n");
2946 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status5
& AFMT_AZ_FORMAT_WTRIG
) {
2947 rdev
->irq
.stat_regs
.evergreen
.afmt_status5
&= ~AFMT_AZ_FORMAT_WTRIG
;
2949 DRM_DEBUG("IH: HDMI4\n");
2953 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status6
& AFMT_AZ_FORMAT_WTRIG
) {
2954 rdev
->irq
.stat_regs
.evergreen
.afmt_status6
&= ~AFMT_AZ_FORMAT_WTRIG
;
2956 DRM_DEBUG("IH: HDMI5\n");
2960 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2964 case 176: /* CP_INT in ring buffer */
2965 case 177: /* CP_INT in IB1 */
2966 case 178: /* CP_INT in IB2 */
2967 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data
);
2968 radeon_fence_process(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
2970 case 181: /* CP EOP event */
2971 DRM_DEBUG("IH: CP EOP\n");
2972 if (rdev
->family
>= CHIP_CAYMAN
) {
2975 radeon_fence_process(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
2978 radeon_fence_process(rdev
, CAYMAN_RING_TYPE_CP1_INDEX
);
2981 radeon_fence_process(rdev
, CAYMAN_RING_TYPE_CP2_INDEX
);
2985 radeon_fence_process(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
2987 case 233: /* GUI IDLE */
2988 DRM_DEBUG("IH: GUI idle\n");
2989 rdev
->pm
.gui_idle
= true;
2990 wake_up(&rdev
->irq
.idle_queue
);
2993 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2997 /* wptr/rptr are in bytes! */
2999 rptr
&= rdev
->ih
.ptr_mask
;
3001 /* make sure wptr hasn't changed while processing */
3002 wptr
= evergreen_get_ih_wptr(rdev
);
3003 if (wptr
!= rdev
->ih
.wptr
)
3006 schedule_work(&rdev
->hotplug_work
);
3008 schedule_work(&rdev
->audio_work
);
3009 rdev
->ih
.rptr
= rptr
;
3010 WREG32(IH_RB_RPTR
, rdev
->ih
.rptr
);
3011 spin_unlock_irqrestore(&rdev
->ih
.lock
, flags
);
3015 static int evergreen_startup(struct radeon_device
*rdev
)
3017 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
3020 /* enable pcie gen2 link */
3021 evergreen_pcie_gen2_enable(rdev
);
3023 if (ASIC_IS_DCE5(rdev
)) {
3024 if (!rdev
->me_fw
|| !rdev
->pfp_fw
|| !rdev
->rlc_fw
|| !rdev
->mc_fw
) {
3025 r
= ni_init_microcode(rdev
);
3027 DRM_ERROR("Failed to load firmware!\n");
3031 r
= ni_mc_load_microcode(rdev
);
3033 DRM_ERROR("Failed to load MC firmware!\n");
3037 if (!rdev
->me_fw
|| !rdev
->pfp_fw
|| !rdev
->rlc_fw
) {
3038 r
= r600_init_microcode(rdev
);
3040 DRM_ERROR("Failed to load firmware!\n");
3046 r
= r600_vram_scratch_init(rdev
);
3050 evergreen_mc_program(rdev
);
3051 if (rdev
->flags
& RADEON_IS_AGP
) {
3052 evergreen_agp_enable(rdev
);
3054 r
= evergreen_pcie_gart_enable(rdev
);
3058 evergreen_gpu_init(rdev
);
3060 r
= evergreen_blit_init(rdev
);
3062 r600_blit_fini(rdev
);
3063 rdev
->asic
->copy
.copy
= NULL
;
3064 dev_warn(rdev
->dev
, "failed blitter (%d) falling back to memcpy\n", r
);
3067 /* allocate wb buffer */
3068 r
= radeon_wb_init(rdev
);
3072 r
= radeon_fence_driver_start_ring(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
3074 dev_err(rdev
->dev
, "failed initializing CP fences (%d).\n", r
);
3079 r
= r600_irq_init(rdev
);
3081 DRM_ERROR("radeon: IH init failed (%d).\n", r
);
3082 radeon_irq_kms_fini(rdev
);
3085 evergreen_irq_set(rdev
);
3087 r
= radeon_ring_init(rdev
, ring
, ring
->ring_size
, RADEON_WB_CP_RPTR_OFFSET
,
3088 R600_CP_RB_RPTR
, R600_CP_RB_WPTR
,
3089 0, 0xfffff, RADEON_CP_PACKET2
);
3092 r
= evergreen_cp_load_microcode(rdev
);
3095 r
= evergreen_cp_resume(rdev
);
3099 r
= radeon_ib_pool_start(rdev
);
3103 r
= radeon_ib_ring_tests(rdev
);
3107 r
= r600_audio_init(rdev
);
3109 DRM_ERROR("radeon: audio init failed\n");
3116 int evergreen_resume(struct radeon_device
*rdev
)
3120 /* reset the asic, the gfx blocks are often in a bad state
3121 * after the driver is unloaded or after a resume
3123 if (radeon_asic_reset(rdev
))
3124 dev_warn(rdev
->dev
, "GPU reset failed !\n");
3125 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3126 * posting will perform necessary task to bring back GPU into good
3130 atom_asic_init(rdev
->mode_info
.atom_context
);
3132 rdev
->accel_working
= true;
3133 r
= evergreen_startup(rdev
);
3135 DRM_ERROR("evergreen startup failed on resume\n");
3136 rdev
->accel_working
= false;
3144 int evergreen_suspend(struct radeon_device
*rdev
)
3146 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
3148 r600_audio_fini(rdev
);
3149 /* FIXME: we should wait for ring to be empty */
3150 radeon_ib_pool_suspend(rdev
);
3151 r600_blit_suspend(rdev
);
3153 ring
->ready
= false;
3154 evergreen_irq_suspend(rdev
);
3155 radeon_wb_disable(rdev
);
3156 evergreen_pcie_gart_disable(rdev
);
3161 /* Plan is to move initialization in that function and use
3162 * helper function so that radeon_device_init pretty much
3163 * do nothing more than calling asic specific function. This
3164 * should also allow to remove a bunch of callback function
3167 int evergreen_init(struct radeon_device
*rdev
)
3172 if (!radeon_get_bios(rdev
)) {
3173 if (ASIC_IS_AVIVO(rdev
))
3176 /* Must be an ATOMBIOS */
3177 if (!rdev
->is_atom_bios
) {
3178 dev_err(rdev
->dev
, "Expecting atombios for evergreen GPU\n");
3181 r
= radeon_atombios_init(rdev
);
3184 /* reset the asic, the gfx blocks are often in a bad state
3185 * after the driver is unloaded or after a resume
3187 if (radeon_asic_reset(rdev
))
3188 dev_warn(rdev
->dev
, "GPU reset failed !\n");
3189 /* Post card if necessary */
3190 if (!radeon_card_posted(rdev
)) {
3192 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
3195 DRM_INFO("GPU not posted. posting now...\n");
3196 atom_asic_init(rdev
->mode_info
.atom_context
);
3198 /* Initialize scratch registers */
3199 r600_scratch_init(rdev
);
3200 /* Initialize surface registers */
3201 radeon_surface_init(rdev
);
3202 /* Initialize clocks */
3203 radeon_get_clock_info(rdev
->ddev
);
3205 r
= radeon_fence_driver_init(rdev
);
3208 /* initialize AGP */
3209 if (rdev
->flags
& RADEON_IS_AGP
) {
3210 r
= radeon_agp_init(rdev
);
3212 radeon_agp_disable(rdev
);
3214 /* initialize memory controller */
3215 r
= evergreen_mc_init(rdev
);
3218 /* Memory manager */
3219 r
= radeon_bo_init(rdev
);
3223 r
= radeon_irq_kms_init(rdev
);
3227 rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
].ring_obj
= NULL
;
3228 r600_ring_init(rdev
, &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
], 1024 * 1024);
3230 rdev
->ih
.ring_obj
= NULL
;
3231 r600_ih_ring_init(rdev
, 64 * 1024);
3233 r
= r600_pcie_gart_init(rdev
);
3237 r
= radeon_ib_pool_init(rdev
);
3238 rdev
->accel_working
= true;
3240 dev_err(rdev
->dev
, "IB initialization failed (%d).\n", r
);
3241 rdev
->accel_working
= false;
3244 r
= evergreen_startup(rdev
);
3246 dev_err(rdev
->dev
, "disabling GPU acceleration\n");
3248 r600_irq_fini(rdev
);
3249 radeon_wb_fini(rdev
);
3251 radeon_irq_kms_fini(rdev
);
3252 evergreen_pcie_gart_fini(rdev
);
3253 rdev
->accel_working
= false;
3256 /* Don't start up if the MC ucode is missing on BTC parts.
3257 * The default clocks and voltages before the MC ucode
3258 * is loaded are not suffient for advanced operations.
3260 if (ASIC_IS_DCE5(rdev
)) {
3261 if (!rdev
->mc_fw
&& !(rdev
->flags
& RADEON_IS_IGP
)) {
3262 DRM_ERROR("radeon: MC ucode required for NI+.\n");
3270 void evergreen_fini(struct radeon_device
*rdev
)
3272 r600_audio_fini(rdev
);
3273 r600_blit_fini(rdev
);
3275 r600_irq_fini(rdev
);
3276 radeon_wb_fini(rdev
);
3278 radeon_irq_kms_fini(rdev
);
3279 evergreen_pcie_gart_fini(rdev
);
3280 r600_vram_scratch_fini(rdev
);
3281 radeon_gem_fini(rdev
);
3282 radeon_fence_driver_fini(rdev
);
3283 radeon_agp_fini(rdev
);
3284 radeon_bo_fini(rdev
);
3285 radeon_atombios_fini(rdev
);
3290 void evergreen_pcie_gen2_enable(struct radeon_device
*rdev
)
3292 u32 link_width_cntl
, speed_cntl
;
3294 if (radeon_pcie_gen2
== 0)
3297 if (rdev
->flags
& RADEON_IS_IGP
)
3300 if (!(rdev
->flags
& RADEON_IS_PCIE
))
3303 /* x2 cards have a special sequence */
3304 if (ASIC_IS_X2(rdev
))
3307 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3308 if ((speed_cntl
& LC_OTHER_SIDE_EVER_SENT_GEN2
) ||
3309 (speed_cntl
& LC_OTHER_SIDE_SUPPORTS_GEN2
)) {
3311 link_width_cntl
= RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
);
3312 link_width_cntl
&= ~LC_UPCONFIGURE_DIS
;
3313 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
3315 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3316 speed_cntl
&= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN
;
3317 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3319 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3320 speed_cntl
|= LC_CLR_FAILED_SPD_CHANGE_CNT
;
3321 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3323 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3324 speed_cntl
&= ~LC_CLR_FAILED_SPD_CHANGE_CNT
;
3325 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3327 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3328 speed_cntl
|= LC_GEN2_EN_STRAP
;
3329 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3332 link_width_cntl
= RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
);
3333 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3335 link_width_cntl
|= LC_UPCONFIGURE_DIS
;
3337 link_width_cntl
&= ~LC_UPCONFIGURE_DIS
;
3338 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);