2 * Copyright 2010 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
29 #include "radeon_asic.h"
30 #include "radeon_drm.h"
31 #include "evergreend.h"
34 #include "evergreen_reg.h"
35 #include "evergreen_blit_shaders.h"
37 #define EVERGREEN_PFP_UCODE_SIZE 1120
38 #define EVERGREEN_PM4_UCODE_SIZE 1376
40 static void evergreen_gpu_init(struct radeon_device
*rdev
);
41 void evergreen_fini(struct radeon_device
*rdev
);
42 static void evergreen_pcie_gen2_enable(struct radeon_device
*rdev
);
44 void evergreen_pre_page_flip(struct radeon_device
*rdev
, int crtc
)
46 /* enable the pflip int */
47 radeon_irq_kms_pflip_irq_get(rdev
, crtc
);
50 void evergreen_post_page_flip(struct radeon_device
*rdev
, int crtc
)
52 /* disable the pflip int */
53 radeon_irq_kms_pflip_irq_put(rdev
, crtc
);
56 u32
evergreen_page_flip(struct radeon_device
*rdev
, int crtc_id
, u64 crtc_base
)
58 struct radeon_crtc
*radeon_crtc
= rdev
->mode_info
.crtcs
[crtc_id
];
59 u32 tmp
= RREG32(EVERGREEN_GRPH_UPDATE
+ radeon_crtc
->crtc_offset
);
61 /* Lock the graphics update lock */
62 tmp
|= EVERGREEN_GRPH_UPDATE_LOCK
;
63 WREG32(EVERGREEN_GRPH_UPDATE
+ radeon_crtc
->crtc_offset
, tmp
);
65 /* update the scanout addresses */
66 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ radeon_crtc
->crtc_offset
,
67 upper_32_bits(crtc_base
));
68 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ radeon_crtc
->crtc_offset
,
71 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ radeon_crtc
->crtc_offset
,
72 upper_32_bits(crtc_base
));
73 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ radeon_crtc
->crtc_offset
,
76 /* Wait for update_pending to go high. */
77 while (!(RREG32(EVERGREEN_GRPH_UPDATE
+ radeon_crtc
->crtc_offset
) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING
));
78 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
80 /* Unlock the lock, so double-buffering can take place inside vblank */
81 tmp
&= ~EVERGREEN_GRPH_UPDATE_LOCK
;
82 WREG32(EVERGREEN_GRPH_UPDATE
+ radeon_crtc
->crtc_offset
, tmp
);
84 /* Return current update_pending status: */
85 return RREG32(EVERGREEN_GRPH_UPDATE
+ radeon_crtc
->crtc_offset
) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING
;
88 /* get temperature in millidegrees */
89 int evergreen_get_temp(struct radeon_device
*rdev
)
94 if (rdev
->family
== CHIP_JUNIPER
) {
95 toffset
= (RREG32(CG_THERMAL_CTRL
) & TOFFSET_MASK
) >>
97 temp
= (RREG32(CG_TS0_STATUS
) & TS0_ADC_DOUT_MASK
) >>
101 actual_temp
= temp
/ 2 - (0x200 - toffset
);
103 actual_temp
= temp
/ 2 + toffset
;
105 actual_temp
= actual_temp
* 1000;
108 temp
= (RREG32(CG_MULT_THERMAL_STATUS
) & ASIC_T_MASK
) >>
113 else if (temp
& 0x200)
115 else if (temp
& 0x100) {
116 actual_temp
= temp
& 0x1ff;
117 actual_temp
|= ~0x1ff;
119 actual_temp
= temp
& 0xff;
121 actual_temp
= (actual_temp
* 1000) / 2;
127 int sumo_get_temp(struct radeon_device
*rdev
)
129 u32 temp
= RREG32(CG_THERMAL_STATUS
) & 0xff;
130 int actual_temp
= temp
- 49;
132 return actual_temp
* 1000;
135 void evergreen_pm_misc(struct radeon_device
*rdev
)
137 int req_ps_idx
= rdev
->pm
.requested_power_state_index
;
138 int req_cm_idx
= rdev
->pm
.requested_clock_mode_index
;
139 struct radeon_power_state
*ps
= &rdev
->pm
.power_state
[req_ps_idx
];
140 struct radeon_voltage
*voltage
= &ps
->clock_info
[req_cm_idx
].voltage
;
142 if (voltage
->type
== VOLTAGE_SW
) {
143 /* 0xff01 is a flag rather then an actual voltage */
144 if (voltage
->voltage
== 0xff01)
146 if (voltage
->voltage
&& (voltage
->voltage
!= rdev
->pm
.current_vddc
)) {
147 radeon_atom_set_voltage(rdev
, voltage
->voltage
, SET_VOLTAGE_TYPE_ASIC_VDDC
);
148 rdev
->pm
.current_vddc
= voltage
->voltage
;
149 DRM_DEBUG("Setting: vddc: %d\n", voltage
->voltage
);
151 /* 0xff01 is a flag rather then an actual voltage */
152 if (voltage
->vddci
== 0xff01)
154 if (voltage
->vddci
&& (voltage
->vddci
!= rdev
->pm
.current_vddci
)) {
155 radeon_atom_set_voltage(rdev
, voltage
->vddci
, SET_VOLTAGE_TYPE_ASIC_VDDCI
);
156 rdev
->pm
.current_vddci
= voltage
->vddci
;
157 DRM_DEBUG("Setting: vddci: %d\n", voltage
->vddci
);
162 void evergreen_pm_prepare(struct radeon_device
*rdev
)
164 struct drm_device
*ddev
= rdev
->ddev
;
165 struct drm_crtc
*crtc
;
166 struct radeon_crtc
*radeon_crtc
;
169 /* disable any active CRTCs */
170 list_for_each_entry(crtc
, &ddev
->mode_config
.crtc_list
, head
) {
171 radeon_crtc
= to_radeon_crtc(crtc
);
172 if (radeon_crtc
->enabled
) {
173 tmp
= RREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
);
174 tmp
|= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE
;
175 WREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
, tmp
);
180 void evergreen_pm_finish(struct radeon_device
*rdev
)
182 struct drm_device
*ddev
= rdev
->ddev
;
183 struct drm_crtc
*crtc
;
184 struct radeon_crtc
*radeon_crtc
;
187 /* enable any active CRTCs */
188 list_for_each_entry(crtc
, &ddev
->mode_config
.crtc_list
, head
) {
189 radeon_crtc
= to_radeon_crtc(crtc
);
190 if (radeon_crtc
->enabled
) {
191 tmp
= RREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
);
192 tmp
&= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE
;
193 WREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
, tmp
);
198 bool evergreen_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
)
200 bool connected
= false;
204 if (RREG32(DC_HPD1_INT_STATUS
) & DC_HPDx_SENSE
)
208 if (RREG32(DC_HPD2_INT_STATUS
) & DC_HPDx_SENSE
)
212 if (RREG32(DC_HPD3_INT_STATUS
) & DC_HPDx_SENSE
)
216 if (RREG32(DC_HPD4_INT_STATUS
) & DC_HPDx_SENSE
)
220 if (RREG32(DC_HPD5_INT_STATUS
) & DC_HPDx_SENSE
)
224 if (RREG32(DC_HPD6_INT_STATUS
) & DC_HPDx_SENSE
)
234 void evergreen_hpd_set_polarity(struct radeon_device
*rdev
,
235 enum radeon_hpd_id hpd
)
238 bool connected
= evergreen_hpd_sense(rdev
, hpd
);
242 tmp
= RREG32(DC_HPD1_INT_CONTROL
);
244 tmp
&= ~DC_HPDx_INT_POLARITY
;
246 tmp
|= DC_HPDx_INT_POLARITY
;
247 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
250 tmp
= RREG32(DC_HPD2_INT_CONTROL
);
252 tmp
&= ~DC_HPDx_INT_POLARITY
;
254 tmp
|= DC_HPDx_INT_POLARITY
;
255 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
258 tmp
= RREG32(DC_HPD3_INT_CONTROL
);
260 tmp
&= ~DC_HPDx_INT_POLARITY
;
262 tmp
|= DC_HPDx_INT_POLARITY
;
263 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
266 tmp
= RREG32(DC_HPD4_INT_CONTROL
);
268 tmp
&= ~DC_HPDx_INT_POLARITY
;
270 tmp
|= DC_HPDx_INT_POLARITY
;
271 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
274 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
276 tmp
&= ~DC_HPDx_INT_POLARITY
;
278 tmp
|= DC_HPDx_INT_POLARITY
;
279 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
282 tmp
= RREG32(DC_HPD6_INT_CONTROL
);
284 tmp
&= ~DC_HPDx_INT_POLARITY
;
286 tmp
|= DC_HPDx_INT_POLARITY
;
287 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
294 void evergreen_hpd_init(struct radeon_device
*rdev
)
296 struct drm_device
*dev
= rdev
->ddev
;
297 struct drm_connector
*connector
;
298 u32 tmp
= DC_HPDx_CONNECTION_TIMER(0x9c4) |
299 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN
;
301 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
302 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
303 switch (radeon_connector
->hpd
.hpd
) {
305 WREG32(DC_HPD1_CONTROL
, tmp
);
306 rdev
->irq
.hpd
[0] = true;
309 WREG32(DC_HPD2_CONTROL
, tmp
);
310 rdev
->irq
.hpd
[1] = true;
313 WREG32(DC_HPD3_CONTROL
, tmp
);
314 rdev
->irq
.hpd
[2] = true;
317 WREG32(DC_HPD4_CONTROL
, tmp
);
318 rdev
->irq
.hpd
[3] = true;
321 WREG32(DC_HPD5_CONTROL
, tmp
);
322 rdev
->irq
.hpd
[4] = true;
325 WREG32(DC_HPD6_CONTROL
, tmp
);
326 rdev
->irq
.hpd
[5] = true;
332 if (rdev
->irq
.installed
)
333 evergreen_irq_set(rdev
);
336 void evergreen_hpd_fini(struct radeon_device
*rdev
)
338 struct drm_device
*dev
= rdev
->ddev
;
339 struct drm_connector
*connector
;
341 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
342 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
343 switch (radeon_connector
->hpd
.hpd
) {
345 WREG32(DC_HPD1_CONTROL
, 0);
346 rdev
->irq
.hpd
[0] = false;
349 WREG32(DC_HPD2_CONTROL
, 0);
350 rdev
->irq
.hpd
[1] = false;
353 WREG32(DC_HPD3_CONTROL
, 0);
354 rdev
->irq
.hpd
[2] = false;
357 WREG32(DC_HPD4_CONTROL
, 0);
358 rdev
->irq
.hpd
[3] = false;
361 WREG32(DC_HPD5_CONTROL
, 0);
362 rdev
->irq
.hpd
[4] = false;
365 WREG32(DC_HPD6_CONTROL
, 0);
366 rdev
->irq
.hpd
[5] = false;
374 /* watermark setup */
376 static u32
evergreen_line_buffer_adjust(struct radeon_device
*rdev
,
377 struct radeon_crtc
*radeon_crtc
,
378 struct drm_display_mode
*mode
,
379 struct drm_display_mode
*other_mode
)
384 * There are 3 line buffers, each one shared by 2 display controllers.
385 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
386 * the display controllers. The paritioning is done via one of four
387 * preset allocations specified in bits 2:0:
388 * first display controller
389 * 0 - first half of lb (3840 * 2)
390 * 1 - first 3/4 of lb (5760 * 2)
391 * 2 - whole lb (7680 * 2), other crtc must be disabled
392 * 3 - first 1/4 of lb (1920 * 2)
393 * second display controller
394 * 4 - second half of lb (3840 * 2)
395 * 5 - second 3/4 of lb (5760 * 2)
396 * 6 - whole lb (7680 * 2), other crtc must be disabled
397 * 7 - last 1/4 of lb (1920 * 2)
399 /* this can get tricky if we have two large displays on a paired group
400 * of crtcs. Ideally for multiple large displays we'd assign them to
401 * non-linked crtcs for maximum line buffer allocation.
403 if (radeon_crtc
->base
.enabled
&& mode
) {
411 /* second controller of the pair uses second half of the lb */
412 if (radeon_crtc
->crtc_id
% 2)
414 WREG32(DC_LB_MEMORY_SPLIT
+ radeon_crtc
->crtc_offset
, tmp
);
416 if (radeon_crtc
->base
.enabled
&& mode
) {
421 if (ASIC_IS_DCE5(rdev
))
427 if (ASIC_IS_DCE5(rdev
))
433 if (ASIC_IS_DCE5(rdev
))
439 if (ASIC_IS_DCE5(rdev
))
446 /* controller not enabled, so no lb used */
450 static u32
evergreen_get_number_of_dram_channels(struct radeon_device
*rdev
)
452 u32 tmp
= RREG32(MC_SHARED_CHMAP
);
454 switch ((tmp
& NOOFCHAN_MASK
) >> NOOFCHAN_SHIFT
) {
467 struct evergreen_wm_params
{
468 u32 dram_channels
; /* number of dram channels */
469 u32 yclk
; /* bandwidth per dram data pin in kHz */
470 u32 sclk
; /* engine clock in kHz */
471 u32 disp_clk
; /* display clock in kHz */
472 u32 src_width
; /* viewport width */
473 u32 active_time
; /* active display time in ns */
474 u32 blank_time
; /* blank time in ns */
475 bool interlaced
; /* mode is interlaced */
476 fixed20_12 vsc
; /* vertical scale ratio */
477 u32 num_heads
; /* number of active crtcs */
478 u32 bytes_per_pixel
; /* bytes per pixel display + overlay */
479 u32 lb_size
; /* line buffer allocated to pipe */
480 u32 vtaps
; /* vertical scaler taps */
483 static u32
evergreen_dram_bandwidth(struct evergreen_wm_params
*wm
)
485 /* Calculate DRAM Bandwidth and the part allocated to display. */
486 fixed20_12 dram_efficiency
; /* 0.7 */
487 fixed20_12 yclk
, dram_channels
, bandwidth
;
490 a
.full
= dfixed_const(1000);
491 yclk
.full
= dfixed_const(wm
->yclk
);
492 yclk
.full
= dfixed_div(yclk
, a
);
493 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
494 a
.full
= dfixed_const(10);
495 dram_efficiency
.full
= dfixed_const(7);
496 dram_efficiency
.full
= dfixed_div(dram_efficiency
, a
);
497 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
498 bandwidth
.full
= dfixed_mul(bandwidth
, dram_efficiency
);
500 return dfixed_trunc(bandwidth
);
503 static u32
evergreen_dram_bandwidth_for_display(struct evergreen_wm_params
*wm
)
505 /* Calculate DRAM Bandwidth and the part allocated to display. */
506 fixed20_12 disp_dram_allocation
; /* 0.3 to 0.7 */
507 fixed20_12 yclk
, dram_channels
, bandwidth
;
510 a
.full
= dfixed_const(1000);
511 yclk
.full
= dfixed_const(wm
->yclk
);
512 yclk
.full
= dfixed_div(yclk
, a
);
513 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
514 a
.full
= dfixed_const(10);
515 disp_dram_allocation
.full
= dfixed_const(3); /* XXX worse case value 0.3 */
516 disp_dram_allocation
.full
= dfixed_div(disp_dram_allocation
, a
);
517 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
518 bandwidth
.full
= dfixed_mul(bandwidth
, disp_dram_allocation
);
520 return dfixed_trunc(bandwidth
);
523 static u32
evergreen_data_return_bandwidth(struct evergreen_wm_params
*wm
)
525 /* Calculate the display Data return Bandwidth */
526 fixed20_12 return_efficiency
; /* 0.8 */
527 fixed20_12 sclk
, bandwidth
;
530 a
.full
= dfixed_const(1000);
531 sclk
.full
= dfixed_const(wm
->sclk
);
532 sclk
.full
= dfixed_div(sclk
, a
);
533 a
.full
= dfixed_const(10);
534 return_efficiency
.full
= dfixed_const(8);
535 return_efficiency
.full
= dfixed_div(return_efficiency
, a
);
536 a
.full
= dfixed_const(32);
537 bandwidth
.full
= dfixed_mul(a
, sclk
);
538 bandwidth
.full
= dfixed_mul(bandwidth
, return_efficiency
);
540 return dfixed_trunc(bandwidth
);
543 static u32
evergreen_dmif_request_bandwidth(struct evergreen_wm_params
*wm
)
545 /* Calculate the DMIF Request Bandwidth */
546 fixed20_12 disp_clk_request_efficiency
; /* 0.8 */
547 fixed20_12 disp_clk
, bandwidth
;
550 a
.full
= dfixed_const(1000);
551 disp_clk
.full
= dfixed_const(wm
->disp_clk
);
552 disp_clk
.full
= dfixed_div(disp_clk
, a
);
553 a
.full
= dfixed_const(10);
554 disp_clk_request_efficiency
.full
= dfixed_const(8);
555 disp_clk_request_efficiency
.full
= dfixed_div(disp_clk_request_efficiency
, a
);
556 a
.full
= dfixed_const(32);
557 bandwidth
.full
= dfixed_mul(a
, disp_clk
);
558 bandwidth
.full
= dfixed_mul(bandwidth
, disp_clk_request_efficiency
);
560 return dfixed_trunc(bandwidth
);
563 static u32
evergreen_available_bandwidth(struct evergreen_wm_params
*wm
)
565 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
566 u32 dram_bandwidth
= evergreen_dram_bandwidth(wm
);
567 u32 data_return_bandwidth
= evergreen_data_return_bandwidth(wm
);
568 u32 dmif_req_bandwidth
= evergreen_dmif_request_bandwidth(wm
);
570 return min(dram_bandwidth
, min(data_return_bandwidth
, dmif_req_bandwidth
));
573 static u32
evergreen_average_bandwidth(struct evergreen_wm_params
*wm
)
575 /* Calculate the display mode Average Bandwidth
576 * DisplayMode should contain the source and destination dimensions,
580 fixed20_12 line_time
;
581 fixed20_12 src_width
;
582 fixed20_12 bandwidth
;
585 a
.full
= dfixed_const(1000);
586 line_time
.full
= dfixed_const(wm
->active_time
+ wm
->blank_time
);
587 line_time
.full
= dfixed_div(line_time
, a
);
588 bpp
.full
= dfixed_const(wm
->bytes_per_pixel
);
589 src_width
.full
= dfixed_const(wm
->src_width
);
590 bandwidth
.full
= dfixed_mul(src_width
, bpp
);
591 bandwidth
.full
= dfixed_mul(bandwidth
, wm
->vsc
);
592 bandwidth
.full
= dfixed_div(bandwidth
, line_time
);
594 return dfixed_trunc(bandwidth
);
597 static u32
evergreen_latency_watermark(struct evergreen_wm_params
*wm
)
599 /* First calcualte the latency in ns */
600 u32 mc_latency
= 2000; /* 2000 ns. */
601 u32 available_bandwidth
= evergreen_available_bandwidth(wm
);
602 u32 worst_chunk_return_time
= (512 * 8 * 1000) / available_bandwidth
;
603 u32 cursor_line_pair_return_time
= (128 * 4 * 1000) / available_bandwidth
;
604 u32 dc_latency
= 40000000 / wm
->disp_clk
; /* dc pipe latency */
605 u32 other_heads_data_return_time
= ((wm
->num_heads
+ 1) * worst_chunk_return_time
) +
606 (wm
->num_heads
* cursor_line_pair_return_time
);
607 u32 latency
= mc_latency
+ other_heads_data_return_time
+ dc_latency
;
608 u32 max_src_lines_per_dst_line
, lb_fill_bw
, line_fill_time
;
611 if (wm
->num_heads
== 0)
614 a
.full
= dfixed_const(2);
615 b
.full
= dfixed_const(1);
616 if ((wm
->vsc
.full
> a
.full
) ||
617 ((wm
->vsc
.full
> b
.full
) && (wm
->vtaps
>= 3)) ||
619 ((wm
->vsc
.full
>= a
.full
) && wm
->interlaced
))
620 max_src_lines_per_dst_line
= 4;
622 max_src_lines_per_dst_line
= 2;
624 a
.full
= dfixed_const(available_bandwidth
);
625 b
.full
= dfixed_const(wm
->num_heads
);
626 a
.full
= dfixed_div(a
, b
);
628 b
.full
= dfixed_const(1000);
629 c
.full
= dfixed_const(wm
->disp_clk
);
630 b
.full
= dfixed_div(c
, b
);
631 c
.full
= dfixed_const(wm
->bytes_per_pixel
);
632 b
.full
= dfixed_mul(b
, c
);
634 lb_fill_bw
= min(dfixed_trunc(a
), dfixed_trunc(b
));
636 a
.full
= dfixed_const(max_src_lines_per_dst_line
* wm
->src_width
* wm
->bytes_per_pixel
);
637 b
.full
= dfixed_const(1000);
638 c
.full
= dfixed_const(lb_fill_bw
);
639 b
.full
= dfixed_div(c
, b
);
640 a
.full
= dfixed_div(a
, b
);
641 line_fill_time
= dfixed_trunc(a
);
643 if (line_fill_time
< wm
->active_time
)
646 return latency
+ (line_fill_time
- wm
->active_time
);
650 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params
*wm
)
652 if (evergreen_average_bandwidth(wm
) <=
653 (evergreen_dram_bandwidth_for_display(wm
) / wm
->num_heads
))
659 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params
*wm
)
661 if (evergreen_average_bandwidth(wm
) <=
662 (evergreen_available_bandwidth(wm
) / wm
->num_heads
))
668 static bool evergreen_check_latency_hiding(struct evergreen_wm_params
*wm
)
670 u32 lb_partitions
= wm
->lb_size
/ wm
->src_width
;
671 u32 line_time
= wm
->active_time
+ wm
->blank_time
;
672 u32 latency_tolerant_lines
;
676 a
.full
= dfixed_const(1);
677 if (wm
->vsc
.full
> a
.full
)
678 latency_tolerant_lines
= 1;
680 if (lb_partitions
<= (wm
->vtaps
+ 1))
681 latency_tolerant_lines
= 1;
683 latency_tolerant_lines
= 2;
686 latency_hiding
= (latency_tolerant_lines
* line_time
+ wm
->blank_time
);
688 if (evergreen_latency_watermark(wm
) <= latency_hiding
)
694 static void evergreen_program_watermarks(struct radeon_device
*rdev
,
695 struct radeon_crtc
*radeon_crtc
,
696 u32 lb_size
, u32 num_heads
)
698 struct drm_display_mode
*mode
= &radeon_crtc
->base
.mode
;
699 struct evergreen_wm_params wm
;
702 u32 latency_watermark_a
= 0, latency_watermark_b
= 0;
703 u32 priority_a_mark
= 0, priority_b_mark
= 0;
704 u32 priority_a_cnt
= PRIORITY_OFF
;
705 u32 priority_b_cnt
= PRIORITY_OFF
;
706 u32 pipe_offset
= radeon_crtc
->crtc_id
* 16;
707 u32 tmp
, arb_control3
;
710 if (radeon_crtc
->base
.enabled
&& num_heads
&& mode
) {
711 pixel_period
= 1000000 / (u32
)mode
->clock
;
712 line_time
= min((u32
)mode
->crtc_htotal
* pixel_period
, (u32
)65535);
716 wm
.yclk
= rdev
->pm
.current_mclk
* 10;
717 wm
.sclk
= rdev
->pm
.current_sclk
* 10;
718 wm
.disp_clk
= mode
->clock
;
719 wm
.src_width
= mode
->crtc_hdisplay
;
720 wm
.active_time
= mode
->crtc_hdisplay
* pixel_period
;
721 wm
.blank_time
= line_time
- wm
.active_time
;
722 wm
.interlaced
= false;
723 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
724 wm
.interlaced
= true;
725 wm
.vsc
= radeon_crtc
->vsc
;
727 if (radeon_crtc
->rmx_type
!= RMX_OFF
)
729 wm
.bytes_per_pixel
= 4; /* XXX: get this from fb config */
730 wm
.lb_size
= lb_size
;
731 wm
.dram_channels
= evergreen_get_number_of_dram_channels(rdev
);
732 wm
.num_heads
= num_heads
;
734 /* set for high clocks */
735 latency_watermark_a
= min(evergreen_latency_watermark(&wm
), (u32
)65535);
736 /* set for low clocks */
737 /* wm.yclk = low clk; wm.sclk = low clk */
738 latency_watermark_b
= min(evergreen_latency_watermark(&wm
), (u32
)65535);
740 /* possibly force display priority to high */
741 /* should really do this at mode validation time... */
742 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm
) ||
743 !evergreen_average_bandwidth_vs_available_bandwidth(&wm
) ||
744 !evergreen_check_latency_hiding(&wm
) ||
745 (rdev
->disp_priority
== 2)) {
746 DRM_DEBUG_KMS("force priority to high\n");
747 priority_a_cnt
|= PRIORITY_ALWAYS_ON
;
748 priority_b_cnt
|= PRIORITY_ALWAYS_ON
;
751 a
.full
= dfixed_const(1000);
752 b
.full
= dfixed_const(mode
->clock
);
753 b
.full
= dfixed_div(b
, a
);
754 c
.full
= dfixed_const(latency_watermark_a
);
755 c
.full
= dfixed_mul(c
, b
);
756 c
.full
= dfixed_mul(c
, radeon_crtc
->hsc
);
757 c
.full
= dfixed_div(c
, a
);
758 a
.full
= dfixed_const(16);
759 c
.full
= dfixed_div(c
, a
);
760 priority_a_mark
= dfixed_trunc(c
);
761 priority_a_cnt
|= priority_a_mark
& PRIORITY_MARK_MASK
;
763 a
.full
= dfixed_const(1000);
764 b
.full
= dfixed_const(mode
->clock
);
765 b
.full
= dfixed_div(b
, a
);
766 c
.full
= dfixed_const(latency_watermark_b
);
767 c
.full
= dfixed_mul(c
, b
);
768 c
.full
= dfixed_mul(c
, radeon_crtc
->hsc
);
769 c
.full
= dfixed_div(c
, a
);
770 a
.full
= dfixed_const(16);
771 c
.full
= dfixed_div(c
, a
);
772 priority_b_mark
= dfixed_trunc(c
);
773 priority_b_cnt
|= priority_b_mark
& PRIORITY_MARK_MASK
;
777 arb_control3
= RREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
);
779 tmp
&= ~LATENCY_WATERMARK_MASK(3);
780 tmp
|= LATENCY_WATERMARK_MASK(1);
781 WREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
, tmp
);
782 WREG32(PIPE0_LATENCY_CONTROL
+ pipe_offset
,
783 (LATENCY_LOW_WATERMARK(latency_watermark_a
) |
784 LATENCY_HIGH_WATERMARK(line_time
)));
786 tmp
= RREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
);
787 tmp
&= ~LATENCY_WATERMARK_MASK(3);
788 tmp
|= LATENCY_WATERMARK_MASK(2);
789 WREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
, tmp
);
790 WREG32(PIPE0_LATENCY_CONTROL
+ pipe_offset
,
791 (LATENCY_LOW_WATERMARK(latency_watermark_b
) |
792 LATENCY_HIGH_WATERMARK(line_time
)));
793 /* restore original selection */
794 WREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
, arb_control3
);
796 /* write the priority marks */
797 WREG32(PRIORITY_A_CNT
+ radeon_crtc
->crtc_offset
, priority_a_cnt
);
798 WREG32(PRIORITY_B_CNT
+ radeon_crtc
->crtc_offset
, priority_b_cnt
);
802 void evergreen_bandwidth_update(struct radeon_device
*rdev
)
804 struct drm_display_mode
*mode0
= NULL
;
805 struct drm_display_mode
*mode1
= NULL
;
806 u32 num_heads
= 0, lb_size
;
809 radeon_update_display_priority(rdev
);
811 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
812 if (rdev
->mode_info
.crtcs
[i
]->base
.enabled
)
815 for (i
= 0; i
< rdev
->num_crtc
; i
+= 2) {
816 mode0
= &rdev
->mode_info
.crtcs
[i
]->base
.mode
;
817 mode1
= &rdev
->mode_info
.crtcs
[i
+1]->base
.mode
;
818 lb_size
= evergreen_line_buffer_adjust(rdev
, rdev
->mode_info
.crtcs
[i
], mode0
, mode1
);
819 evergreen_program_watermarks(rdev
, rdev
->mode_info
.crtcs
[i
], lb_size
, num_heads
);
820 lb_size
= evergreen_line_buffer_adjust(rdev
, rdev
->mode_info
.crtcs
[i
+1], mode1
, mode0
);
821 evergreen_program_watermarks(rdev
, rdev
->mode_info
.crtcs
[i
+1], lb_size
, num_heads
);
825 int evergreen_mc_wait_for_idle(struct radeon_device
*rdev
)
830 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
832 tmp
= RREG32(SRBM_STATUS
) & 0x1F00;
843 void evergreen_pcie_gart_tlb_flush(struct radeon_device
*rdev
)
848 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL
, 0x1);
850 WREG32(VM_CONTEXT0_REQUEST_RESPONSE
, REQUEST_TYPE(1));
851 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
853 tmp
= RREG32(VM_CONTEXT0_REQUEST_RESPONSE
);
854 tmp
= (tmp
& RESPONSE_TYPE_MASK
) >> RESPONSE_TYPE_SHIFT
;
856 printk(KERN_WARNING
"[drm] r600 flush TLB failed\n");
866 int evergreen_pcie_gart_enable(struct radeon_device
*rdev
)
871 if (rdev
->gart
.table
.vram
.robj
== NULL
) {
872 dev_err(rdev
->dev
, "No VRAM object for PCIE GART.\n");
875 r
= radeon_gart_table_vram_pin(rdev
);
878 radeon_gart_restore(rdev
);
880 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
881 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
882 EFFECTIVE_L2_QUEUE_SIZE(7));
883 WREG32(VM_L2_CNTL2
, 0);
884 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
885 /* Setup TLB control */
886 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
887 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
888 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
|
889 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
890 if (rdev
->flags
& RADEON_IS_IGP
) {
891 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL
, tmp
);
892 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL
, tmp
);
893 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL
, tmp
);
895 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
896 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
897 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
899 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
900 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
901 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
902 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
903 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR
, rdev
->mc
.gtt_start
>> 12);
904 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR
, rdev
->mc
.gtt_end
>> 12);
905 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, rdev
->gart
.table_addr
>> 12);
906 WREG32(VM_CONTEXT0_CNTL
, ENABLE_CONTEXT
| PAGE_TABLE_DEPTH(0) |
907 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
);
908 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
,
909 (u32
)(rdev
->dummy_page
.addr
>> 12));
910 WREG32(VM_CONTEXT1_CNTL
, 0);
912 evergreen_pcie_gart_tlb_flush(rdev
);
913 rdev
->gart
.ready
= true;
917 void evergreen_pcie_gart_disable(struct radeon_device
*rdev
)
922 /* Disable all tables */
923 WREG32(VM_CONTEXT0_CNTL
, 0);
924 WREG32(VM_CONTEXT1_CNTL
, 0);
927 WREG32(VM_L2_CNTL
, ENABLE_L2_FRAGMENT_PROCESSING
|
928 EFFECTIVE_L2_QUEUE_SIZE(7));
929 WREG32(VM_L2_CNTL2
, 0);
930 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
931 /* Setup TLB control */
932 tmp
= EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
933 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
934 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
935 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
936 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
937 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
938 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
939 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
940 if (rdev
->gart
.table
.vram
.robj
) {
941 r
= radeon_bo_reserve(rdev
->gart
.table
.vram
.robj
, false);
942 if (likely(r
== 0)) {
943 radeon_bo_kunmap(rdev
->gart
.table
.vram
.robj
);
944 radeon_bo_unpin(rdev
->gart
.table
.vram
.robj
);
945 radeon_bo_unreserve(rdev
->gart
.table
.vram
.robj
);
950 void evergreen_pcie_gart_fini(struct radeon_device
*rdev
)
952 evergreen_pcie_gart_disable(rdev
);
953 radeon_gart_table_vram_free(rdev
);
954 radeon_gart_fini(rdev
);
958 void evergreen_agp_enable(struct radeon_device
*rdev
)
963 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
964 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
965 EFFECTIVE_L2_QUEUE_SIZE(7));
966 WREG32(VM_L2_CNTL2
, 0);
967 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
968 /* Setup TLB control */
969 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
970 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
971 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
|
972 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
973 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
974 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
975 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
976 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
977 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
978 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
979 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
980 WREG32(VM_CONTEXT0_CNTL
, 0);
981 WREG32(VM_CONTEXT1_CNTL
, 0);
984 void evergreen_mc_stop(struct radeon_device
*rdev
, struct evergreen_mc_save
*save
)
986 save
->vga_control
[0] = RREG32(D1VGA_CONTROL
);
987 save
->vga_control
[1] = RREG32(D2VGA_CONTROL
);
988 save
->vga_render_control
= RREG32(VGA_RENDER_CONTROL
);
989 save
->vga_hdp_control
= RREG32(VGA_HDP_CONTROL
);
990 save
->crtc_control
[0] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
);
991 save
->crtc_control
[1] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
992 if (rdev
->num_crtc
>= 4) {
993 save
->vga_control
[2] = RREG32(EVERGREEN_D3VGA_CONTROL
);
994 save
->vga_control
[3] = RREG32(EVERGREEN_D4VGA_CONTROL
);
995 save
->crtc_control
[2] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
);
996 save
->crtc_control
[3] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
998 if (rdev
->num_crtc
>= 6) {
999 save
->vga_control
[4] = RREG32(EVERGREEN_D5VGA_CONTROL
);
1000 save
->vga_control
[5] = RREG32(EVERGREEN_D6VGA_CONTROL
);
1001 save
->crtc_control
[4] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
);
1002 save
->crtc_control
[5] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
1005 /* Stop all video */
1006 WREG32(VGA_RENDER_CONTROL
, 0);
1007 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 1);
1008 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 1);
1009 if (rdev
->num_crtc
>= 4) {
1010 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 1);
1011 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 1);
1013 if (rdev
->num_crtc
>= 6) {
1014 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 1);
1015 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 1);
1017 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
1018 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
1019 if (rdev
->num_crtc
>= 4) {
1020 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
1021 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
1023 if (rdev
->num_crtc
>= 6) {
1024 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
1025 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
1027 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
1028 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
1029 if (rdev
->num_crtc
>= 4) {
1030 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
1031 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
1033 if (rdev
->num_crtc
>= 6) {
1034 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
1035 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
1038 WREG32(D1VGA_CONTROL
, 0);
1039 WREG32(D2VGA_CONTROL
, 0);
1040 if (rdev
->num_crtc
>= 4) {
1041 WREG32(EVERGREEN_D3VGA_CONTROL
, 0);
1042 WREG32(EVERGREEN_D4VGA_CONTROL
, 0);
1044 if (rdev
->num_crtc
>= 6) {
1045 WREG32(EVERGREEN_D5VGA_CONTROL
, 0);
1046 WREG32(EVERGREEN_D6VGA_CONTROL
, 0);
1050 void evergreen_mc_resume(struct radeon_device
*rdev
, struct evergreen_mc_save
*save
)
1052 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC0_REGISTER_OFFSET
,
1053 upper_32_bits(rdev
->mc
.vram_start
));
1054 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC0_REGISTER_OFFSET
,
1055 upper_32_bits(rdev
->mc
.vram_start
));
1056 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
,
1057 (u32
)rdev
->mc
.vram_start
);
1058 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
,
1059 (u32
)rdev
->mc
.vram_start
);
1061 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC1_REGISTER_OFFSET
,
1062 upper_32_bits(rdev
->mc
.vram_start
));
1063 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC1_REGISTER_OFFSET
,
1064 upper_32_bits(rdev
->mc
.vram_start
));
1065 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
,
1066 (u32
)rdev
->mc
.vram_start
);
1067 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
,
1068 (u32
)rdev
->mc
.vram_start
);
1070 if (rdev
->num_crtc
>= 4) {
1071 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC2_REGISTER_OFFSET
,
1072 upper_32_bits(rdev
->mc
.vram_start
));
1073 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC2_REGISTER_OFFSET
,
1074 upper_32_bits(rdev
->mc
.vram_start
));
1075 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
,
1076 (u32
)rdev
->mc
.vram_start
);
1077 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
,
1078 (u32
)rdev
->mc
.vram_start
);
1080 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC3_REGISTER_OFFSET
,
1081 upper_32_bits(rdev
->mc
.vram_start
));
1082 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC3_REGISTER_OFFSET
,
1083 upper_32_bits(rdev
->mc
.vram_start
));
1084 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
,
1085 (u32
)rdev
->mc
.vram_start
);
1086 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
,
1087 (u32
)rdev
->mc
.vram_start
);
1089 if (rdev
->num_crtc
>= 6) {
1090 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC4_REGISTER_OFFSET
,
1091 upper_32_bits(rdev
->mc
.vram_start
));
1092 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC4_REGISTER_OFFSET
,
1093 upper_32_bits(rdev
->mc
.vram_start
));
1094 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
,
1095 (u32
)rdev
->mc
.vram_start
);
1096 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
,
1097 (u32
)rdev
->mc
.vram_start
);
1099 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC5_REGISTER_OFFSET
,
1100 upper_32_bits(rdev
->mc
.vram_start
));
1101 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC5_REGISTER_OFFSET
,
1102 upper_32_bits(rdev
->mc
.vram_start
));
1103 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
,
1104 (u32
)rdev
->mc
.vram_start
);
1105 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
,
1106 (u32
)rdev
->mc
.vram_start
);
1109 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH
, upper_32_bits(rdev
->mc
.vram_start
));
1110 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS
, (u32
)rdev
->mc
.vram_start
);
1111 /* Unlock host access */
1112 WREG32(VGA_HDP_CONTROL
, save
->vga_hdp_control
);
1114 /* Restore video state */
1115 WREG32(D1VGA_CONTROL
, save
->vga_control
[0]);
1116 WREG32(D2VGA_CONTROL
, save
->vga_control
[1]);
1117 if (rdev
->num_crtc
>= 4) {
1118 WREG32(EVERGREEN_D3VGA_CONTROL
, save
->vga_control
[2]);
1119 WREG32(EVERGREEN_D4VGA_CONTROL
, save
->vga_control
[3]);
1121 if (rdev
->num_crtc
>= 6) {
1122 WREG32(EVERGREEN_D5VGA_CONTROL
, save
->vga_control
[4]);
1123 WREG32(EVERGREEN_D6VGA_CONTROL
, save
->vga_control
[5]);
1125 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 1);
1126 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 1);
1127 if (rdev
->num_crtc
>= 4) {
1128 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 1);
1129 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 1);
1131 if (rdev
->num_crtc
>= 6) {
1132 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 1);
1133 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 1);
1135 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, save
->crtc_control
[0]);
1136 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, save
->crtc_control
[1]);
1137 if (rdev
->num_crtc
>= 4) {
1138 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, save
->crtc_control
[2]);
1139 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, save
->crtc_control
[3]);
1141 if (rdev
->num_crtc
>= 6) {
1142 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, save
->crtc_control
[4]);
1143 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, save
->crtc_control
[5]);
1145 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
1146 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
1147 if (rdev
->num_crtc
>= 4) {
1148 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
1149 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
1151 if (rdev
->num_crtc
>= 6) {
1152 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
1153 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
1155 WREG32(VGA_RENDER_CONTROL
, save
->vga_render_control
);
1158 void evergreen_mc_program(struct radeon_device
*rdev
)
1160 struct evergreen_mc_save save
;
1164 /* Initialize HDP */
1165 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
1166 WREG32((0x2c14 + j
), 0x00000000);
1167 WREG32((0x2c18 + j
), 0x00000000);
1168 WREG32((0x2c1c + j
), 0x00000000);
1169 WREG32((0x2c20 + j
), 0x00000000);
1170 WREG32((0x2c24 + j
), 0x00000000);
1172 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL
, 0);
1174 evergreen_mc_stop(rdev
, &save
);
1175 if (evergreen_mc_wait_for_idle(rdev
)) {
1176 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1178 /* Lockout access through VGA aperture*/
1179 WREG32(VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
);
1180 /* Update configuration */
1181 if (rdev
->flags
& RADEON_IS_AGP
) {
1182 if (rdev
->mc
.vram_start
< rdev
->mc
.gtt_start
) {
1183 /* VRAM before AGP */
1184 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
1185 rdev
->mc
.vram_start
>> 12);
1186 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
1187 rdev
->mc
.gtt_end
>> 12);
1189 /* VRAM after AGP */
1190 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
1191 rdev
->mc
.gtt_start
>> 12);
1192 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
1193 rdev
->mc
.vram_end
>> 12);
1196 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
1197 rdev
->mc
.vram_start
>> 12);
1198 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
1199 rdev
->mc
.vram_end
>> 12);
1201 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
, 0);
1202 if (rdev
->flags
& RADEON_IS_IGP
) {
1203 tmp
= RREG32(MC_FUS_VM_FB_OFFSET
) & 0x000FFFFF;
1204 tmp
|= ((rdev
->mc
.vram_end
>> 20) & 0xF) << 24;
1205 tmp
|= ((rdev
->mc
.vram_start
>> 20) & 0xF) << 20;
1206 WREG32(MC_FUS_VM_FB_OFFSET
, tmp
);
1208 tmp
= ((rdev
->mc
.vram_end
>> 24) & 0xFFFF) << 16;
1209 tmp
|= ((rdev
->mc
.vram_start
>> 24) & 0xFFFF);
1210 WREG32(MC_VM_FB_LOCATION
, tmp
);
1211 WREG32(HDP_NONSURFACE_BASE
, (rdev
->mc
.vram_start
>> 8));
1212 WREG32(HDP_NONSURFACE_INFO
, (2 << 7) | (1 << 30));
1213 WREG32(HDP_NONSURFACE_SIZE
, 0x3FFFFFFF);
1214 if (rdev
->flags
& RADEON_IS_AGP
) {
1215 WREG32(MC_VM_AGP_TOP
, rdev
->mc
.gtt_end
>> 16);
1216 WREG32(MC_VM_AGP_BOT
, rdev
->mc
.gtt_start
>> 16);
1217 WREG32(MC_VM_AGP_BASE
, rdev
->mc
.agp_base
>> 22);
1219 WREG32(MC_VM_AGP_BASE
, 0);
1220 WREG32(MC_VM_AGP_TOP
, 0x0FFFFFFF);
1221 WREG32(MC_VM_AGP_BOT
, 0x0FFFFFFF);
1223 if (evergreen_mc_wait_for_idle(rdev
)) {
1224 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1226 evergreen_mc_resume(rdev
, &save
);
1227 /* we need to own VRAM, so turn off the VGA renderer here
1228 * to stop it overwriting our objects */
1229 rv515_vga_render_disable(rdev
);
1235 void evergreen_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
1237 /* set to DX10/11 mode */
1238 radeon_ring_write(rdev
, PACKET3(PACKET3_MODE_CONTROL
, 0));
1239 radeon_ring_write(rdev
, 1);
1240 /* FIXME: implement */
1241 radeon_ring_write(rdev
, PACKET3(PACKET3_INDIRECT_BUFFER
, 2));
1242 radeon_ring_write(rdev
,
1246 (ib
->gpu_addr
& 0xFFFFFFFC));
1247 radeon_ring_write(rdev
, upper_32_bits(ib
->gpu_addr
) & 0xFF);
1248 radeon_ring_write(rdev
, ib
->length_dw
);
1252 static int evergreen_cp_load_microcode(struct radeon_device
*rdev
)
1254 const __be32
*fw_data
;
1257 if (!rdev
->me_fw
|| !rdev
->pfp_fw
)
1265 RB_NO_UPDATE
| RB_BLKSZ(15) | RB_BUFSZ(3));
1267 fw_data
= (const __be32
*)rdev
->pfp_fw
->data
;
1268 WREG32(CP_PFP_UCODE_ADDR
, 0);
1269 for (i
= 0; i
< EVERGREEN_PFP_UCODE_SIZE
; i
++)
1270 WREG32(CP_PFP_UCODE_DATA
, be32_to_cpup(fw_data
++));
1271 WREG32(CP_PFP_UCODE_ADDR
, 0);
1273 fw_data
= (const __be32
*)rdev
->me_fw
->data
;
1274 WREG32(CP_ME_RAM_WADDR
, 0);
1275 for (i
= 0; i
< EVERGREEN_PM4_UCODE_SIZE
; i
++)
1276 WREG32(CP_ME_RAM_DATA
, be32_to_cpup(fw_data
++));
1278 WREG32(CP_PFP_UCODE_ADDR
, 0);
1279 WREG32(CP_ME_RAM_WADDR
, 0);
1280 WREG32(CP_ME_RAM_RADDR
, 0);
1284 static int evergreen_cp_start(struct radeon_device
*rdev
)
1289 r
= radeon_ring_lock(rdev
, 7);
1291 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
1294 radeon_ring_write(rdev
, PACKET3(PACKET3_ME_INITIALIZE
, 5));
1295 radeon_ring_write(rdev
, 0x1);
1296 radeon_ring_write(rdev
, 0x0);
1297 radeon_ring_write(rdev
, rdev
->config
.evergreen
.max_hw_contexts
- 1);
1298 radeon_ring_write(rdev
, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1299 radeon_ring_write(rdev
, 0);
1300 radeon_ring_write(rdev
, 0);
1301 radeon_ring_unlock_commit(rdev
);
1304 WREG32(CP_ME_CNTL
, cp_me
);
1306 r
= radeon_ring_lock(rdev
, evergreen_default_size
+ 19);
1308 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
1312 /* setup clear context state */
1313 radeon_ring_write(rdev
, PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
1314 radeon_ring_write(rdev
, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE
);
1316 for (i
= 0; i
< evergreen_default_size
; i
++)
1317 radeon_ring_write(rdev
, evergreen_default_state
[i
]);
1319 radeon_ring_write(rdev
, PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
1320 radeon_ring_write(rdev
, PACKET3_PREAMBLE_END_CLEAR_STATE
);
1322 /* set clear context state */
1323 radeon_ring_write(rdev
, PACKET3(PACKET3_CLEAR_STATE
, 0));
1324 radeon_ring_write(rdev
, 0);
1326 /* SQ_VTX_BASE_VTX_LOC */
1327 radeon_ring_write(rdev
, 0xc0026f00);
1328 radeon_ring_write(rdev
, 0x00000000);
1329 radeon_ring_write(rdev
, 0x00000000);
1330 radeon_ring_write(rdev
, 0x00000000);
1333 radeon_ring_write(rdev
, 0xc0036f00);
1334 radeon_ring_write(rdev
, 0x00000bc4);
1335 radeon_ring_write(rdev
, 0xffffffff);
1336 radeon_ring_write(rdev
, 0xffffffff);
1337 radeon_ring_write(rdev
, 0xffffffff);
1339 radeon_ring_write(rdev
, 0xc0026900);
1340 radeon_ring_write(rdev
, 0x00000316);
1341 radeon_ring_write(rdev
, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1342 radeon_ring_write(rdev
, 0x00000010); /* */
1344 radeon_ring_unlock_commit(rdev
);
1349 int evergreen_cp_resume(struct radeon_device
*rdev
)
1355 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1356 WREG32(GRBM_SOFT_RESET
, (SOFT_RESET_CP
|
1362 RREG32(GRBM_SOFT_RESET
);
1364 WREG32(GRBM_SOFT_RESET
, 0);
1365 RREG32(GRBM_SOFT_RESET
);
1367 /* Set ring buffer size */
1368 rb_bufsz
= drm_order(rdev
->cp
.ring_size
/ 8);
1369 tmp
= (drm_order(RADEON_GPU_PAGE_SIZE
/8) << 8) | rb_bufsz
;
1371 tmp
|= BUF_SWAP_32BIT
;
1373 WREG32(CP_RB_CNTL
, tmp
);
1374 WREG32(CP_SEM_WAIT_TIMER
, 0x4);
1376 /* Set the write pointer delay */
1377 WREG32(CP_RB_WPTR_DELAY
, 0);
1379 /* Initialize the ring buffer's read and write pointers */
1380 WREG32(CP_RB_CNTL
, tmp
| RB_RPTR_WR_ENA
);
1381 WREG32(CP_RB_RPTR_WR
, 0);
1382 WREG32(CP_RB_WPTR
, 0);
1384 /* set the wb address wether it's enabled or not */
1385 WREG32(CP_RB_RPTR_ADDR
,
1386 ((rdev
->wb
.gpu_addr
+ RADEON_WB_CP_RPTR_OFFSET
) & 0xFFFFFFFC));
1387 WREG32(CP_RB_RPTR_ADDR_HI
, upper_32_bits(rdev
->wb
.gpu_addr
+ RADEON_WB_CP_RPTR_OFFSET
) & 0xFF);
1388 WREG32(SCRATCH_ADDR
, ((rdev
->wb
.gpu_addr
+ RADEON_WB_SCRATCH_OFFSET
) >> 8) & 0xFFFFFFFF);
1390 if (rdev
->wb
.enabled
)
1391 WREG32(SCRATCH_UMSK
, 0xff);
1393 tmp
|= RB_NO_UPDATE
;
1394 WREG32(SCRATCH_UMSK
, 0);
1398 WREG32(CP_RB_CNTL
, tmp
);
1400 WREG32(CP_RB_BASE
, rdev
->cp
.gpu_addr
>> 8);
1401 WREG32(CP_DEBUG
, (1 << 27) | (1 << 28));
1403 rdev
->cp
.rptr
= RREG32(CP_RB_RPTR
);
1404 rdev
->cp
.wptr
= RREG32(CP_RB_WPTR
);
1406 evergreen_cp_start(rdev
);
1407 rdev
->cp
.ready
= true;
1408 r
= radeon_ring_test(rdev
);
1410 rdev
->cp
.ready
= false;
1419 static u32
evergreen_get_tile_pipe_to_backend_map(struct radeon_device
*rdev
,
1422 u32 backend_disable_mask
)
1424 u32 backend_map
= 0;
1425 u32 enabled_backends_mask
= 0;
1426 u32 enabled_backends_count
= 0;
1428 u32 swizzle_pipe
[EVERGREEN_MAX_PIPES
];
1429 u32 cur_backend
= 0;
1431 bool force_no_swizzle
;
1433 if (num_tile_pipes
> EVERGREEN_MAX_PIPES
)
1434 num_tile_pipes
= EVERGREEN_MAX_PIPES
;
1435 if (num_tile_pipes
< 1)
1437 if (num_backends
> EVERGREEN_MAX_BACKENDS
)
1438 num_backends
= EVERGREEN_MAX_BACKENDS
;
1439 if (num_backends
< 1)
1442 for (i
= 0; i
< EVERGREEN_MAX_BACKENDS
; ++i
) {
1443 if (((backend_disable_mask
>> i
) & 1) == 0) {
1444 enabled_backends_mask
|= (1 << i
);
1445 ++enabled_backends_count
;
1447 if (enabled_backends_count
== num_backends
)
1451 if (enabled_backends_count
== 0) {
1452 enabled_backends_mask
= 1;
1453 enabled_backends_count
= 1;
1456 if (enabled_backends_count
!= num_backends
)
1457 num_backends
= enabled_backends_count
;
1459 memset((uint8_t *)&swizzle_pipe
[0], 0, sizeof(u32
) * EVERGREEN_MAX_PIPES
);
1460 switch (rdev
->family
) {
1468 force_no_swizzle
= false;
1475 force_no_swizzle
= true;
1478 if (force_no_swizzle
) {
1479 bool last_backend_enabled
= false;
1481 force_no_swizzle
= false;
1482 for (i
= 0; i
< EVERGREEN_MAX_BACKENDS
; ++i
) {
1483 if (((enabled_backends_mask
>> i
) & 1) == 1) {
1484 if (last_backend_enabled
)
1485 force_no_swizzle
= true;
1486 last_backend_enabled
= true;
1488 last_backend_enabled
= false;
1492 switch (num_tile_pipes
) {
1497 DRM_ERROR("odd number of pipes!\n");
1500 swizzle_pipe
[0] = 0;
1501 swizzle_pipe
[1] = 1;
1504 if (force_no_swizzle
) {
1505 swizzle_pipe
[0] = 0;
1506 swizzle_pipe
[1] = 1;
1507 swizzle_pipe
[2] = 2;
1508 swizzle_pipe
[3] = 3;
1510 swizzle_pipe
[0] = 0;
1511 swizzle_pipe
[1] = 2;
1512 swizzle_pipe
[2] = 1;
1513 swizzle_pipe
[3] = 3;
1517 if (force_no_swizzle
) {
1518 swizzle_pipe
[0] = 0;
1519 swizzle_pipe
[1] = 1;
1520 swizzle_pipe
[2] = 2;
1521 swizzle_pipe
[3] = 3;
1522 swizzle_pipe
[4] = 4;
1523 swizzle_pipe
[5] = 5;
1525 swizzle_pipe
[0] = 0;
1526 swizzle_pipe
[1] = 2;
1527 swizzle_pipe
[2] = 4;
1528 swizzle_pipe
[3] = 1;
1529 swizzle_pipe
[4] = 3;
1530 swizzle_pipe
[5] = 5;
1534 if (force_no_swizzle
) {
1535 swizzle_pipe
[0] = 0;
1536 swizzle_pipe
[1] = 1;
1537 swizzle_pipe
[2] = 2;
1538 swizzle_pipe
[3] = 3;
1539 swizzle_pipe
[4] = 4;
1540 swizzle_pipe
[5] = 5;
1541 swizzle_pipe
[6] = 6;
1542 swizzle_pipe
[7] = 7;
1544 swizzle_pipe
[0] = 0;
1545 swizzle_pipe
[1] = 2;
1546 swizzle_pipe
[2] = 4;
1547 swizzle_pipe
[3] = 6;
1548 swizzle_pipe
[4] = 1;
1549 swizzle_pipe
[5] = 3;
1550 swizzle_pipe
[6] = 5;
1551 swizzle_pipe
[7] = 7;
1556 for (cur_pipe
= 0; cur_pipe
< num_tile_pipes
; ++cur_pipe
) {
1557 while (((1 << cur_backend
) & enabled_backends_mask
) == 0)
1558 cur_backend
= (cur_backend
+ 1) % EVERGREEN_MAX_BACKENDS
;
1560 backend_map
|= (((cur_backend
& 0xf) << (swizzle_pipe
[cur_pipe
] * 4)));
1562 cur_backend
= (cur_backend
+ 1) % EVERGREEN_MAX_BACKENDS
;
1568 static void evergreen_program_channel_remap(struct radeon_device
*rdev
)
1570 u32 tcp_chan_steer_lo
, tcp_chan_steer_hi
, mc_shared_chremap
, tmp
;
1572 tmp
= RREG32(MC_SHARED_CHMAP
);
1573 switch ((tmp
& NOOFCHAN_MASK
) >> NOOFCHAN_SHIFT
) {
1579 /* default mapping */
1580 mc_shared_chremap
= 0x00fac688;
1584 switch (rdev
->family
) {
1588 tcp_chan_steer_lo
= 0x54763210;
1589 tcp_chan_steer_hi
= 0x0000ba98;
1600 tcp_chan_steer_lo
= 0x76543210;
1601 tcp_chan_steer_hi
= 0x0000ba98;
1605 WREG32(TCP_CHAN_STEER_LO
, tcp_chan_steer_lo
);
1606 WREG32(TCP_CHAN_STEER_HI
, tcp_chan_steer_hi
);
1607 WREG32(MC_SHARED_CHREMAP
, mc_shared_chremap
);
1610 static void evergreen_gpu_init(struct radeon_device
*rdev
)
1612 u32 cc_rb_backend_disable
= 0;
1613 u32 cc_gc_shader_pipe_config
;
1614 u32 gb_addr_config
= 0;
1615 u32 mc_shared_chmap
, mc_arb_ramcfg
;
1621 u32 sq_lds_resource_mgmt
;
1622 u32 sq_gpr_resource_mgmt_1
;
1623 u32 sq_gpr_resource_mgmt_2
;
1624 u32 sq_gpr_resource_mgmt_3
;
1625 u32 sq_thread_resource_mgmt
;
1626 u32 sq_thread_resource_mgmt_2
;
1627 u32 sq_stack_resource_mgmt_1
;
1628 u32 sq_stack_resource_mgmt_2
;
1629 u32 sq_stack_resource_mgmt_3
;
1630 u32 vgt_cache_invalidation
;
1631 u32 hdp_host_path_cntl
, tmp
;
1632 int i
, j
, num_shader_engines
, ps_thread_count
;
1634 switch (rdev
->family
) {
1637 rdev
->config
.evergreen
.num_ses
= 2;
1638 rdev
->config
.evergreen
.max_pipes
= 4;
1639 rdev
->config
.evergreen
.max_tile_pipes
= 8;
1640 rdev
->config
.evergreen
.max_simds
= 10;
1641 rdev
->config
.evergreen
.max_backends
= 4 * rdev
->config
.evergreen
.num_ses
;
1642 rdev
->config
.evergreen
.max_gprs
= 256;
1643 rdev
->config
.evergreen
.max_threads
= 248;
1644 rdev
->config
.evergreen
.max_gs_threads
= 32;
1645 rdev
->config
.evergreen
.max_stack_entries
= 512;
1646 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1647 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1648 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1649 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1650 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1651 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1653 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
1654 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1655 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1658 rdev
->config
.evergreen
.num_ses
= 1;
1659 rdev
->config
.evergreen
.max_pipes
= 4;
1660 rdev
->config
.evergreen
.max_tile_pipes
= 4;
1661 rdev
->config
.evergreen
.max_simds
= 10;
1662 rdev
->config
.evergreen
.max_backends
= 4 * rdev
->config
.evergreen
.num_ses
;
1663 rdev
->config
.evergreen
.max_gprs
= 256;
1664 rdev
->config
.evergreen
.max_threads
= 248;
1665 rdev
->config
.evergreen
.max_gs_threads
= 32;
1666 rdev
->config
.evergreen
.max_stack_entries
= 512;
1667 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1668 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1669 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1670 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1671 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1672 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1674 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
1675 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1676 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1679 rdev
->config
.evergreen
.num_ses
= 1;
1680 rdev
->config
.evergreen
.max_pipes
= 4;
1681 rdev
->config
.evergreen
.max_tile_pipes
= 4;
1682 rdev
->config
.evergreen
.max_simds
= 5;
1683 rdev
->config
.evergreen
.max_backends
= 2 * rdev
->config
.evergreen
.num_ses
;
1684 rdev
->config
.evergreen
.max_gprs
= 256;
1685 rdev
->config
.evergreen
.max_threads
= 248;
1686 rdev
->config
.evergreen
.max_gs_threads
= 32;
1687 rdev
->config
.evergreen
.max_stack_entries
= 256;
1688 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1689 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1690 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1691 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1692 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1693 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1695 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
1696 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1697 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1701 rdev
->config
.evergreen
.num_ses
= 1;
1702 rdev
->config
.evergreen
.max_pipes
= 2;
1703 rdev
->config
.evergreen
.max_tile_pipes
= 2;
1704 rdev
->config
.evergreen
.max_simds
= 2;
1705 rdev
->config
.evergreen
.max_backends
= 1 * rdev
->config
.evergreen
.num_ses
;
1706 rdev
->config
.evergreen
.max_gprs
= 256;
1707 rdev
->config
.evergreen
.max_threads
= 192;
1708 rdev
->config
.evergreen
.max_gs_threads
= 16;
1709 rdev
->config
.evergreen
.max_stack_entries
= 256;
1710 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1711 rdev
->config
.evergreen
.sx_max_export_size
= 128;
1712 rdev
->config
.evergreen
.sx_max_export_pos_size
= 32;
1713 rdev
->config
.evergreen
.sx_max_export_smx_size
= 96;
1714 rdev
->config
.evergreen
.max_hw_contexts
= 4;
1715 rdev
->config
.evergreen
.sq_num_cf_insts
= 1;
1717 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x40;
1718 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1719 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1722 rdev
->config
.evergreen
.num_ses
= 1;
1723 rdev
->config
.evergreen
.max_pipes
= 2;
1724 rdev
->config
.evergreen
.max_tile_pipes
= 2;
1725 rdev
->config
.evergreen
.max_simds
= 2;
1726 rdev
->config
.evergreen
.max_backends
= 1 * rdev
->config
.evergreen
.num_ses
;
1727 rdev
->config
.evergreen
.max_gprs
= 256;
1728 rdev
->config
.evergreen
.max_threads
= 192;
1729 rdev
->config
.evergreen
.max_gs_threads
= 16;
1730 rdev
->config
.evergreen
.max_stack_entries
= 256;
1731 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1732 rdev
->config
.evergreen
.sx_max_export_size
= 128;
1733 rdev
->config
.evergreen
.sx_max_export_pos_size
= 32;
1734 rdev
->config
.evergreen
.sx_max_export_smx_size
= 96;
1735 rdev
->config
.evergreen
.max_hw_contexts
= 4;
1736 rdev
->config
.evergreen
.sq_num_cf_insts
= 1;
1738 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x40;
1739 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1740 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1743 rdev
->config
.evergreen
.num_ses
= 1;
1744 rdev
->config
.evergreen
.max_pipes
= 4;
1745 rdev
->config
.evergreen
.max_tile_pipes
= 2;
1746 if (rdev
->pdev
->device
== 0x9648)
1747 rdev
->config
.evergreen
.max_simds
= 3;
1748 else if ((rdev
->pdev
->device
== 0x9647) ||
1749 (rdev
->pdev
->device
== 0x964a))
1750 rdev
->config
.evergreen
.max_simds
= 4;
1752 rdev
->config
.evergreen
.max_simds
= 5;
1753 rdev
->config
.evergreen
.max_backends
= 2 * rdev
->config
.evergreen
.num_ses
;
1754 rdev
->config
.evergreen
.max_gprs
= 256;
1755 rdev
->config
.evergreen
.max_threads
= 248;
1756 rdev
->config
.evergreen
.max_gs_threads
= 32;
1757 rdev
->config
.evergreen
.max_stack_entries
= 256;
1758 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1759 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1760 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1761 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1762 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1763 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1765 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x40;
1766 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1767 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1770 rdev
->config
.evergreen
.num_ses
= 1;
1771 rdev
->config
.evergreen
.max_pipes
= 4;
1772 rdev
->config
.evergreen
.max_tile_pipes
= 4;
1773 rdev
->config
.evergreen
.max_simds
= 2;
1774 rdev
->config
.evergreen
.max_backends
= 1 * rdev
->config
.evergreen
.num_ses
;
1775 rdev
->config
.evergreen
.max_gprs
= 256;
1776 rdev
->config
.evergreen
.max_threads
= 248;
1777 rdev
->config
.evergreen
.max_gs_threads
= 32;
1778 rdev
->config
.evergreen
.max_stack_entries
= 512;
1779 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1780 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1781 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1782 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1783 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1784 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1786 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x40;
1787 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1788 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1791 rdev
->config
.evergreen
.num_ses
= 2;
1792 rdev
->config
.evergreen
.max_pipes
= 4;
1793 rdev
->config
.evergreen
.max_tile_pipes
= 8;
1794 rdev
->config
.evergreen
.max_simds
= 7;
1795 rdev
->config
.evergreen
.max_backends
= 4 * rdev
->config
.evergreen
.num_ses
;
1796 rdev
->config
.evergreen
.max_gprs
= 256;
1797 rdev
->config
.evergreen
.max_threads
= 248;
1798 rdev
->config
.evergreen
.max_gs_threads
= 32;
1799 rdev
->config
.evergreen
.max_stack_entries
= 512;
1800 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1801 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1802 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1803 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1804 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1805 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1807 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
1808 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1809 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1812 rdev
->config
.evergreen
.num_ses
= 1;
1813 rdev
->config
.evergreen
.max_pipes
= 4;
1814 rdev
->config
.evergreen
.max_tile_pipes
= 4;
1815 rdev
->config
.evergreen
.max_simds
= 6;
1816 rdev
->config
.evergreen
.max_backends
= 2 * rdev
->config
.evergreen
.num_ses
;
1817 rdev
->config
.evergreen
.max_gprs
= 256;
1818 rdev
->config
.evergreen
.max_threads
= 248;
1819 rdev
->config
.evergreen
.max_gs_threads
= 32;
1820 rdev
->config
.evergreen
.max_stack_entries
= 256;
1821 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1822 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1823 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1824 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1825 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1826 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1828 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
1829 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1830 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1833 rdev
->config
.evergreen
.num_ses
= 1;
1834 rdev
->config
.evergreen
.max_pipes
= 4;
1835 rdev
->config
.evergreen
.max_tile_pipes
= 2;
1836 rdev
->config
.evergreen
.max_simds
= 2;
1837 rdev
->config
.evergreen
.max_backends
= 1 * rdev
->config
.evergreen
.num_ses
;
1838 rdev
->config
.evergreen
.max_gprs
= 256;
1839 rdev
->config
.evergreen
.max_threads
= 192;
1840 rdev
->config
.evergreen
.max_gs_threads
= 16;
1841 rdev
->config
.evergreen
.max_stack_entries
= 256;
1842 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1843 rdev
->config
.evergreen
.sx_max_export_size
= 128;
1844 rdev
->config
.evergreen
.sx_max_export_pos_size
= 32;
1845 rdev
->config
.evergreen
.sx_max_export_smx_size
= 96;
1846 rdev
->config
.evergreen
.max_hw_contexts
= 4;
1847 rdev
->config
.evergreen
.sq_num_cf_insts
= 1;
1849 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x40;
1850 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1851 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1855 /* Initialize HDP */
1856 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
1857 WREG32((0x2c14 + j
), 0x00000000);
1858 WREG32((0x2c18 + j
), 0x00000000);
1859 WREG32((0x2c1c + j
), 0x00000000);
1860 WREG32((0x2c20 + j
), 0x00000000);
1861 WREG32((0x2c24 + j
), 0x00000000);
1864 WREG32(GRBM_CNTL
, GRBM_READ_TIMEOUT(0xff));
1866 cc_gc_shader_pipe_config
= RREG32(CC_GC_SHADER_PIPE_CONFIG
) & ~2;
1868 cc_gc_shader_pipe_config
|=
1869 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK
<< rdev
->config
.evergreen
.max_pipes
)
1870 & EVERGREEN_MAX_PIPES_MASK
);
1871 cc_gc_shader_pipe_config
|=
1872 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK
<< rdev
->config
.evergreen
.max_simds
)
1873 & EVERGREEN_MAX_SIMDS_MASK
);
1875 cc_rb_backend_disable
=
1876 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK
<< rdev
->config
.evergreen
.max_backends
)
1877 & EVERGREEN_MAX_BACKENDS_MASK
);
1880 mc_shared_chmap
= RREG32(MC_SHARED_CHMAP
);
1881 if (rdev
->flags
& RADEON_IS_IGP
)
1882 mc_arb_ramcfg
= RREG32(FUS_MC_ARB_RAMCFG
);
1884 mc_arb_ramcfg
= RREG32(MC_ARB_RAMCFG
);
1886 switch (rdev
->config
.evergreen
.max_tile_pipes
) {
1889 gb_addr_config
|= NUM_PIPES(0);
1892 gb_addr_config
|= NUM_PIPES(1);
1895 gb_addr_config
|= NUM_PIPES(2);
1898 gb_addr_config
|= NUM_PIPES(3);
1902 gb_addr_config
|= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg
& BURSTLENGTH_MASK
) >> BURSTLENGTH_SHIFT
);
1903 gb_addr_config
|= BANK_INTERLEAVE_SIZE(0);
1904 gb_addr_config
|= NUM_SHADER_ENGINES(rdev
->config
.evergreen
.num_ses
- 1);
1905 gb_addr_config
|= SHADER_ENGINE_TILE_SIZE(1);
1906 gb_addr_config
|= NUM_GPUS(0); /* Hemlock? */
1907 gb_addr_config
|= MULTI_GPU_TILE_SIZE(2);
1909 if (((mc_arb_ramcfg
& NOOFCOLS_MASK
) >> NOOFCOLS_SHIFT
) > 2)
1910 gb_addr_config
|= ROW_SIZE(2);
1912 gb_addr_config
|= ROW_SIZE((mc_arb_ramcfg
& NOOFCOLS_MASK
) >> NOOFCOLS_SHIFT
);
1914 if (rdev
->ddev
->pdev
->device
== 0x689e) {
1917 u8 efuse_box_bit_131_124
;
1919 WREG32(RCU_IND_INDEX
, 0x204);
1920 efuse_straps_4
= RREG32(RCU_IND_DATA
);
1921 WREG32(RCU_IND_INDEX
, 0x203);
1922 efuse_straps_3
= RREG32(RCU_IND_DATA
);
1923 efuse_box_bit_131_124
= (u8
)(((efuse_straps_4
& 0xf) << 4) | ((efuse_straps_3
& 0xf0000000) >> 28));
1925 switch(efuse_box_bit_131_124
) {
1927 gb_backend_map
= 0x76543210;
1930 gb_backend_map
= 0x77553311;
1933 gb_backend_map
= 0x77553300;
1936 gb_backend_map
= 0x77552211;
1939 gb_backend_map
= 0x77443300;
1942 gb_backend_map
= 0x66552211;
1945 gb_backend_map
= 0x77552200;
1948 gb_backend_map
= 0x66442200;
1951 gb_backend_map
= 0x66553311;
1954 DRM_ERROR("bad backend map, using default\n");
1956 evergreen_get_tile_pipe_to_backend_map(rdev
,
1957 rdev
->config
.evergreen
.max_tile_pipes
,
1958 rdev
->config
.evergreen
.max_backends
,
1959 ((EVERGREEN_MAX_BACKENDS_MASK
<<
1960 rdev
->config
.evergreen
.max_backends
) &
1961 EVERGREEN_MAX_BACKENDS_MASK
));
1964 } else if (rdev
->ddev
->pdev
->device
== 0x68b9) {
1966 u8 efuse_box_bit_127_124
;
1968 WREG32(RCU_IND_INDEX
, 0x203);
1969 efuse_straps_3
= RREG32(RCU_IND_DATA
);
1970 efuse_box_bit_127_124
= (u8
)((efuse_straps_3
& 0xF0000000) >> 28);
1972 switch(efuse_box_bit_127_124
) {
1974 gb_backend_map
= 0x00003210;
1980 gb_backend_map
= 0x00003311;
1983 DRM_ERROR("bad backend map, using default\n");
1985 evergreen_get_tile_pipe_to_backend_map(rdev
,
1986 rdev
->config
.evergreen
.max_tile_pipes
,
1987 rdev
->config
.evergreen
.max_backends
,
1988 ((EVERGREEN_MAX_BACKENDS_MASK
<<
1989 rdev
->config
.evergreen
.max_backends
) &
1990 EVERGREEN_MAX_BACKENDS_MASK
));
1994 switch (rdev
->family
) {
1998 gb_backend_map
= 0x66442200;
2001 gb_backend_map
= 0x00002200;
2005 evergreen_get_tile_pipe_to_backend_map(rdev
,
2006 rdev
->config
.evergreen
.max_tile_pipes
,
2007 rdev
->config
.evergreen
.max_backends
,
2008 ((EVERGREEN_MAX_BACKENDS_MASK
<<
2009 rdev
->config
.evergreen
.max_backends
) &
2010 EVERGREEN_MAX_BACKENDS_MASK
));
2014 /* setup tiling info dword. gb_addr_config is not adequate since it does
2015 * not have bank info, so create a custom tiling dword.
2016 * bits 3:0 num_pipes
2017 * bits 7:4 num_banks
2018 * bits 11:8 group_size
2019 * bits 15:12 row_size
2021 rdev
->config
.evergreen
.tile_config
= 0;
2022 switch (rdev
->config
.evergreen
.max_tile_pipes
) {
2025 rdev
->config
.evergreen
.tile_config
|= (0 << 0);
2028 rdev
->config
.evergreen
.tile_config
|= (1 << 0);
2031 rdev
->config
.evergreen
.tile_config
|= (2 << 0);
2034 rdev
->config
.evergreen
.tile_config
|= (3 << 0);
2037 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
2038 if (rdev
->flags
& RADEON_IS_IGP
)
2039 rdev
->config
.evergreen
.tile_config
|= 1 << 4;
2041 rdev
->config
.evergreen
.tile_config
|=
2042 ((mc_arb_ramcfg
& NOOFBANK_MASK
) >> NOOFBANK_SHIFT
) << 4;
2043 rdev
->config
.evergreen
.tile_config
|=
2044 ((mc_arb_ramcfg
& BURSTLENGTH_MASK
) >> BURSTLENGTH_SHIFT
) << 8;
2045 rdev
->config
.evergreen
.tile_config
|=
2046 ((gb_addr_config
& 0x30000000) >> 28) << 12;
2048 rdev
->config
.evergreen
.backend_map
= gb_backend_map
;
2049 WREG32(GB_BACKEND_MAP
, gb_backend_map
);
2050 WREG32(GB_ADDR_CONFIG
, gb_addr_config
);
2051 WREG32(DMIF_ADDR_CONFIG
, gb_addr_config
);
2052 WREG32(HDP_ADDR_CONFIG
, gb_addr_config
);
2054 evergreen_program_channel_remap(rdev
);
2056 num_shader_engines
= ((RREG32(GB_ADDR_CONFIG
) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
2057 grbm_gfx_index
= INSTANCE_BROADCAST_WRITES
;
2059 for (i
= 0; i
< rdev
->config
.evergreen
.num_ses
; i
++) {
2060 u32 rb
= cc_rb_backend_disable
| (0xf0 << 16);
2061 u32 sp
= cc_gc_shader_pipe_config
;
2062 u32 gfx
= grbm_gfx_index
| SE_INDEX(i
);
2064 if (i
== num_shader_engines
) {
2065 rb
|= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK
);
2066 sp
|= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK
);
2069 WREG32(GRBM_GFX_INDEX
, gfx
);
2070 WREG32(RLC_GFX_INDEX
, gfx
);
2072 WREG32(CC_RB_BACKEND_DISABLE
, rb
);
2073 WREG32(CC_SYS_RB_BACKEND_DISABLE
, rb
);
2074 WREG32(GC_USER_RB_BACKEND_DISABLE
, rb
);
2075 WREG32(CC_GC_SHADER_PIPE_CONFIG
, sp
);
2078 grbm_gfx_index
|= SE_BROADCAST_WRITES
;
2079 WREG32(GRBM_GFX_INDEX
, grbm_gfx_index
);
2080 WREG32(RLC_GFX_INDEX
, grbm_gfx_index
);
2082 WREG32(CGTS_SYS_TCC_DISABLE
, 0);
2083 WREG32(CGTS_TCC_DISABLE
, 0);
2084 WREG32(CGTS_USER_SYS_TCC_DISABLE
, 0);
2085 WREG32(CGTS_USER_TCC_DISABLE
, 0);
2087 /* set HW defaults for 3D engine */
2088 WREG32(CP_QUEUE_THRESHOLDS
, (ROQ_IB1_START(0x16) |
2089 ROQ_IB2_START(0x2b)));
2091 WREG32(CP_MEQ_THRESHOLDS
, STQ_SPLIT(0x30));
2093 WREG32(TA_CNTL_AUX
, (DISABLE_CUBE_ANISO
|
2098 sx_debug_1
= RREG32(SX_DEBUG_1
);
2099 sx_debug_1
|= ENABLE_NEW_SMX_ADDRESS
;
2100 WREG32(SX_DEBUG_1
, sx_debug_1
);
2103 smx_dc_ctl0
= RREG32(SMX_DC_CTL0
);
2104 smx_dc_ctl0
&= ~NUMBER_OF_SETS(0x1ff);
2105 smx_dc_ctl0
|= NUMBER_OF_SETS(rdev
->config
.evergreen
.sx_num_of_sets
);
2106 WREG32(SMX_DC_CTL0
, smx_dc_ctl0
);
2108 WREG32(SX_EXPORT_BUFFER_SIZES
, (COLOR_BUFFER_SIZE((rdev
->config
.evergreen
.sx_max_export_size
/ 4) - 1) |
2109 POSITION_BUFFER_SIZE((rdev
->config
.evergreen
.sx_max_export_pos_size
/ 4) - 1) |
2110 SMX_BUFFER_SIZE((rdev
->config
.evergreen
.sx_max_export_smx_size
/ 4) - 1)));
2112 WREG32(PA_SC_FIFO_SIZE
, (SC_PRIM_FIFO_SIZE(rdev
->config
.evergreen
.sc_prim_fifo_size
) |
2113 SC_HIZ_TILE_FIFO_SIZE(rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
) |
2114 SC_EARLYZ_TILE_FIFO_SIZE(rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
)));
2116 WREG32(VGT_NUM_INSTANCES
, 1);
2117 WREG32(SPI_CONFIG_CNTL
, 0);
2118 WREG32(SPI_CONFIG_CNTL_1
, VTX_DONE_DELAY(4));
2119 WREG32(CP_PERFMON_CNTL
, 0);
2121 WREG32(SQ_MS_FIFO_SIZES
, (CACHE_FIFO_SIZE(16 * rdev
->config
.evergreen
.sq_num_cf_insts
) |
2122 FETCH_FIFO_HIWATER(0x4) |
2123 DONE_FIFO_HIWATER(0xe0) |
2124 ALU_UPDATE_FIFO_HIWATER(0x8)));
2126 sq_config
= RREG32(SQ_CONFIG
);
2127 sq_config
&= ~(PS_PRIO(3) |
2131 sq_config
|= (VC_ENABLE
|
2138 switch (rdev
->family
) {
2144 /* no vertex cache */
2145 sq_config
&= ~VC_ENABLE
;
2151 sq_lds_resource_mgmt
= RREG32(SQ_LDS_RESOURCE_MGMT
);
2153 sq_gpr_resource_mgmt_1
= NUM_PS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2))* 12 / 32);
2154 sq_gpr_resource_mgmt_1
|= NUM_VS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 6 / 32);
2155 sq_gpr_resource_mgmt_1
|= NUM_CLAUSE_TEMP_GPRS(4);
2156 sq_gpr_resource_mgmt_2
= NUM_GS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 4 / 32);
2157 sq_gpr_resource_mgmt_2
|= NUM_ES_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 4 / 32);
2158 sq_gpr_resource_mgmt_3
= NUM_HS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 3 / 32);
2159 sq_gpr_resource_mgmt_3
|= NUM_LS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 3 / 32);
2161 switch (rdev
->family
) {
2166 ps_thread_count
= 96;
2169 ps_thread_count
= 128;
2173 sq_thread_resource_mgmt
= NUM_PS_THREADS(ps_thread_count
);
2174 sq_thread_resource_mgmt
|= NUM_VS_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
2175 sq_thread_resource_mgmt
|= NUM_GS_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
2176 sq_thread_resource_mgmt
|= NUM_ES_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
2177 sq_thread_resource_mgmt_2
= NUM_HS_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
2178 sq_thread_resource_mgmt_2
|= NUM_LS_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
2180 sq_stack_resource_mgmt_1
= NUM_PS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2181 sq_stack_resource_mgmt_1
|= NUM_VS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2182 sq_stack_resource_mgmt_2
= NUM_GS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2183 sq_stack_resource_mgmt_2
|= NUM_ES_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2184 sq_stack_resource_mgmt_3
= NUM_HS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2185 sq_stack_resource_mgmt_3
|= NUM_LS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2187 WREG32(SQ_CONFIG
, sq_config
);
2188 WREG32(SQ_GPR_RESOURCE_MGMT_1
, sq_gpr_resource_mgmt_1
);
2189 WREG32(SQ_GPR_RESOURCE_MGMT_2
, sq_gpr_resource_mgmt_2
);
2190 WREG32(SQ_GPR_RESOURCE_MGMT_3
, sq_gpr_resource_mgmt_3
);
2191 WREG32(SQ_THREAD_RESOURCE_MGMT
, sq_thread_resource_mgmt
);
2192 WREG32(SQ_THREAD_RESOURCE_MGMT_2
, sq_thread_resource_mgmt_2
);
2193 WREG32(SQ_STACK_RESOURCE_MGMT_1
, sq_stack_resource_mgmt_1
);
2194 WREG32(SQ_STACK_RESOURCE_MGMT_2
, sq_stack_resource_mgmt_2
);
2195 WREG32(SQ_STACK_RESOURCE_MGMT_3
, sq_stack_resource_mgmt_3
);
2196 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0);
2197 WREG32(SQ_LDS_RESOURCE_MGMT
, sq_lds_resource_mgmt
);
2199 WREG32(PA_SC_FORCE_EOV_MAX_CNTS
, (FORCE_EOV_MAX_CLK_CNT(4095) |
2200 FORCE_EOV_MAX_REZ_CNT(255)));
2202 switch (rdev
->family
) {
2208 vgt_cache_invalidation
= CACHE_INVALIDATION(TC_ONLY
);
2211 vgt_cache_invalidation
= CACHE_INVALIDATION(VC_AND_TC
);
2214 vgt_cache_invalidation
|= AUTO_INVLD_EN(ES_AND_GS_AUTO
);
2215 WREG32(VGT_CACHE_INVALIDATION
, vgt_cache_invalidation
);
2217 WREG32(VGT_GS_VERTEX_REUSE
, 16);
2218 WREG32(PA_SU_LINE_STIPPLE_VALUE
, 0);
2219 WREG32(PA_SC_LINE_STIPPLE_STATE
, 0);
2221 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
2222 WREG32(VGT_OUT_DEALLOC_CNTL
, 16);
2224 WREG32(CB_PERF_CTR0_SEL_0
, 0);
2225 WREG32(CB_PERF_CTR0_SEL_1
, 0);
2226 WREG32(CB_PERF_CTR1_SEL_0
, 0);
2227 WREG32(CB_PERF_CTR1_SEL_1
, 0);
2228 WREG32(CB_PERF_CTR2_SEL_0
, 0);
2229 WREG32(CB_PERF_CTR2_SEL_1
, 0);
2230 WREG32(CB_PERF_CTR3_SEL_0
, 0);
2231 WREG32(CB_PERF_CTR3_SEL_1
, 0);
2233 /* clear render buffer base addresses */
2234 WREG32(CB_COLOR0_BASE
, 0);
2235 WREG32(CB_COLOR1_BASE
, 0);
2236 WREG32(CB_COLOR2_BASE
, 0);
2237 WREG32(CB_COLOR3_BASE
, 0);
2238 WREG32(CB_COLOR4_BASE
, 0);
2239 WREG32(CB_COLOR5_BASE
, 0);
2240 WREG32(CB_COLOR6_BASE
, 0);
2241 WREG32(CB_COLOR7_BASE
, 0);
2242 WREG32(CB_COLOR8_BASE
, 0);
2243 WREG32(CB_COLOR9_BASE
, 0);
2244 WREG32(CB_COLOR10_BASE
, 0);
2245 WREG32(CB_COLOR11_BASE
, 0);
2247 /* set the shader const cache sizes to 0 */
2248 for (i
= SQ_ALU_CONST_BUFFER_SIZE_PS_0
; i
< 0x28200; i
+= 4)
2250 for (i
= SQ_ALU_CONST_BUFFER_SIZE_HS_0
; i
< 0x29000; i
+= 4)
2253 tmp
= RREG32(HDP_MISC_CNTL
);
2254 tmp
|= HDP_FLUSH_INVALIDATE_CACHE
;
2255 WREG32(HDP_MISC_CNTL
, tmp
);
2257 hdp_host_path_cntl
= RREG32(HDP_HOST_PATH_CNTL
);
2258 WREG32(HDP_HOST_PATH_CNTL
, hdp_host_path_cntl
);
2260 WREG32(PA_CL_ENHANCE
, CLIP_VTX_REORDER_ENA
| NUM_CLIP_SEQ(3));
2266 int evergreen_mc_init(struct radeon_device
*rdev
)
2269 int chansize
, numchan
;
2271 /* Get VRAM informations */
2272 rdev
->mc
.vram_is_ddr
= true;
2273 if (rdev
->flags
& RADEON_IS_IGP
)
2274 tmp
= RREG32(FUS_MC_ARB_RAMCFG
);
2276 tmp
= RREG32(MC_ARB_RAMCFG
);
2277 if (tmp
& CHANSIZE_OVERRIDE
) {
2279 } else if (tmp
& CHANSIZE_MASK
) {
2284 tmp
= RREG32(MC_SHARED_CHMAP
);
2285 switch ((tmp
& NOOFCHAN_MASK
) >> NOOFCHAN_SHIFT
) {
2300 rdev
->mc
.vram_width
= numchan
* chansize
;
2301 /* Could aper size report 0 ? */
2302 rdev
->mc
.aper_base
= pci_resource_start(rdev
->pdev
, 0);
2303 rdev
->mc
.aper_size
= pci_resource_len(rdev
->pdev
, 0);
2304 /* Setup GPU memory space */
2305 if (rdev
->flags
& RADEON_IS_IGP
) {
2306 /* size in bytes on fusion */
2307 rdev
->mc
.mc_vram_size
= RREG32(CONFIG_MEMSIZE
);
2308 rdev
->mc
.real_vram_size
= RREG32(CONFIG_MEMSIZE
);
2310 /* size in MB on evergreen */
2311 rdev
->mc
.mc_vram_size
= RREG32(CONFIG_MEMSIZE
) * 1024 * 1024;
2312 rdev
->mc
.real_vram_size
= RREG32(CONFIG_MEMSIZE
) * 1024 * 1024;
2314 rdev
->mc
.visible_vram_size
= rdev
->mc
.aper_size
;
2315 r700_vram_gtt_location(rdev
, &rdev
->mc
);
2316 radeon_update_bandwidth_info(rdev
);
2321 bool evergreen_gpu_is_lockup(struct radeon_device
*rdev
)
2325 u32 grbm_status_se0
, grbm_status_se1
;
2326 struct r100_gpu_lockup
*lockup
= &rdev
->config
.evergreen
.lockup
;
2329 srbm_status
= RREG32(SRBM_STATUS
);
2330 grbm_status
= RREG32(GRBM_STATUS
);
2331 grbm_status_se0
= RREG32(GRBM_STATUS_SE0
);
2332 grbm_status_se1
= RREG32(GRBM_STATUS_SE1
);
2333 if (!(grbm_status
& GUI_ACTIVE
)) {
2334 r100_gpu_lockup_update(lockup
, &rdev
->cp
);
2337 /* force CP activities */
2338 r
= radeon_ring_lock(rdev
, 2);
2341 radeon_ring_write(rdev
, 0x80000000);
2342 radeon_ring_write(rdev
, 0x80000000);
2343 radeon_ring_unlock_commit(rdev
);
2345 rdev
->cp
.rptr
= RREG32(CP_RB_RPTR
);
2346 return r100_gpu_cp_is_lockup(rdev
, lockup
, &rdev
->cp
);
2349 static int evergreen_gpu_soft_reset(struct radeon_device
*rdev
)
2351 struct evergreen_mc_save save
;
2354 if (!(RREG32(GRBM_STATUS
) & GUI_ACTIVE
))
2357 dev_info(rdev
->dev
, "GPU softreset \n");
2358 dev_info(rdev
->dev
, " GRBM_STATUS=0x%08X\n",
2359 RREG32(GRBM_STATUS
));
2360 dev_info(rdev
->dev
, " GRBM_STATUS_SE0=0x%08X\n",
2361 RREG32(GRBM_STATUS_SE0
));
2362 dev_info(rdev
->dev
, " GRBM_STATUS_SE1=0x%08X\n",
2363 RREG32(GRBM_STATUS_SE1
));
2364 dev_info(rdev
->dev
, " SRBM_STATUS=0x%08X\n",
2365 RREG32(SRBM_STATUS
));
2366 evergreen_mc_stop(rdev
, &save
);
2367 if (evergreen_mc_wait_for_idle(rdev
)) {
2368 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
2370 /* Disable CP parsing/prefetching */
2371 WREG32(CP_ME_CNTL
, CP_ME_HALT
| CP_PFP_HALT
);
2373 /* reset all the gfx blocks */
2374 grbm_reset
= (SOFT_RESET_CP
|
2387 dev_info(rdev
->dev
, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset
);
2388 WREG32(GRBM_SOFT_RESET
, grbm_reset
);
2389 (void)RREG32(GRBM_SOFT_RESET
);
2391 WREG32(GRBM_SOFT_RESET
, 0);
2392 (void)RREG32(GRBM_SOFT_RESET
);
2393 /* Wait a little for things to settle down */
2395 dev_info(rdev
->dev
, " GRBM_STATUS=0x%08X\n",
2396 RREG32(GRBM_STATUS
));
2397 dev_info(rdev
->dev
, " GRBM_STATUS_SE0=0x%08X\n",
2398 RREG32(GRBM_STATUS_SE0
));
2399 dev_info(rdev
->dev
, " GRBM_STATUS_SE1=0x%08X\n",
2400 RREG32(GRBM_STATUS_SE1
));
2401 dev_info(rdev
->dev
, " SRBM_STATUS=0x%08X\n",
2402 RREG32(SRBM_STATUS
));
2403 evergreen_mc_resume(rdev
, &save
);
2407 int evergreen_asic_reset(struct radeon_device
*rdev
)
2409 return evergreen_gpu_soft_reset(rdev
);
2414 u32
evergreen_get_vblank_counter(struct radeon_device
*rdev
, int crtc
)
2418 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC0_REGISTER_OFFSET
);
2420 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
2422 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC2_REGISTER_OFFSET
);
2424 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
2426 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC4_REGISTER_OFFSET
);
2428 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
2434 void evergreen_disable_interrupt_state(struct radeon_device
*rdev
)
2438 WREG32(CP_INT_CNTL
, CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
);
2439 WREG32(GRBM_INT_CNTL
, 0);
2440 WREG32(INT_MASK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
2441 WREG32(INT_MASK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
2442 if (rdev
->num_crtc
>= 4) {
2443 WREG32(INT_MASK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
2444 WREG32(INT_MASK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
2446 if (rdev
->num_crtc
>= 6) {
2447 WREG32(INT_MASK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
2448 WREG32(INT_MASK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
2451 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
2452 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
2453 if (rdev
->num_crtc
>= 4) {
2454 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
2455 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
2457 if (rdev
->num_crtc
>= 6) {
2458 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
2459 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
2462 WREG32(DACA_AUTODETECT_INT_CONTROL
, 0);
2463 WREG32(DACB_AUTODETECT_INT_CONTROL
, 0);
2465 tmp
= RREG32(DC_HPD1_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2466 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
2467 tmp
= RREG32(DC_HPD2_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2468 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
2469 tmp
= RREG32(DC_HPD3_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2470 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
2471 tmp
= RREG32(DC_HPD4_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2472 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
2473 tmp
= RREG32(DC_HPD5_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2474 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
2475 tmp
= RREG32(DC_HPD6_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2476 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
2480 int evergreen_irq_set(struct radeon_device
*rdev
)
2482 u32 cp_int_cntl
= CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
;
2483 u32 crtc1
= 0, crtc2
= 0, crtc3
= 0, crtc4
= 0, crtc5
= 0, crtc6
= 0;
2484 u32 hpd1
, hpd2
, hpd3
, hpd4
, hpd5
, hpd6
;
2485 u32 grbm_int_cntl
= 0;
2486 u32 grph1
= 0, grph2
= 0, grph3
= 0, grph4
= 0, grph5
= 0, grph6
= 0;
2488 if (!rdev
->irq
.installed
) {
2489 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2492 /* don't enable anything if the ih is disabled */
2493 if (!rdev
->ih
.enabled
) {
2494 r600_disable_interrupts(rdev
);
2495 /* force the active interrupt state to all disabled */
2496 evergreen_disable_interrupt_state(rdev
);
2500 hpd1
= RREG32(DC_HPD1_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2501 hpd2
= RREG32(DC_HPD2_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2502 hpd3
= RREG32(DC_HPD3_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2503 hpd4
= RREG32(DC_HPD4_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2504 hpd5
= RREG32(DC_HPD5_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2505 hpd6
= RREG32(DC_HPD6_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2507 if (rdev
->irq
.sw_int
) {
2508 DRM_DEBUG("evergreen_irq_set: sw int\n");
2509 cp_int_cntl
|= RB_INT_ENABLE
;
2510 cp_int_cntl
|= TIME_STAMP_INT_ENABLE
;
2512 if (rdev
->irq
.crtc_vblank_int
[0] ||
2513 rdev
->irq
.pflip
[0]) {
2514 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2515 crtc1
|= VBLANK_INT_MASK
;
2517 if (rdev
->irq
.crtc_vblank_int
[1] ||
2518 rdev
->irq
.pflip
[1]) {
2519 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2520 crtc2
|= VBLANK_INT_MASK
;
2522 if (rdev
->irq
.crtc_vblank_int
[2] ||
2523 rdev
->irq
.pflip
[2]) {
2524 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2525 crtc3
|= VBLANK_INT_MASK
;
2527 if (rdev
->irq
.crtc_vblank_int
[3] ||
2528 rdev
->irq
.pflip
[3]) {
2529 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2530 crtc4
|= VBLANK_INT_MASK
;
2532 if (rdev
->irq
.crtc_vblank_int
[4] ||
2533 rdev
->irq
.pflip
[4]) {
2534 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2535 crtc5
|= VBLANK_INT_MASK
;
2537 if (rdev
->irq
.crtc_vblank_int
[5] ||
2538 rdev
->irq
.pflip
[5]) {
2539 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2540 crtc6
|= VBLANK_INT_MASK
;
2542 if (rdev
->irq
.hpd
[0]) {
2543 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2544 hpd1
|= DC_HPDx_INT_EN
;
2546 if (rdev
->irq
.hpd
[1]) {
2547 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2548 hpd2
|= DC_HPDx_INT_EN
;
2550 if (rdev
->irq
.hpd
[2]) {
2551 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2552 hpd3
|= DC_HPDx_INT_EN
;
2554 if (rdev
->irq
.hpd
[3]) {
2555 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2556 hpd4
|= DC_HPDx_INT_EN
;
2558 if (rdev
->irq
.hpd
[4]) {
2559 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2560 hpd5
|= DC_HPDx_INT_EN
;
2562 if (rdev
->irq
.hpd
[5]) {
2563 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2564 hpd6
|= DC_HPDx_INT_EN
;
2566 if (rdev
->irq
.gui_idle
) {
2567 DRM_DEBUG("gui idle\n");
2568 grbm_int_cntl
|= GUI_IDLE_INT_ENABLE
;
2571 WREG32(CP_INT_CNTL
, cp_int_cntl
);
2572 WREG32(GRBM_INT_CNTL
, grbm_int_cntl
);
2574 WREG32(INT_MASK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, crtc1
);
2575 WREG32(INT_MASK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, crtc2
);
2576 if (rdev
->num_crtc
>= 4) {
2577 WREG32(INT_MASK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, crtc3
);
2578 WREG32(INT_MASK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, crtc4
);
2580 if (rdev
->num_crtc
>= 6) {
2581 WREG32(INT_MASK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, crtc5
);
2582 WREG32(INT_MASK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, crtc6
);
2585 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, grph1
);
2586 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, grph2
);
2587 if (rdev
->num_crtc
>= 4) {
2588 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, grph3
);
2589 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, grph4
);
2591 if (rdev
->num_crtc
>= 6) {
2592 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, grph5
);
2593 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, grph6
);
2596 WREG32(DC_HPD1_INT_CONTROL
, hpd1
);
2597 WREG32(DC_HPD2_INT_CONTROL
, hpd2
);
2598 WREG32(DC_HPD3_INT_CONTROL
, hpd3
);
2599 WREG32(DC_HPD4_INT_CONTROL
, hpd4
);
2600 WREG32(DC_HPD5_INT_CONTROL
, hpd5
);
2601 WREG32(DC_HPD6_INT_CONTROL
, hpd6
);
2606 static inline void evergreen_irq_ack(struct radeon_device
*rdev
)
2610 rdev
->irq
.stat_regs
.evergreen
.disp_int
= RREG32(DISP_INTERRUPT_STATUS
);
2611 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE
);
2612 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE2
);
2613 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE3
);
2614 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE4
);
2615 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE5
);
2616 rdev
->irq
.stat_regs
.evergreen
.d1grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
);
2617 rdev
->irq
.stat_regs
.evergreen
.d2grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
2618 if (rdev
->num_crtc
>= 4) {
2619 rdev
->irq
.stat_regs
.evergreen
.d3grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
);
2620 rdev
->irq
.stat_regs
.evergreen
.d4grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
2622 if (rdev
->num_crtc
>= 6) {
2623 rdev
->irq
.stat_regs
.evergreen
.d5grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
);
2624 rdev
->irq
.stat_regs
.evergreen
.d6grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
2627 if (rdev
->irq
.stat_regs
.evergreen
.d1grph_int
& GRPH_PFLIP_INT_OCCURRED
)
2628 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
2629 if (rdev
->irq
.stat_regs
.evergreen
.d2grph_int
& GRPH_PFLIP_INT_OCCURRED
)
2630 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
2631 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& LB_D1_VBLANK_INTERRUPT
)
2632 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, VBLANK_ACK
);
2633 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& LB_D1_VLINE_INTERRUPT
)
2634 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, VLINE_ACK
);
2635 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& LB_D2_VBLANK_INTERRUPT
)
2636 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, VBLANK_ACK
);
2637 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& LB_D2_VLINE_INTERRUPT
)
2638 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, VLINE_ACK
);
2640 if (rdev
->num_crtc
>= 4) {
2641 if (rdev
->irq
.stat_regs
.evergreen
.d3grph_int
& GRPH_PFLIP_INT_OCCURRED
)
2642 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
2643 if (rdev
->irq
.stat_regs
.evergreen
.d4grph_int
& GRPH_PFLIP_INT_OCCURRED
)
2644 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
2645 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& LB_D3_VBLANK_INTERRUPT
)
2646 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, VBLANK_ACK
);
2647 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& LB_D3_VLINE_INTERRUPT
)
2648 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, VLINE_ACK
);
2649 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& LB_D4_VBLANK_INTERRUPT
)
2650 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, VBLANK_ACK
);
2651 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& LB_D4_VLINE_INTERRUPT
)
2652 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, VLINE_ACK
);
2655 if (rdev
->num_crtc
>= 6) {
2656 if (rdev
->irq
.stat_regs
.evergreen
.d5grph_int
& GRPH_PFLIP_INT_OCCURRED
)
2657 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
2658 if (rdev
->irq
.stat_regs
.evergreen
.d6grph_int
& GRPH_PFLIP_INT_OCCURRED
)
2659 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
2660 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& LB_D5_VBLANK_INTERRUPT
)
2661 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, VBLANK_ACK
);
2662 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& LB_D5_VLINE_INTERRUPT
)
2663 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, VLINE_ACK
);
2664 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& LB_D6_VBLANK_INTERRUPT
)
2665 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, VBLANK_ACK
);
2666 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& LB_D6_VLINE_INTERRUPT
)
2667 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, VLINE_ACK
);
2670 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& DC_HPD1_INTERRUPT
) {
2671 tmp
= RREG32(DC_HPD1_INT_CONTROL
);
2672 tmp
|= DC_HPDx_INT_ACK
;
2673 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
2675 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& DC_HPD2_INTERRUPT
) {
2676 tmp
= RREG32(DC_HPD2_INT_CONTROL
);
2677 tmp
|= DC_HPDx_INT_ACK
;
2678 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
2680 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& DC_HPD3_INTERRUPT
) {
2681 tmp
= RREG32(DC_HPD3_INT_CONTROL
);
2682 tmp
|= DC_HPDx_INT_ACK
;
2683 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
2685 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& DC_HPD4_INTERRUPT
) {
2686 tmp
= RREG32(DC_HPD4_INT_CONTROL
);
2687 tmp
|= DC_HPDx_INT_ACK
;
2688 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
2690 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& DC_HPD5_INTERRUPT
) {
2691 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
2692 tmp
|= DC_HPDx_INT_ACK
;
2693 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
2695 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& DC_HPD6_INTERRUPT
) {
2696 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
2697 tmp
|= DC_HPDx_INT_ACK
;
2698 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
2702 void evergreen_irq_disable(struct radeon_device
*rdev
)
2704 r600_disable_interrupts(rdev
);
2705 /* Wait and acknowledge irq */
2707 evergreen_irq_ack(rdev
);
2708 evergreen_disable_interrupt_state(rdev
);
2711 void evergreen_irq_suspend(struct radeon_device
*rdev
)
2713 evergreen_irq_disable(rdev
);
2714 r600_rlc_stop(rdev
);
2717 static inline u32
evergreen_get_ih_wptr(struct radeon_device
*rdev
)
2721 if (rdev
->wb
.enabled
)
2722 wptr
= le32_to_cpu(rdev
->wb
.wb
[R600_WB_IH_WPTR_OFFSET
/4]);
2724 wptr
= RREG32(IH_RB_WPTR
);
2726 if (wptr
& RB_OVERFLOW
) {
2727 /* When a ring buffer overflow happen start parsing interrupt
2728 * from the last not overwritten vector (wptr + 16). Hopefully
2729 * this should allow us to catchup.
2731 dev_warn(rdev
->dev
, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2732 wptr
, rdev
->ih
.rptr
, (wptr
+ 16) + rdev
->ih
.ptr_mask
);
2733 rdev
->ih
.rptr
= (wptr
+ 16) & rdev
->ih
.ptr_mask
;
2734 tmp
= RREG32(IH_RB_CNTL
);
2735 tmp
|= IH_WPTR_OVERFLOW_CLEAR
;
2736 WREG32(IH_RB_CNTL
, tmp
);
2738 return (wptr
& rdev
->ih
.ptr_mask
);
2741 int evergreen_irq_process(struct radeon_device
*rdev
)
2745 u32 src_id
, src_data
;
2747 unsigned long flags
;
2748 bool queue_hotplug
= false;
2750 if (!rdev
->ih
.enabled
|| rdev
->shutdown
)
2753 wptr
= evergreen_get_ih_wptr(rdev
);
2754 rptr
= rdev
->ih
.rptr
;
2755 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr
, wptr
);
2757 spin_lock_irqsave(&rdev
->ih
.lock
, flags
);
2759 spin_unlock_irqrestore(&rdev
->ih
.lock
, flags
);
2763 /* Order reading of wptr vs. reading of IH ring data */
2766 /* display interrupts */
2767 evergreen_irq_ack(rdev
);
2769 rdev
->ih
.wptr
= wptr
;
2770 while (rptr
!= wptr
) {
2771 /* wptr/rptr are in bytes! */
2772 ring_index
= rptr
/ 4;
2773 src_id
= le32_to_cpu(rdev
->ih
.ring
[ring_index
]) & 0xff;
2774 src_data
= le32_to_cpu(rdev
->ih
.ring
[ring_index
+ 1]) & 0xfffffff;
2777 case 1: /* D1 vblank/vline */
2779 case 0: /* D1 vblank */
2780 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& LB_D1_VBLANK_INTERRUPT
) {
2781 if (rdev
->irq
.crtc_vblank_int
[0]) {
2782 drm_handle_vblank(rdev
->ddev
, 0);
2783 rdev
->pm
.vblank_sync
= true;
2784 wake_up(&rdev
->irq
.vblank_queue
);
2786 if (rdev
->irq
.pflip
[0])
2787 radeon_crtc_handle_flip(rdev
, 0);
2788 rdev
->irq
.stat_regs
.evergreen
.disp_int
&= ~LB_D1_VBLANK_INTERRUPT
;
2789 DRM_DEBUG("IH: D1 vblank\n");
2792 case 1: /* D1 vline */
2793 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& LB_D1_VLINE_INTERRUPT
) {
2794 rdev
->irq
.stat_regs
.evergreen
.disp_int
&= ~LB_D1_VLINE_INTERRUPT
;
2795 DRM_DEBUG("IH: D1 vline\n");
2799 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2803 case 2: /* D2 vblank/vline */
2805 case 0: /* D2 vblank */
2806 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& LB_D2_VBLANK_INTERRUPT
) {
2807 if (rdev
->irq
.crtc_vblank_int
[1]) {
2808 drm_handle_vblank(rdev
->ddev
, 1);
2809 rdev
->pm
.vblank_sync
= true;
2810 wake_up(&rdev
->irq
.vblank_queue
);
2812 if (rdev
->irq
.pflip
[1])
2813 radeon_crtc_handle_flip(rdev
, 1);
2814 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
&= ~LB_D2_VBLANK_INTERRUPT
;
2815 DRM_DEBUG("IH: D2 vblank\n");
2818 case 1: /* D2 vline */
2819 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& LB_D2_VLINE_INTERRUPT
) {
2820 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
&= ~LB_D2_VLINE_INTERRUPT
;
2821 DRM_DEBUG("IH: D2 vline\n");
2825 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2829 case 3: /* D3 vblank/vline */
2831 case 0: /* D3 vblank */
2832 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& LB_D3_VBLANK_INTERRUPT
) {
2833 if (rdev
->irq
.crtc_vblank_int
[2]) {
2834 drm_handle_vblank(rdev
->ddev
, 2);
2835 rdev
->pm
.vblank_sync
= true;
2836 wake_up(&rdev
->irq
.vblank_queue
);
2838 if (rdev
->irq
.pflip
[2])
2839 radeon_crtc_handle_flip(rdev
, 2);
2840 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
&= ~LB_D3_VBLANK_INTERRUPT
;
2841 DRM_DEBUG("IH: D3 vblank\n");
2844 case 1: /* D3 vline */
2845 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& LB_D3_VLINE_INTERRUPT
) {
2846 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
&= ~LB_D3_VLINE_INTERRUPT
;
2847 DRM_DEBUG("IH: D3 vline\n");
2851 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2855 case 4: /* D4 vblank/vline */
2857 case 0: /* D4 vblank */
2858 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& LB_D4_VBLANK_INTERRUPT
) {
2859 if (rdev
->irq
.crtc_vblank_int
[3]) {
2860 drm_handle_vblank(rdev
->ddev
, 3);
2861 rdev
->pm
.vblank_sync
= true;
2862 wake_up(&rdev
->irq
.vblank_queue
);
2864 if (rdev
->irq
.pflip
[3])
2865 radeon_crtc_handle_flip(rdev
, 3);
2866 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
&= ~LB_D4_VBLANK_INTERRUPT
;
2867 DRM_DEBUG("IH: D4 vblank\n");
2870 case 1: /* D4 vline */
2871 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& LB_D4_VLINE_INTERRUPT
) {
2872 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
&= ~LB_D4_VLINE_INTERRUPT
;
2873 DRM_DEBUG("IH: D4 vline\n");
2877 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2881 case 5: /* D5 vblank/vline */
2883 case 0: /* D5 vblank */
2884 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& LB_D5_VBLANK_INTERRUPT
) {
2885 if (rdev
->irq
.crtc_vblank_int
[4]) {
2886 drm_handle_vblank(rdev
->ddev
, 4);
2887 rdev
->pm
.vblank_sync
= true;
2888 wake_up(&rdev
->irq
.vblank_queue
);
2890 if (rdev
->irq
.pflip
[4])
2891 radeon_crtc_handle_flip(rdev
, 4);
2892 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
&= ~LB_D5_VBLANK_INTERRUPT
;
2893 DRM_DEBUG("IH: D5 vblank\n");
2896 case 1: /* D5 vline */
2897 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& LB_D5_VLINE_INTERRUPT
) {
2898 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
&= ~LB_D5_VLINE_INTERRUPT
;
2899 DRM_DEBUG("IH: D5 vline\n");
2903 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2907 case 6: /* D6 vblank/vline */
2909 case 0: /* D6 vblank */
2910 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& LB_D6_VBLANK_INTERRUPT
) {
2911 if (rdev
->irq
.crtc_vblank_int
[5]) {
2912 drm_handle_vblank(rdev
->ddev
, 5);
2913 rdev
->pm
.vblank_sync
= true;
2914 wake_up(&rdev
->irq
.vblank_queue
);
2916 if (rdev
->irq
.pflip
[5])
2917 radeon_crtc_handle_flip(rdev
, 5);
2918 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
&= ~LB_D6_VBLANK_INTERRUPT
;
2919 DRM_DEBUG("IH: D6 vblank\n");
2922 case 1: /* D6 vline */
2923 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& LB_D6_VLINE_INTERRUPT
) {
2924 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
&= ~LB_D6_VLINE_INTERRUPT
;
2925 DRM_DEBUG("IH: D6 vline\n");
2929 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2933 case 42: /* HPD hotplug */
2936 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& DC_HPD1_INTERRUPT
) {
2937 rdev
->irq
.stat_regs
.evergreen
.disp_int
&= ~DC_HPD1_INTERRUPT
;
2938 queue_hotplug
= true;
2939 DRM_DEBUG("IH: HPD1\n");
2943 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& DC_HPD2_INTERRUPT
) {
2944 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
&= ~DC_HPD2_INTERRUPT
;
2945 queue_hotplug
= true;
2946 DRM_DEBUG("IH: HPD2\n");
2950 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& DC_HPD3_INTERRUPT
) {
2951 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
&= ~DC_HPD3_INTERRUPT
;
2952 queue_hotplug
= true;
2953 DRM_DEBUG("IH: HPD3\n");
2957 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& DC_HPD4_INTERRUPT
) {
2958 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
&= ~DC_HPD4_INTERRUPT
;
2959 queue_hotplug
= true;
2960 DRM_DEBUG("IH: HPD4\n");
2964 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& DC_HPD5_INTERRUPT
) {
2965 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
&= ~DC_HPD5_INTERRUPT
;
2966 queue_hotplug
= true;
2967 DRM_DEBUG("IH: HPD5\n");
2971 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& DC_HPD6_INTERRUPT
) {
2972 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
&= ~DC_HPD6_INTERRUPT
;
2973 queue_hotplug
= true;
2974 DRM_DEBUG("IH: HPD6\n");
2978 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2982 case 176: /* CP_INT in ring buffer */
2983 case 177: /* CP_INT in IB1 */
2984 case 178: /* CP_INT in IB2 */
2985 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data
);
2986 radeon_fence_process(rdev
);
2988 case 181: /* CP EOP event */
2989 DRM_DEBUG("IH: CP EOP\n");
2990 radeon_fence_process(rdev
);
2992 case 233: /* GUI IDLE */
2993 DRM_DEBUG("IH: GUI idle\n");
2994 rdev
->pm
.gui_idle
= true;
2995 wake_up(&rdev
->irq
.idle_queue
);
2998 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3002 /* wptr/rptr are in bytes! */
3004 rptr
&= rdev
->ih
.ptr_mask
;
3006 /* make sure wptr hasn't changed while processing */
3007 wptr
= evergreen_get_ih_wptr(rdev
);
3008 if (wptr
!= rdev
->ih
.wptr
)
3011 schedule_work(&rdev
->hotplug_work
);
3012 rdev
->ih
.rptr
= rptr
;
3013 WREG32(IH_RB_RPTR
, rdev
->ih
.rptr
);
3014 spin_unlock_irqrestore(&rdev
->ih
.lock
, flags
);
3018 static int evergreen_startup(struct radeon_device
*rdev
)
3022 /* enable pcie gen2 link */
3023 if (!ASIC_IS_DCE5(rdev
))
3024 evergreen_pcie_gen2_enable(rdev
);
3026 if (ASIC_IS_DCE5(rdev
)) {
3027 if (!rdev
->me_fw
|| !rdev
->pfp_fw
|| !rdev
->rlc_fw
|| !rdev
->mc_fw
) {
3028 r
= ni_init_microcode(rdev
);
3030 DRM_ERROR("Failed to load firmware!\n");
3034 r
= ni_mc_load_microcode(rdev
);
3036 DRM_ERROR("Failed to load MC firmware!\n");
3040 if (!rdev
->me_fw
|| !rdev
->pfp_fw
|| !rdev
->rlc_fw
) {
3041 r
= r600_init_microcode(rdev
);
3043 DRM_ERROR("Failed to load firmware!\n");
3049 evergreen_mc_program(rdev
);
3050 if (rdev
->flags
& RADEON_IS_AGP
) {
3051 evergreen_agp_enable(rdev
);
3053 r
= evergreen_pcie_gart_enable(rdev
);
3057 evergreen_gpu_init(rdev
);
3059 r
= evergreen_blit_init(rdev
);
3061 evergreen_blit_fini(rdev
);
3062 rdev
->asic
->copy
= NULL
;
3063 dev_warn(rdev
->dev
, "failed blitter (%d) falling back to memcpy\n", r
);
3066 /* allocate wb buffer */
3067 r
= radeon_wb_init(rdev
);
3072 r
= r600_irq_init(rdev
);
3074 DRM_ERROR("radeon: IH init failed (%d).\n", r
);
3075 radeon_irq_kms_fini(rdev
);
3078 evergreen_irq_set(rdev
);
3080 r
= radeon_ring_init(rdev
, rdev
->cp
.ring_size
);
3083 r
= evergreen_cp_load_microcode(rdev
);
3086 r
= evergreen_cp_resume(rdev
);
3093 int evergreen_resume(struct radeon_device
*rdev
)
3097 /* reset the asic, the gfx blocks are often in a bad state
3098 * after the driver is unloaded or after a resume
3100 if (radeon_asic_reset(rdev
))
3101 dev_warn(rdev
->dev
, "GPU reset failed !\n");
3102 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3103 * posting will perform necessary task to bring back GPU into good
3107 atom_asic_init(rdev
->mode_info
.atom_context
);
3109 r
= evergreen_startup(rdev
);
3111 DRM_ERROR("evergreen startup failed on resume\n");
3115 r
= r600_ib_test(rdev
);
3117 DRM_ERROR("radeon: failed testing IB (%d).\n", r
);
3125 int evergreen_suspend(struct radeon_device
*rdev
)
3129 /* FIXME: we should wait for ring to be empty */
3131 rdev
->cp
.ready
= false;
3132 evergreen_irq_suspend(rdev
);
3133 radeon_wb_disable(rdev
);
3134 evergreen_pcie_gart_disable(rdev
);
3136 /* unpin shaders bo */
3137 r
= radeon_bo_reserve(rdev
->r600_blit
.shader_obj
, false);
3138 if (likely(r
== 0)) {
3139 radeon_bo_unpin(rdev
->r600_blit
.shader_obj
);
3140 radeon_bo_unreserve(rdev
->r600_blit
.shader_obj
);
3146 int evergreen_copy_blit(struct radeon_device
*rdev
,
3147 uint64_t src_offset
, uint64_t dst_offset
,
3148 unsigned num_pages
, struct radeon_fence
*fence
)
3152 mutex_lock(&rdev
->r600_blit
.mutex
);
3153 rdev
->r600_blit
.vb_ib
= NULL
;
3154 r
= evergreen_blit_prepare_copy(rdev
, num_pages
* RADEON_GPU_PAGE_SIZE
);
3156 if (rdev
->r600_blit
.vb_ib
)
3157 radeon_ib_free(rdev
, &rdev
->r600_blit
.vb_ib
);
3158 mutex_unlock(&rdev
->r600_blit
.mutex
);
3161 evergreen_kms_blit_copy(rdev
, src_offset
, dst_offset
, num_pages
* RADEON_GPU_PAGE_SIZE
);
3162 evergreen_blit_done_copy(rdev
, fence
);
3163 mutex_unlock(&rdev
->r600_blit
.mutex
);
3167 /* Plan is to move initialization in that function and use
3168 * helper function so that radeon_device_init pretty much
3169 * do nothing more than calling asic specific function. This
3170 * should also allow to remove a bunch of callback function
3173 int evergreen_init(struct radeon_device
*rdev
)
3177 /* This don't do much */
3178 r
= radeon_gem_init(rdev
);
3182 if (!radeon_get_bios(rdev
)) {
3183 if (ASIC_IS_AVIVO(rdev
))
3186 /* Must be an ATOMBIOS */
3187 if (!rdev
->is_atom_bios
) {
3188 dev_err(rdev
->dev
, "Expecting atombios for evergreen GPU\n");
3191 r
= radeon_atombios_init(rdev
);
3194 /* reset the asic, the gfx blocks are often in a bad state
3195 * after the driver is unloaded or after a resume
3197 if (radeon_asic_reset(rdev
))
3198 dev_warn(rdev
->dev
, "GPU reset failed !\n");
3199 /* Post card if necessary */
3200 if (!radeon_card_posted(rdev
)) {
3202 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
3205 DRM_INFO("GPU not posted. posting now...\n");
3206 atom_asic_init(rdev
->mode_info
.atom_context
);
3208 /* Initialize scratch registers */
3209 r600_scratch_init(rdev
);
3210 /* Initialize surface registers */
3211 radeon_surface_init(rdev
);
3212 /* Initialize clocks */
3213 radeon_get_clock_info(rdev
->ddev
);
3215 r
= radeon_fence_driver_init(rdev
);
3218 /* initialize AGP */
3219 if (rdev
->flags
& RADEON_IS_AGP
) {
3220 r
= radeon_agp_init(rdev
);
3222 radeon_agp_disable(rdev
);
3224 /* initialize memory controller */
3225 r
= evergreen_mc_init(rdev
);
3228 /* Memory manager */
3229 r
= radeon_bo_init(rdev
);
3233 r
= radeon_irq_kms_init(rdev
);
3237 rdev
->cp
.ring_obj
= NULL
;
3238 r600_ring_init(rdev
, 1024 * 1024);
3240 rdev
->ih
.ring_obj
= NULL
;
3241 r600_ih_ring_init(rdev
, 64 * 1024);
3243 r
= r600_pcie_gart_init(rdev
);
3247 rdev
->accel_working
= true;
3248 r
= evergreen_startup(rdev
);
3250 dev_err(rdev
->dev
, "disabling GPU acceleration\n");
3252 r600_irq_fini(rdev
);
3253 radeon_wb_fini(rdev
);
3254 radeon_irq_kms_fini(rdev
);
3255 evergreen_pcie_gart_fini(rdev
);
3256 rdev
->accel_working
= false;
3258 if (rdev
->accel_working
) {
3259 r
= radeon_ib_pool_init(rdev
);
3261 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r
);
3262 rdev
->accel_working
= false;
3264 r
= r600_ib_test(rdev
);
3266 DRM_ERROR("radeon: failed testing IB (%d).\n", r
);
3267 rdev
->accel_working
= false;
3273 void evergreen_fini(struct radeon_device
*rdev
)
3275 evergreen_blit_fini(rdev
);
3277 r600_irq_fini(rdev
);
3278 radeon_wb_fini(rdev
);
3279 radeon_ib_pool_fini(rdev
);
3280 radeon_irq_kms_fini(rdev
);
3281 evergreen_pcie_gart_fini(rdev
);
3282 radeon_gem_fini(rdev
);
3283 radeon_fence_driver_fini(rdev
);
3284 radeon_agp_fini(rdev
);
3285 radeon_bo_fini(rdev
);
3286 radeon_atombios_fini(rdev
);
3291 static void evergreen_pcie_gen2_enable(struct radeon_device
*rdev
)
3293 u32 link_width_cntl
, speed_cntl
;
3295 if (radeon_pcie_gen2
== 0)
3298 if (rdev
->flags
& RADEON_IS_IGP
)
3301 if (!(rdev
->flags
& RADEON_IS_PCIE
))
3304 /* x2 cards have a special sequence */
3305 if (ASIC_IS_X2(rdev
))
3308 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3309 if ((speed_cntl
& LC_OTHER_SIDE_EVER_SENT_GEN2
) ||
3310 (speed_cntl
& LC_OTHER_SIDE_SUPPORTS_GEN2
)) {
3312 link_width_cntl
= RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
);
3313 link_width_cntl
&= ~LC_UPCONFIGURE_DIS
;
3314 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
3316 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3317 speed_cntl
&= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN
;
3318 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3320 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3321 speed_cntl
|= LC_CLR_FAILED_SPD_CHANGE_CNT
;
3322 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3324 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3325 speed_cntl
&= ~LC_CLR_FAILED_SPD_CHANGE_CNT
;
3326 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3328 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3329 speed_cntl
|= LC_GEN2_EN_STRAP
;
3330 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3333 link_width_cntl
= RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
);
3334 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3336 link_width_cntl
|= LC_UPCONFIGURE_DIS
;
3338 link_width_cntl
&= ~LC_UPCONFIGURE_DIS
;
3339 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);