2 * Copyright 2010 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
29 #include "radeon_asic.h"
30 #include "radeon_drm.h"
31 #include "evergreend.h"
34 #include "evergreen_reg.h"
35 #include "evergreen_blit_shaders.h"
37 #define EVERGREEN_PFP_UCODE_SIZE 1120
38 #define EVERGREEN_PM4_UCODE_SIZE 1376
40 static void evergreen_gpu_init(struct radeon_device
*rdev
);
41 void evergreen_fini(struct radeon_device
*rdev
);
42 void evergreen_pcie_gen2_enable(struct radeon_device
*rdev
);
43 extern void cayman_cp_int_cntl_setup(struct radeon_device
*rdev
,
44 int ring
, u32 cp_int_cntl
);
46 void evergreen_tiling_fields(unsigned tiling_flags
, unsigned *bankw
,
47 unsigned *bankh
, unsigned *mtaspect
,
50 *bankw
= (tiling_flags
>> RADEON_TILING_EG_BANKW_SHIFT
) & RADEON_TILING_EG_BANKW_MASK
;
51 *bankh
= (tiling_flags
>> RADEON_TILING_EG_BANKH_SHIFT
) & RADEON_TILING_EG_BANKH_MASK
;
52 *mtaspect
= (tiling_flags
>> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT
) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK
;
53 *tile_split
= (tiling_flags
>> RADEON_TILING_EG_TILE_SPLIT_SHIFT
) & RADEON_TILING_EG_TILE_SPLIT_MASK
;
56 case 1: *bankw
= EVERGREEN_ADDR_SURF_BANK_WIDTH_1
; break;
57 case 2: *bankw
= EVERGREEN_ADDR_SURF_BANK_WIDTH_2
; break;
58 case 4: *bankw
= EVERGREEN_ADDR_SURF_BANK_WIDTH_4
; break;
59 case 8: *bankw
= EVERGREEN_ADDR_SURF_BANK_WIDTH_8
; break;
63 case 1: *bankh
= EVERGREEN_ADDR_SURF_BANK_HEIGHT_1
; break;
64 case 2: *bankh
= EVERGREEN_ADDR_SURF_BANK_HEIGHT_2
; break;
65 case 4: *bankh
= EVERGREEN_ADDR_SURF_BANK_HEIGHT_4
; break;
66 case 8: *bankh
= EVERGREEN_ADDR_SURF_BANK_HEIGHT_8
; break;
70 case 1: *mtaspect
= EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1
; break;
71 case 2: *mtaspect
= EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2
; break;
72 case 4: *mtaspect
= EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4
; break;
73 case 8: *mtaspect
= EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8
; break;
77 void evergreen_fix_pci_max_read_req_size(struct radeon_device
*rdev
)
82 cap
= pci_pcie_cap(rdev
->pdev
);
86 err
= pci_read_config_word(rdev
->pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
90 v
= (ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12;
92 /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
93 * to avoid hangs or perfomance issues
95 if ((v
== 0) || (v
== 6) || (v
== 7)) {
96 ctl
&= ~PCI_EXP_DEVCTL_READRQ
;
98 pci_write_config_word(rdev
->pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
103 * dce4_wait_for_vblank - vblank wait asic callback.
105 * @rdev: radeon_device pointer
106 * @crtc: crtc to wait for vblank on
108 * Wait for vblank on the requested crtc (evergreen+).
110 void dce4_wait_for_vblank(struct radeon_device
*rdev
, int crtc
)
112 struct radeon_crtc
*radeon_crtc
= rdev
->mode_info
.crtcs
[crtc
];
115 if (RREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
) & EVERGREEN_CRTC_MASTER_EN
) {
116 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
117 if (!(RREG32(EVERGREEN_CRTC_STATUS
+ radeon_crtc
->crtc_offset
) & EVERGREEN_CRTC_V_BLANK
))
121 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
122 if (RREG32(EVERGREEN_CRTC_STATUS
+ radeon_crtc
->crtc_offset
) & EVERGREEN_CRTC_V_BLANK
)
130 * radeon_irq_kms_pflip_irq_get - pre-pageflip callback.
132 * @rdev: radeon_device pointer
133 * @crtc: crtc to prepare for pageflip on
135 * Pre-pageflip callback (evergreen+).
136 * Enables the pageflip irq (vblank irq).
138 void evergreen_pre_page_flip(struct radeon_device
*rdev
, int crtc
)
140 /* enable the pflip int */
141 radeon_irq_kms_pflip_irq_get(rdev
, crtc
);
145 * evergreen_post_page_flip - pos-pageflip callback.
147 * @rdev: radeon_device pointer
148 * @crtc: crtc to cleanup pageflip on
150 * Post-pageflip callback (evergreen+).
151 * Disables the pageflip irq (vblank irq).
153 void evergreen_post_page_flip(struct radeon_device
*rdev
, int crtc
)
155 /* disable the pflip int */
156 radeon_irq_kms_pflip_irq_put(rdev
, crtc
);
160 * evergreen_page_flip - pageflip callback.
162 * @rdev: radeon_device pointer
163 * @crtc_id: crtc to cleanup pageflip on
164 * @crtc_base: new address of the crtc (GPU MC address)
166 * Does the actual pageflip (evergreen+).
167 * During vblank we take the crtc lock and wait for the update_pending
168 * bit to go high, when it does, we release the lock, and allow the
169 * double buffered update to take place.
170 * Returns the current update pending status.
172 u32
evergreen_page_flip(struct radeon_device
*rdev
, int crtc_id
, u64 crtc_base
)
174 struct radeon_crtc
*radeon_crtc
= rdev
->mode_info
.crtcs
[crtc_id
];
175 u32 tmp
= RREG32(EVERGREEN_GRPH_UPDATE
+ radeon_crtc
->crtc_offset
);
178 /* Lock the graphics update lock */
179 tmp
|= EVERGREEN_GRPH_UPDATE_LOCK
;
180 WREG32(EVERGREEN_GRPH_UPDATE
+ radeon_crtc
->crtc_offset
, tmp
);
182 /* update the scanout addresses */
183 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ radeon_crtc
->crtc_offset
,
184 upper_32_bits(crtc_base
));
185 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ radeon_crtc
->crtc_offset
,
188 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ radeon_crtc
->crtc_offset
,
189 upper_32_bits(crtc_base
));
190 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ radeon_crtc
->crtc_offset
,
193 /* Wait for update_pending to go high. */
194 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
195 if (RREG32(EVERGREEN_GRPH_UPDATE
+ radeon_crtc
->crtc_offset
) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING
)
199 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
201 /* Unlock the lock, so double-buffering can take place inside vblank */
202 tmp
&= ~EVERGREEN_GRPH_UPDATE_LOCK
;
203 WREG32(EVERGREEN_GRPH_UPDATE
+ radeon_crtc
->crtc_offset
, tmp
);
205 /* Return current update_pending status: */
206 return RREG32(EVERGREEN_GRPH_UPDATE
+ radeon_crtc
->crtc_offset
) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING
;
209 /* get temperature in millidegrees */
210 int evergreen_get_temp(struct radeon_device
*rdev
)
215 if (rdev
->family
== CHIP_JUNIPER
) {
216 toffset
= (RREG32(CG_THERMAL_CTRL
) & TOFFSET_MASK
) >>
218 temp
= (RREG32(CG_TS0_STATUS
) & TS0_ADC_DOUT_MASK
) >>
222 actual_temp
= temp
/ 2 - (0x200 - toffset
);
224 actual_temp
= temp
/ 2 + toffset
;
226 actual_temp
= actual_temp
* 1000;
229 temp
= (RREG32(CG_MULT_THERMAL_STATUS
) & ASIC_T_MASK
) >>
234 else if (temp
& 0x200)
236 else if (temp
& 0x100) {
237 actual_temp
= temp
& 0x1ff;
238 actual_temp
|= ~0x1ff;
240 actual_temp
= temp
& 0xff;
242 actual_temp
= (actual_temp
* 1000) / 2;
248 int sumo_get_temp(struct radeon_device
*rdev
)
250 u32 temp
= RREG32(CG_THERMAL_STATUS
) & 0xff;
251 int actual_temp
= temp
- 49;
253 return actual_temp
* 1000;
257 * sumo_pm_init_profile - Initialize power profiles callback.
259 * @rdev: radeon_device pointer
261 * Initialize the power states used in profile mode
262 * (sumo, trinity, SI).
263 * Used for profile mode only.
265 void sumo_pm_init_profile(struct radeon_device
*rdev
)
270 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
271 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
272 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
273 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 0;
276 if (rdev
->flags
& RADEON_IS_MOBILITY
)
277 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_BATTERY
, 0);
279 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 0);
281 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= idx
;
282 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= idx
;
283 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
284 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
286 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= idx
;
287 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= idx
;
288 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
289 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
291 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= idx
;
292 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= idx
;
293 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
294 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 0;
296 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= idx
;
297 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= idx
;
298 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
299 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 0;
302 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 0);
303 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= idx
;
304 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= idx
;
305 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
306 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
=
307 rdev
->pm
.power_state
[idx
].num_clock_modes
- 1;
309 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= idx
;
310 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= idx
;
311 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
312 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
=
313 rdev
->pm
.power_state
[idx
].num_clock_modes
- 1;
317 * evergreen_pm_misc - set additional pm hw parameters callback.
319 * @rdev: radeon_device pointer
321 * Set non-clock parameters associated with a power state
322 * (voltage, etc.) (evergreen+).
324 void evergreen_pm_misc(struct radeon_device
*rdev
)
326 int req_ps_idx
= rdev
->pm
.requested_power_state_index
;
327 int req_cm_idx
= rdev
->pm
.requested_clock_mode_index
;
328 struct radeon_power_state
*ps
= &rdev
->pm
.power_state
[req_ps_idx
];
329 struct radeon_voltage
*voltage
= &ps
->clock_info
[req_cm_idx
].voltage
;
331 if (voltage
->type
== VOLTAGE_SW
) {
332 /* 0xff01 is a flag rather then an actual voltage */
333 if (voltage
->voltage
== 0xff01)
335 if (voltage
->voltage
&& (voltage
->voltage
!= rdev
->pm
.current_vddc
)) {
336 radeon_atom_set_voltage(rdev
, voltage
->voltage
, SET_VOLTAGE_TYPE_ASIC_VDDC
);
337 rdev
->pm
.current_vddc
= voltage
->voltage
;
338 DRM_DEBUG("Setting: vddc: %d\n", voltage
->voltage
);
340 /* 0xff01 is a flag rather then an actual voltage */
341 if (voltage
->vddci
== 0xff01)
343 if (voltage
->vddci
&& (voltage
->vddci
!= rdev
->pm
.current_vddci
)) {
344 radeon_atom_set_voltage(rdev
, voltage
->vddci
, SET_VOLTAGE_TYPE_ASIC_VDDCI
);
345 rdev
->pm
.current_vddci
= voltage
->vddci
;
346 DRM_DEBUG("Setting: vddci: %d\n", voltage
->vddci
);
352 * evergreen_pm_prepare - pre-power state change callback.
354 * @rdev: radeon_device pointer
356 * Prepare for a power state change (evergreen+).
358 void evergreen_pm_prepare(struct radeon_device
*rdev
)
360 struct drm_device
*ddev
= rdev
->ddev
;
361 struct drm_crtc
*crtc
;
362 struct radeon_crtc
*radeon_crtc
;
365 /* disable any active CRTCs */
366 list_for_each_entry(crtc
, &ddev
->mode_config
.crtc_list
, head
) {
367 radeon_crtc
= to_radeon_crtc(crtc
);
368 if (radeon_crtc
->enabled
) {
369 tmp
= RREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
);
370 tmp
|= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE
;
371 WREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
, tmp
);
377 * evergreen_pm_finish - post-power state change callback.
379 * @rdev: radeon_device pointer
381 * Clean up after a power state change (evergreen+).
383 void evergreen_pm_finish(struct radeon_device
*rdev
)
385 struct drm_device
*ddev
= rdev
->ddev
;
386 struct drm_crtc
*crtc
;
387 struct radeon_crtc
*radeon_crtc
;
390 /* enable any active CRTCs */
391 list_for_each_entry(crtc
, &ddev
->mode_config
.crtc_list
, head
) {
392 radeon_crtc
= to_radeon_crtc(crtc
);
393 if (radeon_crtc
->enabled
) {
394 tmp
= RREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
);
395 tmp
&= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE
;
396 WREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
, tmp
);
402 * evergreen_hpd_sense - hpd sense callback.
404 * @rdev: radeon_device pointer
405 * @hpd: hpd (hotplug detect) pin
407 * Checks if a digital monitor is connected (evergreen+).
408 * Returns true if connected, false if not connected.
410 bool evergreen_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
)
412 bool connected
= false;
416 if (RREG32(DC_HPD1_INT_STATUS
) & DC_HPDx_SENSE
)
420 if (RREG32(DC_HPD2_INT_STATUS
) & DC_HPDx_SENSE
)
424 if (RREG32(DC_HPD3_INT_STATUS
) & DC_HPDx_SENSE
)
428 if (RREG32(DC_HPD4_INT_STATUS
) & DC_HPDx_SENSE
)
432 if (RREG32(DC_HPD5_INT_STATUS
) & DC_HPDx_SENSE
)
436 if (RREG32(DC_HPD6_INT_STATUS
) & DC_HPDx_SENSE
)
447 * evergreen_hpd_set_polarity - hpd set polarity callback.
449 * @rdev: radeon_device pointer
450 * @hpd: hpd (hotplug detect) pin
452 * Set the polarity of the hpd pin (evergreen+).
454 void evergreen_hpd_set_polarity(struct radeon_device
*rdev
,
455 enum radeon_hpd_id hpd
)
458 bool connected
= evergreen_hpd_sense(rdev
, hpd
);
462 tmp
= RREG32(DC_HPD1_INT_CONTROL
);
464 tmp
&= ~DC_HPDx_INT_POLARITY
;
466 tmp
|= DC_HPDx_INT_POLARITY
;
467 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
470 tmp
= RREG32(DC_HPD2_INT_CONTROL
);
472 tmp
&= ~DC_HPDx_INT_POLARITY
;
474 tmp
|= DC_HPDx_INT_POLARITY
;
475 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
478 tmp
= RREG32(DC_HPD3_INT_CONTROL
);
480 tmp
&= ~DC_HPDx_INT_POLARITY
;
482 tmp
|= DC_HPDx_INT_POLARITY
;
483 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
486 tmp
= RREG32(DC_HPD4_INT_CONTROL
);
488 tmp
&= ~DC_HPDx_INT_POLARITY
;
490 tmp
|= DC_HPDx_INT_POLARITY
;
491 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
494 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
496 tmp
&= ~DC_HPDx_INT_POLARITY
;
498 tmp
|= DC_HPDx_INT_POLARITY
;
499 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
502 tmp
= RREG32(DC_HPD6_INT_CONTROL
);
504 tmp
&= ~DC_HPDx_INT_POLARITY
;
506 tmp
|= DC_HPDx_INT_POLARITY
;
507 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
515 * evergreen_hpd_init - hpd setup callback.
517 * @rdev: radeon_device pointer
519 * Setup the hpd pins used by the card (evergreen+).
520 * Enable the pin, set the polarity, and enable the hpd interrupts.
522 void evergreen_hpd_init(struct radeon_device
*rdev
)
524 struct drm_device
*dev
= rdev
->ddev
;
525 struct drm_connector
*connector
;
526 unsigned enabled
= 0;
527 u32 tmp
= DC_HPDx_CONNECTION_TIMER(0x9c4) |
528 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN
;
530 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
531 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
532 switch (radeon_connector
->hpd
.hpd
) {
534 WREG32(DC_HPD1_CONTROL
, tmp
);
537 WREG32(DC_HPD2_CONTROL
, tmp
);
540 WREG32(DC_HPD3_CONTROL
, tmp
);
543 WREG32(DC_HPD4_CONTROL
, tmp
);
546 WREG32(DC_HPD5_CONTROL
, tmp
);
549 WREG32(DC_HPD6_CONTROL
, tmp
);
554 radeon_hpd_set_polarity(rdev
, radeon_connector
->hpd
.hpd
);
555 enabled
|= 1 << radeon_connector
->hpd
.hpd
;
557 radeon_irq_kms_enable_hpd(rdev
, enabled
);
561 * evergreen_hpd_fini - hpd tear down callback.
563 * @rdev: radeon_device pointer
565 * Tear down the hpd pins used by the card (evergreen+).
566 * Disable the hpd interrupts.
568 void evergreen_hpd_fini(struct radeon_device
*rdev
)
570 struct drm_device
*dev
= rdev
->ddev
;
571 struct drm_connector
*connector
;
572 unsigned disabled
= 0;
574 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
575 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
576 switch (radeon_connector
->hpd
.hpd
) {
578 WREG32(DC_HPD1_CONTROL
, 0);
581 WREG32(DC_HPD2_CONTROL
, 0);
584 WREG32(DC_HPD3_CONTROL
, 0);
587 WREG32(DC_HPD4_CONTROL
, 0);
590 WREG32(DC_HPD5_CONTROL
, 0);
593 WREG32(DC_HPD6_CONTROL
, 0);
598 disabled
|= 1 << radeon_connector
->hpd
.hpd
;
600 radeon_irq_kms_disable_hpd(rdev
, disabled
);
603 /* watermark setup */
605 static u32
evergreen_line_buffer_adjust(struct radeon_device
*rdev
,
606 struct radeon_crtc
*radeon_crtc
,
607 struct drm_display_mode
*mode
,
608 struct drm_display_mode
*other_mode
)
613 * There are 3 line buffers, each one shared by 2 display controllers.
614 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
615 * the display controllers. The paritioning is done via one of four
616 * preset allocations specified in bits 2:0:
617 * first display controller
618 * 0 - first half of lb (3840 * 2)
619 * 1 - first 3/4 of lb (5760 * 2)
620 * 2 - whole lb (7680 * 2), other crtc must be disabled
621 * 3 - first 1/4 of lb (1920 * 2)
622 * second display controller
623 * 4 - second half of lb (3840 * 2)
624 * 5 - second 3/4 of lb (5760 * 2)
625 * 6 - whole lb (7680 * 2), other crtc must be disabled
626 * 7 - last 1/4 of lb (1920 * 2)
628 /* this can get tricky if we have two large displays on a paired group
629 * of crtcs. Ideally for multiple large displays we'd assign them to
630 * non-linked crtcs for maximum line buffer allocation.
632 if (radeon_crtc
->base
.enabled
&& mode
) {
640 /* second controller of the pair uses second half of the lb */
641 if (radeon_crtc
->crtc_id
% 2)
643 WREG32(DC_LB_MEMORY_SPLIT
+ radeon_crtc
->crtc_offset
, tmp
);
645 if (radeon_crtc
->base
.enabled
&& mode
) {
650 if (ASIC_IS_DCE5(rdev
))
656 if (ASIC_IS_DCE5(rdev
))
662 if (ASIC_IS_DCE5(rdev
))
668 if (ASIC_IS_DCE5(rdev
))
675 /* controller not enabled, so no lb used */
679 u32
evergreen_get_number_of_dram_channels(struct radeon_device
*rdev
)
681 u32 tmp
= RREG32(MC_SHARED_CHMAP
);
683 switch ((tmp
& NOOFCHAN_MASK
) >> NOOFCHAN_SHIFT
) {
696 struct evergreen_wm_params
{
697 u32 dram_channels
; /* number of dram channels */
698 u32 yclk
; /* bandwidth per dram data pin in kHz */
699 u32 sclk
; /* engine clock in kHz */
700 u32 disp_clk
; /* display clock in kHz */
701 u32 src_width
; /* viewport width */
702 u32 active_time
; /* active display time in ns */
703 u32 blank_time
; /* blank time in ns */
704 bool interlaced
; /* mode is interlaced */
705 fixed20_12 vsc
; /* vertical scale ratio */
706 u32 num_heads
; /* number of active crtcs */
707 u32 bytes_per_pixel
; /* bytes per pixel display + overlay */
708 u32 lb_size
; /* line buffer allocated to pipe */
709 u32 vtaps
; /* vertical scaler taps */
712 static u32
evergreen_dram_bandwidth(struct evergreen_wm_params
*wm
)
714 /* Calculate DRAM Bandwidth and the part allocated to display. */
715 fixed20_12 dram_efficiency
; /* 0.7 */
716 fixed20_12 yclk
, dram_channels
, bandwidth
;
719 a
.full
= dfixed_const(1000);
720 yclk
.full
= dfixed_const(wm
->yclk
);
721 yclk
.full
= dfixed_div(yclk
, a
);
722 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
723 a
.full
= dfixed_const(10);
724 dram_efficiency
.full
= dfixed_const(7);
725 dram_efficiency
.full
= dfixed_div(dram_efficiency
, a
);
726 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
727 bandwidth
.full
= dfixed_mul(bandwidth
, dram_efficiency
);
729 return dfixed_trunc(bandwidth
);
732 static u32
evergreen_dram_bandwidth_for_display(struct evergreen_wm_params
*wm
)
734 /* Calculate DRAM Bandwidth and the part allocated to display. */
735 fixed20_12 disp_dram_allocation
; /* 0.3 to 0.7 */
736 fixed20_12 yclk
, dram_channels
, bandwidth
;
739 a
.full
= dfixed_const(1000);
740 yclk
.full
= dfixed_const(wm
->yclk
);
741 yclk
.full
= dfixed_div(yclk
, a
);
742 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
743 a
.full
= dfixed_const(10);
744 disp_dram_allocation
.full
= dfixed_const(3); /* XXX worse case value 0.3 */
745 disp_dram_allocation
.full
= dfixed_div(disp_dram_allocation
, a
);
746 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
747 bandwidth
.full
= dfixed_mul(bandwidth
, disp_dram_allocation
);
749 return dfixed_trunc(bandwidth
);
752 static u32
evergreen_data_return_bandwidth(struct evergreen_wm_params
*wm
)
754 /* Calculate the display Data return Bandwidth */
755 fixed20_12 return_efficiency
; /* 0.8 */
756 fixed20_12 sclk
, bandwidth
;
759 a
.full
= dfixed_const(1000);
760 sclk
.full
= dfixed_const(wm
->sclk
);
761 sclk
.full
= dfixed_div(sclk
, a
);
762 a
.full
= dfixed_const(10);
763 return_efficiency
.full
= dfixed_const(8);
764 return_efficiency
.full
= dfixed_div(return_efficiency
, a
);
765 a
.full
= dfixed_const(32);
766 bandwidth
.full
= dfixed_mul(a
, sclk
);
767 bandwidth
.full
= dfixed_mul(bandwidth
, return_efficiency
);
769 return dfixed_trunc(bandwidth
);
772 static u32
evergreen_dmif_request_bandwidth(struct evergreen_wm_params
*wm
)
774 /* Calculate the DMIF Request Bandwidth */
775 fixed20_12 disp_clk_request_efficiency
; /* 0.8 */
776 fixed20_12 disp_clk
, bandwidth
;
779 a
.full
= dfixed_const(1000);
780 disp_clk
.full
= dfixed_const(wm
->disp_clk
);
781 disp_clk
.full
= dfixed_div(disp_clk
, a
);
782 a
.full
= dfixed_const(10);
783 disp_clk_request_efficiency
.full
= dfixed_const(8);
784 disp_clk_request_efficiency
.full
= dfixed_div(disp_clk_request_efficiency
, a
);
785 a
.full
= dfixed_const(32);
786 bandwidth
.full
= dfixed_mul(a
, disp_clk
);
787 bandwidth
.full
= dfixed_mul(bandwidth
, disp_clk_request_efficiency
);
789 return dfixed_trunc(bandwidth
);
792 static u32
evergreen_available_bandwidth(struct evergreen_wm_params
*wm
)
794 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
795 u32 dram_bandwidth
= evergreen_dram_bandwidth(wm
);
796 u32 data_return_bandwidth
= evergreen_data_return_bandwidth(wm
);
797 u32 dmif_req_bandwidth
= evergreen_dmif_request_bandwidth(wm
);
799 return min(dram_bandwidth
, min(data_return_bandwidth
, dmif_req_bandwidth
));
802 static u32
evergreen_average_bandwidth(struct evergreen_wm_params
*wm
)
804 /* Calculate the display mode Average Bandwidth
805 * DisplayMode should contain the source and destination dimensions,
809 fixed20_12 line_time
;
810 fixed20_12 src_width
;
811 fixed20_12 bandwidth
;
814 a
.full
= dfixed_const(1000);
815 line_time
.full
= dfixed_const(wm
->active_time
+ wm
->blank_time
);
816 line_time
.full
= dfixed_div(line_time
, a
);
817 bpp
.full
= dfixed_const(wm
->bytes_per_pixel
);
818 src_width
.full
= dfixed_const(wm
->src_width
);
819 bandwidth
.full
= dfixed_mul(src_width
, bpp
);
820 bandwidth
.full
= dfixed_mul(bandwidth
, wm
->vsc
);
821 bandwidth
.full
= dfixed_div(bandwidth
, line_time
);
823 return dfixed_trunc(bandwidth
);
826 static u32
evergreen_latency_watermark(struct evergreen_wm_params
*wm
)
828 /* First calcualte the latency in ns */
829 u32 mc_latency
= 2000; /* 2000 ns. */
830 u32 available_bandwidth
= evergreen_available_bandwidth(wm
);
831 u32 worst_chunk_return_time
= (512 * 8 * 1000) / available_bandwidth
;
832 u32 cursor_line_pair_return_time
= (128 * 4 * 1000) / available_bandwidth
;
833 u32 dc_latency
= 40000000 / wm
->disp_clk
; /* dc pipe latency */
834 u32 other_heads_data_return_time
= ((wm
->num_heads
+ 1) * worst_chunk_return_time
) +
835 (wm
->num_heads
* cursor_line_pair_return_time
);
836 u32 latency
= mc_latency
+ other_heads_data_return_time
+ dc_latency
;
837 u32 max_src_lines_per_dst_line
, lb_fill_bw
, line_fill_time
;
840 if (wm
->num_heads
== 0)
843 a
.full
= dfixed_const(2);
844 b
.full
= dfixed_const(1);
845 if ((wm
->vsc
.full
> a
.full
) ||
846 ((wm
->vsc
.full
> b
.full
) && (wm
->vtaps
>= 3)) ||
848 ((wm
->vsc
.full
>= a
.full
) && wm
->interlaced
))
849 max_src_lines_per_dst_line
= 4;
851 max_src_lines_per_dst_line
= 2;
853 a
.full
= dfixed_const(available_bandwidth
);
854 b
.full
= dfixed_const(wm
->num_heads
);
855 a
.full
= dfixed_div(a
, b
);
857 b
.full
= dfixed_const(1000);
858 c
.full
= dfixed_const(wm
->disp_clk
);
859 b
.full
= dfixed_div(c
, b
);
860 c
.full
= dfixed_const(wm
->bytes_per_pixel
);
861 b
.full
= dfixed_mul(b
, c
);
863 lb_fill_bw
= min(dfixed_trunc(a
), dfixed_trunc(b
));
865 a
.full
= dfixed_const(max_src_lines_per_dst_line
* wm
->src_width
* wm
->bytes_per_pixel
);
866 b
.full
= dfixed_const(1000);
867 c
.full
= dfixed_const(lb_fill_bw
);
868 b
.full
= dfixed_div(c
, b
);
869 a
.full
= dfixed_div(a
, b
);
870 line_fill_time
= dfixed_trunc(a
);
872 if (line_fill_time
< wm
->active_time
)
875 return latency
+ (line_fill_time
- wm
->active_time
);
879 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params
*wm
)
881 if (evergreen_average_bandwidth(wm
) <=
882 (evergreen_dram_bandwidth_for_display(wm
) / wm
->num_heads
))
888 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params
*wm
)
890 if (evergreen_average_bandwidth(wm
) <=
891 (evergreen_available_bandwidth(wm
) / wm
->num_heads
))
897 static bool evergreen_check_latency_hiding(struct evergreen_wm_params
*wm
)
899 u32 lb_partitions
= wm
->lb_size
/ wm
->src_width
;
900 u32 line_time
= wm
->active_time
+ wm
->blank_time
;
901 u32 latency_tolerant_lines
;
905 a
.full
= dfixed_const(1);
906 if (wm
->vsc
.full
> a
.full
)
907 latency_tolerant_lines
= 1;
909 if (lb_partitions
<= (wm
->vtaps
+ 1))
910 latency_tolerant_lines
= 1;
912 latency_tolerant_lines
= 2;
915 latency_hiding
= (latency_tolerant_lines
* line_time
+ wm
->blank_time
);
917 if (evergreen_latency_watermark(wm
) <= latency_hiding
)
923 static void evergreen_program_watermarks(struct radeon_device
*rdev
,
924 struct radeon_crtc
*radeon_crtc
,
925 u32 lb_size
, u32 num_heads
)
927 struct drm_display_mode
*mode
= &radeon_crtc
->base
.mode
;
928 struct evergreen_wm_params wm
;
931 u32 latency_watermark_a
= 0, latency_watermark_b
= 0;
932 u32 priority_a_mark
= 0, priority_b_mark
= 0;
933 u32 priority_a_cnt
= PRIORITY_OFF
;
934 u32 priority_b_cnt
= PRIORITY_OFF
;
935 u32 pipe_offset
= radeon_crtc
->crtc_id
* 16;
936 u32 tmp
, arb_control3
;
939 if (radeon_crtc
->base
.enabled
&& num_heads
&& mode
) {
940 pixel_period
= 1000000 / (u32
)mode
->clock
;
941 line_time
= min((u32
)mode
->crtc_htotal
* pixel_period
, (u32
)65535);
945 wm
.yclk
= rdev
->pm
.current_mclk
* 10;
946 wm
.sclk
= rdev
->pm
.current_sclk
* 10;
947 wm
.disp_clk
= mode
->clock
;
948 wm
.src_width
= mode
->crtc_hdisplay
;
949 wm
.active_time
= mode
->crtc_hdisplay
* pixel_period
;
950 wm
.blank_time
= line_time
- wm
.active_time
;
951 wm
.interlaced
= false;
952 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
953 wm
.interlaced
= true;
954 wm
.vsc
= radeon_crtc
->vsc
;
956 if (radeon_crtc
->rmx_type
!= RMX_OFF
)
958 wm
.bytes_per_pixel
= 4; /* XXX: get this from fb config */
959 wm
.lb_size
= lb_size
;
960 wm
.dram_channels
= evergreen_get_number_of_dram_channels(rdev
);
961 wm
.num_heads
= num_heads
;
963 /* set for high clocks */
964 latency_watermark_a
= min(evergreen_latency_watermark(&wm
), (u32
)65535);
965 /* set for low clocks */
966 /* wm.yclk = low clk; wm.sclk = low clk */
967 latency_watermark_b
= min(evergreen_latency_watermark(&wm
), (u32
)65535);
969 /* possibly force display priority to high */
970 /* should really do this at mode validation time... */
971 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm
) ||
972 !evergreen_average_bandwidth_vs_available_bandwidth(&wm
) ||
973 !evergreen_check_latency_hiding(&wm
) ||
974 (rdev
->disp_priority
== 2)) {
975 DRM_DEBUG_KMS("force priority to high\n");
976 priority_a_cnt
|= PRIORITY_ALWAYS_ON
;
977 priority_b_cnt
|= PRIORITY_ALWAYS_ON
;
980 a
.full
= dfixed_const(1000);
981 b
.full
= dfixed_const(mode
->clock
);
982 b
.full
= dfixed_div(b
, a
);
983 c
.full
= dfixed_const(latency_watermark_a
);
984 c
.full
= dfixed_mul(c
, b
);
985 c
.full
= dfixed_mul(c
, radeon_crtc
->hsc
);
986 c
.full
= dfixed_div(c
, a
);
987 a
.full
= dfixed_const(16);
988 c
.full
= dfixed_div(c
, a
);
989 priority_a_mark
= dfixed_trunc(c
);
990 priority_a_cnt
|= priority_a_mark
& PRIORITY_MARK_MASK
;
992 a
.full
= dfixed_const(1000);
993 b
.full
= dfixed_const(mode
->clock
);
994 b
.full
= dfixed_div(b
, a
);
995 c
.full
= dfixed_const(latency_watermark_b
);
996 c
.full
= dfixed_mul(c
, b
);
997 c
.full
= dfixed_mul(c
, radeon_crtc
->hsc
);
998 c
.full
= dfixed_div(c
, a
);
999 a
.full
= dfixed_const(16);
1000 c
.full
= dfixed_div(c
, a
);
1001 priority_b_mark
= dfixed_trunc(c
);
1002 priority_b_cnt
|= priority_b_mark
& PRIORITY_MARK_MASK
;
1006 arb_control3
= RREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
);
1008 tmp
&= ~LATENCY_WATERMARK_MASK(3);
1009 tmp
|= LATENCY_WATERMARK_MASK(1);
1010 WREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
, tmp
);
1011 WREG32(PIPE0_LATENCY_CONTROL
+ pipe_offset
,
1012 (LATENCY_LOW_WATERMARK(latency_watermark_a
) |
1013 LATENCY_HIGH_WATERMARK(line_time
)));
1015 tmp
= RREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
);
1016 tmp
&= ~LATENCY_WATERMARK_MASK(3);
1017 tmp
|= LATENCY_WATERMARK_MASK(2);
1018 WREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
, tmp
);
1019 WREG32(PIPE0_LATENCY_CONTROL
+ pipe_offset
,
1020 (LATENCY_LOW_WATERMARK(latency_watermark_b
) |
1021 LATENCY_HIGH_WATERMARK(line_time
)));
1022 /* restore original selection */
1023 WREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
, arb_control3
);
1025 /* write the priority marks */
1026 WREG32(PRIORITY_A_CNT
+ radeon_crtc
->crtc_offset
, priority_a_cnt
);
1027 WREG32(PRIORITY_B_CNT
+ radeon_crtc
->crtc_offset
, priority_b_cnt
);
1032 * evergreen_bandwidth_update - update display watermarks callback.
1034 * @rdev: radeon_device pointer
1036 * Update the display watermarks based on the requested mode(s)
1039 void evergreen_bandwidth_update(struct radeon_device
*rdev
)
1041 struct drm_display_mode
*mode0
= NULL
;
1042 struct drm_display_mode
*mode1
= NULL
;
1043 u32 num_heads
= 0, lb_size
;
1046 radeon_update_display_priority(rdev
);
1048 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
1049 if (rdev
->mode_info
.crtcs
[i
]->base
.enabled
)
1052 for (i
= 0; i
< rdev
->num_crtc
; i
+= 2) {
1053 mode0
= &rdev
->mode_info
.crtcs
[i
]->base
.mode
;
1054 mode1
= &rdev
->mode_info
.crtcs
[i
+1]->base
.mode
;
1055 lb_size
= evergreen_line_buffer_adjust(rdev
, rdev
->mode_info
.crtcs
[i
], mode0
, mode1
);
1056 evergreen_program_watermarks(rdev
, rdev
->mode_info
.crtcs
[i
], lb_size
, num_heads
);
1057 lb_size
= evergreen_line_buffer_adjust(rdev
, rdev
->mode_info
.crtcs
[i
+1], mode1
, mode0
);
1058 evergreen_program_watermarks(rdev
, rdev
->mode_info
.crtcs
[i
+1], lb_size
, num_heads
);
1063 * evergreen_mc_wait_for_idle - wait for MC idle callback.
1065 * @rdev: radeon_device pointer
1067 * Wait for the MC (memory controller) to be idle.
1069 * Returns 0 if the MC is idle, -1 if not.
1071 int evergreen_mc_wait_for_idle(struct radeon_device
*rdev
)
1076 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1077 /* read MC_STATUS */
1078 tmp
= RREG32(SRBM_STATUS
) & 0x1F00;
1089 void evergreen_pcie_gart_tlb_flush(struct radeon_device
*rdev
)
1094 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL
, 0x1);
1096 WREG32(VM_CONTEXT0_REQUEST_RESPONSE
, REQUEST_TYPE(1));
1097 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1098 /* read MC_STATUS */
1099 tmp
= RREG32(VM_CONTEXT0_REQUEST_RESPONSE
);
1100 tmp
= (tmp
& RESPONSE_TYPE_MASK
) >> RESPONSE_TYPE_SHIFT
;
1102 printk(KERN_WARNING
"[drm] r600 flush TLB failed\n");
1112 int evergreen_pcie_gart_enable(struct radeon_device
*rdev
)
1117 if (rdev
->gart
.robj
== NULL
) {
1118 dev_err(rdev
->dev
, "No VRAM object for PCIE GART.\n");
1121 r
= radeon_gart_table_vram_pin(rdev
);
1124 radeon_gart_restore(rdev
);
1125 /* Setup L2 cache */
1126 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
1127 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
1128 EFFECTIVE_L2_QUEUE_SIZE(7));
1129 WREG32(VM_L2_CNTL2
, 0);
1130 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1131 /* Setup TLB control */
1132 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
1133 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
1134 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
|
1135 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1136 if (rdev
->flags
& RADEON_IS_IGP
) {
1137 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL
, tmp
);
1138 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL
, tmp
);
1139 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL
, tmp
);
1141 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
1142 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
1143 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
1144 if ((rdev
->family
== CHIP_JUNIPER
) ||
1145 (rdev
->family
== CHIP_CYPRESS
) ||
1146 (rdev
->family
== CHIP_HEMLOCK
) ||
1147 (rdev
->family
== CHIP_BARTS
))
1148 WREG32(MC_VM_MD_L1_TLB3_CNTL
, tmp
);
1150 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
1151 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
1152 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
1153 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
1154 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR
, rdev
->mc
.gtt_start
>> 12);
1155 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR
, rdev
->mc
.gtt_end
>> 12);
1156 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, rdev
->gart
.table_addr
>> 12);
1157 WREG32(VM_CONTEXT0_CNTL
, ENABLE_CONTEXT
| PAGE_TABLE_DEPTH(0) |
1158 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
);
1159 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
,
1160 (u32
)(rdev
->dummy_page
.addr
>> 12));
1161 WREG32(VM_CONTEXT1_CNTL
, 0);
1163 evergreen_pcie_gart_tlb_flush(rdev
);
1164 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1165 (unsigned)(rdev
->mc
.gtt_size
>> 20),
1166 (unsigned long long)rdev
->gart
.table_addr
);
1167 rdev
->gart
.ready
= true;
1171 void evergreen_pcie_gart_disable(struct radeon_device
*rdev
)
1175 /* Disable all tables */
1176 WREG32(VM_CONTEXT0_CNTL
, 0);
1177 WREG32(VM_CONTEXT1_CNTL
, 0);
1179 /* Setup L2 cache */
1180 WREG32(VM_L2_CNTL
, ENABLE_L2_FRAGMENT_PROCESSING
|
1181 EFFECTIVE_L2_QUEUE_SIZE(7));
1182 WREG32(VM_L2_CNTL2
, 0);
1183 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1184 /* Setup TLB control */
1185 tmp
= EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1186 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
1187 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
1188 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
1189 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
1190 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
1191 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
1192 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
1193 radeon_gart_table_vram_unpin(rdev
);
1196 void evergreen_pcie_gart_fini(struct radeon_device
*rdev
)
1198 evergreen_pcie_gart_disable(rdev
);
1199 radeon_gart_table_vram_free(rdev
);
1200 radeon_gart_fini(rdev
);
1204 void evergreen_agp_enable(struct radeon_device
*rdev
)
1208 /* Setup L2 cache */
1209 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
1210 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
1211 EFFECTIVE_L2_QUEUE_SIZE(7));
1212 WREG32(VM_L2_CNTL2
, 0);
1213 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1214 /* Setup TLB control */
1215 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
1216 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
1217 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
|
1218 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1219 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
1220 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
1221 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
1222 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
1223 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
1224 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
1225 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
1226 WREG32(VM_CONTEXT0_CNTL
, 0);
1227 WREG32(VM_CONTEXT1_CNTL
, 0);
1230 void evergreen_mc_stop(struct radeon_device
*rdev
, struct evergreen_mc_save
*save
)
1232 save
->vga_control
[0] = RREG32(D1VGA_CONTROL
);
1233 save
->vga_control
[1] = RREG32(D2VGA_CONTROL
);
1234 save
->vga_render_control
= RREG32(VGA_RENDER_CONTROL
);
1235 save
->vga_hdp_control
= RREG32(VGA_HDP_CONTROL
);
1236 save
->crtc_control
[0] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
);
1237 save
->crtc_control
[1] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
1238 if (rdev
->num_crtc
>= 4) {
1239 save
->vga_control
[2] = RREG32(EVERGREEN_D3VGA_CONTROL
);
1240 save
->vga_control
[3] = RREG32(EVERGREEN_D4VGA_CONTROL
);
1241 save
->crtc_control
[2] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
);
1242 save
->crtc_control
[3] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
1244 if (rdev
->num_crtc
>= 6) {
1245 save
->vga_control
[4] = RREG32(EVERGREEN_D5VGA_CONTROL
);
1246 save
->vga_control
[5] = RREG32(EVERGREEN_D6VGA_CONTROL
);
1247 save
->crtc_control
[4] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
);
1248 save
->crtc_control
[5] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
1251 /* Stop all video */
1252 WREG32(VGA_RENDER_CONTROL
, 0);
1253 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 1);
1254 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 1);
1255 if (rdev
->num_crtc
>= 4) {
1256 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 1);
1257 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 1);
1259 if (rdev
->num_crtc
>= 6) {
1260 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 1);
1261 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 1);
1263 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
1264 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
1265 if (rdev
->num_crtc
>= 4) {
1266 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
1267 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
1269 if (rdev
->num_crtc
>= 6) {
1270 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
1271 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
1273 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
1274 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
1275 if (rdev
->num_crtc
>= 4) {
1276 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
1277 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
1279 if (rdev
->num_crtc
>= 6) {
1280 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
1281 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
1284 WREG32(D1VGA_CONTROL
, 0);
1285 WREG32(D2VGA_CONTROL
, 0);
1286 if (rdev
->num_crtc
>= 4) {
1287 WREG32(EVERGREEN_D3VGA_CONTROL
, 0);
1288 WREG32(EVERGREEN_D4VGA_CONTROL
, 0);
1290 if (rdev
->num_crtc
>= 6) {
1291 WREG32(EVERGREEN_D5VGA_CONTROL
, 0);
1292 WREG32(EVERGREEN_D6VGA_CONTROL
, 0);
1296 void evergreen_mc_resume(struct radeon_device
*rdev
, struct evergreen_mc_save
*save
)
1298 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC0_REGISTER_OFFSET
,
1299 upper_32_bits(rdev
->mc
.vram_start
));
1300 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC0_REGISTER_OFFSET
,
1301 upper_32_bits(rdev
->mc
.vram_start
));
1302 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
,
1303 (u32
)rdev
->mc
.vram_start
);
1304 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
,
1305 (u32
)rdev
->mc
.vram_start
);
1307 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC1_REGISTER_OFFSET
,
1308 upper_32_bits(rdev
->mc
.vram_start
));
1309 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC1_REGISTER_OFFSET
,
1310 upper_32_bits(rdev
->mc
.vram_start
));
1311 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
,
1312 (u32
)rdev
->mc
.vram_start
);
1313 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
,
1314 (u32
)rdev
->mc
.vram_start
);
1316 if (rdev
->num_crtc
>= 4) {
1317 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC2_REGISTER_OFFSET
,
1318 upper_32_bits(rdev
->mc
.vram_start
));
1319 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC2_REGISTER_OFFSET
,
1320 upper_32_bits(rdev
->mc
.vram_start
));
1321 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
,
1322 (u32
)rdev
->mc
.vram_start
);
1323 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
,
1324 (u32
)rdev
->mc
.vram_start
);
1326 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC3_REGISTER_OFFSET
,
1327 upper_32_bits(rdev
->mc
.vram_start
));
1328 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC3_REGISTER_OFFSET
,
1329 upper_32_bits(rdev
->mc
.vram_start
));
1330 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
,
1331 (u32
)rdev
->mc
.vram_start
);
1332 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
,
1333 (u32
)rdev
->mc
.vram_start
);
1335 if (rdev
->num_crtc
>= 6) {
1336 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC4_REGISTER_OFFSET
,
1337 upper_32_bits(rdev
->mc
.vram_start
));
1338 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC4_REGISTER_OFFSET
,
1339 upper_32_bits(rdev
->mc
.vram_start
));
1340 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
,
1341 (u32
)rdev
->mc
.vram_start
);
1342 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
,
1343 (u32
)rdev
->mc
.vram_start
);
1345 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC5_REGISTER_OFFSET
,
1346 upper_32_bits(rdev
->mc
.vram_start
));
1347 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC5_REGISTER_OFFSET
,
1348 upper_32_bits(rdev
->mc
.vram_start
));
1349 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
,
1350 (u32
)rdev
->mc
.vram_start
);
1351 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
,
1352 (u32
)rdev
->mc
.vram_start
);
1355 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH
, upper_32_bits(rdev
->mc
.vram_start
));
1356 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS
, (u32
)rdev
->mc
.vram_start
);
1357 /* Unlock host access */
1358 WREG32(VGA_HDP_CONTROL
, save
->vga_hdp_control
);
1360 /* Restore video state */
1361 WREG32(D1VGA_CONTROL
, save
->vga_control
[0]);
1362 WREG32(D2VGA_CONTROL
, save
->vga_control
[1]);
1363 if (rdev
->num_crtc
>= 4) {
1364 WREG32(EVERGREEN_D3VGA_CONTROL
, save
->vga_control
[2]);
1365 WREG32(EVERGREEN_D4VGA_CONTROL
, save
->vga_control
[3]);
1367 if (rdev
->num_crtc
>= 6) {
1368 WREG32(EVERGREEN_D5VGA_CONTROL
, save
->vga_control
[4]);
1369 WREG32(EVERGREEN_D6VGA_CONTROL
, save
->vga_control
[5]);
1371 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 1);
1372 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 1);
1373 if (rdev
->num_crtc
>= 4) {
1374 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 1);
1375 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 1);
1377 if (rdev
->num_crtc
>= 6) {
1378 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 1);
1379 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 1);
1381 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, save
->crtc_control
[0]);
1382 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, save
->crtc_control
[1]);
1383 if (rdev
->num_crtc
>= 4) {
1384 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, save
->crtc_control
[2]);
1385 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, save
->crtc_control
[3]);
1387 if (rdev
->num_crtc
>= 6) {
1388 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, save
->crtc_control
[4]);
1389 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, save
->crtc_control
[5]);
1391 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
1392 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
1393 if (rdev
->num_crtc
>= 4) {
1394 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
1395 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
1397 if (rdev
->num_crtc
>= 6) {
1398 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
1399 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
1401 WREG32(VGA_RENDER_CONTROL
, save
->vga_render_control
);
1404 void evergreen_mc_program(struct radeon_device
*rdev
)
1406 struct evergreen_mc_save save
;
1410 /* Initialize HDP */
1411 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
1412 WREG32((0x2c14 + j
), 0x00000000);
1413 WREG32((0x2c18 + j
), 0x00000000);
1414 WREG32((0x2c1c + j
), 0x00000000);
1415 WREG32((0x2c20 + j
), 0x00000000);
1416 WREG32((0x2c24 + j
), 0x00000000);
1418 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL
, 0);
1420 evergreen_mc_stop(rdev
, &save
);
1421 if (evergreen_mc_wait_for_idle(rdev
)) {
1422 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1424 /* Lockout access through VGA aperture*/
1425 WREG32(VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
);
1426 /* Update configuration */
1427 if (rdev
->flags
& RADEON_IS_AGP
) {
1428 if (rdev
->mc
.vram_start
< rdev
->mc
.gtt_start
) {
1429 /* VRAM before AGP */
1430 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
1431 rdev
->mc
.vram_start
>> 12);
1432 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
1433 rdev
->mc
.gtt_end
>> 12);
1435 /* VRAM after AGP */
1436 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
1437 rdev
->mc
.gtt_start
>> 12);
1438 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
1439 rdev
->mc
.vram_end
>> 12);
1442 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
1443 rdev
->mc
.vram_start
>> 12);
1444 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
1445 rdev
->mc
.vram_end
>> 12);
1447 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
, rdev
->vram_scratch
.gpu_addr
>> 12);
1448 /* llano/ontario only */
1449 if ((rdev
->family
== CHIP_PALM
) ||
1450 (rdev
->family
== CHIP_SUMO
) ||
1451 (rdev
->family
== CHIP_SUMO2
)) {
1452 tmp
= RREG32(MC_FUS_VM_FB_OFFSET
) & 0x000FFFFF;
1453 tmp
|= ((rdev
->mc
.vram_end
>> 20) & 0xF) << 24;
1454 tmp
|= ((rdev
->mc
.vram_start
>> 20) & 0xF) << 20;
1455 WREG32(MC_FUS_VM_FB_OFFSET
, tmp
);
1457 tmp
= ((rdev
->mc
.vram_end
>> 24) & 0xFFFF) << 16;
1458 tmp
|= ((rdev
->mc
.vram_start
>> 24) & 0xFFFF);
1459 WREG32(MC_VM_FB_LOCATION
, tmp
);
1460 WREG32(HDP_NONSURFACE_BASE
, (rdev
->mc
.vram_start
>> 8));
1461 WREG32(HDP_NONSURFACE_INFO
, (2 << 7) | (1 << 30));
1462 WREG32(HDP_NONSURFACE_SIZE
, 0x3FFFFFFF);
1463 if (rdev
->flags
& RADEON_IS_AGP
) {
1464 WREG32(MC_VM_AGP_TOP
, rdev
->mc
.gtt_end
>> 16);
1465 WREG32(MC_VM_AGP_BOT
, rdev
->mc
.gtt_start
>> 16);
1466 WREG32(MC_VM_AGP_BASE
, rdev
->mc
.agp_base
>> 22);
1468 WREG32(MC_VM_AGP_BASE
, 0);
1469 WREG32(MC_VM_AGP_TOP
, 0x0FFFFFFF);
1470 WREG32(MC_VM_AGP_BOT
, 0x0FFFFFFF);
1472 if (evergreen_mc_wait_for_idle(rdev
)) {
1473 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1475 evergreen_mc_resume(rdev
, &save
);
1476 /* we need to own VRAM, so turn off the VGA renderer here
1477 * to stop it overwriting our objects */
1478 rv515_vga_render_disable(rdev
);
1484 void evergreen_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
1486 struct radeon_ring
*ring
= &rdev
->ring
[ib
->ring
];
1489 /* set to DX10/11 mode */
1490 radeon_ring_write(ring
, PACKET3(PACKET3_MODE_CONTROL
, 0));
1491 radeon_ring_write(ring
, 1);
1493 if (ring
->rptr_save_reg
) {
1494 next_rptr
= ring
->wptr
+ 3 + 4;
1495 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
1496 radeon_ring_write(ring
, ((ring
->rptr_save_reg
-
1497 PACKET3_SET_CONFIG_REG_START
) >> 2));
1498 radeon_ring_write(ring
, next_rptr
);
1499 } else if (rdev
->wb
.enabled
) {
1500 next_rptr
= ring
->wptr
+ 5 + 4;
1501 radeon_ring_write(ring
, PACKET3(PACKET3_MEM_WRITE
, 3));
1502 radeon_ring_write(ring
, ring
->next_rptr_gpu_addr
& 0xfffffffc);
1503 radeon_ring_write(ring
, (upper_32_bits(ring
->next_rptr_gpu_addr
) & 0xff) | (1 << 18));
1504 radeon_ring_write(ring
, next_rptr
);
1505 radeon_ring_write(ring
, 0);
1508 radeon_ring_write(ring
, PACKET3(PACKET3_INDIRECT_BUFFER
, 2));
1509 radeon_ring_write(ring
,
1513 (ib
->gpu_addr
& 0xFFFFFFFC));
1514 radeon_ring_write(ring
, upper_32_bits(ib
->gpu_addr
) & 0xFF);
1515 radeon_ring_write(ring
, ib
->length_dw
);
1519 static int evergreen_cp_load_microcode(struct radeon_device
*rdev
)
1521 const __be32
*fw_data
;
1524 if (!rdev
->me_fw
|| !rdev
->pfp_fw
)
1532 RB_NO_UPDATE
| RB_BLKSZ(15) | RB_BUFSZ(3));
1534 fw_data
= (const __be32
*)rdev
->pfp_fw
->data
;
1535 WREG32(CP_PFP_UCODE_ADDR
, 0);
1536 for (i
= 0; i
< EVERGREEN_PFP_UCODE_SIZE
; i
++)
1537 WREG32(CP_PFP_UCODE_DATA
, be32_to_cpup(fw_data
++));
1538 WREG32(CP_PFP_UCODE_ADDR
, 0);
1540 fw_data
= (const __be32
*)rdev
->me_fw
->data
;
1541 WREG32(CP_ME_RAM_WADDR
, 0);
1542 for (i
= 0; i
< EVERGREEN_PM4_UCODE_SIZE
; i
++)
1543 WREG32(CP_ME_RAM_DATA
, be32_to_cpup(fw_data
++));
1545 WREG32(CP_PFP_UCODE_ADDR
, 0);
1546 WREG32(CP_ME_RAM_WADDR
, 0);
1547 WREG32(CP_ME_RAM_RADDR
, 0);
1551 static int evergreen_cp_start(struct radeon_device
*rdev
)
1553 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
1557 r
= radeon_ring_lock(rdev
, ring
, 7);
1559 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
1562 radeon_ring_write(ring
, PACKET3(PACKET3_ME_INITIALIZE
, 5));
1563 radeon_ring_write(ring
, 0x1);
1564 radeon_ring_write(ring
, 0x0);
1565 radeon_ring_write(ring
, rdev
->config
.evergreen
.max_hw_contexts
- 1);
1566 radeon_ring_write(ring
, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1567 radeon_ring_write(ring
, 0);
1568 radeon_ring_write(ring
, 0);
1569 radeon_ring_unlock_commit(rdev
, ring
);
1572 WREG32(CP_ME_CNTL
, cp_me
);
1574 r
= radeon_ring_lock(rdev
, ring
, evergreen_default_size
+ 19);
1576 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
1580 /* setup clear context state */
1581 radeon_ring_write(ring
, PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
1582 radeon_ring_write(ring
, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE
);
1584 for (i
= 0; i
< evergreen_default_size
; i
++)
1585 radeon_ring_write(ring
, evergreen_default_state
[i
]);
1587 radeon_ring_write(ring
, PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
1588 radeon_ring_write(ring
, PACKET3_PREAMBLE_END_CLEAR_STATE
);
1590 /* set clear context state */
1591 radeon_ring_write(ring
, PACKET3(PACKET3_CLEAR_STATE
, 0));
1592 radeon_ring_write(ring
, 0);
1594 /* SQ_VTX_BASE_VTX_LOC */
1595 radeon_ring_write(ring
, 0xc0026f00);
1596 radeon_ring_write(ring
, 0x00000000);
1597 radeon_ring_write(ring
, 0x00000000);
1598 radeon_ring_write(ring
, 0x00000000);
1601 radeon_ring_write(ring
, 0xc0036f00);
1602 radeon_ring_write(ring
, 0x00000bc4);
1603 radeon_ring_write(ring
, 0xffffffff);
1604 radeon_ring_write(ring
, 0xffffffff);
1605 radeon_ring_write(ring
, 0xffffffff);
1607 radeon_ring_write(ring
, 0xc0026900);
1608 radeon_ring_write(ring
, 0x00000316);
1609 radeon_ring_write(ring
, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1610 radeon_ring_write(ring
, 0x00000010); /* */
1612 radeon_ring_unlock_commit(rdev
, ring
);
1617 int evergreen_cp_resume(struct radeon_device
*rdev
)
1619 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
1624 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1625 WREG32(GRBM_SOFT_RESET
, (SOFT_RESET_CP
|
1631 RREG32(GRBM_SOFT_RESET
);
1633 WREG32(GRBM_SOFT_RESET
, 0);
1634 RREG32(GRBM_SOFT_RESET
);
1636 /* Set ring buffer size */
1637 rb_bufsz
= drm_order(ring
->ring_size
/ 8);
1638 tmp
= (drm_order(RADEON_GPU_PAGE_SIZE
/8) << 8) | rb_bufsz
;
1640 tmp
|= BUF_SWAP_32BIT
;
1642 WREG32(CP_RB_CNTL
, tmp
);
1643 WREG32(CP_SEM_WAIT_TIMER
, 0x0);
1644 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL
, 0x0);
1646 /* Set the write pointer delay */
1647 WREG32(CP_RB_WPTR_DELAY
, 0);
1649 /* Initialize the ring buffer's read and write pointers */
1650 WREG32(CP_RB_CNTL
, tmp
| RB_RPTR_WR_ENA
);
1651 WREG32(CP_RB_RPTR_WR
, 0);
1653 WREG32(CP_RB_WPTR
, ring
->wptr
);
1655 /* set the wb address wether it's enabled or not */
1656 WREG32(CP_RB_RPTR_ADDR
,
1657 ((rdev
->wb
.gpu_addr
+ RADEON_WB_CP_RPTR_OFFSET
) & 0xFFFFFFFC));
1658 WREG32(CP_RB_RPTR_ADDR_HI
, upper_32_bits(rdev
->wb
.gpu_addr
+ RADEON_WB_CP_RPTR_OFFSET
) & 0xFF);
1659 WREG32(SCRATCH_ADDR
, ((rdev
->wb
.gpu_addr
+ RADEON_WB_SCRATCH_OFFSET
) >> 8) & 0xFFFFFFFF);
1661 if (rdev
->wb
.enabled
)
1662 WREG32(SCRATCH_UMSK
, 0xff);
1664 tmp
|= RB_NO_UPDATE
;
1665 WREG32(SCRATCH_UMSK
, 0);
1669 WREG32(CP_RB_CNTL
, tmp
);
1671 WREG32(CP_RB_BASE
, ring
->gpu_addr
>> 8);
1672 WREG32(CP_DEBUG
, (1 << 27) | (1 << 28));
1674 ring
->rptr
= RREG32(CP_RB_RPTR
);
1676 evergreen_cp_start(rdev
);
1678 r
= radeon_ring_test(rdev
, RADEON_RING_TYPE_GFX_INDEX
, ring
);
1680 ring
->ready
= false;
1689 static void evergreen_gpu_init(struct radeon_device
*rdev
)
1692 u32 mc_shared_chmap
, mc_arb_ramcfg
;
1696 u32 sq_lds_resource_mgmt
;
1697 u32 sq_gpr_resource_mgmt_1
;
1698 u32 sq_gpr_resource_mgmt_2
;
1699 u32 sq_gpr_resource_mgmt_3
;
1700 u32 sq_thread_resource_mgmt
;
1701 u32 sq_thread_resource_mgmt_2
;
1702 u32 sq_stack_resource_mgmt_1
;
1703 u32 sq_stack_resource_mgmt_2
;
1704 u32 sq_stack_resource_mgmt_3
;
1705 u32 vgt_cache_invalidation
;
1706 u32 hdp_host_path_cntl
, tmp
;
1707 u32 disabled_rb_mask
;
1708 int i
, j
, num_shader_engines
, ps_thread_count
;
1710 switch (rdev
->family
) {
1713 rdev
->config
.evergreen
.num_ses
= 2;
1714 rdev
->config
.evergreen
.max_pipes
= 4;
1715 rdev
->config
.evergreen
.max_tile_pipes
= 8;
1716 rdev
->config
.evergreen
.max_simds
= 10;
1717 rdev
->config
.evergreen
.max_backends
= 4 * rdev
->config
.evergreen
.num_ses
;
1718 rdev
->config
.evergreen
.max_gprs
= 256;
1719 rdev
->config
.evergreen
.max_threads
= 248;
1720 rdev
->config
.evergreen
.max_gs_threads
= 32;
1721 rdev
->config
.evergreen
.max_stack_entries
= 512;
1722 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1723 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1724 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1725 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1726 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1727 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1729 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
1730 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1731 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1732 gb_addr_config
= CYPRESS_GB_ADDR_CONFIG_GOLDEN
;
1735 rdev
->config
.evergreen
.num_ses
= 1;
1736 rdev
->config
.evergreen
.max_pipes
= 4;
1737 rdev
->config
.evergreen
.max_tile_pipes
= 4;
1738 rdev
->config
.evergreen
.max_simds
= 10;
1739 rdev
->config
.evergreen
.max_backends
= 4 * rdev
->config
.evergreen
.num_ses
;
1740 rdev
->config
.evergreen
.max_gprs
= 256;
1741 rdev
->config
.evergreen
.max_threads
= 248;
1742 rdev
->config
.evergreen
.max_gs_threads
= 32;
1743 rdev
->config
.evergreen
.max_stack_entries
= 512;
1744 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1745 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1746 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1747 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1748 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1749 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1751 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
1752 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1753 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1754 gb_addr_config
= JUNIPER_GB_ADDR_CONFIG_GOLDEN
;
1757 rdev
->config
.evergreen
.num_ses
= 1;
1758 rdev
->config
.evergreen
.max_pipes
= 4;
1759 rdev
->config
.evergreen
.max_tile_pipes
= 4;
1760 rdev
->config
.evergreen
.max_simds
= 5;
1761 rdev
->config
.evergreen
.max_backends
= 2 * rdev
->config
.evergreen
.num_ses
;
1762 rdev
->config
.evergreen
.max_gprs
= 256;
1763 rdev
->config
.evergreen
.max_threads
= 248;
1764 rdev
->config
.evergreen
.max_gs_threads
= 32;
1765 rdev
->config
.evergreen
.max_stack_entries
= 256;
1766 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1767 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1768 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1769 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1770 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1771 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1773 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
1774 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1775 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1776 gb_addr_config
= REDWOOD_GB_ADDR_CONFIG_GOLDEN
;
1780 rdev
->config
.evergreen
.num_ses
= 1;
1781 rdev
->config
.evergreen
.max_pipes
= 2;
1782 rdev
->config
.evergreen
.max_tile_pipes
= 2;
1783 rdev
->config
.evergreen
.max_simds
= 2;
1784 rdev
->config
.evergreen
.max_backends
= 1 * rdev
->config
.evergreen
.num_ses
;
1785 rdev
->config
.evergreen
.max_gprs
= 256;
1786 rdev
->config
.evergreen
.max_threads
= 192;
1787 rdev
->config
.evergreen
.max_gs_threads
= 16;
1788 rdev
->config
.evergreen
.max_stack_entries
= 256;
1789 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1790 rdev
->config
.evergreen
.sx_max_export_size
= 128;
1791 rdev
->config
.evergreen
.sx_max_export_pos_size
= 32;
1792 rdev
->config
.evergreen
.sx_max_export_smx_size
= 96;
1793 rdev
->config
.evergreen
.max_hw_contexts
= 4;
1794 rdev
->config
.evergreen
.sq_num_cf_insts
= 1;
1796 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x40;
1797 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1798 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1799 gb_addr_config
= CEDAR_GB_ADDR_CONFIG_GOLDEN
;
1802 rdev
->config
.evergreen
.num_ses
= 1;
1803 rdev
->config
.evergreen
.max_pipes
= 2;
1804 rdev
->config
.evergreen
.max_tile_pipes
= 2;
1805 rdev
->config
.evergreen
.max_simds
= 2;
1806 rdev
->config
.evergreen
.max_backends
= 1 * rdev
->config
.evergreen
.num_ses
;
1807 rdev
->config
.evergreen
.max_gprs
= 256;
1808 rdev
->config
.evergreen
.max_threads
= 192;
1809 rdev
->config
.evergreen
.max_gs_threads
= 16;
1810 rdev
->config
.evergreen
.max_stack_entries
= 256;
1811 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1812 rdev
->config
.evergreen
.sx_max_export_size
= 128;
1813 rdev
->config
.evergreen
.sx_max_export_pos_size
= 32;
1814 rdev
->config
.evergreen
.sx_max_export_smx_size
= 96;
1815 rdev
->config
.evergreen
.max_hw_contexts
= 4;
1816 rdev
->config
.evergreen
.sq_num_cf_insts
= 1;
1818 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x40;
1819 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1820 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1821 gb_addr_config
= CEDAR_GB_ADDR_CONFIG_GOLDEN
;
1824 rdev
->config
.evergreen
.num_ses
= 1;
1825 rdev
->config
.evergreen
.max_pipes
= 4;
1826 rdev
->config
.evergreen
.max_tile_pipes
= 2;
1827 if (rdev
->pdev
->device
== 0x9648)
1828 rdev
->config
.evergreen
.max_simds
= 3;
1829 else if ((rdev
->pdev
->device
== 0x9647) ||
1830 (rdev
->pdev
->device
== 0x964a))
1831 rdev
->config
.evergreen
.max_simds
= 4;
1833 rdev
->config
.evergreen
.max_simds
= 5;
1834 rdev
->config
.evergreen
.max_backends
= 2 * rdev
->config
.evergreen
.num_ses
;
1835 rdev
->config
.evergreen
.max_gprs
= 256;
1836 rdev
->config
.evergreen
.max_threads
= 248;
1837 rdev
->config
.evergreen
.max_gs_threads
= 32;
1838 rdev
->config
.evergreen
.max_stack_entries
= 256;
1839 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1840 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1841 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1842 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1843 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1844 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1846 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x40;
1847 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1848 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1849 gb_addr_config
= REDWOOD_GB_ADDR_CONFIG_GOLDEN
;
1852 rdev
->config
.evergreen
.num_ses
= 1;
1853 rdev
->config
.evergreen
.max_pipes
= 4;
1854 rdev
->config
.evergreen
.max_tile_pipes
= 4;
1855 rdev
->config
.evergreen
.max_simds
= 2;
1856 rdev
->config
.evergreen
.max_backends
= 1 * rdev
->config
.evergreen
.num_ses
;
1857 rdev
->config
.evergreen
.max_gprs
= 256;
1858 rdev
->config
.evergreen
.max_threads
= 248;
1859 rdev
->config
.evergreen
.max_gs_threads
= 32;
1860 rdev
->config
.evergreen
.max_stack_entries
= 512;
1861 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1862 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1863 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1864 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1865 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1866 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1868 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x40;
1869 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1870 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1871 gb_addr_config
= REDWOOD_GB_ADDR_CONFIG_GOLDEN
;
1874 rdev
->config
.evergreen
.num_ses
= 2;
1875 rdev
->config
.evergreen
.max_pipes
= 4;
1876 rdev
->config
.evergreen
.max_tile_pipes
= 8;
1877 rdev
->config
.evergreen
.max_simds
= 7;
1878 rdev
->config
.evergreen
.max_backends
= 4 * rdev
->config
.evergreen
.num_ses
;
1879 rdev
->config
.evergreen
.max_gprs
= 256;
1880 rdev
->config
.evergreen
.max_threads
= 248;
1881 rdev
->config
.evergreen
.max_gs_threads
= 32;
1882 rdev
->config
.evergreen
.max_stack_entries
= 512;
1883 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1884 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1885 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1886 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1887 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1888 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1890 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
1891 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1892 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1893 gb_addr_config
= BARTS_GB_ADDR_CONFIG_GOLDEN
;
1896 rdev
->config
.evergreen
.num_ses
= 1;
1897 rdev
->config
.evergreen
.max_pipes
= 4;
1898 rdev
->config
.evergreen
.max_tile_pipes
= 4;
1899 rdev
->config
.evergreen
.max_simds
= 6;
1900 rdev
->config
.evergreen
.max_backends
= 2 * rdev
->config
.evergreen
.num_ses
;
1901 rdev
->config
.evergreen
.max_gprs
= 256;
1902 rdev
->config
.evergreen
.max_threads
= 248;
1903 rdev
->config
.evergreen
.max_gs_threads
= 32;
1904 rdev
->config
.evergreen
.max_stack_entries
= 256;
1905 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1906 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1907 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1908 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1909 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1910 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1912 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
1913 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1914 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1915 gb_addr_config
= TURKS_GB_ADDR_CONFIG_GOLDEN
;
1918 rdev
->config
.evergreen
.num_ses
= 1;
1919 rdev
->config
.evergreen
.max_pipes
= 4;
1920 rdev
->config
.evergreen
.max_tile_pipes
= 2;
1921 rdev
->config
.evergreen
.max_simds
= 2;
1922 rdev
->config
.evergreen
.max_backends
= 1 * rdev
->config
.evergreen
.num_ses
;
1923 rdev
->config
.evergreen
.max_gprs
= 256;
1924 rdev
->config
.evergreen
.max_threads
= 192;
1925 rdev
->config
.evergreen
.max_gs_threads
= 16;
1926 rdev
->config
.evergreen
.max_stack_entries
= 256;
1927 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1928 rdev
->config
.evergreen
.sx_max_export_size
= 128;
1929 rdev
->config
.evergreen
.sx_max_export_pos_size
= 32;
1930 rdev
->config
.evergreen
.sx_max_export_smx_size
= 96;
1931 rdev
->config
.evergreen
.max_hw_contexts
= 4;
1932 rdev
->config
.evergreen
.sq_num_cf_insts
= 1;
1934 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x40;
1935 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1936 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1937 gb_addr_config
= CAICOS_GB_ADDR_CONFIG_GOLDEN
;
1941 /* Initialize HDP */
1942 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
1943 WREG32((0x2c14 + j
), 0x00000000);
1944 WREG32((0x2c18 + j
), 0x00000000);
1945 WREG32((0x2c1c + j
), 0x00000000);
1946 WREG32((0x2c20 + j
), 0x00000000);
1947 WREG32((0x2c24 + j
), 0x00000000);
1950 WREG32(GRBM_CNTL
, GRBM_READ_TIMEOUT(0xff));
1952 evergreen_fix_pci_max_read_req_size(rdev
);
1954 mc_shared_chmap
= RREG32(MC_SHARED_CHMAP
);
1955 if ((rdev
->family
== CHIP_PALM
) ||
1956 (rdev
->family
== CHIP_SUMO
) ||
1957 (rdev
->family
== CHIP_SUMO2
))
1958 mc_arb_ramcfg
= RREG32(FUS_MC_ARB_RAMCFG
);
1960 mc_arb_ramcfg
= RREG32(MC_ARB_RAMCFG
);
1962 /* setup tiling info dword. gb_addr_config is not adequate since it does
1963 * not have bank info, so create a custom tiling dword.
1964 * bits 3:0 num_pipes
1965 * bits 7:4 num_banks
1966 * bits 11:8 group_size
1967 * bits 15:12 row_size
1969 rdev
->config
.evergreen
.tile_config
= 0;
1970 switch (rdev
->config
.evergreen
.max_tile_pipes
) {
1973 rdev
->config
.evergreen
.tile_config
|= (0 << 0);
1976 rdev
->config
.evergreen
.tile_config
|= (1 << 0);
1979 rdev
->config
.evergreen
.tile_config
|= (2 << 0);
1982 rdev
->config
.evergreen
.tile_config
|= (3 << 0);
1985 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
1986 if (rdev
->flags
& RADEON_IS_IGP
)
1987 rdev
->config
.evergreen
.tile_config
|= 1 << 4;
1989 if ((mc_arb_ramcfg
& NOOFBANK_MASK
) >> NOOFBANK_SHIFT
)
1990 rdev
->config
.evergreen
.tile_config
|= 1 << 4;
1992 rdev
->config
.evergreen
.tile_config
|= 0 << 4;
1994 rdev
->config
.evergreen
.tile_config
|= 0 << 8;
1995 rdev
->config
.evergreen
.tile_config
|=
1996 ((gb_addr_config
& 0x30000000) >> 28) << 12;
1998 num_shader_engines
= (gb_addr_config
& NUM_SHADER_ENGINES(3) >> 12) + 1;
2000 if ((rdev
->family
>= CHIP_CEDAR
) && (rdev
->family
<= CHIP_HEMLOCK
)) {
2004 WREG32(RCU_IND_INDEX
, 0x204);
2005 efuse_straps_4
= RREG32(RCU_IND_DATA
);
2006 WREG32(RCU_IND_INDEX
, 0x203);
2007 efuse_straps_3
= RREG32(RCU_IND_DATA
);
2008 tmp
= (((efuse_straps_4
& 0xf) << 4) |
2009 ((efuse_straps_3
& 0xf0000000) >> 28));
2012 for (i
= (rdev
->config
.evergreen
.num_ses
- 1); i
>= 0; i
--) {
2013 u32 rb_disable_bitmap
;
2015 WREG32(GRBM_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
| SE_INDEX(i
));
2016 WREG32(RLC_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
| SE_INDEX(i
));
2017 rb_disable_bitmap
= (RREG32(CC_RB_BACKEND_DISABLE
) & 0x00ff0000) >> 16;
2019 tmp
|= rb_disable_bitmap
;
2022 /* enabled rb are just the one not disabled :) */
2023 disabled_rb_mask
= tmp
;
2025 WREG32(GRBM_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
| SE_BROADCAST_WRITES
);
2026 WREG32(RLC_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
| SE_BROADCAST_WRITES
);
2028 WREG32(GB_ADDR_CONFIG
, gb_addr_config
);
2029 WREG32(DMIF_ADDR_CONFIG
, gb_addr_config
);
2030 WREG32(HDP_ADDR_CONFIG
, gb_addr_config
);
2032 tmp
= gb_addr_config
& NUM_PIPES_MASK
;
2033 tmp
= r6xx_remap_render_backend(rdev
, tmp
, rdev
->config
.evergreen
.max_backends
,
2034 EVERGREEN_MAX_BACKENDS
, disabled_rb_mask
);
2035 WREG32(GB_BACKEND_MAP
, tmp
);
2037 WREG32(CGTS_SYS_TCC_DISABLE
, 0);
2038 WREG32(CGTS_TCC_DISABLE
, 0);
2039 WREG32(CGTS_USER_SYS_TCC_DISABLE
, 0);
2040 WREG32(CGTS_USER_TCC_DISABLE
, 0);
2042 /* set HW defaults for 3D engine */
2043 WREG32(CP_QUEUE_THRESHOLDS
, (ROQ_IB1_START(0x16) |
2044 ROQ_IB2_START(0x2b)));
2046 WREG32(CP_MEQ_THRESHOLDS
, STQ_SPLIT(0x30));
2048 WREG32(TA_CNTL_AUX
, (DISABLE_CUBE_ANISO
|
2053 sx_debug_1
= RREG32(SX_DEBUG_1
);
2054 sx_debug_1
|= ENABLE_NEW_SMX_ADDRESS
;
2055 WREG32(SX_DEBUG_1
, sx_debug_1
);
2058 smx_dc_ctl0
= RREG32(SMX_DC_CTL0
);
2059 smx_dc_ctl0
&= ~NUMBER_OF_SETS(0x1ff);
2060 smx_dc_ctl0
|= NUMBER_OF_SETS(rdev
->config
.evergreen
.sx_num_of_sets
);
2061 WREG32(SMX_DC_CTL0
, smx_dc_ctl0
);
2063 if (rdev
->family
<= CHIP_SUMO2
)
2064 WREG32(SMX_SAR_CTL0
, 0x00010000);
2066 WREG32(SX_EXPORT_BUFFER_SIZES
, (COLOR_BUFFER_SIZE((rdev
->config
.evergreen
.sx_max_export_size
/ 4) - 1) |
2067 POSITION_BUFFER_SIZE((rdev
->config
.evergreen
.sx_max_export_pos_size
/ 4) - 1) |
2068 SMX_BUFFER_SIZE((rdev
->config
.evergreen
.sx_max_export_smx_size
/ 4) - 1)));
2070 WREG32(PA_SC_FIFO_SIZE
, (SC_PRIM_FIFO_SIZE(rdev
->config
.evergreen
.sc_prim_fifo_size
) |
2071 SC_HIZ_TILE_FIFO_SIZE(rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
) |
2072 SC_EARLYZ_TILE_FIFO_SIZE(rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
)));
2074 WREG32(VGT_NUM_INSTANCES
, 1);
2075 WREG32(SPI_CONFIG_CNTL
, 0);
2076 WREG32(SPI_CONFIG_CNTL_1
, VTX_DONE_DELAY(4));
2077 WREG32(CP_PERFMON_CNTL
, 0);
2079 WREG32(SQ_MS_FIFO_SIZES
, (CACHE_FIFO_SIZE(16 * rdev
->config
.evergreen
.sq_num_cf_insts
) |
2080 FETCH_FIFO_HIWATER(0x4) |
2081 DONE_FIFO_HIWATER(0xe0) |
2082 ALU_UPDATE_FIFO_HIWATER(0x8)));
2084 sq_config
= RREG32(SQ_CONFIG
);
2085 sq_config
&= ~(PS_PRIO(3) |
2089 sq_config
|= (VC_ENABLE
|
2096 switch (rdev
->family
) {
2102 /* no vertex cache */
2103 sq_config
&= ~VC_ENABLE
;
2109 sq_lds_resource_mgmt
= RREG32(SQ_LDS_RESOURCE_MGMT
);
2111 sq_gpr_resource_mgmt_1
= NUM_PS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2))* 12 / 32);
2112 sq_gpr_resource_mgmt_1
|= NUM_VS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 6 / 32);
2113 sq_gpr_resource_mgmt_1
|= NUM_CLAUSE_TEMP_GPRS(4);
2114 sq_gpr_resource_mgmt_2
= NUM_GS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 4 / 32);
2115 sq_gpr_resource_mgmt_2
|= NUM_ES_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 4 / 32);
2116 sq_gpr_resource_mgmt_3
= NUM_HS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 3 / 32);
2117 sq_gpr_resource_mgmt_3
|= NUM_LS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 3 / 32);
2119 switch (rdev
->family
) {
2124 ps_thread_count
= 96;
2127 ps_thread_count
= 128;
2131 sq_thread_resource_mgmt
= NUM_PS_THREADS(ps_thread_count
);
2132 sq_thread_resource_mgmt
|= NUM_VS_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
2133 sq_thread_resource_mgmt
|= NUM_GS_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
2134 sq_thread_resource_mgmt
|= NUM_ES_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
2135 sq_thread_resource_mgmt_2
= NUM_HS_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
2136 sq_thread_resource_mgmt_2
|= NUM_LS_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
2138 sq_stack_resource_mgmt_1
= NUM_PS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2139 sq_stack_resource_mgmt_1
|= NUM_VS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2140 sq_stack_resource_mgmt_2
= NUM_GS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2141 sq_stack_resource_mgmt_2
|= NUM_ES_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2142 sq_stack_resource_mgmt_3
= NUM_HS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2143 sq_stack_resource_mgmt_3
|= NUM_LS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2145 WREG32(SQ_CONFIG
, sq_config
);
2146 WREG32(SQ_GPR_RESOURCE_MGMT_1
, sq_gpr_resource_mgmt_1
);
2147 WREG32(SQ_GPR_RESOURCE_MGMT_2
, sq_gpr_resource_mgmt_2
);
2148 WREG32(SQ_GPR_RESOURCE_MGMT_3
, sq_gpr_resource_mgmt_3
);
2149 WREG32(SQ_THREAD_RESOURCE_MGMT
, sq_thread_resource_mgmt
);
2150 WREG32(SQ_THREAD_RESOURCE_MGMT_2
, sq_thread_resource_mgmt_2
);
2151 WREG32(SQ_STACK_RESOURCE_MGMT_1
, sq_stack_resource_mgmt_1
);
2152 WREG32(SQ_STACK_RESOURCE_MGMT_2
, sq_stack_resource_mgmt_2
);
2153 WREG32(SQ_STACK_RESOURCE_MGMT_3
, sq_stack_resource_mgmt_3
);
2154 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0);
2155 WREG32(SQ_LDS_RESOURCE_MGMT
, sq_lds_resource_mgmt
);
2157 WREG32(PA_SC_FORCE_EOV_MAX_CNTS
, (FORCE_EOV_MAX_CLK_CNT(4095) |
2158 FORCE_EOV_MAX_REZ_CNT(255)));
2160 switch (rdev
->family
) {
2166 vgt_cache_invalidation
= CACHE_INVALIDATION(TC_ONLY
);
2169 vgt_cache_invalidation
= CACHE_INVALIDATION(VC_AND_TC
);
2172 vgt_cache_invalidation
|= AUTO_INVLD_EN(ES_AND_GS_AUTO
);
2173 WREG32(VGT_CACHE_INVALIDATION
, vgt_cache_invalidation
);
2175 WREG32(VGT_GS_VERTEX_REUSE
, 16);
2176 WREG32(PA_SU_LINE_STIPPLE_VALUE
, 0);
2177 WREG32(PA_SC_LINE_STIPPLE_STATE
, 0);
2179 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
2180 WREG32(VGT_OUT_DEALLOC_CNTL
, 16);
2182 WREG32(CB_PERF_CTR0_SEL_0
, 0);
2183 WREG32(CB_PERF_CTR0_SEL_1
, 0);
2184 WREG32(CB_PERF_CTR1_SEL_0
, 0);
2185 WREG32(CB_PERF_CTR1_SEL_1
, 0);
2186 WREG32(CB_PERF_CTR2_SEL_0
, 0);
2187 WREG32(CB_PERF_CTR2_SEL_1
, 0);
2188 WREG32(CB_PERF_CTR3_SEL_0
, 0);
2189 WREG32(CB_PERF_CTR3_SEL_1
, 0);
2191 /* clear render buffer base addresses */
2192 WREG32(CB_COLOR0_BASE
, 0);
2193 WREG32(CB_COLOR1_BASE
, 0);
2194 WREG32(CB_COLOR2_BASE
, 0);
2195 WREG32(CB_COLOR3_BASE
, 0);
2196 WREG32(CB_COLOR4_BASE
, 0);
2197 WREG32(CB_COLOR5_BASE
, 0);
2198 WREG32(CB_COLOR6_BASE
, 0);
2199 WREG32(CB_COLOR7_BASE
, 0);
2200 WREG32(CB_COLOR8_BASE
, 0);
2201 WREG32(CB_COLOR9_BASE
, 0);
2202 WREG32(CB_COLOR10_BASE
, 0);
2203 WREG32(CB_COLOR11_BASE
, 0);
2205 /* set the shader const cache sizes to 0 */
2206 for (i
= SQ_ALU_CONST_BUFFER_SIZE_PS_0
; i
< 0x28200; i
+= 4)
2208 for (i
= SQ_ALU_CONST_BUFFER_SIZE_HS_0
; i
< 0x29000; i
+= 4)
2211 tmp
= RREG32(HDP_MISC_CNTL
);
2212 tmp
|= HDP_FLUSH_INVALIDATE_CACHE
;
2213 WREG32(HDP_MISC_CNTL
, tmp
);
2215 hdp_host_path_cntl
= RREG32(HDP_HOST_PATH_CNTL
);
2216 WREG32(HDP_HOST_PATH_CNTL
, hdp_host_path_cntl
);
2218 WREG32(PA_CL_ENHANCE
, CLIP_VTX_REORDER_ENA
| NUM_CLIP_SEQ(3));
2224 int evergreen_mc_init(struct radeon_device
*rdev
)
2227 int chansize
, numchan
;
2229 /* Get VRAM informations */
2230 rdev
->mc
.vram_is_ddr
= true;
2231 if ((rdev
->family
== CHIP_PALM
) ||
2232 (rdev
->family
== CHIP_SUMO
) ||
2233 (rdev
->family
== CHIP_SUMO2
))
2234 tmp
= RREG32(FUS_MC_ARB_RAMCFG
);
2236 tmp
= RREG32(MC_ARB_RAMCFG
);
2237 if (tmp
& CHANSIZE_OVERRIDE
) {
2239 } else if (tmp
& CHANSIZE_MASK
) {
2244 tmp
= RREG32(MC_SHARED_CHMAP
);
2245 switch ((tmp
& NOOFCHAN_MASK
) >> NOOFCHAN_SHIFT
) {
2260 rdev
->mc
.vram_width
= numchan
* chansize
;
2261 /* Could aper size report 0 ? */
2262 rdev
->mc
.aper_base
= pci_resource_start(rdev
->pdev
, 0);
2263 rdev
->mc
.aper_size
= pci_resource_len(rdev
->pdev
, 0);
2264 /* Setup GPU memory space */
2265 if ((rdev
->family
== CHIP_PALM
) ||
2266 (rdev
->family
== CHIP_SUMO
) ||
2267 (rdev
->family
== CHIP_SUMO2
)) {
2268 /* size in bytes on fusion */
2269 rdev
->mc
.mc_vram_size
= RREG32(CONFIG_MEMSIZE
);
2270 rdev
->mc
.real_vram_size
= RREG32(CONFIG_MEMSIZE
);
2272 /* size in MB on evergreen/cayman/tn */
2273 rdev
->mc
.mc_vram_size
= RREG32(CONFIG_MEMSIZE
) * 1024 * 1024;
2274 rdev
->mc
.real_vram_size
= RREG32(CONFIG_MEMSIZE
) * 1024 * 1024;
2276 rdev
->mc
.visible_vram_size
= rdev
->mc
.aper_size
;
2277 r700_vram_gtt_location(rdev
, &rdev
->mc
);
2278 radeon_update_bandwidth_info(rdev
);
2283 bool evergreen_gpu_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
2287 u32 grbm_status_se0
, grbm_status_se1
;
2289 srbm_status
= RREG32(SRBM_STATUS
);
2290 grbm_status
= RREG32(GRBM_STATUS
);
2291 grbm_status_se0
= RREG32(GRBM_STATUS_SE0
);
2292 grbm_status_se1
= RREG32(GRBM_STATUS_SE1
);
2293 if (!(grbm_status
& GUI_ACTIVE
)) {
2294 radeon_ring_lockup_update(ring
);
2297 /* force CP activities */
2298 radeon_ring_force_activity(rdev
, ring
);
2299 return radeon_ring_test_lockup(rdev
, ring
);
2302 static int evergreen_gpu_soft_reset(struct radeon_device
*rdev
)
2304 struct evergreen_mc_save save
;
2307 if (!(RREG32(GRBM_STATUS
) & GUI_ACTIVE
))
2310 dev_info(rdev
->dev
, "GPU softreset \n");
2311 dev_info(rdev
->dev
, " GRBM_STATUS=0x%08X\n",
2312 RREG32(GRBM_STATUS
));
2313 dev_info(rdev
->dev
, " GRBM_STATUS_SE0=0x%08X\n",
2314 RREG32(GRBM_STATUS_SE0
));
2315 dev_info(rdev
->dev
, " GRBM_STATUS_SE1=0x%08X\n",
2316 RREG32(GRBM_STATUS_SE1
));
2317 dev_info(rdev
->dev
, " SRBM_STATUS=0x%08X\n",
2318 RREG32(SRBM_STATUS
));
2319 dev_info(rdev
->dev
, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2320 RREG32(CP_STALLED_STAT1
));
2321 dev_info(rdev
->dev
, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
2322 RREG32(CP_STALLED_STAT2
));
2323 dev_info(rdev
->dev
, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
2324 RREG32(CP_BUSY_STAT
));
2325 dev_info(rdev
->dev
, " R_008680_CP_STAT = 0x%08X\n",
2327 evergreen_mc_stop(rdev
, &save
);
2328 if (evergreen_mc_wait_for_idle(rdev
)) {
2329 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
2331 /* Disable CP parsing/prefetching */
2332 WREG32(CP_ME_CNTL
, CP_ME_HALT
| CP_PFP_HALT
);
2334 /* reset all the gfx blocks */
2335 grbm_reset
= (SOFT_RESET_CP
|
2348 dev_info(rdev
->dev
, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset
);
2349 WREG32(GRBM_SOFT_RESET
, grbm_reset
);
2350 (void)RREG32(GRBM_SOFT_RESET
);
2352 WREG32(GRBM_SOFT_RESET
, 0);
2353 (void)RREG32(GRBM_SOFT_RESET
);
2354 /* Wait a little for things to settle down */
2356 dev_info(rdev
->dev
, " GRBM_STATUS=0x%08X\n",
2357 RREG32(GRBM_STATUS
));
2358 dev_info(rdev
->dev
, " GRBM_STATUS_SE0=0x%08X\n",
2359 RREG32(GRBM_STATUS_SE0
));
2360 dev_info(rdev
->dev
, " GRBM_STATUS_SE1=0x%08X\n",
2361 RREG32(GRBM_STATUS_SE1
));
2362 dev_info(rdev
->dev
, " SRBM_STATUS=0x%08X\n",
2363 RREG32(SRBM_STATUS
));
2364 dev_info(rdev
->dev
, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2365 RREG32(CP_STALLED_STAT1
));
2366 dev_info(rdev
->dev
, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
2367 RREG32(CP_STALLED_STAT2
));
2368 dev_info(rdev
->dev
, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
2369 RREG32(CP_BUSY_STAT
));
2370 dev_info(rdev
->dev
, " R_008680_CP_STAT = 0x%08X\n",
2372 evergreen_mc_resume(rdev
, &save
);
2376 int evergreen_asic_reset(struct radeon_device
*rdev
)
2378 return evergreen_gpu_soft_reset(rdev
);
2383 u32
evergreen_get_vblank_counter(struct radeon_device
*rdev
, int crtc
)
2387 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC0_REGISTER_OFFSET
);
2389 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
2391 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC2_REGISTER_OFFSET
);
2393 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
2395 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC4_REGISTER_OFFSET
);
2397 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
2403 void evergreen_disable_interrupt_state(struct radeon_device
*rdev
)
2407 if (rdev
->family
>= CHIP_CAYMAN
) {
2408 cayman_cp_int_cntl_setup(rdev
, 0,
2409 CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
);
2410 cayman_cp_int_cntl_setup(rdev
, 1, 0);
2411 cayman_cp_int_cntl_setup(rdev
, 2, 0);
2413 WREG32(CP_INT_CNTL
, CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
);
2414 WREG32(GRBM_INT_CNTL
, 0);
2415 WREG32(INT_MASK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
2416 WREG32(INT_MASK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
2417 if (rdev
->num_crtc
>= 4) {
2418 WREG32(INT_MASK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
2419 WREG32(INT_MASK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
2421 if (rdev
->num_crtc
>= 6) {
2422 WREG32(INT_MASK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
2423 WREG32(INT_MASK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
2426 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
2427 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
2428 if (rdev
->num_crtc
>= 4) {
2429 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
2430 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
2432 if (rdev
->num_crtc
>= 6) {
2433 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
2434 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
2437 /* only one DAC on DCE6 */
2438 if (!ASIC_IS_DCE6(rdev
))
2439 WREG32(DACA_AUTODETECT_INT_CONTROL
, 0);
2440 WREG32(DACB_AUTODETECT_INT_CONTROL
, 0);
2442 tmp
= RREG32(DC_HPD1_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2443 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
2444 tmp
= RREG32(DC_HPD2_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2445 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
2446 tmp
= RREG32(DC_HPD3_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2447 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
2448 tmp
= RREG32(DC_HPD4_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2449 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
2450 tmp
= RREG32(DC_HPD5_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2451 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
2452 tmp
= RREG32(DC_HPD6_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2453 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
2457 int evergreen_irq_set(struct radeon_device
*rdev
)
2459 u32 cp_int_cntl
= CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
;
2460 u32 cp_int_cntl1
= 0, cp_int_cntl2
= 0;
2461 u32 crtc1
= 0, crtc2
= 0, crtc3
= 0, crtc4
= 0, crtc5
= 0, crtc6
= 0;
2462 u32 hpd1
, hpd2
, hpd3
, hpd4
, hpd5
, hpd6
;
2463 u32 grbm_int_cntl
= 0;
2464 u32 grph1
= 0, grph2
= 0, grph3
= 0, grph4
= 0, grph5
= 0, grph6
= 0;
2465 u32 afmt1
= 0, afmt2
= 0, afmt3
= 0, afmt4
= 0, afmt5
= 0, afmt6
= 0;
2467 if (!rdev
->irq
.installed
) {
2468 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2471 /* don't enable anything if the ih is disabled */
2472 if (!rdev
->ih
.enabled
) {
2473 r600_disable_interrupts(rdev
);
2474 /* force the active interrupt state to all disabled */
2475 evergreen_disable_interrupt_state(rdev
);
2479 hpd1
= RREG32(DC_HPD1_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2480 hpd2
= RREG32(DC_HPD2_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2481 hpd3
= RREG32(DC_HPD3_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2482 hpd4
= RREG32(DC_HPD4_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2483 hpd5
= RREG32(DC_HPD5_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2484 hpd6
= RREG32(DC_HPD6_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2486 afmt1
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
2487 afmt2
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
2488 afmt3
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
2489 afmt4
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
2490 afmt5
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
2491 afmt6
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
2493 if (rdev
->family
>= CHIP_CAYMAN
) {
2494 /* enable CP interrupts on all rings */
2495 if (atomic_read(&rdev
->irq
.ring_int
[RADEON_RING_TYPE_GFX_INDEX
])) {
2496 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2497 cp_int_cntl
|= TIME_STAMP_INT_ENABLE
;
2499 if (atomic_read(&rdev
->irq
.ring_int
[CAYMAN_RING_TYPE_CP1_INDEX
])) {
2500 DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
2501 cp_int_cntl1
|= TIME_STAMP_INT_ENABLE
;
2503 if (atomic_read(&rdev
->irq
.ring_int
[CAYMAN_RING_TYPE_CP2_INDEX
])) {
2504 DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
2505 cp_int_cntl2
|= TIME_STAMP_INT_ENABLE
;
2508 if (atomic_read(&rdev
->irq
.ring_int
[RADEON_RING_TYPE_GFX_INDEX
])) {
2509 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2510 cp_int_cntl
|= RB_INT_ENABLE
;
2511 cp_int_cntl
|= TIME_STAMP_INT_ENABLE
;
2515 if (rdev
->irq
.crtc_vblank_int
[0] ||
2516 atomic_read(&rdev
->irq
.pflip
[0])) {
2517 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2518 crtc1
|= VBLANK_INT_MASK
;
2520 if (rdev
->irq
.crtc_vblank_int
[1] ||
2521 atomic_read(&rdev
->irq
.pflip
[1])) {
2522 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2523 crtc2
|= VBLANK_INT_MASK
;
2525 if (rdev
->irq
.crtc_vblank_int
[2] ||
2526 atomic_read(&rdev
->irq
.pflip
[2])) {
2527 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2528 crtc3
|= VBLANK_INT_MASK
;
2530 if (rdev
->irq
.crtc_vblank_int
[3] ||
2531 atomic_read(&rdev
->irq
.pflip
[3])) {
2532 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2533 crtc4
|= VBLANK_INT_MASK
;
2535 if (rdev
->irq
.crtc_vblank_int
[4] ||
2536 atomic_read(&rdev
->irq
.pflip
[4])) {
2537 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2538 crtc5
|= VBLANK_INT_MASK
;
2540 if (rdev
->irq
.crtc_vblank_int
[5] ||
2541 atomic_read(&rdev
->irq
.pflip
[5])) {
2542 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2543 crtc6
|= VBLANK_INT_MASK
;
2545 if (rdev
->irq
.hpd
[0]) {
2546 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2547 hpd1
|= DC_HPDx_INT_EN
;
2549 if (rdev
->irq
.hpd
[1]) {
2550 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2551 hpd2
|= DC_HPDx_INT_EN
;
2553 if (rdev
->irq
.hpd
[2]) {
2554 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2555 hpd3
|= DC_HPDx_INT_EN
;
2557 if (rdev
->irq
.hpd
[3]) {
2558 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2559 hpd4
|= DC_HPDx_INT_EN
;
2561 if (rdev
->irq
.hpd
[4]) {
2562 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2563 hpd5
|= DC_HPDx_INT_EN
;
2565 if (rdev
->irq
.hpd
[5]) {
2566 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2567 hpd6
|= DC_HPDx_INT_EN
;
2569 if (rdev
->irq
.afmt
[0]) {
2570 DRM_DEBUG("evergreen_irq_set: hdmi 0\n");
2571 afmt1
|= AFMT_AZ_FORMAT_WTRIG_MASK
;
2573 if (rdev
->irq
.afmt
[1]) {
2574 DRM_DEBUG("evergreen_irq_set: hdmi 1\n");
2575 afmt2
|= AFMT_AZ_FORMAT_WTRIG_MASK
;
2577 if (rdev
->irq
.afmt
[2]) {
2578 DRM_DEBUG("evergreen_irq_set: hdmi 2\n");
2579 afmt3
|= AFMT_AZ_FORMAT_WTRIG_MASK
;
2581 if (rdev
->irq
.afmt
[3]) {
2582 DRM_DEBUG("evergreen_irq_set: hdmi 3\n");
2583 afmt4
|= AFMT_AZ_FORMAT_WTRIG_MASK
;
2585 if (rdev
->irq
.afmt
[4]) {
2586 DRM_DEBUG("evergreen_irq_set: hdmi 4\n");
2587 afmt5
|= AFMT_AZ_FORMAT_WTRIG_MASK
;
2589 if (rdev
->irq
.afmt
[5]) {
2590 DRM_DEBUG("evergreen_irq_set: hdmi 5\n");
2591 afmt6
|= AFMT_AZ_FORMAT_WTRIG_MASK
;
2593 if (rdev
->irq
.gui_idle
) {
2594 DRM_DEBUG("gui idle\n");
2595 grbm_int_cntl
|= GUI_IDLE_INT_ENABLE
;
2598 if (rdev
->family
>= CHIP_CAYMAN
) {
2599 cayman_cp_int_cntl_setup(rdev
, 0, cp_int_cntl
);
2600 cayman_cp_int_cntl_setup(rdev
, 1, cp_int_cntl1
);
2601 cayman_cp_int_cntl_setup(rdev
, 2, cp_int_cntl2
);
2603 WREG32(CP_INT_CNTL
, cp_int_cntl
);
2604 WREG32(GRBM_INT_CNTL
, grbm_int_cntl
);
2606 WREG32(INT_MASK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, crtc1
);
2607 WREG32(INT_MASK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, crtc2
);
2608 if (rdev
->num_crtc
>= 4) {
2609 WREG32(INT_MASK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, crtc3
);
2610 WREG32(INT_MASK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, crtc4
);
2612 if (rdev
->num_crtc
>= 6) {
2613 WREG32(INT_MASK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, crtc5
);
2614 WREG32(INT_MASK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, crtc6
);
2617 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, grph1
);
2618 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, grph2
);
2619 if (rdev
->num_crtc
>= 4) {
2620 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, grph3
);
2621 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, grph4
);
2623 if (rdev
->num_crtc
>= 6) {
2624 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, grph5
);
2625 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, grph6
);
2628 WREG32(DC_HPD1_INT_CONTROL
, hpd1
);
2629 WREG32(DC_HPD2_INT_CONTROL
, hpd2
);
2630 WREG32(DC_HPD3_INT_CONTROL
, hpd3
);
2631 WREG32(DC_HPD4_INT_CONTROL
, hpd4
);
2632 WREG32(DC_HPD5_INT_CONTROL
, hpd5
);
2633 WREG32(DC_HPD6_INT_CONTROL
, hpd6
);
2635 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, afmt1
);
2636 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, afmt2
);
2637 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, afmt3
);
2638 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, afmt4
);
2639 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, afmt5
);
2640 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, afmt6
);
2645 static void evergreen_irq_ack(struct radeon_device
*rdev
)
2649 rdev
->irq
.stat_regs
.evergreen
.disp_int
= RREG32(DISP_INTERRUPT_STATUS
);
2650 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE
);
2651 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE2
);
2652 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE3
);
2653 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE4
);
2654 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE5
);
2655 rdev
->irq
.stat_regs
.evergreen
.d1grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
);
2656 rdev
->irq
.stat_regs
.evergreen
.d2grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
2657 if (rdev
->num_crtc
>= 4) {
2658 rdev
->irq
.stat_regs
.evergreen
.d3grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
);
2659 rdev
->irq
.stat_regs
.evergreen
.d4grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
2661 if (rdev
->num_crtc
>= 6) {
2662 rdev
->irq
.stat_regs
.evergreen
.d5grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
);
2663 rdev
->irq
.stat_regs
.evergreen
.d6grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
2666 rdev
->irq
.stat_regs
.evergreen
.afmt_status1
= RREG32(AFMT_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
);
2667 rdev
->irq
.stat_regs
.evergreen
.afmt_status2
= RREG32(AFMT_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
2668 rdev
->irq
.stat_regs
.evergreen
.afmt_status3
= RREG32(AFMT_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
);
2669 rdev
->irq
.stat_regs
.evergreen
.afmt_status4
= RREG32(AFMT_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
2670 rdev
->irq
.stat_regs
.evergreen
.afmt_status5
= RREG32(AFMT_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
);
2671 rdev
->irq
.stat_regs
.evergreen
.afmt_status6
= RREG32(AFMT_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
2673 if (rdev
->irq
.stat_regs
.evergreen
.d1grph_int
& GRPH_PFLIP_INT_OCCURRED
)
2674 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
2675 if (rdev
->irq
.stat_regs
.evergreen
.d2grph_int
& GRPH_PFLIP_INT_OCCURRED
)
2676 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
2677 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& LB_D1_VBLANK_INTERRUPT
)
2678 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, VBLANK_ACK
);
2679 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& LB_D1_VLINE_INTERRUPT
)
2680 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, VLINE_ACK
);
2681 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& LB_D2_VBLANK_INTERRUPT
)
2682 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, VBLANK_ACK
);
2683 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& LB_D2_VLINE_INTERRUPT
)
2684 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, VLINE_ACK
);
2686 if (rdev
->num_crtc
>= 4) {
2687 if (rdev
->irq
.stat_regs
.evergreen
.d3grph_int
& GRPH_PFLIP_INT_OCCURRED
)
2688 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
2689 if (rdev
->irq
.stat_regs
.evergreen
.d4grph_int
& GRPH_PFLIP_INT_OCCURRED
)
2690 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
2691 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& LB_D3_VBLANK_INTERRUPT
)
2692 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, VBLANK_ACK
);
2693 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& LB_D3_VLINE_INTERRUPT
)
2694 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, VLINE_ACK
);
2695 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& LB_D4_VBLANK_INTERRUPT
)
2696 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, VBLANK_ACK
);
2697 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& LB_D4_VLINE_INTERRUPT
)
2698 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, VLINE_ACK
);
2701 if (rdev
->num_crtc
>= 6) {
2702 if (rdev
->irq
.stat_regs
.evergreen
.d5grph_int
& GRPH_PFLIP_INT_OCCURRED
)
2703 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
2704 if (rdev
->irq
.stat_regs
.evergreen
.d6grph_int
& GRPH_PFLIP_INT_OCCURRED
)
2705 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
2706 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& LB_D5_VBLANK_INTERRUPT
)
2707 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, VBLANK_ACK
);
2708 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& LB_D5_VLINE_INTERRUPT
)
2709 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, VLINE_ACK
);
2710 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& LB_D6_VBLANK_INTERRUPT
)
2711 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, VBLANK_ACK
);
2712 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& LB_D6_VLINE_INTERRUPT
)
2713 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, VLINE_ACK
);
2716 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& DC_HPD1_INTERRUPT
) {
2717 tmp
= RREG32(DC_HPD1_INT_CONTROL
);
2718 tmp
|= DC_HPDx_INT_ACK
;
2719 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
2721 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& DC_HPD2_INTERRUPT
) {
2722 tmp
= RREG32(DC_HPD2_INT_CONTROL
);
2723 tmp
|= DC_HPDx_INT_ACK
;
2724 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
2726 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& DC_HPD3_INTERRUPT
) {
2727 tmp
= RREG32(DC_HPD3_INT_CONTROL
);
2728 tmp
|= DC_HPDx_INT_ACK
;
2729 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
2731 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& DC_HPD4_INTERRUPT
) {
2732 tmp
= RREG32(DC_HPD4_INT_CONTROL
);
2733 tmp
|= DC_HPDx_INT_ACK
;
2734 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
2736 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& DC_HPD5_INTERRUPT
) {
2737 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
2738 tmp
|= DC_HPDx_INT_ACK
;
2739 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
2741 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& DC_HPD6_INTERRUPT
) {
2742 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
2743 tmp
|= DC_HPDx_INT_ACK
;
2744 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
2746 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status1
& AFMT_AZ_FORMAT_WTRIG
) {
2747 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
);
2748 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
2749 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, tmp
);
2751 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status2
& AFMT_AZ_FORMAT_WTRIG
) {
2752 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
2753 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
2754 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, tmp
);
2756 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status3
& AFMT_AZ_FORMAT_WTRIG
) {
2757 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
);
2758 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
2759 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, tmp
);
2761 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status4
& AFMT_AZ_FORMAT_WTRIG
) {
2762 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
2763 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
2764 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, tmp
);
2766 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status5
& AFMT_AZ_FORMAT_WTRIG
) {
2767 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
);
2768 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
2769 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, tmp
);
2771 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status6
& AFMT_AZ_FORMAT_WTRIG
) {
2772 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
2773 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
2774 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, tmp
);
2778 void evergreen_irq_disable(struct radeon_device
*rdev
)
2780 r600_disable_interrupts(rdev
);
2781 /* Wait and acknowledge irq */
2783 evergreen_irq_ack(rdev
);
2784 evergreen_disable_interrupt_state(rdev
);
2787 void evergreen_irq_suspend(struct radeon_device
*rdev
)
2789 evergreen_irq_disable(rdev
);
2790 r600_rlc_stop(rdev
);
2793 static u32
evergreen_get_ih_wptr(struct radeon_device
*rdev
)
2797 if (rdev
->wb
.enabled
)
2798 wptr
= le32_to_cpu(rdev
->wb
.wb
[R600_WB_IH_WPTR_OFFSET
/4]);
2800 wptr
= RREG32(IH_RB_WPTR
);
2802 if (wptr
& RB_OVERFLOW
) {
2803 /* When a ring buffer overflow happen start parsing interrupt
2804 * from the last not overwritten vector (wptr + 16). Hopefully
2805 * this should allow us to catchup.
2807 dev_warn(rdev
->dev
, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2808 wptr
, rdev
->ih
.rptr
, (wptr
+ 16) + rdev
->ih
.ptr_mask
);
2809 rdev
->ih
.rptr
= (wptr
+ 16) & rdev
->ih
.ptr_mask
;
2810 tmp
= RREG32(IH_RB_CNTL
);
2811 tmp
|= IH_WPTR_OVERFLOW_CLEAR
;
2812 WREG32(IH_RB_CNTL
, tmp
);
2814 return (wptr
& rdev
->ih
.ptr_mask
);
2817 int evergreen_irq_process(struct radeon_device
*rdev
)
2821 u32 src_id
, src_data
;
2823 bool queue_hotplug
= false;
2824 bool queue_hdmi
= false;
2826 if (!rdev
->ih
.enabled
|| rdev
->shutdown
)
2829 wptr
= evergreen_get_ih_wptr(rdev
);
2832 /* is somebody else already processing irqs? */
2833 if (atomic_xchg(&rdev
->ih
.lock
, 1))
2836 rptr
= rdev
->ih
.rptr
;
2837 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr
, wptr
);
2839 /* Order reading of wptr vs. reading of IH ring data */
2842 /* display interrupts */
2843 evergreen_irq_ack(rdev
);
2845 while (rptr
!= wptr
) {
2846 /* wptr/rptr are in bytes! */
2847 ring_index
= rptr
/ 4;
2848 src_id
= le32_to_cpu(rdev
->ih
.ring
[ring_index
]) & 0xff;
2849 src_data
= le32_to_cpu(rdev
->ih
.ring
[ring_index
+ 1]) & 0xfffffff;
2852 case 1: /* D1 vblank/vline */
2854 case 0: /* D1 vblank */
2855 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& LB_D1_VBLANK_INTERRUPT
) {
2856 if (rdev
->irq
.crtc_vblank_int
[0]) {
2857 drm_handle_vblank(rdev
->ddev
, 0);
2858 rdev
->pm
.vblank_sync
= true;
2859 wake_up(&rdev
->irq
.vblank_queue
);
2861 if (atomic_read(&rdev
->irq
.pflip
[0]))
2862 radeon_crtc_handle_flip(rdev
, 0);
2863 rdev
->irq
.stat_regs
.evergreen
.disp_int
&= ~LB_D1_VBLANK_INTERRUPT
;
2864 DRM_DEBUG("IH: D1 vblank\n");
2867 case 1: /* D1 vline */
2868 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& LB_D1_VLINE_INTERRUPT
) {
2869 rdev
->irq
.stat_regs
.evergreen
.disp_int
&= ~LB_D1_VLINE_INTERRUPT
;
2870 DRM_DEBUG("IH: D1 vline\n");
2874 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2878 case 2: /* D2 vblank/vline */
2880 case 0: /* D2 vblank */
2881 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& LB_D2_VBLANK_INTERRUPT
) {
2882 if (rdev
->irq
.crtc_vblank_int
[1]) {
2883 drm_handle_vblank(rdev
->ddev
, 1);
2884 rdev
->pm
.vblank_sync
= true;
2885 wake_up(&rdev
->irq
.vblank_queue
);
2887 if (atomic_read(&rdev
->irq
.pflip
[1]))
2888 radeon_crtc_handle_flip(rdev
, 1);
2889 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
&= ~LB_D2_VBLANK_INTERRUPT
;
2890 DRM_DEBUG("IH: D2 vblank\n");
2893 case 1: /* D2 vline */
2894 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& LB_D2_VLINE_INTERRUPT
) {
2895 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
&= ~LB_D2_VLINE_INTERRUPT
;
2896 DRM_DEBUG("IH: D2 vline\n");
2900 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2904 case 3: /* D3 vblank/vline */
2906 case 0: /* D3 vblank */
2907 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& LB_D3_VBLANK_INTERRUPT
) {
2908 if (rdev
->irq
.crtc_vblank_int
[2]) {
2909 drm_handle_vblank(rdev
->ddev
, 2);
2910 rdev
->pm
.vblank_sync
= true;
2911 wake_up(&rdev
->irq
.vblank_queue
);
2913 if (atomic_read(&rdev
->irq
.pflip
[2]))
2914 radeon_crtc_handle_flip(rdev
, 2);
2915 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
&= ~LB_D3_VBLANK_INTERRUPT
;
2916 DRM_DEBUG("IH: D3 vblank\n");
2919 case 1: /* D3 vline */
2920 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& LB_D3_VLINE_INTERRUPT
) {
2921 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
&= ~LB_D3_VLINE_INTERRUPT
;
2922 DRM_DEBUG("IH: D3 vline\n");
2926 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2930 case 4: /* D4 vblank/vline */
2932 case 0: /* D4 vblank */
2933 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& LB_D4_VBLANK_INTERRUPT
) {
2934 if (rdev
->irq
.crtc_vblank_int
[3]) {
2935 drm_handle_vblank(rdev
->ddev
, 3);
2936 rdev
->pm
.vblank_sync
= true;
2937 wake_up(&rdev
->irq
.vblank_queue
);
2939 if (atomic_read(&rdev
->irq
.pflip
[3]))
2940 radeon_crtc_handle_flip(rdev
, 3);
2941 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
&= ~LB_D4_VBLANK_INTERRUPT
;
2942 DRM_DEBUG("IH: D4 vblank\n");
2945 case 1: /* D4 vline */
2946 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& LB_D4_VLINE_INTERRUPT
) {
2947 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
&= ~LB_D4_VLINE_INTERRUPT
;
2948 DRM_DEBUG("IH: D4 vline\n");
2952 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2956 case 5: /* D5 vblank/vline */
2958 case 0: /* D5 vblank */
2959 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& LB_D5_VBLANK_INTERRUPT
) {
2960 if (rdev
->irq
.crtc_vblank_int
[4]) {
2961 drm_handle_vblank(rdev
->ddev
, 4);
2962 rdev
->pm
.vblank_sync
= true;
2963 wake_up(&rdev
->irq
.vblank_queue
);
2965 if (atomic_read(&rdev
->irq
.pflip
[4]))
2966 radeon_crtc_handle_flip(rdev
, 4);
2967 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
&= ~LB_D5_VBLANK_INTERRUPT
;
2968 DRM_DEBUG("IH: D5 vblank\n");
2971 case 1: /* D5 vline */
2972 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& LB_D5_VLINE_INTERRUPT
) {
2973 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
&= ~LB_D5_VLINE_INTERRUPT
;
2974 DRM_DEBUG("IH: D5 vline\n");
2978 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2982 case 6: /* D6 vblank/vline */
2984 case 0: /* D6 vblank */
2985 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& LB_D6_VBLANK_INTERRUPT
) {
2986 if (rdev
->irq
.crtc_vblank_int
[5]) {
2987 drm_handle_vblank(rdev
->ddev
, 5);
2988 rdev
->pm
.vblank_sync
= true;
2989 wake_up(&rdev
->irq
.vblank_queue
);
2991 if (atomic_read(&rdev
->irq
.pflip
[5]))
2992 radeon_crtc_handle_flip(rdev
, 5);
2993 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
&= ~LB_D6_VBLANK_INTERRUPT
;
2994 DRM_DEBUG("IH: D6 vblank\n");
2997 case 1: /* D6 vline */
2998 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& LB_D6_VLINE_INTERRUPT
) {
2999 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
&= ~LB_D6_VLINE_INTERRUPT
;
3000 DRM_DEBUG("IH: D6 vline\n");
3004 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3008 case 42: /* HPD hotplug */
3011 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& DC_HPD1_INTERRUPT
) {
3012 rdev
->irq
.stat_regs
.evergreen
.disp_int
&= ~DC_HPD1_INTERRUPT
;
3013 queue_hotplug
= true;
3014 DRM_DEBUG("IH: HPD1\n");
3018 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& DC_HPD2_INTERRUPT
) {
3019 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
&= ~DC_HPD2_INTERRUPT
;
3020 queue_hotplug
= true;
3021 DRM_DEBUG("IH: HPD2\n");
3025 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& DC_HPD3_INTERRUPT
) {
3026 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
&= ~DC_HPD3_INTERRUPT
;
3027 queue_hotplug
= true;
3028 DRM_DEBUG("IH: HPD3\n");
3032 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& DC_HPD4_INTERRUPT
) {
3033 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
&= ~DC_HPD4_INTERRUPT
;
3034 queue_hotplug
= true;
3035 DRM_DEBUG("IH: HPD4\n");
3039 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& DC_HPD5_INTERRUPT
) {
3040 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
&= ~DC_HPD5_INTERRUPT
;
3041 queue_hotplug
= true;
3042 DRM_DEBUG("IH: HPD5\n");
3046 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& DC_HPD6_INTERRUPT
) {
3047 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
&= ~DC_HPD6_INTERRUPT
;
3048 queue_hotplug
= true;
3049 DRM_DEBUG("IH: HPD6\n");
3053 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3060 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status1
& AFMT_AZ_FORMAT_WTRIG
) {
3061 rdev
->irq
.stat_regs
.evergreen
.afmt_status1
&= ~AFMT_AZ_FORMAT_WTRIG
;
3063 DRM_DEBUG("IH: HDMI0\n");
3067 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status2
& AFMT_AZ_FORMAT_WTRIG
) {
3068 rdev
->irq
.stat_regs
.evergreen
.afmt_status2
&= ~AFMT_AZ_FORMAT_WTRIG
;
3070 DRM_DEBUG("IH: HDMI1\n");
3074 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status3
& AFMT_AZ_FORMAT_WTRIG
) {
3075 rdev
->irq
.stat_regs
.evergreen
.afmt_status3
&= ~AFMT_AZ_FORMAT_WTRIG
;
3077 DRM_DEBUG("IH: HDMI2\n");
3081 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status4
& AFMT_AZ_FORMAT_WTRIG
) {
3082 rdev
->irq
.stat_regs
.evergreen
.afmt_status4
&= ~AFMT_AZ_FORMAT_WTRIG
;
3084 DRM_DEBUG("IH: HDMI3\n");
3088 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status5
& AFMT_AZ_FORMAT_WTRIG
) {
3089 rdev
->irq
.stat_regs
.evergreen
.afmt_status5
&= ~AFMT_AZ_FORMAT_WTRIG
;
3091 DRM_DEBUG("IH: HDMI4\n");
3095 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status6
& AFMT_AZ_FORMAT_WTRIG
) {
3096 rdev
->irq
.stat_regs
.evergreen
.afmt_status6
&= ~AFMT_AZ_FORMAT_WTRIG
;
3098 DRM_DEBUG("IH: HDMI5\n");
3102 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3106 case 176: /* CP_INT in ring buffer */
3107 case 177: /* CP_INT in IB1 */
3108 case 178: /* CP_INT in IB2 */
3109 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data
);
3110 radeon_fence_process(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
3112 case 181: /* CP EOP event */
3113 DRM_DEBUG("IH: CP EOP\n");
3114 if (rdev
->family
>= CHIP_CAYMAN
) {
3117 radeon_fence_process(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
3120 radeon_fence_process(rdev
, CAYMAN_RING_TYPE_CP1_INDEX
);
3123 radeon_fence_process(rdev
, CAYMAN_RING_TYPE_CP2_INDEX
);
3127 radeon_fence_process(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
3129 case 233: /* GUI IDLE */
3130 DRM_DEBUG("IH: GUI idle\n");
3131 wake_up(&rdev
->irq
.idle_queue
);
3134 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3138 /* wptr/rptr are in bytes! */
3140 rptr
&= rdev
->ih
.ptr_mask
;
3143 schedule_work(&rdev
->hotplug_work
);
3145 schedule_work(&rdev
->audio_work
);
3146 rdev
->ih
.rptr
= rptr
;
3147 WREG32(IH_RB_RPTR
, rdev
->ih
.rptr
);
3148 atomic_set(&rdev
->ih
.lock
, 0);
3150 /* make sure wptr hasn't changed while processing */
3151 wptr
= evergreen_get_ih_wptr(rdev
);
3158 static int evergreen_startup(struct radeon_device
*rdev
)
3160 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
3163 /* enable pcie gen2 link */
3164 evergreen_pcie_gen2_enable(rdev
);
3166 if (ASIC_IS_DCE5(rdev
)) {
3167 if (!rdev
->me_fw
|| !rdev
->pfp_fw
|| !rdev
->rlc_fw
|| !rdev
->mc_fw
) {
3168 r
= ni_init_microcode(rdev
);
3170 DRM_ERROR("Failed to load firmware!\n");
3174 r
= ni_mc_load_microcode(rdev
);
3176 DRM_ERROR("Failed to load MC firmware!\n");
3180 if (!rdev
->me_fw
|| !rdev
->pfp_fw
|| !rdev
->rlc_fw
) {
3181 r
= r600_init_microcode(rdev
);
3183 DRM_ERROR("Failed to load firmware!\n");
3189 r
= r600_vram_scratch_init(rdev
);
3193 evergreen_mc_program(rdev
);
3194 if (rdev
->flags
& RADEON_IS_AGP
) {
3195 evergreen_agp_enable(rdev
);
3197 r
= evergreen_pcie_gart_enable(rdev
);
3201 evergreen_gpu_init(rdev
);
3203 r
= evergreen_blit_init(rdev
);
3205 r600_blit_fini(rdev
);
3206 rdev
->asic
->copy
.copy
= NULL
;
3207 dev_warn(rdev
->dev
, "failed blitter (%d) falling back to memcpy\n", r
);
3210 /* allocate wb buffer */
3211 r
= radeon_wb_init(rdev
);
3215 r
= radeon_fence_driver_start_ring(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
3217 dev_err(rdev
->dev
, "failed initializing CP fences (%d).\n", r
);
3222 r
= r600_irq_init(rdev
);
3224 DRM_ERROR("radeon: IH init failed (%d).\n", r
);
3225 radeon_irq_kms_fini(rdev
);
3228 evergreen_irq_set(rdev
);
3230 r
= radeon_ring_init(rdev
, ring
, ring
->ring_size
, RADEON_WB_CP_RPTR_OFFSET
,
3231 R600_CP_RB_RPTR
, R600_CP_RB_WPTR
,
3232 0, 0xfffff, RADEON_CP_PACKET2
);
3235 r
= evergreen_cp_load_microcode(rdev
);
3238 r
= evergreen_cp_resume(rdev
);
3242 r
= radeon_ib_pool_init(rdev
);
3244 dev_err(rdev
->dev
, "IB initialization failed (%d).\n", r
);
3248 r
= r600_audio_init(rdev
);
3250 DRM_ERROR("radeon: audio init failed\n");
3257 int evergreen_resume(struct radeon_device
*rdev
)
3261 /* reset the asic, the gfx blocks are often in a bad state
3262 * after the driver is unloaded or after a resume
3264 if (radeon_asic_reset(rdev
))
3265 dev_warn(rdev
->dev
, "GPU reset failed !\n");
3266 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3267 * posting will perform necessary task to bring back GPU into good
3271 atom_asic_init(rdev
->mode_info
.atom_context
);
3273 rdev
->accel_working
= true;
3274 r
= evergreen_startup(rdev
);
3276 DRM_ERROR("evergreen startup failed on resume\n");
3277 rdev
->accel_working
= false;
3285 int evergreen_suspend(struct radeon_device
*rdev
)
3287 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
3289 r600_audio_fini(rdev
);
3291 ring
->ready
= false;
3292 evergreen_irq_suspend(rdev
);
3293 radeon_wb_disable(rdev
);
3294 evergreen_pcie_gart_disable(rdev
);
3299 /* Plan is to move initialization in that function and use
3300 * helper function so that radeon_device_init pretty much
3301 * do nothing more than calling asic specific function. This
3302 * should also allow to remove a bunch of callback function
3305 int evergreen_init(struct radeon_device
*rdev
)
3310 if (!radeon_get_bios(rdev
)) {
3311 if (ASIC_IS_AVIVO(rdev
))
3314 /* Must be an ATOMBIOS */
3315 if (!rdev
->is_atom_bios
) {
3316 dev_err(rdev
->dev
, "Expecting atombios for evergreen GPU\n");
3319 r
= radeon_atombios_init(rdev
);
3322 /* reset the asic, the gfx blocks are often in a bad state
3323 * after the driver is unloaded or after a resume
3325 if (radeon_asic_reset(rdev
))
3326 dev_warn(rdev
->dev
, "GPU reset failed !\n");
3327 /* Post card if necessary */
3328 if (!radeon_card_posted(rdev
)) {
3330 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
3333 DRM_INFO("GPU not posted. posting now...\n");
3334 atom_asic_init(rdev
->mode_info
.atom_context
);
3336 /* Initialize scratch registers */
3337 r600_scratch_init(rdev
);
3338 /* Initialize surface registers */
3339 radeon_surface_init(rdev
);
3340 /* Initialize clocks */
3341 radeon_get_clock_info(rdev
->ddev
);
3343 r
= radeon_fence_driver_init(rdev
);
3346 /* initialize AGP */
3347 if (rdev
->flags
& RADEON_IS_AGP
) {
3348 r
= radeon_agp_init(rdev
);
3350 radeon_agp_disable(rdev
);
3352 /* initialize memory controller */
3353 r
= evergreen_mc_init(rdev
);
3356 /* Memory manager */
3357 r
= radeon_bo_init(rdev
);
3361 r
= radeon_irq_kms_init(rdev
);
3365 rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
].ring_obj
= NULL
;
3366 r600_ring_init(rdev
, &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
], 1024 * 1024);
3368 rdev
->ih
.ring_obj
= NULL
;
3369 r600_ih_ring_init(rdev
, 64 * 1024);
3371 r
= r600_pcie_gart_init(rdev
);
3375 rdev
->accel_working
= true;
3376 r
= evergreen_startup(rdev
);
3378 dev_err(rdev
->dev
, "disabling GPU acceleration\n");
3380 r600_irq_fini(rdev
);
3381 radeon_wb_fini(rdev
);
3382 radeon_ib_pool_fini(rdev
);
3383 radeon_irq_kms_fini(rdev
);
3384 evergreen_pcie_gart_fini(rdev
);
3385 rdev
->accel_working
= false;
3388 /* Don't start up if the MC ucode is missing on BTC parts.
3389 * The default clocks and voltages before the MC ucode
3390 * is loaded are not suffient for advanced operations.
3392 if (ASIC_IS_DCE5(rdev
)) {
3393 if (!rdev
->mc_fw
&& !(rdev
->flags
& RADEON_IS_IGP
)) {
3394 DRM_ERROR("radeon: MC ucode required for NI+.\n");
3402 void evergreen_fini(struct radeon_device
*rdev
)
3404 r600_audio_fini(rdev
);
3405 r600_blit_fini(rdev
);
3407 r600_irq_fini(rdev
);
3408 radeon_wb_fini(rdev
);
3409 radeon_ib_pool_fini(rdev
);
3410 radeon_irq_kms_fini(rdev
);
3411 evergreen_pcie_gart_fini(rdev
);
3412 r600_vram_scratch_fini(rdev
);
3413 radeon_gem_fini(rdev
);
3414 radeon_fence_driver_fini(rdev
);
3415 radeon_agp_fini(rdev
);
3416 radeon_bo_fini(rdev
);
3417 radeon_atombios_fini(rdev
);
3422 void evergreen_pcie_gen2_enable(struct radeon_device
*rdev
)
3424 u32 link_width_cntl
, speed_cntl
, mask
;
3427 if (radeon_pcie_gen2
== 0)
3430 if (rdev
->flags
& RADEON_IS_IGP
)
3433 if (!(rdev
->flags
& RADEON_IS_PCIE
))
3436 /* x2 cards have a special sequence */
3437 if (ASIC_IS_X2(rdev
))
3440 ret
= drm_pcie_get_speed_cap_mask(rdev
->ddev
, &mask
);
3444 if (!(mask
& DRM_PCIE_SPEED_50
))
3447 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
3449 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3450 if ((speed_cntl
& LC_OTHER_SIDE_EVER_SENT_GEN2
) ||
3451 (speed_cntl
& LC_OTHER_SIDE_SUPPORTS_GEN2
)) {
3453 link_width_cntl
= RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
);
3454 link_width_cntl
&= ~LC_UPCONFIGURE_DIS
;
3455 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
3457 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3458 speed_cntl
&= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN
;
3459 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3461 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3462 speed_cntl
|= LC_CLR_FAILED_SPD_CHANGE_CNT
;
3463 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3465 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3466 speed_cntl
&= ~LC_CLR_FAILED_SPD_CHANGE_CNT
;
3467 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3469 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3470 speed_cntl
|= LC_GEN2_EN_STRAP
;
3471 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3474 link_width_cntl
= RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
);
3475 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3477 link_width_cntl
|= LC_UPCONFIGURE_DIS
;
3479 link_width_cntl
&= ~LC_UPCONFIGURE_DIS
;
3480 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);