2 * Copyright 2010 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
29 #include "radeon_asic.h"
30 #include "radeon_drm.h"
31 #include "evergreend.h"
34 #include "evergreen_reg.h"
35 #include "evergreen_blit_shaders.h"
37 #define EVERGREEN_PFP_UCODE_SIZE 1120
38 #define EVERGREEN_PM4_UCODE_SIZE 1376
40 static void evergreen_gpu_init(struct radeon_device
*rdev
);
41 void evergreen_fini(struct radeon_device
*rdev
);
42 void evergreen_pcie_gen2_enable(struct radeon_device
*rdev
);
43 extern void cayman_cp_int_cntl_setup(struct radeon_device
*rdev
,
44 int ring
, u32 cp_int_cntl
);
46 void evergreen_tiling_fields(unsigned tiling_flags
, unsigned *bankw
,
47 unsigned *bankh
, unsigned *mtaspect
,
50 *bankw
= (tiling_flags
>> RADEON_TILING_EG_BANKW_SHIFT
) & RADEON_TILING_EG_BANKW_MASK
;
51 *bankh
= (tiling_flags
>> RADEON_TILING_EG_BANKH_SHIFT
) & RADEON_TILING_EG_BANKH_MASK
;
52 *mtaspect
= (tiling_flags
>> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT
) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK
;
53 *tile_split
= (tiling_flags
>> RADEON_TILING_EG_TILE_SPLIT_SHIFT
) & RADEON_TILING_EG_TILE_SPLIT_MASK
;
56 case 1: *bankw
= EVERGREEN_ADDR_SURF_BANK_WIDTH_1
; break;
57 case 2: *bankw
= EVERGREEN_ADDR_SURF_BANK_WIDTH_2
; break;
58 case 4: *bankw
= EVERGREEN_ADDR_SURF_BANK_WIDTH_4
; break;
59 case 8: *bankw
= EVERGREEN_ADDR_SURF_BANK_WIDTH_8
; break;
63 case 1: *bankh
= EVERGREEN_ADDR_SURF_BANK_HEIGHT_1
; break;
64 case 2: *bankh
= EVERGREEN_ADDR_SURF_BANK_HEIGHT_2
; break;
65 case 4: *bankh
= EVERGREEN_ADDR_SURF_BANK_HEIGHT_4
; break;
66 case 8: *bankh
= EVERGREEN_ADDR_SURF_BANK_HEIGHT_8
; break;
70 case 1: *mtaspect
= EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1
; break;
71 case 2: *mtaspect
= EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2
; break;
72 case 4: *mtaspect
= EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4
; break;
73 case 8: *mtaspect
= EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8
; break;
77 void evergreen_fix_pci_max_read_req_size(struct radeon_device
*rdev
)
82 cap
= pci_pcie_cap(rdev
->pdev
);
86 err
= pci_read_config_word(rdev
->pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
90 v
= (ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12;
92 /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
93 * to avoid hangs or perfomance issues
95 if ((v
== 0) || (v
== 6) || (v
== 7)) {
96 ctl
&= ~PCI_EXP_DEVCTL_READRQ
;
98 pci_write_config_word(rdev
->pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
102 void dce4_wait_for_vblank(struct radeon_device
*rdev
, int crtc
)
104 struct radeon_crtc
*radeon_crtc
= rdev
->mode_info
.crtcs
[crtc
];
107 if (RREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
) & EVERGREEN_CRTC_MASTER_EN
) {
108 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
109 if (!(RREG32(EVERGREEN_CRTC_STATUS
+ radeon_crtc
->crtc_offset
) & EVERGREEN_CRTC_V_BLANK
))
113 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
114 if (RREG32(EVERGREEN_CRTC_STATUS
+ radeon_crtc
->crtc_offset
) & EVERGREEN_CRTC_V_BLANK
)
121 void evergreen_pre_page_flip(struct radeon_device
*rdev
, int crtc
)
123 /* enable the pflip int */
124 radeon_irq_kms_pflip_irq_get(rdev
, crtc
);
127 void evergreen_post_page_flip(struct radeon_device
*rdev
, int crtc
)
129 /* disable the pflip int */
130 radeon_irq_kms_pflip_irq_put(rdev
, crtc
);
133 u32
evergreen_page_flip(struct radeon_device
*rdev
, int crtc_id
, u64 crtc_base
)
135 struct radeon_crtc
*radeon_crtc
= rdev
->mode_info
.crtcs
[crtc_id
];
136 u32 tmp
= RREG32(EVERGREEN_GRPH_UPDATE
+ radeon_crtc
->crtc_offset
);
139 /* Lock the graphics update lock */
140 tmp
|= EVERGREEN_GRPH_UPDATE_LOCK
;
141 WREG32(EVERGREEN_GRPH_UPDATE
+ radeon_crtc
->crtc_offset
, tmp
);
143 /* update the scanout addresses */
144 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ radeon_crtc
->crtc_offset
,
145 upper_32_bits(crtc_base
));
146 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ radeon_crtc
->crtc_offset
,
149 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ radeon_crtc
->crtc_offset
,
150 upper_32_bits(crtc_base
));
151 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ radeon_crtc
->crtc_offset
,
154 /* Wait for update_pending to go high. */
155 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
156 if (RREG32(EVERGREEN_GRPH_UPDATE
+ radeon_crtc
->crtc_offset
) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING
)
160 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
162 /* Unlock the lock, so double-buffering can take place inside vblank */
163 tmp
&= ~EVERGREEN_GRPH_UPDATE_LOCK
;
164 WREG32(EVERGREEN_GRPH_UPDATE
+ radeon_crtc
->crtc_offset
, tmp
);
166 /* Return current update_pending status: */
167 return RREG32(EVERGREEN_GRPH_UPDATE
+ radeon_crtc
->crtc_offset
) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING
;
170 /* get temperature in millidegrees */
171 int evergreen_get_temp(struct radeon_device
*rdev
)
176 if (rdev
->family
== CHIP_JUNIPER
) {
177 toffset
= (RREG32(CG_THERMAL_CTRL
) & TOFFSET_MASK
) >>
179 temp
= (RREG32(CG_TS0_STATUS
) & TS0_ADC_DOUT_MASK
) >>
183 actual_temp
= temp
/ 2 - (0x200 - toffset
);
185 actual_temp
= temp
/ 2 + toffset
;
187 actual_temp
= actual_temp
* 1000;
190 temp
= (RREG32(CG_MULT_THERMAL_STATUS
) & ASIC_T_MASK
) >>
195 else if (temp
& 0x200)
197 else if (temp
& 0x100) {
198 actual_temp
= temp
& 0x1ff;
199 actual_temp
|= ~0x1ff;
201 actual_temp
= temp
& 0xff;
203 actual_temp
= (actual_temp
* 1000) / 2;
209 int sumo_get_temp(struct radeon_device
*rdev
)
211 u32 temp
= RREG32(CG_THERMAL_STATUS
) & 0xff;
212 int actual_temp
= temp
- 49;
214 return actual_temp
* 1000;
217 void sumo_pm_init_profile(struct radeon_device
*rdev
)
222 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
223 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
224 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
225 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 0;
228 if (rdev
->flags
& RADEON_IS_MOBILITY
)
229 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_BATTERY
, 0);
231 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 0);
233 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= idx
;
234 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= idx
;
235 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
236 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
238 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= idx
;
239 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= idx
;
240 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
241 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
243 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= idx
;
244 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= idx
;
245 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
246 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 0;
248 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= idx
;
249 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= idx
;
250 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
251 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 0;
254 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 0);
255 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= idx
;
256 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= idx
;
257 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
258 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
=
259 rdev
->pm
.power_state
[idx
].num_clock_modes
- 1;
261 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= idx
;
262 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= idx
;
263 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
264 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
=
265 rdev
->pm
.power_state
[idx
].num_clock_modes
- 1;
268 void evergreen_pm_misc(struct radeon_device
*rdev
)
270 int req_ps_idx
= rdev
->pm
.requested_power_state_index
;
271 int req_cm_idx
= rdev
->pm
.requested_clock_mode_index
;
272 struct radeon_power_state
*ps
= &rdev
->pm
.power_state
[req_ps_idx
];
273 struct radeon_voltage
*voltage
= &ps
->clock_info
[req_cm_idx
].voltage
;
275 if (voltage
->type
== VOLTAGE_SW
) {
276 /* 0xff01 is a flag rather then an actual voltage */
277 if (voltage
->voltage
== 0xff01)
279 if (voltage
->voltage
&& (voltage
->voltage
!= rdev
->pm
.current_vddc
)) {
280 radeon_atom_set_voltage(rdev
, voltage
->voltage
, SET_VOLTAGE_TYPE_ASIC_VDDC
);
281 rdev
->pm
.current_vddc
= voltage
->voltage
;
282 DRM_DEBUG("Setting: vddc: %d\n", voltage
->voltage
);
284 /* 0xff01 is a flag rather then an actual voltage */
285 if (voltage
->vddci
== 0xff01)
287 if (voltage
->vddci
&& (voltage
->vddci
!= rdev
->pm
.current_vddci
)) {
288 radeon_atom_set_voltage(rdev
, voltage
->vddci
, SET_VOLTAGE_TYPE_ASIC_VDDCI
);
289 rdev
->pm
.current_vddci
= voltage
->vddci
;
290 DRM_DEBUG("Setting: vddci: %d\n", voltage
->vddci
);
295 void evergreen_pm_prepare(struct radeon_device
*rdev
)
297 struct drm_device
*ddev
= rdev
->ddev
;
298 struct drm_crtc
*crtc
;
299 struct radeon_crtc
*radeon_crtc
;
302 /* disable any active CRTCs */
303 list_for_each_entry(crtc
, &ddev
->mode_config
.crtc_list
, head
) {
304 radeon_crtc
= to_radeon_crtc(crtc
);
305 if (radeon_crtc
->enabled
) {
306 tmp
= RREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
);
307 tmp
|= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE
;
308 WREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
, tmp
);
313 void evergreen_pm_finish(struct radeon_device
*rdev
)
315 struct drm_device
*ddev
= rdev
->ddev
;
316 struct drm_crtc
*crtc
;
317 struct radeon_crtc
*radeon_crtc
;
320 /* enable any active CRTCs */
321 list_for_each_entry(crtc
, &ddev
->mode_config
.crtc_list
, head
) {
322 radeon_crtc
= to_radeon_crtc(crtc
);
323 if (radeon_crtc
->enabled
) {
324 tmp
= RREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
);
325 tmp
&= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE
;
326 WREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
, tmp
);
331 bool evergreen_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
)
333 bool connected
= false;
337 if (RREG32(DC_HPD1_INT_STATUS
) & DC_HPDx_SENSE
)
341 if (RREG32(DC_HPD2_INT_STATUS
) & DC_HPDx_SENSE
)
345 if (RREG32(DC_HPD3_INT_STATUS
) & DC_HPDx_SENSE
)
349 if (RREG32(DC_HPD4_INT_STATUS
) & DC_HPDx_SENSE
)
353 if (RREG32(DC_HPD5_INT_STATUS
) & DC_HPDx_SENSE
)
357 if (RREG32(DC_HPD6_INT_STATUS
) & DC_HPDx_SENSE
)
367 void evergreen_hpd_set_polarity(struct radeon_device
*rdev
,
368 enum radeon_hpd_id hpd
)
371 bool connected
= evergreen_hpd_sense(rdev
, hpd
);
375 tmp
= RREG32(DC_HPD1_INT_CONTROL
);
377 tmp
&= ~DC_HPDx_INT_POLARITY
;
379 tmp
|= DC_HPDx_INT_POLARITY
;
380 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
383 tmp
= RREG32(DC_HPD2_INT_CONTROL
);
385 tmp
&= ~DC_HPDx_INT_POLARITY
;
387 tmp
|= DC_HPDx_INT_POLARITY
;
388 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
391 tmp
= RREG32(DC_HPD3_INT_CONTROL
);
393 tmp
&= ~DC_HPDx_INT_POLARITY
;
395 tmp
|= DC_HPDx_INT_POLARITY
;
396 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
399 tmp
= RREG32(DC_HPD4_INT_CONTROL
);
401 tmp
&= ~DC_HPDx_INT_POLARITY
;
403 tmp
|= DC_HPDx_INT_POLARITY
;
404 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
407 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
409 tmp
&= ~DC_HPDx_INT_POLARITY
;
411 tmp
|= DC_HPDx_INT_POLARITY
;
412 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
415 tmp
= RREG32(DC_HPD6_INT_CONTROL
);
417 tmp
&= ~DC_HPDx_INT_POLARITY
;
419 tmp
|= DC_HPDx_INT_POLARITY
;
420 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
427 void evergreen_hpd_init(struct radeon_device
*rdev
)
429 struct drm_device
*dev
= rdev
->ddev
;
430 struct drm_connector
*connector
;
431 unsigned enabled
= 0;
432 u32 tmp
= DC_HPDx_CONNECTION_TIMER(0x9c4) |
433 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN
;
435 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
436 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
437 switch (radeon_connector
->hpd
.hpd
) {
439 WREG32(DC_HPD1_CONTROL
, tmp
);
442 WREG32(DC_HPD2_CONTROL
, tmp
);
445 WREG32(DC_HPD3_CONTROL
, tmp
);
448 WREG32(DC_HPD4_CONTROL
, tmp
);
451 WREG32(DC_HPD5_CONTROL
, tmp
);
454 WREG32(DC_HPD6_CONTROL
, tmp
);
459 radeon_hpd_set_polarity(rdev
, radeon_connector
->hpd
.hpd
);
460 enabled
|= 1 << radeon_connector
->hpd
.hpd
;
462 radeon_irq_kms_enable_hpd(rdev
, enabled
);
465 void evergreen_hpd_fini(struct radeon_device
*rdev
)
467 struct drm_device
*dev
= rdev
->ddev
;
468 struct drm_connector
*connector
;
469 unsigned disabled
= 0;
471 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
472 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
473 switch (radeon_connector
->hpd
.hpd
) {
475 WREG32(DC_HPD1_CONTROL
, 0);
478 WREG32(DC_HPD2_CONTROL
, 0);
481 WREG32(DC_HPD3_CONTROL
, 0);
484 WREG32(DC_HPD4_CONTROL
, 0);
487 WREG32(DC_HPD5_CONTROL
, 0);
490 WREG32(DC_HPD6_CONTROL
, 0);
495 disabled
|= 1 << radeon_connector
->hpd
.hpd
;
497 radeon_irq_kms_disable_hpd(rdev
, disabled
);
500 /* watermark setup */
502 static u32
evergreen_line_buffer_adjust(struct radeon_device
*rdev
,
503 struct radeon_crtc
*radeon_crtc
,
504 struct drm_display_mode
*mode
,
505 struct drm_display_mode
*other_mode
)
510 * There are 3 line buffers, each one shared by 2 display controllers.
511 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
512 * the display controllers. The paritioning is done via one of four
513 * preset allocations specified in bits 2:0:
514 * first display controller
515 * 0 - first half of lb (3840 * 2)
516 * 1 - first 3/4 of lb (5760 * 2)
517 * 2 - whole lb (7680 * 2), other crtc must be disabled
518 * 3 - first 1/4 of lb (1920 * 2)
519 * second display controller
520 * 4 - second half of lb (3840 * 2)
521 * 5 - second 3/4 of lb (5760 * 2)
522 * 6 - whole lb (7680 * 2), other crtc must be disabled
523 * 7 - last 1/4 of lb (1920 * 2)
525 /* this can get tricky if we have two large displays on a paired group
526 * of crtcs. Ideally for multiple large displays we'd assign them to
527 * non-linked crtcs for maximum line buffer allocation.
529 if (radeon_crtc
->base
.enabled
&& mode
) {
537 /* second controller of the pair uses second half of the lb */
538 if (radeon_crtc
->crtc_id
% 2)
540 WREG32(DC_LB_MEMORY_SPLIT
+ radeon_crtc
->crtc_offset
, tmp
);
542 if (radeon_crtc
->base
.enabled
&& mode
) {
547 if (ASIC_IS_DCE5(rdev
))
553 if (ASIC_IS_DCE5(rdev
))
559 if (ASIC_IS_DCE5(rdev
))
565 if (ASIC_IS_DCE5(rdev
))
572 /* controller not enabled, so no lb used */
576 u32
evergreen_get_number_of_dram_channels(struct radeon_device
*rdev
)
578 u32 tmp
= RREG32(MC_SHARED_CHMAP
);
580 switch ((tmp
& NOOFCHAN_MASK
) >> NOOFCHAN_SHIFT
) {
593 struct evergreen_wm_params
{
594 u32 dram_channels
; /* number of dram channels */
595 u32 yclk
; /* bandwidth per dram data pin in kHz */
596 u32 sclk
; /* engine clock in kHz */
597 u32 disp_clk
; /* display clock in kHz */
598 u32 src_width
; /* viewport width */
599 u32 active_time
; /* active display time in ns */
600 u32 blank_time
; /* blank time in ns */
601 bool interlaced
; /* mode is interlaced */
602 fixed20_12 vsc
; /* vertical scale ratio */
603 u32 num_heads
; /* number of active crtcs */
604 u32 bytes_per_pixel
; /* bytes per pixel display + overlay */
605 u32 lb_size
; /* line buffer allocated to pipe */
606 u32 vtaps
; /* vertical scaler taps */
609 static u32
evergreen_dram_bandwidth(struct evergreen_wm_params
*wm
)
611 /* Calculate DRAM Bandwidth and the part allocated to display. */
612 fixed20_12 dram_efficiency
; /* 0.7 */
613 fixed20_12 yclk
, dram_channels
, bandwidth
;
616 a
.full
= dfixed_const(1000);
617 yclk
.full
= dfixed_const(wm
->yclk
);
618 yclk
.full
= dfixed_div(yclk
, a
);
619 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
620 a
.full
= dfixed_const(10);
621 dram_efficiency
.full
= dfixed_const(7);
622 dram_efficiency
.full
= dfixed_div(dram_efficiency
, a
);
623 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
624 bandwidth
.full
= dfixed_mul(bandwidth
, dram_efficiency
);
626 return dfixed_trunc(bandwidth
);
629 static u32
evergreen_dram_bandwidth_for_display(struct evergreen_wm_params
*wm
)
631 /* Calculate DRAM Bandwidth and the part allocated to display. */
632 fixed20_12 disp_dram_allocation
; /* 0.3 to 0.7 */
633 fixed20_12 yclk
, dram_channels
, bandwidth
;
636 a
.full
= dfixed_const(1000);
637 yclk
.full
= dfixed_const(wm
->yclk
);
638 yclk
.full
= dfixed_div(yclk
, a
);
639 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
640 a
.full
= dfixed_const(10);
641 disp_dram_allocation
.full
= dfixed_const(3); /* XXX worse case value 0.3 */
642 disp_dram_allocation
.full
= dfixed_div(disp_dram_allocation
, a
);
643 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
644 bandwidth
.full
= dfixed_mul(bandwidth
, disp_dram_allocation
);
646 return dfixed_trunc(bandwidth
);
649 static u32
evergreen_data_return_bandwidth(struct evergreen_wm_params
*wm
)
651 /* Calculate the display Data return Bandwidth */
652 fixed20_12 return_efficiency
; /* 0.8 */
653 fixed20_12 sclk
, bandwidth
;
656 a
.full
= dfixed_const(1000);
657 sclk
.full
= dfixed_const(wm
->sclk
);
658 sclk
.full
= dfixed_div(sclk
, a
);
659 a
.full
= dfixed_const(10);
660 return_efficiency
.full
= dfixed_const(8);
661 return_efficiency
.full
= dfixed_div(return_efficiency
, a
);
662 a
.full
= dfixed_const(32);
663 bandwidth
.full
= dfixed_mul(a
, sclk
);
664 bandwidth
.full
= dfixed_mul(bandwidth
, return_efficiency
);
666 return dfixed_trunc(bandwidth
);
669 static u32
evergreen_dmif_request_bandwidth(struct evergreen_wm_params
*wm
)
671 /* Calculate the DMIF Request Bandwidth */
672 fixed20_12 disp_clk_request_efficiency
; /* 0.8 */
673 fixed20_12 disp_clk
, bandwidth
;
676 a
.full
= dfixed_const(1000);
677 disp_clk
.full
= dfixed_const(wm
->disp_clk
);
678 disp_clk
.full
= dfixed_div(disp_clk
, a
);
679 a
.full
= dfixed_const(10);
680 disp_clk_request_efficiency
.full
= dfixed_const(8);
681 disp_clk_request_efficiency
.full
= dfixed_div(disp_clk_request_efficiency
, a
);
682 a
.full
= dfixed_const(32);
683 bandwidth
.full
= dfixed_mul(a
, disp_clk
);
684 bandwidth
.full
= dfixed_mul(bandwidth
, disp_clk_request_efficiency
);
686 return dfixed_trunc(bandwidth
);
689 static u32
evergreen_available_bandwidth(struct evergreen_wm_params
*wm
)
691 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
692 u32 dram_bandwidth
= evergreen_dram_bandwidth(wm
);
693 u32 data_return_bandwidth
= evergreen_data_return_bandwidth(wm
);
694 u32 dmif_req_bandwidth
= evergreen_dmif_request_bandwidth(wm
);
696 return min(dram_bandwidth
, min(data_return_bandwidth
, dmif_req_bandwidth
));
699 static u32
evergreen_average_bandwidth(struct evergreen_wm_params
*wm
)
701 /* Calculate the display mode Average Bandwidth
702 * DisplayMode should contain the source and destination dimensions,
706 fixed20_12 line_time
;
707 fixed20_12 src_width
;
708 fixed20_12 bandwidth
;
711 a
.full
= dfixed_const(1000);
712 line_time
.full
= dfixed_const(wm
->active_time
+ wm
->blank_time
);
713 line_time
.full
= dfixed_div(line_time
, a
);
714 bpp
.full
= dfixed_const(wm
->bytes_per_pixel
);
715 src_width
.full
= dfixed_const(wm
->src_width
);
716 bandwidth
.full
= dfixed_mul(src_width
, bpp
);
717 bandwidth
.full
= dfixed_mul(bandwidth
, wm
->vsc
);
718 bandwidth
.full
= dfixed_div(bandwidth
, line_time
);
720 return dfixed_trunc(bandwidth
);
723 static u32
evergreen_latency_watermark(struct evergreen_wm_params
*wm
)
725 /* First calcualte the latency in ns */
726 u32 mc_latency
= 2000; /* 2000 ns. */
727 u32 available_bandwidth
= evergreen_available_bandwidth(wm
);
728 u32 worst_chunk_return_time
= (512 * 8 * 1000) / available_bandwidth
;
729 u32 cursor_line_pair_return_time
= (128 * 4 * 1000) / available_bandwidth
;
730 u32 dc_latency
= 40000000 / wm
->disp_clk
; /* dc pipe latency */
731 u32 other_heads_data_return_time
= ((wm
->num_heads
+ 1) * worst_chunk_return_time
) +
732 (wm
->num_heads
* cursor_line_pair_return_time
);
733 u32 latency
= mc_latency
+ other_heads_data_return_time
+ dc_latency
;
734 u32 max_src_lines_per_dst_line
, lb_fill_bw
, line_fill_time
;
737 if (wm
->num_heads
== 0)
740 a
.full
= dfixed_const(2);
741 b
.full
= dfixed_const(1);
742 if ((wm
->vsc
.full
> a
.full
) ||
743 ((wm
->vsc
.full
> b
.full
) && (wm
->vtaps
>= 3)) ||
745 ((wm
->vsc
.full
>= a
.full
) && wm
->interlaced
))
746 max_src_lines_per_dst_line
= 4;
748 max_src_lines_per_dst_line
= 2;
750 a
.full
= dfixed_const(available_bandwidth
);
751 b
.full
= dfixed_const(wm
->num_heads
);
752 a
.full
= dfixed_div(a
, b
);
754 b
.full
= dfixed_const(1000);
755 c
.full
= dfixed_const(wm
->disp_clk
);
756 b
.full
= dfixed_div(c
, b
);
757 c
.full
= dfixed_const(wm
->bytes_per_pixel
);
758 b
.full
= dfixed_mul(b
, c
);
760 lb_fill_bw
= min(dfixed_trunc(a
), dfixed_trunc(b
));
762 a
.full
= dfixed_const(max_src_lines_per_dst_line
* wm
->src_width
* wm
->bytes_per_pixel
);
763 b
.full
= dfixed_const(1000);
764 c
.full
= dfixed_const(lb_fill_bw
);
765 b
.full
= dfixed_div(c
, b
);
766 a
.full
= dfixed_div(a
, b
);
767 line_fill_time
= dfixed_trunc(a
);
769 if (line_fill_time
< wm
->active_time
)
772 return latency
+ (line_fill_time
- wm
->active_time
);
776 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params
*wm
)
778 if (evergreen_average_bandwidth(wm
) <=
779 (evergreen_dram_bandwidth_for_display(wm
) / wm
->num_heads
))
785 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params
*wm
)
787 if (evergreen_average_bandwidth(wm
) <=
788 (evergreen_available_bandwidth(wm
) / wm
->num_heads
))
794 static bool evergreen_check_latency_hiding(struct evergreen_wm_params
*wm
)
796 u32 lb_partitions
= wm
->lb_size
/ wm
->src_width
;
797 u32 line_time
= wm
->active_time
+ wm
->blank_time
;
798 u32 latency_tolerant_lines
;
802 a
.full
= dfixed_const(1);
803 if (wm
->vsc
.full
> a
.full
)
804 latency_tolerant_lines
= 1;
806 if (lb_partitions
<= (wm
->vtaps
+ 1))
807 latency_tolerant_lines
= 1;
809 latency_tolerant_lines
= 2;
812 latency_hiding
= (latency_tolerant_lines
* line_time
+ wm
->blank_time
);
814 if (evergreen_latency_watermark(wm
) <= latency_hiding
)
820 static void evergreen_program_watermarks(struct radeon_device
*rdev
,
821 struct radeon_crtc
*radeon_crtc
,
822 u32 lb_size
, u32 num_heads
)
824 struct drm_display_mode
*mode
= &radeon_crtc
->base
.mode
;
825 struct evergreen_wm_params wm
;
828 u32 latency_watermark_a
= 0, latency_watermark_b
= 0;
829 u32 priority_a_mark
= 0, priority_b_mark
= 0;
830 u32 priority_a_cnt
= PRIORITY_OFF
;
831 u32 priority_b_cnt
= PRIORITY_OFF
;
832 u32 pipe_offset
= radeon_crtc
->crtc_id
* 16;
833 u32 tmp
, arb_control3
;
836 if (radeon_crtc
->base
.enabled
&& num_heads
&& mode
) {
837 pixel_period
= 1000000 / (u32
)mode
->clock
;
838 line_time
= min((u32
)mode
->crtc_htotal
* pixel_period
, (u32
)65535);
842 wm
.yclk
= rdev
->pm
.current_mclk
* 10;
843 wm
.sclk
= rdev
->pm
.current_sclk
* 10;
844 wm
.disp_clk
= mode
->clock
;
845 wm
.src_width
= mode
->crtc_hdisplay
;
846 wm
.active_time
= mode
->crtc_hdisplay
* pixel_period
;
847 wm
.blank_time
= line_time
- wm
.active_time
;
848 wm
.interlaced
= false;
849 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
850 wm
.interlaced
= true;
851 wm
.vsc
= radeon_crtc
->vsc
;
853 if (radeon_crtc
->rmx_type
!= RMX_OFF
)
855 wm
.bytes_per_pixel
= 4; /* XXX: get this from fb config */
856 wm
.lb_size
= lb_size
;
857 wm
.dram_channels
= evergreen_get_number_of_dram_channels(rdev
);
858 wm
.num_heads
= num_heads
;
860 /* set for high clocks */
861 latency_watermark_a
= min(evergreen_latency_watermark(&wm
), (u32
)65535);
862 /* set for low clocks */
863 /* wm.yclk = low clk; wm.sclk = low clk */
864 latency_watermark_b
= min(evergreen_latency_watermark(&wm
), (u32
)65535);
866 /* possibly force display priority to high */
867 /* should really do this at mode validation time... */
868 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm
) ||
869 !evergreen_average_bandwidth_vs_available_bandwidth(&wm
) ||
870 !evergreen_check_latency_hiding(&wm
) ||
871 (rdev
->disp_priority
== 2)) {
872 DRM_DEBUG_KMS("force priority to high\n");
873 priority_a_cnt
|= PRIORITY_ALWAYS_ON
;
874 priority_b_cnt
|= PRIORITY_ALWAYS_ON
;
877 a
.full
= dfixed_const(1000);
878 b
.full
= dfixed_const(mode
->clock
);
879 b
.full
= dfixed_div(b
, a
);
880 c
.full
= dfixed_const(latency_watermark_a
);
881 c
.full
= dfixed_mul(c
, b
);
882 c
.full
= dfixed_mul(c
, radeon_crtc
->hsc
);
883 c
.full
= dfixed_div(c
, a
);
884 a
.full
= dfixed_const(16);
885 c
.full
= dfixed_div(c
, a
);
886 priority_a_mark
= dfixed_trunc(c
);
887 priority_a_cnt
|= priority_a_mark
& PRIORITY_MARK_MASK
;
889 a
.full
= dfixed_const(1000);
890 b
.full
= dfixed_const(mode
->clock
);
891 b
.full
= dfixed_div(b
, a
);
892 c
.full
= dfixed_const(latency_watermark_b
);
893 c
.full
= dfixed_mul(c
, b
);
894 c
.full
= dfixed_mul(c
, radeon_crtc
->hsc
);
895 c
.full
= dfixed_div(c
, a
);
896 a
.full
= dfixed_const(16);
897 c
.full
= dfixed_div(c
, a
);
898 priority_b_mark
= dfixed_trunc(c
);
899 priority_b_cnt
|= priority_b_mark
& PRIORITY_MARK_MASK
;
903 arb_control3
= RREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
);
905 tmp
&= ~LATENCY_WATERMARK_MASK(3);
906 tmp
|= LATENCY_WATERMARK_MASK(1);
907 WREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
, tmp
);
908 WREG32(PIPE0_LATENCY_CONTROL
+ pipe_offset
,
909 (LATENCY_LOW_WATERMARK(latency_watermark_a
) |
910 LATENCY_HIGH_WATERMARK(line_time
)));
912 tmp
= RREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
);
913 tmp
&= ~LATENCY_WATERMARK_MASK(3);
914 tmp
|= LATENCY_WATERMARK_MASK(2);
915 WREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
, tmp
);
916 WREG32(PIPE0_LATENCY_CONTROL
+ pipe_offset
,
917 (LATENCY_LOW_WATERMARK(latency_watermark_b
) |
918 LATENCY_HIGH_WATERMARK(line_time
)));
919 /* restore original selection */
920 WREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
, arb_control3
);
922 /* write the priority marks */
923 WREG32(PRIORITY_A_CNT
+ radeon_crtc
->crtc_offset
, priority_a_cnt
);
924 WREG32(PRIORITY_B_CNT
+ radeon_crtc
->crtc_offset
, priority_b_cnt
);
928 void evergreen_bandwidth_update(struct radeon_device
*rdev
)
930 struct drm_display_mode
*mode0
= NULL
;
931 struct drm_display_mode
*mode1
= NULL
;
932 u32 num_heads
= 0, lb_size
;
935 radeon_update_display_priority(rdev
);
937 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
938 if (rdev
->mode_info
.crtcs
[i
]->base
.enabled
)
941 for (i
= 0; i
< rdev
->num_crtc
; i
+= 2) {
942 mode0
= &rdev
->mode_info
.crtcs
[i
]->base
.mode
;
943 mode1
= &rdev
->mode_info
.crtcs
[i
+1]->base
.mode
;
944 lb_size
= evergreen_line_buffer_adjust(rdev
, rdev
->mode_info
.crtcs
[i
], mode0
, mode1
);
945 evergreen_program_watermarks(rdev
, rdev
->mode_info
.crtcs
[i
], lb_size
, num_heads
);
946 lb_size
= evergreen_line_buffer_adjust(rdev
, rdev
->mode_info
.crtcs
[i
+1], mode1
, mode0
);
947 evergreen_program_watermarks(rdev
, rdev
->mode_info
.crtcs
[i
+1], lb_size
, num_heads
);
951 int evergreen_mc_wait_for_idle(struct radeon_device
*rdev
)
956 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
958 tmp
= RREG32(SRBM_STATUS
) & 0x1F00;
969 void evergreen_pcie_gart_tlb_flush(struct radeon_device
*rdev
)
974 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL
, 0x1);
976 WREG32(VM_CONTEXT0_REQUEST_RESPONSE
, REQUEST_TYPE(1));
977 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
979 tmp
= RREG32(VM_CONTEXT0_REQUEST_RESPONSE
);
980 tmp
= (tmp
& RESPONSE_TYPE_MASK
) >> RESPONSE_TYPE_SHIFT
;
982 printk(KERN_WARNING
"[drm] r600 flush TLB failed\n");
992 int evergreen_pcie_gart_enable(struct radeon_device
*rdev
)
997 if (rdev
->gart
.robj
== NULL
) {
998 dev_err(rdev
->dev
, "No VRAM object for PCIE GART.\n");
1001 r
= radeon_gart_table_vram_pin(rdev
);
1004 radeon_gart_restore(rdev
);
1005 /* Setup L2 cache */
1006 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
1007 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
1008 EFFECTIVE_L2_QUEUE_SIZE(7));
1009 WREG32(VM_L2_CNTL2
, 0);
1010 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1011 /* Setup TLB control */
1012 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
1013 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
1014 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
|
1015 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1016 if (rdev
->flags
& RADEON_IS_IGP
) {
1017 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL
, tmp
);
1018 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL
, tmp
);
1019 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL
, tmp
);
1021 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
1022 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
1023 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
1024 if ((rdev
->family
== CHIP_JUNIPER
) ||
1025 (rdev
->family
== CHIP_CYPRESS
) ||
1026 (rdev
->family
== CHIP_HEMLOCK
) ||
1027 (rdev
->family
== CHIP_BARTS
))
1028 WREG32(MC_VM_MD_L1_TLB3_CNTL
, tmp
);
1030 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
1031 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
1032 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
1033 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
1034 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR
, rdev
->mc
.gtt_start
>> 12);
1035 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR
, rdev
->mc
.gtt_end
>> 12);
1036 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, rdev
->gart
.table_addr
>> 12);
1037 WREG32(VM_CONTEXT0_CNTL
, ENABLE_CONTEXT
| PAGE_TABLE_DEPTH(0) |
1038 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
);
1039 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
,
1040 (u32
)(rdev
->dummy_page
.addr
>> 12));
1041 WREG32(VM_CONTEXT1_CNTL
, 0);
1043 evergreen_pcie_gart_tlb_flush(rdev
);
1044 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1045 (unsigned)(rdev
->mc
.gtt_size
>> 20),
1046 (unsigned long long)rdev
->gart
.table_addr
);
1047 rdev
->gart
.ready
= true;
1051 void evergreen_pcie_gart_disable(struct radeon_device
*rdev
)
1055 /* Disable all tables */
1056 WREG32(VM_CONTEXT0_CNTL
, 0);
1057 WREG32(VM_CONTEXT1_CNTL
, 0);
1059 /* Setup L2 cache */
1060 WREG32(VM_L2_CNTL
, ENABLE_L2_FRAGMENT_PROCESSING
|
1061 EFFECTIVE_L2_QUEUE_SIZE(7));
1062 WREG32(VM_L2_CNTL2
, 0);
1063 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1064 /* Setup TLB control */
1065 tmp
= EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1066 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
1067 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
1068 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
1069 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
1070 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
1071 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
1072 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
1073 radeon_gart_table_vram_unpin(rdev
);
1076 void evergreen_pcie_gart_fini(struct radeon_device
*rdev
)
1078 evergreen_pcie_gart_disable(rdev
);
1079 radeon_gart_table_vram_free(rdev
);
1080 radeon_gart_fini(rdev
);
1084 void evergreen_agp_enable(struct radeon_device
*rdev
)
1088 /* Setup L2 cache */
1089 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
1090 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
1091 EFFECTIVE_L2_QUEUE_SIZE(7));
1092 WREG32(VM_L2_CNTL2
, 0);
1093 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1094 /* Setup TLB control */
1095 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
1096 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
1097 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
|
1098 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1099 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
1100 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
1101 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
1102 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
1103 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
1104 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
1105 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
1106 WREG32(VM_CONTEXT0_CNTL
, 0);
1107 WREG32(VM_CONTEXT1_CNTL
, 0);
1110 void evergreen_mc_stop(struct radeon_device
*rdev
, struct evergreen_mc_save
*save
)
1112 save
->vga_control
[0] = RREG32(D1VGA_CONTROL
);
1113 save
->vga_control
[1] = RREG32(D2VGA_CONTROL
);
1114 save
->vga_render_control
= RREG32(VGA_RENDER_CONTROL
);
1115 save
->vga_hdp_control
= RREG32(VGA_HDP_CONTROL
);
1116 save
->crtc_control
[0] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
);
1117 save
->crtc_control
[1] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
1118 if (rdev
->num_crtc
>= 4) {
1119 save
->vga_control
[2] = RREG32(EVERGREEN_D3VGA_CONTROL
);
1120 save
->vga_control
[3] = RREG32(EVERGREEN_D4VGA_CONTROL
);
1121 save
->crtc_control
[2] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
);
1122 save
->crtc_control
[3] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
1124 if (rdev
->num_crtc
>= 6) {
1125 save
->vga_control
[4] = RREG32(EVERGREEN_D5VGA_CONTROL
);
1126 save
->vga_control
[5] = RREG32(EVERGREEN_D6VGA_CONTROL
);
1127 save
->crtc_control
[4] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
);
1128 save
->crtc_control
[5] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
1131 /* Stop all video */
1132 WREG32(VGA_RENDER_CONTROL
, 0);
1133 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 1);
1134 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 1);
1135 if (rdev
->num_crtc
>= 4) {
1136 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 1);
1137 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 1);
1139 if (rdev
->num_crtc
>= 6) {
1140 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 1);
1141 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 1);
1143 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
1144 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
1145 if (rdev
->num_crtc
>= 4) {
1146 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
1147 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
1149 if (rdev
->num_crtc
>= 6) {
1150 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
1151 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
1153 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
1154 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
1155 if (rdev
->num_crtc
>= 4) {
1156 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
1157 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
1159 if (rdev
->num_crtc
>= 6) {
1160 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
1161 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
1164 WREG32(D1VGA_CONTROL
, 0);
1165 WREG32(D2VGA_CONTROL
, 0);
1166 if (rdev
->num_crtc
>= 4) {
1167 WREG32(EVERGREEN_D3VGA_CONTROL
, 0);
1168 WREG32(EVERGREEN_D4VGA_CONTROL
, 0);
1170 if (rdev
->num_crtc
>= 6) {
1171 WREG32(EVERGREEN_D5VGA_CONTROL
, 0);
1172 WREG32(EVERGREEN_D6VGA_CONTROL
, 0);
1176 void evergreen_mc_resume(struct radeon_device
*rdev
, struct evergreen_mc_save
*save
)
1178 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC0_REGISTER_OFFSET
,
1179 upper_32_bits(rdev
->mc
.vram_start
));
1180 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC0_REGISTER_OFFSET
,
1181 upper_32_bits(rdev
->mc
.vram_start
));
1182 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
,
1183 (u32
)rdev
->mc
.vram_start
);
1184 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
,
1185 (u32
)rdev
->mc
.vram_start
);
1187 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC1_REGISTER_OFFSET
,
1188 upper_32_bits(rdev
->mc
.vram_start
));
1189 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC1_REGISTER_OFFSET
,
1190 upper_32_bits(rdev
->mc
.vram_start
));
1191 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
,
1192 (u32
)rdev
->mc
.vram_start
);
1193 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
,
1194 (u32
)rdev
->mc
.vram_start
);
1196 if (rdev
->num_crtc
>= 4) {
1197 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC2_REGISTER_OFFSET
,
1198 upper_32_bits(rdev
->mc
.vram_start
));
1199 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC2_REGISTER_OFFSET
,
1200 upper_32_bits(rdev
->mc
.vram_start
));
1201 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
,
1202 (u32
)rdev
->mc
.vram_start
);
1203 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
,
1204 (u32
)rdev
->mc
.vram_start
);
1206 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC3_REGISTER_OFFSET
,
1207 upper_32_bits(rdev
->mc
.vram_start
));
1208 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC3_REGISTER_OFFSET
,
1209 upper_32_bits(rdev
->mc
.vram_start
));
1210 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
,
1211 (u32
)rdev
->mc
.vram_start
);
1212 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
,
1213 (u32
)rdev
->mc
.vram_start
);
1215 if (rdev
->num_crtc
>= 6) {
1216 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC4_REGISTER_OFFSET
,
1217 upper_32_bits(rdev
->mc
.vram_start
));
1218 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC4_REGISTER_OFFSET
,
1219 upper_32_bits(rdev
->mc
.vram_start
));
1220 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
,
1221 (u32
)rdev
->mc
.vram_start
);
1222 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
,
1223 (u32
)rdev
->mc
.vram_start
);
1225 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC5_REGISTER_OFFSET
,
1226 upper_32_bits(rdev
->mc
.vram_start
));
1227 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC5_REGISTER_OFFSET
,
1228 upper_32_bits(rdev
->mc
.vram_start
));
1229 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
,
1230 (u32
)rdev
->mc
.vram_start
);
1231 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
,
1232 (u32
)rdev
->mc
.vram_start
);
1235 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH
, upper_32_bits(rdev
->mc
.vram_start
));
1236 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS
, (u32
)rdev
->mc
.vram_start
);
1237 /* Unlock host access */
1238 WREG32(VGA_HDP_CONTROL
, save
->vga_hdp_control
);
1240 /* Restore video state */
1241 WREG32(D1VGA_CONTROL
, save
->vga_control
[0]);
1242 WREG32(D2VGA_CONTROL
, save
->vga_control
[1]);
1243 if (rdev
->num_crtc
>= 4) {
1244 WREG32(EVERGREEN_D3VGA_CONTROL
, save
->vga_control
[2]);
1245 WREG32(EVERGREEN_D4VGA_CONTROL
, save
->vga_control
[3]);
1247 if (rdev
->num_crtc
>= 6) {
1248 WREG32(EVERGREEN_D5VGA_CONTROL
, save
->vga_control
[4]);
1249 WREG32(EVERGREEN_D6VGA_CONTROL
, save
->vga_control
[5]);
1251 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 1);
1252 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 1);
1253 if (rdev
->num_crtc
>= 4) {
1254 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 1);
1255 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 1);
1257 if (rdev
->num_crtc
>= 6) {
1258 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 1);
1259 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 1);
1261 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, save
->crtc_control
[0]);
1262 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, save
->crtc_control
[1]);
1263 if (rdev
->num_crtc
>= 4) {
1264 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, save
->crtc_control
[2]);
1265 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, save
->crtc_control
[3]);
1267 if (rdev
->num_crtc
>= 6) {
1268 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, save
->crtc_control
[4]);
1269 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, save
->crtc_control
[5]);
1271 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
1272 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
1273 if (rdev
->num_crtc
>= 4) {
1274 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
1275 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
1277 if (rdev
->num_crtc
>= 6) {
1278 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
1279 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
1281 WREG32(VGA_RENDER_CONTROL
, save
->vga_render_control
);
1284 void evergreen_mc_program(struct radeon_device
*rdev
)
1286 struct evergreen_mc_save save
;
1290 /* Initialize HDP */
1291 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
1292 WREG32((0x2c14 + j
), 0x00000000);
1293 WREG32((0x2c18 + j
), 0x00000000);
1294 WREG32((0x2c1c + j
), 0x00000000);
1295 WREG32((0x2c20 + j
), 0x00000000);
1296 WREG32((0x2c24 + j
), 0x00000000);
1298 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL
, 0);
1300 evergreen_mc_stop(rdev
, &save
);
1301 if (evergreen_mc_wait_for_idle(rdev
)) {
1302 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1304 /* Lockout access through VGA aperture*/
1305 WREG32(VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
);
1306 /* Update configuration */
1307 if (rdev
->flags
& RADEON_IS_AGP
) {
1308 if (rdev
->mc
.vram_start
< rdev
->mc
.gtt_start
) {
1309 /* VRAM before AGP */
1310 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
1311 rdev
->mc
.vram_start
>> 12);
1312 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
1313 rdev
->mc
.gtt_end
>> 12);
1315 /* VRAM after AGP */
1316 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
1317 rdev
->mc
.gtt_start
>> 12);
1318 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
1319 rdev
->mc
.vram_end
>> 12);
1322 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
1323 rdev
->mc
.vram_start
>> 12);
1324 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
1325 rdev
->mc
.vram_end
>> 12);
1327 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
, rdev
->vram_scratch
.gpu_addr
>> 12);
1328 /* llano/ontario only */
1329 if ((rdev
->family
== CHIP_PALM
) ||
1330 (rdev
->family
== CHIP_SUMO
) ||
1331 (rdev
->family
== CHIP_SUMO2
)) {
1332 tmp
= RREG32(MC_FUS_VM_FB_OFFSET
) & 0x000FFFFF;
1333 tmp
|= ((rdev
->mc
.vram_end
>> 20) & 0xF) << 24;
1334 tmp
|= ((rdev
->mc
.vram_start
>> 20) & 0xF) << 20;
1335 WREG32(MC_FUS_VM_FB_OFFSET
, tmp
);
1337 tmp
= ((rdev
->mc
.vram_end
>> 24) & 0xFFFF) << 16;
1338 tmp
|= ((rdev
->mc
.vram_start
>> 24) & 0xFFFF);
1339 WREG32(MC_VM_FB_LOCATION
, tmp
);
1340 WREG32(HDP_NONSURFACE_BASE
, (rdev
->mc
.vram_start
>> 8));
1341 WREG32(HDP_NONSURFACE_INFO
, (2 << 7) | (1 << 30));
1342 WREG32(HDP_NONSURFACE_SIZE
, 0x3FFFFFFF);
1343 if (rdev
->flags
& RADEON_IS_AGP
) {
1344 WREG32(MC_VM_AGP_TOP
, rdev
->mc
.gtt_end
>> 16);
1345 WREG32(MC_VM_AGP_BOT
, rdev
->mc
.gtt_start
>> 16);
1346 WREG32(MC_VM_AGP_BASE
, rdev
->mc
.agp_base
>> 22);
1348 WREG32(MC_VM_AGP_BASE
, 0);
1349 WREG32(MC_VM_AGP_TOP
, 0x0FFFFFFF);
1350 WREG32(MC_VM_AGP_BOT
, 0x0FFFFFFF);
1352 if (evergreen_mc_wait_for_idle(rdev
)) {
1353 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1355 evergreen_mc_resume(rdev
, &save
);
1356 /* we need to own VRAM, so turn off the VGA renderer here
1357 * to stop it overwriting our objects */
1358 rv515_vga_render_disable(rdev
);
1364 void evergreen_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
1366 struct radeon_ring
*ring
= &rdev
->ring
[ib
->ring
];
1368 /* set to DX10/11 mode */
1369 radeon_ring_write(ring
, PACKET3(PACKET3_MODE_CONTROL
, 0));
1370 radeon_ring_write(ring
, 1);
1371 /* FIXME: implement */
1372 radeon_ring_write(ring
, PACKET3(PACKET3_INDIRECT_BUFFER
, 2));
1373 radeon_ring_write(ring
,
1377 (ib
->gpu_addr
& 0xFFFFFFFC));
1378 radeon_ring_write(ring
, upper_32_bits(ib
->gpu_addr
) & 0xFF);
1379 radeon_ring_write(ring
, ib
->length_dw
);
1383 static int evergreen_cp_load_microcode(struct radeon_device
*rdev
)
1385 const __be32
*fw_data
;
1388 if (!rdev
->me_fw
|| !rdev
->pfp_fw
)
1396 RB_NO_UPDATE
| RB_BLKSZ(15) | RB_BUFSZ(3));
1398 fw_data
= (const __be32
*)rdev
->pfp_fw
->data
;
1399 WREG32(CP_PFP_UCODE_ADDR
, 0);
1400 for (i
= 0; i
< EVERGREEN_PFP_UCODE_SIZE
; i
++)
1401 WREG32(CP_PFP_UCODE_DATA
, be32_to_cpup(fw_data
++));
1402 WREG32(CP_PFP_UCODE_ADDR
, 0);
1404 fw_data
= (const __be32
*)rdev
->me_fw
->data
;
1405 WREG32(CP_ME_RAM_WADDR
, 0);
1406 for (i
= 0; i
< EVERGREEN_PM4_UCODE_SIZE
; i
++)
1407 WREG32(CP_ME_RAM_DATA
, be32_to_cpup(fw_data
++));
1409 WREG32(CP_PFP_UCODE_ADDR
, 0);
1410 WREG32(CP_ME_RAM_WADDR
, 0);
1411 WREG32(CP_ME_RAM_RADDR
, 0);
1415 static int evergreen_cp_start(struct radeon_device
*rdev
)
1417 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
1421 r
= radeon_ring_lock(rdev
, ring
, 7);
1423 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
1426 radeon_ring_write(ring
, PACKET3(PACKET3_ME_INITIALIZE
, 5));
1427 radeon_ring_write(ring
, 0x1);
1428 radeon_ring_write(ring
, 0x0);
1429 radeon_ring_write(ring
, rdev
->config
.evergreen
.max_hw_contexts
- 1);
1430 radeon_ring_write(ring
, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1431 radeon_ring_write(ring
, 0);
1432 radeon_ring_write(ring
, 0);
1433 radeon_ring_unlock_commit(rdev
, ring
);
1436 WREG32(CP_ME_CNTL
, cp_me
);
1438 r
= radeon_ring_lock(rdev
, ring
, evergreen_default_size
+ 19);
1440 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
1444 /* setup clear context state */
1445 radeon_ring_write(ring
, PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
1446 radeon_ring_write(ring
, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE
);
1448 for (i
= 0; i
< evergreen_default_size
; i
++)
1449 radeon_ring_write(ring
, evergreen_default_state
[i
]);
1451 radeon_ring_write(ring
, PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
1452 radeon_ring_write(ring
, PACKET3_PREAMBLE_END_CLEAR_STATE
);
1454 /* set clear context state */
1455 radeon_ring_write(ring
, PACKET3(PACKET3_CLEAR_STATE
, 0));
1456 radeon_ring_write(ring
, 0);
1458 /* SQ_VTX_BASE_VTX_LOC */
1459 radeon_ring_write(ring
, 0xc0026f00);
1460 radeon_ring_write(ring
, 0x00000000);
1461 radeon_ring_write(ring
, 0x00000000);
1462 radeon_ring_write(ring
, 0x00000000);
1465 radeon_ring_write(ring
, 0xc0036f00);
1466 radeon_ring_write(ring
, 0x00000bc4);
1467 radeon_ring_write(ring
, 0xffffffff);
1468 radeon_ring_write(ring
, 0xffffffff);
1469 radeon_ring_write(ring
, 0xffffffff);
1471 radeon_ring_write(ring
, 0xc0026900);
1472 radeon_ring_write(ring
, 0x00000316);
1473 radeon_ring_write(ring
, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1474 radeon_ring_write(ring
, 0x00000010); /* */
1476 radeon_ring_unlock_commit(rdev
, ring
);
1481 int evergreen_cp_resume(struct radeon_device
*rdev
)
1483 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
1488 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1489 WREG32(GRBM_SOFT_RESET
, (SOFT_RESET_CP
|
1495 RREG32(GRBM_SOFT_RESET
);
1497 WREG32(GRBM_SOFT_RESET
, 0);
1498 RREG32(GRBM_SOFT_RESET
);
1500 /* Set ring buffer size */
1501 rb_bufsz
= drm_order(ring
->ring_size
/ 8);
1502 tmp
= (drm_order(RADEON_GPU_PAGE_SIZE
/8) << 8) | rb_bufsz
;
1504 tmp
|= BUF_SWAP_32BIT
;
1506 WREG32(CP_RB_CNTL
, tmp
);
1507 WREG32(CP_SEM_WAIT_TIMER
, 0x0);
1508 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL
, 0x0);
1510 /* Set the write pointer delay */
1511 WREG32(CP_RB_WPTR_DELAY
, 0);
1513 /* Initialize the ring buffer's read and write pointers */
1514 WREG32(CP_RB_CNTL
, tmp
| RB_RPTR_WR_ENA
);
1515 WREG32(CP_RB_RPTR_WR
, 0);
1517 WREG32(CP_RB_WPTR
, ring
->wptr
);
1519 /* set the wb address wether it's enabled or not */
1520 WREG32(CP_RB_RPTR_ADDR
,
1521 ((rdev
->wb
.gpu_addr
+ RADEON_WB_CP_RPTR_OFFSET
) & 0xFFFFFFFC));
1522 WREG32(CP_RB_RPTR_ADDR_HI
, upper_32_bits(rdev
->wb
.gpu_addr
+ RADEON_WB_CP_RPTR_OFFSET
) & 0xFF);
1523 WREG32(SCRATCH_ADDR
, ((rdev
->wb
.gpu_addr
+ RADEON_WB_SCRATCH_OFFSET
) >> 8) & 0xFFFFFFFF);
1525 if (rdev
->wb
.enabled
)
1526 WREG32(SCRATCH_UMSK
, 0xff);
1528 tmp
|= RB_NO_UPDATE
;
1529 WREG32(SCRATCH_UMSK
, 0);
1533 WREG32(CP_RB_CNTL
, tmp
);
1535 WREG32(CP_RB_BASE
, ring
->gpu_addr
>> 8);
1536 WREG32(CP_DEBUG
, (1 << 27) | (1 << 28));
1538 ring
->rptr
= RREG32(CP_RB_RPTR
);
1540 evergreen_cp_start(rdev
);
1542 r
= radeon_ring_test(rdev
, RADEON_RING_TYPE_GFX_INDEX
, ring
);
1544 ring
->ready
= false;
1553 static void evergreen_gpu_init(struct radeon_device
*rdev
)
1556 u32 mc_shared_chmap
, mc_arb_ramcfg
;
1560 u32 sq_lds_resource_mgmt
;
1561 u32 sq_gpr_resource_mgmt_1
;
1562 u32 sq_gpr_resource_mgmt_2
;
1563 u32 sq_gpr_resource_mgmt_3
;
1564 u32 sq_thread_resource_mgmt
;
1565 u32 sq_thread_resource_mgmt_2
;
1566 u32 sq_stack_resource_mgmt_1
;
1567 u32 sq_stack_resource_mgmt_2
;
1568 u32 sq_stack_resource_mgmt_3
;
1569 u32 vgt_cache_invalidation
;
1570 u32 hdp_host_path_cntl
, tmp
;
1571 u32 disabled_rb_mask
;
1572 int i
, j
, num_shader_engines
, ps_thread_count
;
1574 switch (rdev
->family
) {
1577 rdev
->config
.evergreen
.num_ses
= 2;
1578 rdev
->config
.evergreen
.max_pipes
= 4;
1579 rdev
->config
.evergreen
.max_tile_pipes
= 8;
1580 rdev
->config
.evergreen
.max_simds
= 10;
1581 rdev
->config
.evergreen
.max_backends
= 4 * rdev
->config
.evergreen
.num_ses
;
1582 rdev
->config
.evergreen
.max_gprs
= 256;
1583 rdev
->config
.evergreen
.max_threads
= 248;
1584 rdev
->config
.evergreen
.max_gs_threads
= 32;
1585 rdev
->config
.evergreen
.max_stack_entries
= 512;
1586 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1587 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1588 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1589 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1590 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1591 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1593 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
1594 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1595 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1596 gb_addr_config
= CYPRESS_GB_ADDR_CONFIG_GOLDEN
;
1599 rdev
->config
.evergreen
.num_ses
= 1;
1600 rdev
->config
.evergreen
.max_pipes
= 4;
1601 rdev
->config
.evergreen
.max_tile_pipes
= 4;
1602 rdev
->config
.evergreen
.max_simds
= 10;
1603 rdev
->config
.evergreen
.max_backends
= 4 * rdev
->config
.evergreen
.num_ses
;
1604 rdev
->config
.evergreen
.max_gprs
= 256;
1605 rdev
->config
.evergreen
.max_threads
= 248;
1606 rdev
->config
.evergreen
.max_gs_threads
= 32;
1607 rdev
->config
.evergreen
.max_stack_entries
= 512;
1608 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1609 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1610 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1611 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1612 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1613 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1615 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
1616 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1617 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1618 gb_addr_config
= JUNIPER_GB_ADDR_CONFIG_GOLDEN
;
1621 rdev
->config
.evergreen
.num_ses
= 1;
1622 rdev
->config
.evergreen
.max_pipes
= 4;
1623 rdev
->config
.evergreen
.max_tile_pipes
= 4;
1624 rdev
->config
.evergreen
.max_simds
= 5;
1625 rdev
->config
.evergreen
.max_backends
= 2 * rdev
->config
.evergreen
.num_ses
;
1626 rdev
->config
.evergreen
.max_gprs
= 256;
1627 rdev
->config
.evergreen
.max_threads
= 248;
1628 rdev
->config
.evergreen
.max_gs_threads
= 32;
1629 rdev
->config
.evergreen
.max_stack_entries
= 256;
1630 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1631 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1632 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1633 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1634 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1635 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1637 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
1638 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1639 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1640 gb_addr_config
= REDWOOD_GB_ADDR_CONFIG_GOLDEN
;
1644 rdev
->config
.evergreen
.num_ses
= 1;
1645 rdev
->config
.evergreen
.max_pipes
= 2;
1646 rdev
->config
.evergreen
.max_tile_pipes
= 2;
1647 rdev
->config
.evergreen
.max_simds
= 2;
1648 rdev
->config
.evergreen
.max_backends
= 1 * rdev
->config
.evergreen
.num_ses
;
1649 rdev
->config
.evergreen
.max_gprs
= 256;
1650 rdev
->config
.evergreen
.max_threads
= 192;
1651 rdev
->config
.evergreen
.max_gs_threads
= 16;
1652 rdev
->config
.evergreen
.max_stack_entries
= 256;
1653 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1654 rdev
->config
.evergreen
.sx_max_export_size
= 128;
1655 rdev
->config
.evergreen
.sx_max_export_pos_size
= 32;
1656 rdev
->config
.evergreen
.sx_max_export_smx_size
= 96;
1657 rdev
->config
.evergreen
.max_hw_contexts
= 4;
1658 rdev
->config
.evergreen
.sq_num_cf_insts
= 1;
1660 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x40;
1661 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1662 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1663 gb_addr_config
= CEDAR_GB_ADDR_CONFIG_GOLDEN
;
1666 rdev
->config
.evergreen
.num_ses
= 1;
1667 rdev
->config
.evergreen
.max_pipes
= 2;
1668 rdev
->config
.evergreen
.max_tile_pipes
= 2;
1669 rdev
->config
.evergreen
.max_simds
= 2;
1670 rdev
->config
.evergreen
.max_backends
= 1 * rdev
->config
.evergreen
.num_ses
;
1671 rdev
->config
.evergreen
.max_gprs
= 256;
1672 rdev
->config
.evergreen
.max_threads
= 192;
1673 rdev
->config
.evergreen
.max_gs_threads
= 16;
1674 rdev
->config
.evergreen
.max_stack_entries
= 256;
1675 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1676 rdev
->config
.evergreen
.sx_max_export_size
= 128;
1677 rdev
->config
.evergreen
.sx_max_export_pos_size
= 32;
1678 rdev
->config
.evergreen
.sx_max_export_smx_size
= 96;
1679 rdev
->config
.evergreen
.max_hw_contexts
= 4;
1680 rdev
->config
.evergreen
.sq_num_cf_insts
= 1;
1682 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x40;
1683 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1684 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1685 gb_addr_config
= CEDAR_GB_ADDR_CONFIG_GOLDEN
;
1688 rdev
->config
.evergreen
.num_ses
= 1;
1689 rdev
->config
.evergreen
.max_pipes
= 4;
1690 rdev
->config
.evergreen
.max_tile_pipes
= 2;
1691 if (rdev
->pdev
->device
== 0x9648)
1692 rdev
->config
.evergreen
.max_simds
= 3;
1693 else if ((rdev
->pdev
->device
== 0x9647) ||
1694 (rdev
->pdev
->device
== 0x964a))
1695 rdev
->config
.evergreen
.max_simds
= 4;
1697 rdev
->config
.evergreen
.max_simds
= 5;
1698 rdev
->config
.evergreen
.max_backends
= 2 * rdev
->config
.evergreen
.num_ses
;
1699 rdev
->config
.evergreen
.max_gprs
= 256;
1700 rdev
->config
.evergreen
.max_threads
= 248;
1701 rdev
->config
.evergreen
.max_gs_threads
= 32;
1702 rdev
->config
.evergreen
.max_stack_entries
= 256;
1703 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1704 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1705 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1706 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1707 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1708 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1710 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x40;
1711 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1712 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1713 gb_addr_config
= REDWOOD_GB_ADDR_CONFIG_GOLDEN
;
1716 rdev
->config
.evergreen
.num_ses
= 1;
1717 rdev
->config
.evergreen
.max_pipes
= 4;
1718 rdev
->config
.evergreen
.max_tile_pipes
= 4;
1719 rdev
->config
.evergreen
.max_simds
= 2;
1720 rdev
->config
.evergreen
.max_backends
= 1 * rdev
->config
.evergreen
.num_ses
;
1721 rdev
->config
.evergreen
.max_gprs
= 256;
1722 rdev
->config
.evergreen
.max_threads
= 248;
1723 rdev
->config
.evergreen
.max_gs_threads
= 32;
1724 rdev
->config
.evergreen
.max_stack_entries
= 512;
1725 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1726 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1727 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1728 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1729 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1730 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1732 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x40;
1733 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1734 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1735 gb_addr_config
= REDWOOD_GB_ADDR_CONFIG_GOLDEN
;
1738 rdev
->config
.evergreen
.num_ses
= 2;
1739 rdev
->config
.evergreen
.max_pipes
= 4;
1740 rdev
->config
.evergreen
.max_tile_pipes
= 8;
1741 rdev
->config
.evergreen
.max_simds
= 7;
1742 rdev
->config
.evergreen
.max_backends
= 4 * rdev
->config
.evergreen
.num_ses
;
1743 rdev
->config
.evergreen
.max_gprs
= 256;
1744 rdev
->config
.evergreen
.max_threads
= 248;
1745 rdev
->config
.evergreen
.max_gs_threads
= 32;
1746 rdev
->config
.evergreen
.max_stack_entries
= 512;
1747 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1748 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1749 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1750 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1751 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1752 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1754 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
1755 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1756 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1757 gb_addr_config
= BARTS_GB_ADDR_CONFIG_GOLDEN
;
1760 rdev
->config
.evergreen
.num_ses
= 1;
1761 rdev
->config
.evergreen
.max_pipes
= 4;
1762 rdev
->config
.evergreen
.max_tile_pipes
= 4;
1763 rdev
->config
.evergreen
.max_simds
= 6;
1764 rdev
->config
.evergreen
.max_backends
= 2 * rdev
->config
.evergreen
.num_ses
;
1765 rdev
->config
.evergreen
.max_gprs
= 256;
1766 rdev
->config
.evergreen
.max_threads
= 248;
1767 rdev
->config
.evergreen
.max_gs_threads
= 32;
1768 rdev
->config
.evergreen
.max_stack_entries
= 256;
1769 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1770 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1771 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1772 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1773 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1774 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1776 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
1777 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1778 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1779 gb_addr_config
= TURKS_GB_ADDR_CONFIG_GOLDEN
;
1782 rdev
->config
.evergreen
.num_ses
= 1;
1783 rdev
->config
.evergreen
.max_pipes
= 4;
1784 rdev
->config
.evergreen
.max_tile_pipes
= 2;
1785 rdev
->config
.evergreen
.max_simds
= 2;
1786 rdev
->config
.evergreen
.max_backends
= 1 * rdev
->config
.evergreen
.num_ses
;
1787 rdev
->config
.evergreen
.max_gprs
= 256;
1788 rdev
->config
.evergreen
.max_threads
= 192;
1789 rdev
->config
.evergreen
.max_gs_threads
= 16;
1790 rdev
->config
.evergreen
.max_stack_entries
= 256;
1791 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1792 rdev
->config
.evergreen
.sx_max_export_size
= 128;
1793 rdev
->config
.evergreen
.sx_max_export_pos_size
= 32;
1794 rdev
->config
.evergreen
.sx_max_export_smx_size
= 96;
1795 rdev
->config
.evergreen
.max_hw_contexts
= 4;
1796 rdev
->config
.evergreen
.sq_num_cf_insts
= 1;
1798 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x40;
1799 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1800 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1801 gb_addr_config
= CAICOS_GB_ADDR_CONFIG_GOLDEN
;
1805 /* Initialize HDP */
1806 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
1807 WREG32((0x2c14 + j
), 0x00000000);
1808 WREG32((0x2c18 + j
), 0x00000000);
1809 WREG32((0x2c1c + j
), 0x00000000);
1810 WREG32((0x2c20 + j
), 0x00000000);
1811 WREG32((0x2c24 + j
), 0x00000000);
1814 WREG32(GRBM_CNTL
, GRBM_READ_TIMEOUT(0xff));
1816 evergreen_fix_pci_max_read_req_size(rdev
);
1818 mc_shared_chmap
= RREG32(MC_SHARED_CHMAP
);
1819 if ((rdev
->family
== CHIP_PALM
) ||
1820 (rdev
->family
== CHIP_SUMO
) ||
1821 (rdev
->family
== CHIP_SUMO2
))
1822 mc_arb_ramcfg
= RREG32(FUS_MC_ARB_RAMCFG
);
1824 mc_arb_ramcfg
= RREG32(MC_ARB_RAMCFG
);
1826 /* setup tiling info dword. gb_addr_config is not adequate since it does
1827 * not have bank info, so create a custom tiling dword.
1828 * bits 3:0 num_pipes
1829 * bits 7:4 num_banks
1830 * bits 11:8 group_size
1831 * bits 15:12 row_size
1833 rdev
->config
.evergreen
.tile_config
= 0;
1834 switch (rdev
->config
.evergreen
.max_tile_pipes
) {
1837 rdev
->config
.evergreen
.tile_config
|= (0 << 0);
1840 rdev
->config
.evergreen
.tile_config
|= (1 << 0);
1843 rdev
->config
.evergreen
.tile_config
|= (2 << 0);
1846 rdev
->config
.evergreen
.tile_config
|= (3 << 0);
1849 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
1850 if (rdev
->flags
& RADEON_IS_IGP
)
1851 rdev
->config
.evergreen
.tile_config
|= 1 << 4;
1853 if ((mc_arb_ramcfg
& NOOFBANK_MASK
) >> NOOFBANK_SHIFT
)
1854 rdev
->config
.evergreen
.tile_config
|= 1 << 4;
1856 rdev
->config
.evergreen
.tile_config
|= 0 << 4;
1858 rdev
->config
.evergreen
.tile_config
|= 0 << 8;
1859 rdev
->config
.evergreen
.tile_config
|=
1860 ((gb_addr_config
& 0x30000000) >> 28) << 12;
1862 num_shader_engines
= (gb_addr_config
& NUM_SHADER_ENGINES(3) >> 12) + 1;
1864 if ((rdev
->family
>= CHIP_CEDAR
) && (rdev
->family
<= CHIP_HEMLOCK
)) {
1868 WREG32(RCU_IND_INDEX
, 0x204);
1869 efuse_straps_4
= RREG32(RCU_IND_DATA
);
1870 WREG32(RCU_IND_INDEX
, 0x203);
1871 efuse_straps_3
= RREG32(RCU_IND_DATA
);
1872 tmp
= (((efuse_straps_4
& 0xf) << 4) |
1873 ((efuse_straps_3
& 0xf0000000) >> 28));
1876 for (i
= (rdev
->config
.evergreen
.num_ses
- 1); i
>= 0; i
--) {
1877 u32 rb_disable_bitmap
;
1879 WREG32(GRBM_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
| SE_INDEX(i
));
1880 WREG32(RLC_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
| SE_INDEX(i
));
1881 rb_disable_bitmap
= (RREG32(CC_RB_BACKEND_DISABLE
) & 0x00ff0000) >> 16;
1883 tmp
|= rb_disable_bitmap
;
1886 /* enabled rb are just the one not disabled :) */
1887 disabled_rb_mask
= tmp
;
1889 WREG32(GRBM_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
| SE_BROADCAST_WRITES
);
1890 WREG32(RLC_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
| SE_BROADCAST_WRITES
);
1892 WREG32(GB_ADDR_CONFIG
, gb_addr_config
);
1893 WREG32(DMIF_ADDR_CONFIG
, gb_addr_config
);
1894 WREG32(HDP_ADDR_CONFIG
, gb_addr_config
);
1896 tmp
= gb_addr_config
& NUM_PIPES_MASK
;
1897 tmp
= r6xx_remap_render_backend(rdev
, tmp
, rdev
->config
.evergreen
.max_backends
,
1898 EVERGREEN_MAX_BACKENDS
, disabled_rb_mask
);
1899 WREG32(GB_BACKEND_MAP
, tmp
);
1901 WREG32(CGTS_SYS_TCC_DISABLE
, 0);
1902 WREG32(CGTS_TCC_DISABLE
, 0);
1903 WREG32(CGTS_USER_SYS_TCC_DISABLE
, 0);
1904 WREG32(CGTS_USER_TCC_DISABLE
, 0);
1906 /* set HW defaults for 3D engine */
1907 WREG32(CP_QUEUE_THRESHOLDS
, (ROQ_IB1_START(0x16) |
1908 ROQ_IB2_START(0x2b)));
1910 WREG32(CP_MEQ_THRESHOLDS
, STQ_SPLIT(0x30));
1912 WREG32(TA_CNTL_AUX
, (DISABLE_CUBE_ANISO
|
1917 sx_debug_1
= RREG32(SX_DEBUG_1
);
1918 sx_debug_1
|= ENABLE_NEW_SMX_ADDRESS
;
1919 WREG32(SX_DEBUG_1
, sx_debug_1
);
1922 smx_dc_ctl0
= RREG32(SMX_DC_CTL0
);
1923 smx_dc_ctl0
&= ~NUMBER_OF_SETS(0x1ff);
1924 smx_dc_ctl0
|= NUMBER_OF_SETS(rdev
->config
.evergreen
.sx_num_of_sets
);
1925 WREG32(SMX_DC_CTL0
, smx_dc_ctl0
);
1927 if (rdev
->family
<= CHIP_SUMO2
)
1928 WREG32(SMX_SAR_CTL0
, 0x00010000);
1930 WREG32(SX_EXPORT_BUFFER_SIZES
, (COLOR_BUFFER_SIZE((rdev
->config
.evergreen
.sx_max_export_size
/ 4) - 1) |
1931 POSITION_BUFFER_SIZE((rdev
->config
.evergreen
.sx_max_export_pos_size
/ 4) - 1) |
1932 SMX_BUFFER_SIZE((rdev
->config
.evergreen
.sx_max_export_smx_size
/ 4) - 1)));
1934 WREG32(PA_SC_FIFO_SIZE
, (SC_PRIM_FIFO_SIZE(rdev
->config
.evergreen
.sc_prim_fifo_size
) |
1935 SC_HIZ_TILE_FIFO_SIZE(rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
) |
1936 SC_EARLYZ_TILE_FIFO_SIZE(rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
)));
1938 WREG32(VGT_NUM_INSTANCES
, 1);
1939 WREG32(SPI_CONFIG_CNTL
, 0);
1940 WREG32(SPI_CONFIG_CNTL_1
, VTX_DONE_DELAY(4));
1941 WREG32(CP_PERFMON_CNTL
, 0);
1943 WREG32(SQ_MS_FIFO_SIZES
, (CACHE_FIFO_SIZE(16 * rdev
->config
.evergreen
.sq_num_cf_insts
) |
1944 FETCH_FIFO_HIWATER(0x4) |
1945 DONE_FIFO_HIWATER(0xe0) |
1946 ALU_UPDATE_FIFO_HIWATER(0x8)));
1948 sq_config
= RREG32(SQ_CONFIG
);
1949 sq_config
&= ~(PS_PRIO(3) |
1953 sq_config
|= (VC_ENABLE
|
1960 switch (rdev
->family
) {
1966 /* no vertex cache */
1967 sq_config
&= ~VC_ENABLE
;
1973 sq_lds_resource_mgmt
= RREG32(SQ_LDS_RESOURCE_MGMT
);
1975 sq_gpr_resource_mgmt_1
= NUM_PS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2))* 12 / 32);
1976 sq_gpr_resource_mgmt_1
|= NUM_VS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 6 / 32);
1977 sq_gpr_resource_mgmt_1
|= NUM_CLAUSE_TEMP_GPRS(4);
1978 sq_gpr_resource_mgmt_2
= NUM_GS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 4 / 32);
1979 sq_gpr_resource_mgmt_2
|= NUM_ES_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 4 / 32);
1980 sq_gpr_resource_mgmt_3
= NUM_HS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 3 / 32);
1981 sq_gpr_resource_mgmt_3
|= NUM_LS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 3 / 32);
1983 switch (rdev
->family
) {
1988 ps_thread_count
= 96;
1991 ps_thread_count
= 128;
1995 sq_thread_resource_mgmt
= NUM_PS_THREADS(ps_thread_count
);
1996 sq_thread_resource_mgmt
|= NUM_VS_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
1997 sq_thread_resource_mgmt
|= NUM_GS_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
1998 sq_thread_resource_mgmt
|= NUM_ES_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
1999 sq_thread_resource_mgmt_2
= NUM_HS_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
2000 sq_thread_resource_mgmt_2
|= NUM_LS_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
2002 sq_stack_resource_mgmt_1
= NUM_PS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2003 sq_stack_resource_mgmt_1
|= NUM_VS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2004 sq_stack_resource_mgmt_2
= NUM_GS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2005 sq_stack_resource_mgmt_2
|= NUM_ES_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2006 sq_stack_resource_mgmt_3
= NUM_HS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2007 sq_stack_resource_mgmt_3
|= NUM_LS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2009 WREG32(SQ_CONFIG
, sq_config
);
2010 WREG32(SQ_GPR_RESOURCE_MGMT_1
, sq_gpr_resource_mgmt_1
);
2011 WREG32(SQ_GPR_RESOURCE_MGMT_2
, sq_gpr_resource_mgmt_2
);
2012 WREG32(SQ_GPR_RESOURCE_MGMT_3
, sq_gpr_resource_mgmt_3
);
2013 WREG32(SQ_THREAD_RESOURCE_MGMT
, sq_thread_resource_mgmt
);
2014 WREG32(SQ_THREAD_RESOURCE_MGMT_2
, sq_thread_resource_mgmt_2
);
2015 WREG32(SQ_STACK_RESOURCE_MGMT_1
, sq_stack_resource_mgmt_1
);
2016 WREG32(SQ_STACK_RESOURCE_MGMT_2
, sq_stack_resource_mgmt_2
);
2017 WREG32(SQ_STACK_RESOURCE_MGMT_3
, sq_stack_resource_mgmt_3
);
2018 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0);
2019 WREG32(SQ_LDS_RESOURCE_MGMT
, sq_lds_resource_mgmt
);
2021 WREG32(PA_SC_FORCE_EOV_MAX_CNTS
, (FORCE_EOV_MAX_CLK_CNT(4095) |
2022 FORCE_EOV_MAX_REZ_CNT(255)));
2024 switch (rdev
->family
) {
2030 vgt_cache_invalidation
= CACHE_INVALIDATION(TC_ONLY
);
2033 vgt_cache_invalidation
= CACHE_INVALIDATION(VC_AND_TC
);
2036 vgt_cache_invalidation
|= AUTO_INVLD_EN(ES_AND_GS_AUTO
);
2037 WREG32(VGT_CACHE_INVALIDATION
, vgt_cache_invalidation
);
2039 WREG32(VGT_GS_VERTEX_REUSE
, 16);
2040 WREG32(PA_SU_LINE_STIPPLE_VALUE
, 0);
2041 WREG32(PA_SC_LINE_STIPPLE_STATE
, 0);
2043 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
2044 WREG32(VGT_OUT_DEALLOC_CNTL
, 16);
2046 WREG32(CB_PERF_CTR0_SEL_0
, 0);
2047 WREG32(CB_PERF_CTR0_SEL_1
, 0);
2048 WREG32(CB_PERF_CTR1_SEL_0
, 0);
2049 WREG32(CB_PERF_CTR1_SEL_1
, 0);
2050 WREG32(CB_PERF_CTR2_SEL_0
, 0);
2051 WREG32(CB_PERF_CTR2_SEL_1
, 0);
2052 WREG32(CB_PERF_CTR3_SEL_0
, 0);
2053 WREG32(CB_PERF_CTR3_SEL_1
, 0);
2055 /* clear render buffer base addresses */
2056 WREG32(CB_COLOR0_BASE
, 0);
2057 WREG32(CB_COLOR1_BASE
, 0);
2058 WREG32(CB_COLOR2_BASE
, 0);
2059 WREG32(CB_COLOR3_BASE
, 0);
2060 WREG32(CB_COLOR4_BASE
, 0);
2061 WREG32(CB_COLOR5_BASE
, 0);
2062 WREG32(CB_COLOR6_BASE
, 0);
2063 WREG32(CB_COLOR7_BASE
, 0);
2064 WREG32(CB_COLOR8_BASE
, 0);
2065 WREG32(CB_COLOR9_BASE
, 0);
2066 WREG32(CB_COLOR10_BASE
, 0);
2067 WREG32(CB_COLOR11_BASE
, 0);
2069 /* set the shader const cache sizes to 0 */
2070 for (i
= SQ_ALU_CONST_BUFFER_SIZE_PS_0
; i
< 0x28200; i
+= 4)
2072 for (i
= SQ_ALU_CONST_BUFFER_SIZE_HS_0
; i
< 0x29000; i
+= 4)
2075 tmp
= RREG32(HDP_MISC_CNTL
);
2076 tmp
|= HDP_FLUSH_INVALIDATE_CACHE
;
2077 WREG32(HDP_MISC_CNTL
, tmp
);
2079 hdp_host_path_cntl
= RREG32(HDP_HOST_PATH_CNTL
);
2080 WREG32(HDP_HOST_PATH_CNTL
, hdp_host_path_cntl
);
2082 WREG32(PA_CL_ENHANCE
, CLIP_VTX_REORDER_ENA
| NUM_CLIP_SEQ(3));
2088 int evergreen_mc_init(struct radeon_device
*rdev
)
2091 int chansize
, numchan
;
2093 /* Get VRAM informations */
2094 rdev
->mc
.vram_is_ddr
= true;
2095 if ((rdev
->family
== CHIP_PALM
) ||
2096 (rdev
->family
== CHIP_SUMO
) ||
2097 (rdev
->family
== CHIP_SUMO2
))
2098 tmp
= RREG32(FUS_MC_ARB_RAMCFG
);
2100 tmp
= RREG32(MC_ARB_RAMCFG
);
2101 if (tmp
& CHANSIZE_OVERRIDE
) {
2103 } else if (tmp
& CHANSIZE_MASK
) {
2108 tmp
= RREG32(MC_SHARED_CHMAP
);
2109 switch ((tmp
& NOOFCHAN_MASK
) >> NOOFCHAN_SHIFT
) {
2124 rdev
->mc
.vram_width
= numchan
* chansize
;
2125 /* Could aper size report 0 ? */
2126 rdev
->mc
.aper_base
= pci_resource_start(rdev
->pdev
, 0);
2127 rdev
->mc
.aper_size
= pci_resource_len(rdev
->pdev
, 0);
2128 /* Setup GPU memory space */
2129 if ((rdev
->family
== CHIP_PALM
) ||
2130 (rdev
->family
== CHIP_SUMO
) ||
2131 (rdev
->family
== CHIP_SUMO2
)) {
2132 /* size in bytes on fusion */
2133 rdev
->mc
.mc_vram_size
= RREG32(CONFIG_MEMSIZE
);
2134 rdev
->mc
.real_vram_size
= RREG32(CONFIG_MEMSIZE
);
2136 /* size in MB on evergreen/cayman/tn */
2137 rdev
->mc
.mc_vram_size
= RREG32(CONFIG_MEMSIZE
) * 1024 * 1024;
2138 rdev
->mc
.real_vram_size
= RREG32(CONFIG_MEMSIZE
) * 1024 * 1024;
2140 rdev
->mc
.visible_vram_size
= rdev
->mc
.aper_size
;
2141 r700_vram_gtt_location(rdev
, &rdev
->mc
);
2142 radeon_update_bandwidth_info(rdev
);
2147 bool evergreen_gpu_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
2151 u32 grbm_status_se0
, grbm_status_se1
;
2153 srbm_status
= RREG32(SRBM_STATUS
);
2154 grbm_status
= RREG32(GRBM_STATUS
);
2155 grbm_status_se0
= RREG32(GRBM_STATUS_SE0
);
2156 grbm_status_se1
= RREG32(GRBM_STATUS_SE1
);
2157 if (!(grbm_status
& GUI_ACTIVE
)) {
2158 radeon_ring_lockup_update(ring
);
2161 /* force CP activities */
2162 radeon_ring_force_activity(rdev
, ring
);
2163 return radeon_ring_test_lockup(rdev
, ring
);
2166 static int evergreen_gpu_soft_reset(struct radeon_device
*rdev
)
2168 struct evergreen_mc_save save
;
2171 if (!(RREG32(GRBM_STATUS
) & GUI_ACTIVE
))
2174 dev_info(rdev
->dev
, "GPU softreset \n");
2175 dev_info(rdev
->dev
, " GRBM_STATUS=0x%08X\n",
2176 RREG32(GRBM_STATUS
));
2177 dev_info(rdev
->dev
, " GRBM_STATUS_SE0=0x%08X\n",
2178 RREG32(GRBM_STATUS_SE0
));
2179 dev_info(rdev
->dev
, " GRBM_STATUS_SE1=0x%08X\n",
2180 RREG32(GRBM_STATUS_SE1
));
2181 dev_info(rdev
->dev
, " SRBM_STATUS=0x%08X\n",
2182 RREG32(SRBM_STATUS
));
2183 evergreen_mc_stop(rdev
, &save
);
2184 if (evergreen_mc_wait_for_idle(rdev
)) {
2185 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
2187 /* Disable CP parsing/prefetching */
2188 WREG32(CP_ME_CNTL
, CP_ME_HALT
| CP_PFP_HALT
);
2190 /* reset all the gfx blocks */
2191 grbm_reset
= (SOFT_RESET_CP
|
2204 dev_info(rdev
->dev
, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset
);
2205 WREG32(GRBM_SOFT_RESET
, grbm_reset
);
2206 (void)RREG32(GRBM_SOFT_RESET
);
2208 WREG32(GRBM_SOFT_RESET
, 0);
2209 (void)RREG32(GRBM_SOFT_RESET
);
2210 /* Wait a little for things to settle down */
2212 dev_info(rdev
->dev
, " GRBM_STATUS=0x%08X\n",
2213 RREG32(GRBM_STATUS
));
2214 dev_info(rdev
->dev
, " GRBM_STATUS_SE0=0x%08X\n",
2215 RREG32(GRBM_STATUS_SE0
));
2216 dev_info(rdev
->dev
, " GRBM_STATUS_SE1=0x%08X\n",
2217 RREG32(GRBM_STATUS_SE1
));
2218 dev_info(rdev
->dev
, " SRBM_STATUS=0x%08X\n",
2219 RREG32(SRBM_STATUS
));
2220 evergreen_mc_resume(rdev
, &save
);
2224 int evergreen_asic_reset(struct radeon_device
*rdev
)
2226 return evergreen_gpu_soft_reset(rdev
);
2231 u32
evergreen_get_vblank_counter(struct radeon_device
*rdev
, int crtc
)
2235 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC0_REGISTER_OFFSET
);
2237 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
2239 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC2_REGISTER_OFFSET
);
2241 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
2243 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC4_REGISTER_OFFSET
);
2245 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
2251 void evergreen_disable_interrupt_state(struct radeon_device
*rdev
)
2255 if (rdev
->family
>= CHIP_CAYMAN
) {
2256 cayman_cp_int_cntl_setup(rdev
, 0,
2257 CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
);
2258 cayman_cp_int_cntl_setup(rdev
, 1, 0);
2259 cayman_cp_int_cntl_setup(rdev
, 2, 0);
2261 WREG32(CP_INT_CNTL
, CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
);
2262 WREG32(GRBM_INT_CNTL
, 0);
2263 WREG32(INT_MASK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
2264 WREG32(INT_MASK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
2265 if (rdev
->num_crtc
>= 4) {
2266 WREG32(INT_MASK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
2267 WREG32(INT_MASK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
2269 if (rdev
->num_crtc
>= 6) {
2270 WREG32(INT_MASK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
2271 WREG32(INT_MASK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
2274 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
2275 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
2276 if (rdev
->num_crtc
>= 4) {
2277 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
2278 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
2280 if (rdev
->num_crtc
>= 6) {
2281 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
2282 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
2285 /* only one DAC on DCE6 */
2286 if (!ASIC_IS_DCE6(rdev
))
2287 WREG32(DACA_AUTODETECT_INT_CONTROL
, 0);
2288 WREG32(DACB_AUTODETECT_INT_CONTROL
, 0);
2290 tmp
= RREG32(DC_HPD1_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2291 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
2292 tmp
= RREG32(DC_HPD2_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2293 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
2294 tmp
= RREG32(DC_HPD3_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2295 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
2296 tmp
= RREG32(DC_HPD4_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2297 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
2298 tmp
= RREG32(DC_HPD5_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2299 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
2300 tmp
= RREG32(DC_HPD6_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2301 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
2305 int evergreen_irq_set(struct radeon_device
*rdev
)
2307 u32 cp_int_cntl
= CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
;
2308 u32 cp_int_cntl1
= 0, cp_int_cntl2
= 0;
2309 u32 crtc1
= 0, crtc2
= 0, crtc3
= 0, crtc4
= 0, crtc5
= 0, crtc6
= 0;
2310 u32 hpd1
, hpd2
, hpd3
, hpd4
, hpd5
, hpd6
;
2311 u32 grbm_int_cntl
= 0;
2312 u32 grph1
= 0, grph2
= 0, grph3
= 0, grph4
= 0, grph5
= 0, grph6
= 0;
2313 u32 afmt1
= 0, afmt2
= 0, afmt3
= 0, afmt4
= 0, afmt5
= 0, afmt6
= 0;
2315 if (!rdev
->irq
.installed
) {
2316 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2319 /* don't enable anything if the ih is disabled */
2320 if (!rdev
->ih
.enabled
) {
2321 r600_disable_interrupts(rdev
);
2322 /* force the active interrupt state to all disabled */
2323 evergreen_disable_interrupt_state(rdev
);
2327 hpd1
= RREG32(DC_HPD1_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2328 hpd2
= RREG32(DC_HPD2_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2329 hpd3
= RREG32(DC_HPD3_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2330 hpd4
= RREG32(DC_HPD4_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2331 hpd5
= RREG32(DC_HPD5_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2332 hpd6
= RREG32(DC_HPD6_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2334 afmt1
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
2335 afmt2
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
2336 afmt3
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
2337 afmt4
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
2338 afmt5
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
2339 afmt6
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
2341 if (rdev
->family
>= CHIP_CAYMAN
) {
2342 /* enable CP interrupts on all rings */
2343 if (atomic_read(&rdev
->irq
.ring_int
[RADEON_RING_TYPE_GFX_INDEX
])) {
2344 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2345 cp_int_cntl
|= TIME_STAMP_INT_ENABLE
;
2347 if (atomic_read(&rdev
->irq
.ring_int
[CAYMAN_RING_TYPE_CP1_INDEX
])) {
2348 DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
2349 cp_int_cntl1
|= TIME_STAMP_INT_ENABLE
;
2351 if (atomic_read(&rdev
->irq
.ring_int
[CAYMAN_RING_TYPE_CP2_INDEX
])) {
2352 DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
2353 cp_int_cntl2
|= TIME_STAMP_INT_ENABLE
;
2356 if (atomic_read(&rdev
->irq
.ring_int
[RADEON_RING_TYPE_GFX_INDEX
])) {
2357 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2358 cp_int_cntl
|= RB_INT_ENABLE
;
2359 cp_int_cntl
|= TIME_STAMP_INT_ENABLE
;
2363 if (rdev
->irq
.crtc_vblank_int
[0] ||
2364 atomic_read(&rdev
->irq
.pflip
[0])) {
2365 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2366 crtc1
|= VBLANK_INT_MASK
;
2368 if (rdev
->irq
.crtc_vblank_int
[1] ||
2369 atomic_read(&rdev
->irq
.pflip
[1])) {
2370 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2371 crtc2
|= VBLANK_INT_MASK
;
2373 if (rdev
->irq
.crtc_vblank_int
[2] ||
2374 atomic_read(&rdev
->irq
.pflip
[2])) {
2375 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2376 crtc3
|= VBLANK_INT_MASK
;
2378 if (rdev
->irq
.crtc_vblank_int
[3] ||
2379 atomic_read(&rdev
->irq
.pflip
[3])) {
2380 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2381 crtc4
|= VBLANK_INT_MASK
;
2383 if (rdev
->irq
.crtc_vblank_int
[4] ||
2384 atomic_read(&rdev
->irq
.pflip
[4])) {
2385 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2386 crtc5
|= VBLANK_INT_MASK
;
2388 if (rdev
->irq
.crtc_vblank_int
[5] ||
2389 atomic_read(&rdev
->irq
.pflip
[5])) {
2390 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2391 crtc6
|= VBLANK_INT_MASK
;
2393 if (rdev
->irq
.hpd
[0]) {
2394 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2395 hpd1
|= DC_HPDx_INT_EN
;
2397 if (rdev
->irq
.hpd
[1]) {
2398 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2399 hpd2
|= DC_HPDx_INT_EN
;
2401 if (rdev
->irq
.hpd
[2]) {
2402 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2403 hpd3
|= DC_HPDx_INT_EN
;
2405 if (rdev
->irq
.hpd
[3]) {
2406 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2407 hpd4
|= DC_HPDx_INT_EN
;
2409 if (rdev
->irq
.hpd
[4]) {
2410 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2411 hpd5
|= DC_HPDx_INT_EN
;
2413 if (rdev
->irq
.hpd
[5]) {
2414 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2415 hpd6
|= DC_HPDx_INT_EN
;
2417 if (rdev
->irq
.afmt
[0]) {
2418 DRM_DEBUG("evergreen_irq_set: hdmi 0\n");
2419 afmt1
|= AFMT_AZ_FORMAT_WTRIG_MASK
;
2421 if (rdev
->irq
.afmt
[1]) {
2422 DRM_DEBUG("evergreen_irq_set: hdmi 1\n");
2423 afmt2
|= AFMT_AZ_FORMAT_WTRIG_MASK
;
2425 if (rdev
->irq
.afmt
[2]) {
2426 DRM_DEBUG("evergreen_irq_set: hdmi 2\n");
2427 afmt3
|= AFMT_AZ_FORMAT_WTRIG_MASK
;
2429 if (rdev
->irq
.afmt
[3]) {
2430 DRM_DEBUG("evergreen_irq_set: hdmi 3\n");
2431 afmt4
|= AFMT_AZ_FORMAT_WTRIG_MASK
;
2433 if (rdev
->irq
.afmt
[4]) {
2434 DRM_DEBUG("evergreen_irq_set: hdmi 4\n");
2435 afmt5
|= AFMT_AZ_FORMAT_WTRIG_MASK
;
2437 if (rdev
->irq
.afmt
[5]) {
2438 DRM_DEBUG("evergreen_irq_set: hdmi 5\n");
2439 afmt6
|= AFMT_AZ_FORMAT_WTRIG_MASK
;
2441 if (rdev
->irq
.gui_idle
) {
2442 DRM_DEBUG("gui idle\n");
2443 grbm_int_cntl
|= GUI_IDLE_INT_ENABLE
;
2446 if (rdev
->family
>= CHIP_CAYMAN
) {
2447 cayman_cp_int_cntl_setup(rdev
, 0, cp_int_cntl
);
2448 cayman_cp_int_cntl_setup(rdev
, 1, cp_int_cntl1
);
2449 cayman_cp_int_cntl_setup(rdev
, 2, cp_int_cntl2
);
2451 WREG32(CP_INT_CNTL
, cp_int_cntl
);
2452 WREG32(GRBM_INT_CNTL
, grbm_int_cntl
);
2454 WREG32(INT_MASK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, crtc1
);
2455 WREG32(INT_MASK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, crtc2
);
2456 if (rdev
->num_crtc
>= 4) {
2457 WREG32(INT_MASK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, crtc3
);
2458 WREG32(INT_MASK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, crtc4
);
2460 if (rdev
->num_crtc
>= 6) {
2461 WREG32(INT_MASK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, crtc5
);
2462 WREG32(INT_MASK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, crtc6
);
2465 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, grph1
);
2466 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, grph2
);
2467 if (rdev
->num_crtc
>= 4) {
2468 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, grph3
);
2469 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, grph4
);
2471 if (rdev
->num_crtc
>= 6) {
2472 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, grph5
);
2473 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, grph6
);
2476 WREG32(DC_HPD1_INT_CONTROL
, hpd1
);
2477 WREG32(DC_HPD2_INT_CONTROL
, hpd2
);
2478 WREG32(DC_HPD3_INT_CONTROL
, hpd3
);
2479 WREG32(DC_HPD4_INT_CONTROL
, hpd4
);
2480 WREG32(DC_HPD5_INT_CONTROL
, hpd5
);
2481 WREG32(DC_HPD6_INT_CONTROL
, hpd6
);
2483 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, afmt1
);
2484 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, afmt2
);
2485 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, afmt3
);
2486 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, afmt4
);
2487 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, afmt5
);
2488 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, afmt6
);
2493 static void evergreen_irq_ack(struct radeon_device
*rdev
)
2497 rdev
->irq
.stat_regs
.evergreen
.disp_int
= RREG32(DISP_INTERRUPT_STATUS
);
2498 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE
);
2499 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE2
);
2500 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE3
);
2501 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE4
);
2502 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE5
);
2503 rdev
->irq
.stat_regs
.evergreen
.d1grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
);
2504 rdev
->irq
.stat_regs
.evergreen
.d2grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
2505 if (rdev
->num_crtc
>= 4) {
2506 rdev
->irq
.stat_regs
.evergreen
.d3grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
);
2507 rdev
->irq
.stat_regs
.evergreen
.d4grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
2509 if (rdev
->num_crtc
>= 6) {
2510 rdev
->irq
.stat_regs
.evergreen
.d5grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
);
2511 rdev
->irq
.stat_regs
.evergreen
.d6grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
2514 rdev
->irq
.stat_regs
.evergreen
.afmt_status1
= RREG32(AFMT_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
);
2515 rdev
->irq
.stat_regs
.evergreen
.afmt_status2
= RREG32(AFMT_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
2516 rdev
->irq
.stat_regs
.evergreen
.afmt_status3
= RREG32(AFMT_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
);
2517 rdev
->irq
.stat_regs
.evergreen
.afmt_status4
= RREG32(AFMT_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
2518 rdev
->irq
.stat_regs
.evergreen
.afmt_status5
= RREG32(AFMT_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
);
2519 rdev
->irq
.stat_regs
.evergreen
.afmt_status6
= RREG32(AFMT_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
2521 if (rdev
->irq
.stat_regs
.evergreen
.d1grph_int
& GRPH_PFLIP_INT_OCCURRED
)
2522 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
2523 if (rdev
->irq
.stat_regs
.evergreen
.d2grph_int
& GRPH_PFLIP_INT_OCCURRED
)
2524 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
2525 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& LB_D1_VBLANK_INTERRUPT
)
2526 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, VBLANK_ACK
);
2527 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& LB_D1_VLINE_INTERRUPT
)
2528 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, VLINE_ACK
);
2529 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& LB_D2_VBLANK_INTERRUPT
)
2530 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, VBLANK_ACK
);
2531 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& LB_D2_VLINE_INTERRUPT
)
2532 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, VLINE_ACK
);
2534 if (rdev
->num_crtc
>= 4) {
2535 if (rdev
->irq
.stat_regs
.evergreen
.d3grph_int
& GRPH_PFLIP_INT_OCCURRED
)
2536 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
2537 if (rdev
->irq
.stat_regs
.evergreen
.d4grph_int
& GRPH_PFLIP_INT_OCCURRED
)
2538 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
2539 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& LB_D3_VBLANK_INTERRUPT
)
2540 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, VBLANK_ACK
);
2541 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& LB_D3_VLINE_INTERRUPT
)
2542 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, VLINE_ACK
);
2543 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& LB_D4_VBLANK_INTERRUPT
)
2544 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, VBLANK_ACK
);
2545 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& LB_D4_VLINE_INTERRUPT
)
2546 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, VLINE_ACK
);
2549 if (rdev
->num_crtc
>= 6) {
2550 if (rdev
->irq
.stat_regs
.evergreen
.d5grph_int
& GRPH_PFLIP_INT_OCCURRED
)
2551 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
2552 if (rdev
->irq
.stat_regs
.evergreen
.d6grph_int
& GRPH_PFLIP_INT_OCCURRED
)
2553 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
2554 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& LB_D5_VBLANK_INTERRUPT
)
2555 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, VBLANK_ACK
);
2556 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& LB_D5_VLINE_INTERRUPT
)
2557 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, VLINE_ACK
);
2558 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& LB_D6_VBLANK_INTERRUPT
)
2559 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, VBLANK_ACK
);
2560 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& LB_D6_VLINE_INTERRUPT
)
2561 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, VLINE_ACK
);
2564 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& DC_HPD1_INTERRUPT
) {
2565 tmp
= RREG32(DC_HPD1_INT_CONTROL
);
2566 tmp
|= DC_HPDx_INT_ACK
;
2567 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
2569 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& DC_HPD2_INTERRUPT
) {
2570 tmp
= RREG32(DC_HPD2_INT_CONTROL
);
2571 tmp
|= DC_HPDx_INT_ACK
;
2572 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
2574 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& DC_HPD3_INTERRUPT
) {
2575 tmp
= RREG32(DC_HPD3_INT_CONTROL
);
2576 tmp
|= DC_HPDx_INT_ACK
;
2577 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
2579 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& DC_HPD4_INTERRUPT
) {
2580 tmp
= RREG32(DC_HPD4_INT_CONTROL
);
2581 tmp
|= DC_HPDx_INT_ACK
;
2582 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
2584 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& DC_HPD5_INTERRUPT
) {
2585 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
2586 tmp
|= DC_HPDx_INT_ACK
;
2587 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
2589 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& DC_HPD6_INTERRUPT
) {
2590 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
2591 tmp
|= DC_HPDx_INT_ACK
;
2592 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
2594 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status1
& AFMT_AZ_FORMAT_WTRIG
) {
2595 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
);
2596 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
2597 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, tmp
);
2599 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status2
& AFMT_AZ_FORMAT_WTRIG
) {
2600 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
2601 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
2602 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, tmp
);
2604 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status3
& AFMT_AZ_FORMAT_WTRIG
) {
2605 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
);
2606 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
2607 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, tmp
);
2609 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status4
& AFMT_AZ_FORMAT_WTRIG
) {
2610 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
2611 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
2612 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, tmp
);
2614 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status5
& AFMT_AZ_FORMAT_WTRIG
) {
2615 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
);
2616 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
2617 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, tmp
);
2619 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status6
& AFMT_AZ_FORMAT_WTRIG
) {
2620 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
2621 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
2622 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, tmp
);
2626 void evergreen_irq_disable(struct radeon_device
*rdev
)
2628 r600_disable_interrupts(rdev
);
2629 /* Wait and acknowledge irq */
2631 evergreen_irq_ack(rdev
);
2632 evergreen_disable_interrupt_state(rdev
);
2635 void evergreen_irq_suspend(struct radeon_device
*rdev
)
2637 evergreen_irq_disable(rdev
);
2638 r600_rlc_stop(rdev
);
2641 static u32
evergreen_get_ih_wptr(struct radeon_device
*rdev
)
2645 if (rdev
->wb
.enabled
)
2646 wptr
= le32_to_cpu(rdev
->wb
.wb
[R600_WB_IH_WPTR_OFFSET
/4]);
2648 wptr
= RREG32(IH_RB_WPTR
);
2650 if (wptr
& RB_OVERFLOW
) {
2651 /* When a ring buffer overflow happen start parsing interrupt
2652 * from the last not overwritten vector (wptr + 16). Hopefully
2653 * this should allow us to catchup.
2655 dev_warn(rdev
->dev
, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2656 wptr
, rdev
->ih
.rptr
, (wptr
+ 16) + rdev
->ih
.ptr_mask
);
2657 rdev
->ih
.rptr
= (wptr
+ 16) & rdev
->ih
.ptr_mask
;
2658 tmp
= RREG32(IH_RB_CNTL
);
2659 tmp
|= IH_WPTR_OVERFLOW_CLEAR
;
2660 WREG32(IH_RB_CNTL
, tmp
);
2662 return (wptr
& rdev
->ih
.ptr_mask
);
2665 int evergreen_irq_process(struct radeon_device
*rdev
)
2669 u32 src_id
, src_data
;
2671 bool queue_hotplug
= false;
2672 bool queue_hdmi
= false;
2674 if (!rdev
->ih
.enabled
|| rdev
->shutdown
)
2677 wptr
= evergreen_get_ih_wptr(rdev
);
2680 /* is somebody else already processing irqs? */
2681 if (atomic_xchg(&rdev
->ih
.lock
, 1))
2684 rptr
= rdev
->ih
.rptr
;
2685 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr
, wptr
);
2687 /* Order reading of wptr vs. reading of IH ring data */
2690 /* display interrupts */
2691 evergreen_irq_ack(rdev
);
2693 while (rptr
!= wptr
) {
2694 /* wptr/rptr are in bytes! */
2695 ring_index
= rptr
/ 4;
2696 src_id
= le32_to_cpu(rdev
->ih
.ring
[ring_index
]) & 0xff;
2697 src_data
= le32_to_cpu(rdev
->ih
.ring
[ring_index
+ 1]) & 0xfffffff;
2700 case 1: /* D1 vblank/vline */
2702 case 0: /* D1 vblank */
2703 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& LB_D1_VBLANK_INTERRUPT
) {
2704 if (rdev
->irq
.crtc_vblank_int
[0]) {
2705 drm_handle_vblank(rdev
->ddev
, 0);
2706 rdev
->pm
.vblank_sync
= true;
2707 wake_up(&rdev
->irq
.vblank_queue
);
2709 if (atomic_read(&rdev
->irq
.pflip
[0]))
2710 radeon_crtc_handle_flip(rdev
, 0);
2711 rdev
->irq
.stat_regs
.evergreen
.disp_int
&= ~LB_D1_VBLANK_INTERRUPT
;
2712 DRM_DEBUG("IH: D1 vblank\n");
2715 case 1: /* D1 vline */
2716 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& LB_D1_VLINE_INTERRUPT
) {
2717 rdev
->irq
.stat_regs
.evergreen
.disp_int
&= ~LB_D1_VLINE_INTERRUPT
;
2718 DRM_DEBUG("IH: D1 vline\n");
2722 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2726 case 2: /* D2 vblank/vline */
2728 case 0: /* D2 vblank */
2729 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& LB_D2_VBLANK_INTERRUPT
) {
2730 if (rdev
->irq
.crtc_vblank_int
[1]) {
2731 drm_handle_vblank(rdev
->ddev
, 1);
2732 rdev
->pm
.vblank_sync
= true;
2733 wake_up(&rdev
->irq
.vblank_queue
);
2735 if (atomic_read(&rdev
->irq
.pflip
[1]))
2736 radeon_crtc_handle_flip(rdev
, 1);
2737 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
&= ~LB_D2_VBLANK_INTERRUPT
;
2738 DRM_DEBUG("IH: D2 vblank\n");
2741 case 1: /* D2 vline */
2742 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& LB_D2_VLINE_INTERRUPT
) {
2743 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
&= ~LB_D2_VLINE_INTERRUPT
;
2744 DRM_DEBUG("IH: D2 vline\n");
2748 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2752 case 3: /* D3 vblank/vline */
2754 case 0: /* D3 vblank */
2755 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& LB_D3_VBLANK_INTERRUPT
) {
2756 if (rdev
->irq
.crtc_vblank_int
[2]) {
2757 drm_handle_vblank(rdev
->ddev
, 2);
2758 rdev
->pm
.vblank_sync
= true;
2759 wake_up(&rdev
->irq
.vblank_queue
);
2761 if (atomic_read(&rdev
->irq
.pflip
[2]))
2762 radeon_crtc_handle_flip(rdev
, 2);
2763 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
&= ~LB_D3_VBLANK_INTERRUPT
;
2764 DRM_DEBUG("IH: D3 vblank\n");
2767 case 1: /* D3 vline */
2768 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& LB_D3_VLINE_INTERRUPT
) {
2769 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
&= ~LB_D3_VLINE_INTERRUPT
;
2770 DRM_DEBUG("IH: D3 vline\n");
2774 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2778 case 4: /* D4 vblank/vline */
2780 case 0: /* D4 vblank */
2781 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& LB_D4_VBLANK_INTERRUPT
) {
2782 if (rdev
->irq
.crtc_vblank_int
[3]) {
2783 drm_handle_vblank(rdev
->ddev
, 3);
2784 rdev
->pm
.vblank_sync
= true;
2785 wake_up(&rdev
->irq
.vblank_queue
);
2787 if (atomic_read(&rdev
->irq
.pflip
[3]))
2788 radeon_crtc_handle_flip(rdev
, 3);
2789 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
&= ~LB_D4_VBLANK_INTERRUPT
;
2790 DRM_DEBUG("IH: D4 vblank\n");
2793 case 1: /* D4 vline */
2794 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& LB_D4_VLINE_INTERRUPT
) {
2795 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
&= ~LB_D4_VLINE_INTERRUPT
;
2796 DRM_DEBUG("IH: D4 vline\n");
2800 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2804 case 5: /* D5 vblank/vline */
2806 case 0: /* D5 vblank */
2807 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& LB_D5_VBLANK_INTERRUPT
) {
2808 if (rdev
->irq
.crtc_vblank_int
[4]) {
2809 drm_handle_vblank(rdev
->ddev
, 4);
2810 rdev
->pm
.vblank_sync
= true;
2811 wake_up(&rdev
->irq
.vblank_queue
);
2813 if (atomic_read(&rdev
->irq
.pflip
[4]))
2814 radeon_crtc_handle_flip(rdev
, 4);
2815 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
&= ~LB_D5_VBLANK_INTERRUPT
;
2816 DRM_DEBUG("IH: D5 vblank\n");
2819 case 1: /* D5 vline */
2820 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& LB_D5_VLINE_INTERRUPT
) {
2821 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
&= ~LB_D5_VLINE_INTERRUPT
;
2822 DRM_DEBUG("IH: D5 vline\n");
2826 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2830 case 6: /* D6 vblank/vline */
2832 case 0: /* D6 vblank */
2833 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& LB_D6_VBLANK_INTERRUPT
) {
2834 if (rdev
->irq
.crtc_vblank_int
[5]) {
2835 drm_handle_vblank(rdev
->ddev
, 5);
2836 rdev
->pm
.vblank_sync
= true;
2837 wake_up(&rdev
->irq
.vblank_queue
);
2839 if (atomic_read(&rdev
->irq
.pflip
[5]))
2840 radeon_crtc_handle_flip(rdev
, 5);
2841 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
&= ~LB_D6_VBLANK_INTERRUPT
;
2842 DRM_DEBUG("IH: D6 vblank\n");
2845 case 1: /* D6 vline */
2846 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& LB_D6_VLINE_INTERRUPT
) {
2847 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
&= ~LB_D6_VLINE_INTERRUPT
;
2848 DRM_DEBUG("IH: D6 vline\n");
2852 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2856 case 42: /* HPD hotplug */
2859 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& DC_HPD1_INTERRUPT
) {
2860 rdev
->irq
.stat_regs
.evergreen
.disp_int
&= ~DC_HPD1_INTERRUPT
;
2861 queue_hotplug
= true;
2862 DRM_DEBUG("IH: HPD1\n");
2866 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& DC_HPD2_INTERRUPT
) {
2867 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
&= ~DC_HPD2_INTERRUPT
;
2868 queue_hotplug
= true;
2869 DRM_DEBUG("IH: HPD2\n");
2873 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& DC_HPD3_INTERRUPT
) {
2874 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
&= ~DC_HPD3_INTERRUPT
;
2875 queue_hotplug
= true;
2876 DRM_DEBUG("IH: HPD3\n");
2880 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& DC_HPD4_INTERRUPT
) {
2881 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
&= ~DC_HPD4_INTERRUPT
;
2882 queue_hotplug
= true;
2883 DRM_DEBUG("IH: HPD4\n");
2887 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& DC_HPD5_INTERRUPT
) {
2888 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
&= ~DC_HPD5_INTERRUPT
;
2889 queue_hotplug
= true;
2890 DRM_DEBUG("IH: HPD5\n");
2894 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& DC_HPD6_INTERRUPT
) {
2895 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
&= ~DC_HPD6_INTERRUPT
;
2896 queue_hotplug
= true;
2897 DRM_DEBUG("IH: HPD6\n");
2901 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2908 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status1
& AFMT_AZ_FORMAT_WTRIG
) {
2909 rdev
->irq
.stat_regs
.evergreen
.afmt_status1
&= ~AFMT_AZ_FORMAT_WTRIG
;
2911 DRM_DEBUG("IH: HDMI0\n");
2915 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status2
& AFMT_AZ_FORMAT_WTRIG
) {
2916 rdev
->irq
.stat_regs
.evergreen
.afmt_status2
&= ~AFMT_AZ_FORMAT_WTRIG
;
2918 DRM_DEBUG("IH: HDMI1\n");
2922 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status3
& AFMT_AZ_FORMAT_WTRIG
) {
2923 rdev
->irq
.stat_regs
.evergreen
.afmt_status3
&= ~AFMT_AZ_FORMAT_WTRIG
;
2925 DRM_DEBUG("IH: HDMI2\n");
2929 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status4
& AFMT_AZ_FORMAT_WTRIG
) {
2930 rdev
->irq
.stat_regs
.evergreen
.afmt_status4
&= ~AFMT_AZ_FORMAT_WTRIG
;
2932 DRM_DEBUG("IH: HDMI3\n");
2936 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status5
& AFMT_AZ_FORMAT_WTRIG
) {
2937 rdev
->irq
.stat_regs
.evergreen
.afmt_status5
&= ~AFMT_AZ_FORMAT_WTRIG
;
2939 DRM_DEBUG("IH: HDMI4\n");
2943 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status6
& AFMT_AZ_FORMAT_WTRIG
) {
2944 rdev
->irq
.stat_regs
.evergreen
.afmt_status6
&= ~AFMT_AZ_FORMAT_WTRIG
;
2946 DRM_DEBUG("IH: HDMI5\n");
2950 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2954 case 176: /* CP_INT in ring buffer */
2955 case 177: /* CP_INT in IB1 */
2956 case 178: /* CP_INT in IB2 */
2957 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data
);
2958 radeon_fence_process(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
2960 case 181: /* CP EOP event */
2961 DRM_DEBUG("IH: CP EOP\n");
2962 if (rdev
->family
>= CHIP_CAYMAN
) {
2965 radeon_fence_process(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
2968 radeon_fence_process(rdev
, CAYMAN_RING_TYPE_CP1_INDEX
);
2971 radeon_fence_process(rdev
, CAYMAN_RING_TYPE_CP2_INDEX
);
2975 radeon_fence_process(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
2977 case 233: /* GUI IDLE */
2978 DRM_DEBUG("IH: GUI idle\n");
2979 wake_up(&rdev
->irq
.idle_queue
);
2982 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2986 /* wptr/rptr are in bytes! */
2988 rptr
&= rdev
->ih
.ptr_mask
;
2991 schedule_work(&rdev
->hotplug_work
);
2993 schedule_work(&rdev
->audio_work
);
2994 rdev
->ih
.rptr
= rptr
;
2995 WREG32(IH_RB_RPTR
, rdev
->ih
.rptr
);
2996 atomic_set(&rdev
->ih
.lock
, 0);
2998 /* make sure wptr hasn't changed while processing */
2999 wptr
= evergreen_get_ih_wptr(rdev
);
3006 static int evergreen_startup(struct radeon_device
*rdev
)
3008 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
3011 /* enable pcie gen2 link */
3012 evergreen_pcie_gen2_enable(rdev
);
3014 if (ASIC_IS_DCE5(rdev
)) {
3015 if (!rdev
->me_fw
|| !rdev
->pfp_fw
|| !rdev
->rlc_fw
|| !rdev
->mc_fw
) {
3016 r
= ni_init_microcode(rdev
);
3018 DRM_ERROR("Failed to load firmware!\n");
3022 r
= ni_mc_load_microcode(rdev
);
3024 DRM_ERROR("Failed to load MC firmware!\n");
3028 if (!rdev
->me_fw
|| !rdev
->pfp_fw
|| !rdev
->rlc_fw
) {
3029 r
= r600_init_microcode(rdev
);
3031 DRM_ERROR("Failed to load firmware!\n");
3037 r
= r600_vram_scratch_init(rdev
);
3041 evergreen_mc_program(rdev
);
3042 if (rdev
->flags
& RADEON_IS_AGP
) {
3043 evergreen_agp_enable(rdev
);
3045 r
= evergreen_pcie_gart_enable(rdev
);
3049 evergreen_gpu_init(rdev
);
3051 r
= evergreen_blit_init(rdev
);
3053 r600_blit_fini(rdev
);
3054 rdev
->asic
->copy
.copy
= NULL
;
3055 dev_warn(rdev
->dev
, "failed blitter (%d) falling back to memcpy\n", r
);
3058 /* allocate wb buffer */
3059 r
= radeon_wb_init(rdev
);
3063 r
= radeon_fence_driver_start_ring(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
3065 dev_err(rdev
->dev
, "failed initializing CP fences (%d).\n", r
);
3070 r
= r600_irq_init(rdev
);
3072 DRM_ERROR("radeon: IH init failed (%d).\n", r
);
3073 radeon_irq_kms_fini(rdev
);
3076 evergreen_irq_set(rdev
);
3078 r
= radeon_ring_init(rdev
, ring
, ring
->ring_size
, RADEON_WB_CP_RPTR_OFFSET
,
3079 R600_CP_RB_RPTR
, R600_CP_RB_WPTR
,
3080 0, 0xfffff, RADEON_CP_PACKET2
);
3083 r
= evergreen_cp_load_microcode(rdev
);
3086 r
= evergreen_cp_resume(rdev
);
3090 r
= radeon_ib_pool_init(rdev
);
3092 dev_err(rdev
->dev
, "IB initialization failed (%d).\n", r
);
3096 r
= r600_audio_init(rdev
);
3098 DRM_ERROR("radeon: audio init failed\n");
3105 int evergreen_resume(struct radeon_device
*rdev
)
3109 /* reset the asic, the gfx blocks are often in a bad state
3110 * after the driver is unloaded or after a resume
3112 if (radeon_asic_reset(rdev
))
3113 dev_warn(rdev
->dev
, "GPU reset failed !\n");
3114 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3115 * posting will perform necessary task to bring back GPU into good
3119 atom_asic_init(rdev
->mode_info
.atom_context
);
3121 rdev
->accel_working
= true;
3122 r
= evergreen_startup(rdev
);
3124 DRM_ERROR("evergreen startup failed on resume\n");
3125 rdev
->accel_working
= false;
3133 int evergreen_suspend(struct radeon_device
*rdev
)
3135 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
3137 r600_audio_fini(rdev
);
3139 ring
->ready
= false;
3140 evergreen_irq_suspend(rdev
);
3141 radeon_wb_disable(rdev
);
3142 evergreen_pcie_gart_disable(rdev
);
3147 /* Plan is to move initialization in that function and use
3148 * helper function so that radeon_device_init pretty much
3149 * do nothing more than calling asic specific function. This
3150 * should also allow to remove a bunch of callback function
3153 int evergreen_init(struct radeon_device
*rdev
)
3158 if (!radeon_get_bios(rdev
)) {
3159 if (ASIC_IS_AVIVO(rdev
))
3162 /* Must be an ATOMBIOS */
3163 if (!rdev
->is_atom_bios
) {
3164 dev_err(rdev
->dev
, "Expecting atombios for evergreen GPU\n");
3167 r
= radeon_atombios_init(rdev
);
3170 /* reset the asic, the gfx blocks are often in a bad state
3171 * after the driver is unloaded or after a resume
3173 if (radeon_asic_reset(rdev
))
3174 dev_warn(rdev
->dev
, "GPU reset failed !\n");
3175 /* Post card if necessary */
3176 if (!radeon_card_posted(rdev
)) {
3178 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
3181 DRM_INFO("GPU not posted. posting now...\n");
3182 atom_asic_init(rdev
->mode_info
.atom_context
);
3184 /* Initialize scratch registers */
3185 r600_scratch_init(rdev
);
3186 /* Initialize surface registers */
3187 radeon_surface_init(rdev
);
3188 /* Initialize clocks */
3189 radeon_get_clock_info(rdev
->ddev
);
3191 r
= radeon_fence_driver_init(rdev
);
3194 /* initialize AGP */
3195 if (rdev
->flags
& RADEON_IS_AGP
) {
3196 r
= radeon_agp_init(rdev
);
3198 radeon_agp_disable(rdev
);
3200 /* initialize memory controller */
3201 r
= evergreen_mc_init(rdev
);
3204 /* Memory manager */
3205 r
= radeon_bo_init(rdev
);
3209 r
= radeon_irq_kms_init(rdev
);
3213 rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
].ring_obj
= NULL
;
3214 r600_ring_init(rdev
, &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
], 1024 * 1024);
3216 rdev
->ih
.ring_obj
= NULL
;
3217 r600_ih_ring_init(rdev
, 64 * 1024);
3219 r
= r600_pcie_gart_init(rdev
);
3223 rdev
->accel_working
= true;
3224 r
= evergreen_startup(rdev
);
3226 dev_err(rdev
->dev
, "disabling GPU acceleration\n");
3228 r600_irq_fini(rdev
);
3229 radeon_wb_fini(rdev
);
3230 radeon_ib_pool_fini(rdev
);
3231 radeon_irq_kms_fini(rdev
);
3232 evergreen_pcie_gart_fini(rdev
);
3233 rdev
->accel_working
= false;
3236 /* Don't start up if the MC ucode is missing on BTC parts.
3237 * The default clocks and voltages before the MC ucode
3238 * is loaded are not suffient for advanced operations.
3240 if (ASIC_IS_DCE5(rdev
)) {
3241 if (!rdev
->mc_fw
&& !(rdev
->flags
& RADEON_IS_IGP
)) {
3242 DRM_ERROR("radeon: MC ucode required for NI+.\n");
3250 void evergreen_fini(struct radeon_device
*rdev
)
3252 r600_audio_fini(rdev
);
3253 r600_blit_fini(rdev
);
3255 r600_irq_fini(rdev
);
3256 radeon_wb_fini(rdev
);
3257 radeon_ib_pool_fini(rdev
);
3258 radeon_irq_kms_fini(rdev
);
3259 evergreen_pcie_gart_fini(rdev
);
3260 r600_vram_scratch_fini(rdev
);
3261 radeon_gem_fini(rdev
);
3262 radeon_fence_driver_fini(rdev
);
3263 radeon_agp_fini(rdev
);
3264 radeon_bo_fini(rdev
);
3265 radeon_atombios_fini(rdev
);
3270 void evergreen_pcie_gen2_enable(struct radeon_device
*rdev
)
3272 u32 link_width_cntl
, speed_cntl
;
3274 if (radeon_pcie_gen2
== 0)
3277 if (rdev
->flags
& RADEON_IS_IGP
)
3280 if (!(rdev
->flags
& RADEON_IS_PCIE
))
3283 /* x2 cards have a special sequence */
3284 if (ASIC_IS_X2(rdev
))
3287 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3288 if ((speed_cntl
& LC_OTHER_SIDE_EVER_SENT_GEN2
) ||
3289 (speed_cntl
& LC_OTHER_SIDE_SUPPORTS_GEN2
)) {
3291 link_width_cntl
= RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
);
3292 link_width_cntl
&= ~LC_UPCONFIGURE_DIS
;
3293 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
3295 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3296 speed_cntl
&= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN
;
3297 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3299 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3300 speed_cntl
|= LC_CLR_FAILED_SPD_CHANGE_CNT
;
3301 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3303 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3304 speed_cntl
&= ~LC_CLR_FAILED_SPD_CHANGE_CNT
;
3305 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3307 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3308 speed_cntl
|= LC_GEN2_EN_STRAP
;
3309 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3312 link_width_cntl
= RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
);
3313 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3315 link_width_cntl
|= LC_UPCONFIGURE_DIS
;
3317 link_width_cntl
&= ~LC_UPCONFIGURE_DIS
;
3318 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);