2 * Copyright 2010 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
29 #include "radeon_asic.h"
30 #include <drm/radeon_drm.h>
31 #include "evergreend.h"
34 #include "evergreen_reg.h"
35 #include "evergreen_blit_shaders.h"
37 #define EVERGREEN_PFP_UCODE_SIZE 1120
38 #define EVERGREEN_PM4_UCODE_SIZE 1376
40 static const u32 crtc_offsets
[6] =
42 EVERGREEN_CRTC0_REGISTER_OFFSET
,
43 EVERGREEN_CRTC1_REGISTER_OFFSET
,
44 EVERGREEN_CRTC2_REGISTER_OFFSET
,
45 EVERGREEN_CRTC3_REGISTER_OFFSET
,
46 EVERGREEN_CRTC4_REGISTER_OFFSET
,
47 EVERGREEN_CRTC5_REGISTER_OFFSET
50 static void evergreen_gpu_init(struct radeon_device
*rdev
);
51 void evergreen_fini(struct radeon_device
*rdev
);
52 void evergreen_pcie_gen2_enable(struct radeon_device
*rdev
);
53 extern void cayman_cp_int_cntl_setup(struct radeon_device
*rdev
,
54 int ring
, u32 cp_int_cntl
);
56 void evergreen_tiling_fields(unsigned tiling_flags
, unsigned *bankw
,
57 unsigned *bankh
, unsigned *mtaspect
,
60 *bankw
= (tiling_flags
>> RADEON_TILING_EG_BANKW_SHIFT
) & RADEON_TILING_EG_BANKW_MASK
;
61 *bankh
= (tiling_flags
>> RADEON_TILING_EG_BANKH_SHIFT
) & RADEON_TILING_EG_BANKH_MASK
;
62 *mtaspect
= (tiling_flags
>> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT
) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK
;
63 *tile_split
= (tiling_flags
>> RADEON_TILING_EG_TILE_SPLIT_SHIFT
) & RADEON_TILING_EG_TILE_SPLIT_MASK
;
66 case 1: *bankw
= EVERGREEN_ADDR_SURF_BANK_WIDTH_1
; break;
67 case 2: *bankw
= EVERGREEN_ADDR_SURF_BANK_WIDTH_2
; break;
68 case 4: *bankw
= EVERGREEN_ADDR_SURF_BANK_WIDTH_4
; break;
69 case 8: *bankw
= EVERGREEN_ADDR_SURF_BANK_WIDTH_8
; break;
73 case 1: *bankh
= EVERGREEN_ADDR_SURF_BANK_HEIGHT_1
; break;
74 case 2: *bankh
= EVERGREEN_ADDR_SURF_BANK_HEIGHT_2
; break;
75 case 4: *bankh
= EVERGREEN_ADDR_SURF_BANK_HEIGHT_4
; break;
76 case 8: *bankh
= EVERGREEN_ADDR_SURF_BANK_HEIGHT_8
; break;
80 case 1: *mtaspect
= EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1
; break;
81 case 2: *mtaspect
= EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2
; break;
82 case 4: *mtaspect
= EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4
; break;
83 case 8: *mtaspect
= EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8
; break;
87 static int sumo_set_uvd_clock(struct radeon_device
*rdev
, u32 clock
,
88 u32 cntl_reg
, u32 status_reg
)
91 struct atom_clock_dividers dividers
;
93 r
= radeon_atom_get_clock_dividers(rdev
, COMPUTE_ENGINE_PLL_PARAM
,
94 clock
, false, ÷rs
);
98 WREG32_P(cntl_reg
, dividers
.post_div
, ~(DCLK_DIR_CNTL_EN
|DCLK_DIVIDER_MASK
));
100 for (i
= 0; i
< 100; i
++) {
101 if (RREG32(status_reg
) & DCLK_STATUS
)
111 int sumo_set_uvd_clocks(struct radeon_device
*rdev
, u32 vclk
, u32 dclk
)
114 u32 cg_scratch
= RREG32(CG_SCRATCH1
);
116 r
= sumo_set_uvd_clock(rdev
, vclk
, CG_VCLK_CNTL
, CG_VCLK_STATUS
);
119 cg_scratch
&= 0xffff0000;
120 cg_scratch
|= vclk
/ 100; /* Mhz */
122 r
= sumo_set_uvd_clock(rdev
, dclk
, CG_DCLK_CNTL
, CG_DCLK_STATUS
);
125 cg_scratch
&= 0x0000ffff;
126 cg_scratch
|= (dclk
/ 100) << 16; /* Mhz */
129 WREG32(CG_SCRATCH1
, cg_scratch
);
134 void evergreen_fix_pci_max_read_req_size(struct radeon_device
*rdev
)
139 err
= pcie_capability_read_word(rdev
->pdev
, PCI_EXP_DEVCTL
, &ctl
);
143 v
= (ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12;
145 /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
146 * to avoid hangs or perfomance issues
148 if ((v
== 0) || (v
== 6) || (v
== 7)) {
149 ctl
&= ~PCI_EXP_DEVCTL_READRQ
;
151 pcie_capability_write_word(rdev
->pdev
, PCI_EXP_DEVCTL
, ctl
);
156 * dce4_wait_for_vblank - vblank wait asic callback.
158 * @rdev: radeon_device pointer
159 * @crtc: crtc to wait for vblank on
161 * Wait for vblank on the requested crtc (evergreen+).
163 void dce4_wait_for_vblank(struct radeon_device
*rdev
, int crtc
)
167 if (crtc
>= rdev
->num_crtc
)
170 if (RREG32(EVERGREEN_CRTC_CONTROL
+ crtc_offsets
[crtc
]) & EVERGREEN_CRTC_MASTER_EN
) {
171 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
172 if (!(RREG32(EVERGREEN_CRTC_STATUS
+ crtc_offsets
[crtc
]) & EVERGREEN_CRTC_V_BLANK
))
176 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
177 if (RREG32(EVERGREEN_CRTC_STATUS
+ crtc_offsets
[crtc
]) & EVERGREEN_CRTC_V_BLANK
)
185 * radeon_irq_kms_pflip_irq_get - pre-pageflip callback.
187 * @rdev: radeon_device pointer
188 * @crtc: crtc to prepare for pageflip on
190 * Pre-pageflip callback (evergreen+).
191 * Enables the pageflip irq (vblank irq).
193 void evergreen_pre_page_flip(struct radeon_device
*rdev
, int crtc
)
195 /* enable the pflip int */
196 radeon_irq_kms_pflip_irq_get(rdev
, crtc
);
200 * evergreen_post_page_flip - pos-pageflip callback.
202 * @rdev: radeon_device pointer
203 * @crtc: crtc to cleanup pageflip on
205 * Post-pageflip callback (evergreen+).
206 * Disables the pageflip irq (vblank irq).
208 void evergreen_post_page_flip(struct radeon_device
*rdev
, int crtc
)
210 /* disable the pflip int */
211 radeon_irq_kms_pflip_irq_put(rdev
, crtc
);
215 * evergreen_page_flip - pageflip callback.
217 * @rdev: radeon_device pointer
218 * @crtc_id: crtc to cleanup pageflip on
219 * @crtc_base: new address of the crtc (GPU MC address)
221 * Does the actual pageflip (evergreen+).
222 * During vblank we take the crtc lock and wait for the update_pending
223 * bit to go high, when it does, we release the lock, and allow the
224 * double buffered update to take place.
225 * Returns the current update pending status.
227 u32
evergreen_page_flip(struct radeon_device
*rdev
, int crtc_id
, u64 crtc_base
)
229 struct radeon_crtc
*radeon_crtc
= rdev
->mode_info
.crtcs
[crtc_id
];
230 u32 tmp
= RREG32(EVERGREEN_GRPH_UPDATE
+ radeon_crtc
->crtc_offset
);
233 /* Lock the graphics update lock */
234 tmp
|= EVERGREEN_GRPH_UPDATE_LOCK
;
235 WREG32(EVERGREEN_GRPH_UPDATE
+ radeon_crtc
->crtc_offset
, tmp
);
237 /* update the scanout addresses */
238 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ radeon_crtc
->crtc_offset
,
239 upper_32_bits(crtc_base
));
240 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ radeon_crtc
->crtc_offset
,
243 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ radeon_crtc
->crtc_offset
,
244 upper_32_bits(crtc_base
));
245 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ radeon_crtc
->crtc_offset
,
248 /* Wait for update_pending to go high. */
249 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
250 if (RREG32(EVERGREEN_GRPH_UPDATE
+ radeon_crtc
->crtc_offset
) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING
)
254 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
256 /* Unlock the lock, so double-buffering can take place inside vblank */
257 tmp
&= ~EVERGREEN_GRPH_UPDATE_LOCK
;
258 WREG32(EVERGREEN_GRPH_UPDATE
+ radeon_crtc
->crtc_offset
, tmp
);
260 /* Return current update_pending status: */
261 return RREG32(EVERGREEN_GRPH_UPDATE
+ radeon_crtc
->crtc_offset
) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING
;
264 /* get temperature in millidegrees */
265 int evergreen_get_temp(struct radeon_device
*rdev
)
270 if (rdev
->family
== CHIP_JUNIPER
) {
271 toffset
= (RREG32(CG_THERMAL_CTRL
) & TOFFSET_MASK
) >>
273 temp
= (RREG32(CG_TS0_STATUS
) & TS0_ADC_DOUT_MASK
) >>
277 actual_temp
= temp
/ 2 - (0x200 - toffset
);
279 actual_temp
= temp
/ 2 + toffset
;
281 actual_temp
= actual_temp
* 1000;
284 temp
= (RREG32(CG_MULT_THERMAL_STATUS
) & ASIC_T_MASK
) >>
289 else if (temp
& 0x200)
291 else if (temp
& 0x100) {
292 actual_temp
= temp
& 0x1ff;
293 actual_temp
|= ~0x1ff;
295 actual_temp
= temp
& 0xff;
297 actual_temp
= (actual_temp
* 1000) / 2;
303 int sumo_get_temp(struct radeon_device
*rdev
)
305 u32 temp
= RREG32(CG_THERMAL_STATUS
) & 0xff;
306 int actual_temp
= temp
- 49;
308 return actual_temp
* 1000;
312 * sumo_pm_init_profile - Initialize power profiles callback.
314 * @rdev: radeon_device pointer
316 * Initialize the power states used in profile mode
317 * (sumo, trinity, SI).
318 * Used for profile mode only.
320 void sumo_pm_init_profile(struct radeon_device
*rdev
)
325 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
326 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
327 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
328 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 0;
331 if (rdev
->flags
& RADEON_IS_MOBILITY
)
332 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_BATTERY
, 0);
334 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 0);
336 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= idx
;
337 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= idx
;
338 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
339 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
341 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= idx
;
342 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= idx
;
343 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
344 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
346 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= idx
;
347 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= idx
;
348 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
349 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 0;
351 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= idx
;
352 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= idx
;
353 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
354 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 0;
357 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 0);
358 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= idx
;
359 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= idx
;
360 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
361 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
=
362 rdev
->pm
.power_state
[idx
].num_clock_modes
- 1;
364 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= idx
;
365 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= idx
;
366 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
367 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
=
368 rdev
->pm
.power_state
[idx
].num_clock_modes
- 1;
372 * btc_pm_init_profile - Initialize power profiles callback.
374 * @rdev: radeon_device pointer
376 * Initialize the power states used in profile mode
378 * Used for profile mode only.
380 void btc_pm_init_profile(struct radeon_device
*rdev
)
385 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
386 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
387 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
388 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 2;
389 /* starting with BTC, there is one state that is used for both
390 * MH and SH. Difference is that we always use the high clock index for
393 if (rdev
->flags
& RADEON_IS_MOBILITY
)
394 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_BATTERY
, 0);
396 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 0);
398 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= idx
;
399 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= idx
;
400 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
401 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
403 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= idx
;
404 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= idx
;
405 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
406 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 1;
408 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= idx
;
409 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= idx
;
410 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
411 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 2;
413 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= idx
;
414 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= idx
;
415 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
416 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
418 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= idx
;
419 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= idx
;
420 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
421 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 1;
423 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= idx
;
424 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= idx
;
425 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
426 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 2;
430 * evergreen_pm_misc - set additional pm hw parameters callback.
432 * @rdev: radeon_device pointer
434 * Set non-clock parameters associated with a power state
435 * (voltage, etc.) (evergreen+).
437 void evergreen_pm_misc(struct radeon_device
*rdev
)
439 int req_ps_idx
= rdev
->pm
.requested_power_state_index
;
440 int req_cm_idx
= rdev
->pm
.requested_clock_mode_index
;
441 struct radeon_power_state
*ps
= &rdev
->pm
.power_state
[req_ps_idx
];
442 struct radeon_voltage
*voltage
= &ps
->clock_info
[req_cm_idx
].voltage
;
444 if (voltage
->type
== VOLTAGE_SW
) {
445 /* 0xff01 is a flag rather then an actual voltage */
446 if (voltage
->voltage
== 0xff01)
448 if (voltage
->voltage
&& (voltage
->voltage
!= rdev
->pm
.current_vddc
)) {
449 radeon_atom_set_voltage(rdev
, voltage
->voltage
, SET_VOLTAGE_TYPE_ASIC_VDDC
);
450 rdev
->pm
.current_vddc
= voltage
->voltage
;
451 DRM_DEBUG("Setting: vddc: %d\n", voltage
->voltage
);
454 /* starting with BTC, there is one state that is used for both
455 * MH and SH. Difference is that we always use the high clock index for
458 if ((rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) &&
459 (rdev
->family
>= CHIP_BARTS
) &&
460 rdev
->pm
.active_crtc_count
&&
461 ((rdev
->pm
.profile_index
== PM_PROFILE_MID_MH_IDX
) ||
462 (rdev
->pm
.profile_index
== PM_PROFILE_LOW_MH_IDX
)))
463 voltage
= &rdev
->pm
.power_state
[req_ps_idx
].
464 clock_info
[rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
].voltage
;
466 /* 0xff01 is a flag rather then an actual voltage */
467 if (voltage
->vddci
== 0xff01)
469 if (voltage
->vddci
&& (voltage
->vddci
!= rdev
->pm
.current_vddci
)) {
470 radeon_atom_set_voltage(rdev
, voltage
->vddci
, SET_VOLTAGE_TYPE_ASIC_VDDCI
);
471 rdev
->pm
.current_vddci
= voltage
->vddci
;
472 DRM_DEBUG("Setting: vddci: %d\n", voltage
->vddci
);
478 * evergreen_pm_prepare - pre-power state change callback.
480 * @rdev: radeon_device pointer
482 * Prepare for a power state change (evergreen+).
484 void evergreen_pm_prepare(struct radeon_device
*rdev
)
486 struct drm_device
*ddev
= rdev
->ddev
;
487 struct drm_crtc
*crtc
;
488 struct radeon_crtc
*radeon_crtc
;
491 /* disable any active CRTCs */
492 list_for_each_entry(crtc
, &ddev
->mode_config
.crtc_list
, head
) {
493 radeon_crtc
= to_radeon_crtc(crtc
);
494 if (radeon_crtc
->enabled
) {
495 tmp
= RREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
);
496 tmp
|= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE
;
497 WREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
, tmp
);
503 * evergreen_pm_finish - post-power state change callback.
505 * @rdev: radeon_device pointer
507 * Clean up after a power state change (evergreen+).
509 void evergreen_pm_finish(struct radeon_device
*rdev
)
511 struct drm_device
*ddev
= rdev
->ddev
;
512 struct drm_crtc
*crtc
;
513 struct radeon_crtc
*radeon_crtc
;
516 /* enable any active CRTCs */
517 list_for_each_entry(crtc
, &ddev
->mode_config
.crtc_list
, head
) {
518 radeon_crtc
= to_radeon_crtc(crtc
);
519 if (radeon_crtc
->enabled
) {
520 tmp
= RREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
);
521 tmp
&= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE
;
522 WREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
, tmp
);
528 * evergreen_hpd_sense - hpd sense callback.
530 * @rdev: radeon_device pointer
531 * @hpd: hpd (hotplug detect) pin
533 * Checks if a digital monitor is connected (evergreen+).
534 * Returns true if connected, false if not connected.
536 bool evergreen_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
)
538 bool connected
= false;
542 if (RREG32(DC_HPD1_INT_STATUS
) & DC_HPDx_SENSE
)
546 if (RREG32(DC_HPD2_INT_STATUS
) & DC_HPDx_SENSE
)
550 if (RREG32(DC_HPD3_INT_STATUS
) & DC_HPDx_SENSE
)
554 if (RREG32(DC_HPD4_INT_STATUS
) & DC_HPDx_SENSE
)
558 if (RREG32(DC_HPD5_INT_STATUS
) & DC_HPDx_SENSE
)
562 if (RREG32(DC_HPD6_INT_STATUS
) & DC_HPDx_SENSE
)
573 * evergreen_hpd_set_polarity - hpd set polarity callback.
575 * @rdev: radeon_device pointer
576 * @hpd: hpd (hotplug detect) pin
578 * Set the polarity of the hpd pin (evergreen+).
580 void evergreen_hpd_set_polarity(struct radeon_device
*rdev
,
581 enum radeon_hpd_id hpd
)
584 bool connected
= evergreen_hpd_sense(rdev
, hpd
);
588 tmp
= RREG32(DC_HPD1_INT_CONTROL
);
590 tmp
&= ~DC_HPDx_INT_POLARITY
;
592 tmp
|= DC_HPDx_INT_POLARITY
;
593 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
596 tmp
= RREG32(DC_HPD2_INT_CONTROL
);
598 tmp
&= ~DC_HPDx_INT_POLARITY
;
600 tmp
|= DC_HPDx_INT_POLARITY
;
601 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
604 tmp
= RREG32(DC_HPD3_INT_CONTROL
);
606 tmp
&= ~DC_HPDx_INT_POLARITY
;
608 tmp
|= DC_HPDx_INT_POLARITY
;
609 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
612 tmp
= RREG32(DC_HPD4_INT_CONTROL
);
614 tmp
&= ~DC_HPDx_INT_POLARITY
;
616 tmp
|= DC_HPDx_INT_POLARITY
;
617 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
620 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
622 tmp
&= ~DC_HPDx_INT_POLARITY
;
624 tmp
|= DC_HPDx_INT_POLARITY
;
625 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
628 tmp
= RREG32(DC_HPD6_INT_CONTROL
);
630 tmp
&= ~DC_HPDx_INT_POLARITY
;
632 tmp
|= DC_HPDx_INT_POLARITY
;
633 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
641 * evergreen_hpd_init - hpd setup callback.
643 * @rdev: radeon_device pointer
645 * Setup the hpd pins used by the card (evergreen+).
646 * Enable the pin, set the polarity, and enable the hpd interrupts.
648 void evergreen_hpd_init(struct radeon_device
*rdev
)
650 struct drm_device
*dev
= rdev
->ddev
;
651 struct drm_connector
*connector
;
652 unsigned enabled
= 0;
653 u32 tmp
= DC_HPDx_CONNECTION_TIMER(0x9c4) |
654 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN
;
656 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
657 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
658 switch (radeon_connector
->hpd
.hpd
) {
660 WREG32(DC_HPD1_CONTROL
, tmp
);
663 WREG32(DC_HPD2_CONTROL
, tmp
);
666 WREG32(DC_HPD3_CONTROL
, tmp
);
669 WREG32(DC_HPD4_CONTROL
, tmp
);
672 WREG32(DC_HPD5_CONTROL
, tmp
);
675 WREG32(DC_HPD6_CONTROL
, tmp
);
680 radeon_hpd_set_polarity(rdev
, radeon_connector
->hpd
.hpd
);
681 enabled
|= 1 << radeon_connector
->hpd
.hpd
;
683 radeon_irq_kms_enable_hpd(rdev
, enabled
);
687 * evergreen_hpd_fini - hpd tear down callback.
689 * @rdev: radeon_device pointer
691 * Tear down the hpd pins used by the card (evergreen+).
692 * Disable the hpd interrupts.
694 void evergreen_hpd_fini(struct radeon_device
*rdev
)
696 struct drm_device
*dev
= rdev
->ddev
;
697 struct drm_connector
*connector
;
698 unsigned disabled
= 0;
700 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
701 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
702 switch (radeon_connector
->hpd
.hpd
) {
704 WREG32(DC_HPD1_CONTROL
, 0);
707 WREG32(DC_HPD2_CONTROL
, 0);
710 WREG32(DC_HPD3_CONTROL
, 0);
713 WREG32(DC_HPD4_CONTROL
, 0);
716 WREG32(DC_HPD5_CONTROL
, 0);
719 WREG32(DC_HPD6_CONTROL
, 0);
724 disabled
|= 1 << radeon_connector
->hpd
.hpd
;
726 radeon_irq_kms_disable_hpd(rdev
, disabled
);
729 /* watermark setup */
731 static u32
evergreen_line_buffer_adjust(struct radeon_device
*rdev
,
732 struct radeon_crtc
*radeon_crtc
,
733 struct drm_display_mode
*mode
,
734 struct drm_display_mode
*other_mode
)
739 * There are 3 line buffers, each one shared by 2 display controllers.
740 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
741 * the display controllers. The paritioning is done via one of four
742 * preset allocations specified in bits 2:0:
743 * first display controller
744 * 0 - first half of lb (3840 * 2)
745 * 1 - first 3/4 of lb (5760 * 2)
746 * 2 - whole lb (7680 * 2), other crtc must be disabled
747 * 3 - first 1/4 of lb (1920 * 2)
748 * second display controller
749 * 4 - second half of lb (3840 * 2)
750 * 5 - second 3/4 of lb (5760 * 2)
751 * 6 - whole lb (7680 * 2), other crtc must be disabled
752 * 7 - last 1/4 of lb (1920 * 2)
754 /* this can get tricky if we have two large displays on a paired group
755 * of crtcs. Ideally for multiple large displays we'd assign them to
756 * non-linked crtcs for maximum line buffer allocation.
758 if (radeon_crtc
->base
.enabled
&& mode
) {
766 /* second controller of the pair uses second half of the lb */
767 if (radeon_crtc
->crtc_id
% 2)
769 WREG32(DC_LB_MEMORY_SPLIT
+ radeon_crtc
->crtc_offset
, tmp
);
771 if (radeon_crtc
->base
.enabled
&& mode
) {
776 if (ASIC_IS_DCE5(rdev
))
782 if (ASIC_IS_DCE5(rdev
))
788 if (ASIC_IS_DCE5(rdev
))
794 if (ASIC_IS_DCE5(rdev
))
801 /* controller not enabled, so no lb used */
805 u32
evergreen_get_number_of_dram_channels(struct radeon_device
*rdev
)
807 u32 tmp
= RREG32(MC_SHARED_CHMAP
);
809 switch ((tmp
& NOOFCHAN_MASK
) >> NOOFCHAN_SHIFT
) {
822 struct evergreen_wm_params
{
823 u32 dram_channels
; /* number of dram channels */
824 u32 yclk
; /* bandwidth per dram data pin in kHz */
825 u32 sclk
; /* engine clock in kHz */
826 u32 disp_clk
; /* display clock in kHz */
827 u32 src_width
; /* viewport width */
828 u32 active_time
; /* active display time in ns */
829 u32 blank_time
; /* blank time in ns */
830 bool interlaced
; /* mode is interlaced */
831 fixed20_12 vsc
; /* vertical scale ratio */
832 u32 num_heads
; /* number of active crtcs */
833 u32 bytes_per_pixel
; /* bytes per pixel display + overlay */
834 u32 lb_size
; /* line buffer allocated to pipe */
835 u32 vtaps
; /* vertical scaler taps */
838 static u32
evergreen_dram_bandwidth(struct evergreen_wm_params
*wm
)
840 /* Calculate DRAM Bandwidth and the part allocated to display. */
841 fixed20_12 dram_efficiency
; /* 0.7 */
842 fixed20_12 yclk
, dram_channels
, bandwidth
;
845 a
.full
= dfixed_const(1000);
846 yclk
.full
= dfixed_const(wm
->yclk
);
847 yclk
.full
= dfixed_div(yclk
, a
);
848 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
849 a
.full
= dfixed_const(10);
850 dram_efficiency
.full
= dfixed_const(7);
851 dram_efficiency
.full
= dfixed_div(dram_efficiency
, a
);
852 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
853 bandwidth
.full
= dfixed_mul(bandwidth
, dram_efficiency
);
855 return dfixed_trunc(bandwidth
);
858 static u32
evergreen_dram_bandwidth_for_display(struct evergreen_wm_params
*wm
)
860 /* Calculate DRAM Bandwidth and the part allocated to display. */
861 fixed20_12 disp_dram_allocation
; /* 0.3 to 0.7 */
862 fixed20_12 yclk
, dram_channels
, bandwidth
;
865 a
.full
= dfixed_const(1000);
866 yclk
.full
= dfixed_const(wm
->yclk
);
867 yclk
.full
= dfixed_div(yclk
, a
);
868 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
869 a
.full
= dfixed_const(10);
870 disp_dram_allocation
.full
= dfixed_const(3); /* XXX worse case value 0.3 */
871 disp_dram_allocation
.full
= dfixed_div(disp_dram_allocation
, a
);
872 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
873 bandwidth
.full
= dfixed_mul(bandwidth
, disp_dram_allocation
);
875 return dfixed_trunc(bandwidth
);
878 static u32
evergreen_data_return_bandwidth(struct evergreen_wm_params
*wm
)
880 /* Calculate the display Data return Bandwidth */
881 fixed20_12 return_efficiency
; /* 0.8 */
882 fixed20_12 sclk
, bandwidth
;
885 a
.full
= dfixed_const(1000);
886 sclk
.full
= dfixed_const(wm
->sclk
);
887 sclk
.full
= dfixed_div(sclk
, a
);
888 a
.full
= dfixed_const(10);
889 return_efficiency
.full
= dfixed_const(8);
890 return_efficiency
.full
= dfixed_div(return_efficiency
, a
);
891 a
.full
= dfixed_const(32);
892 bandwidth
.full
= dfixed_mul(a
, sclk
);
893 bandwidth
.full
= dfixed_mul(bandwidth
, return_efficiency
);
895 return dfixed_trunc(bandwidth
);
898 static u32
evergreen_dmif_request_bandwidth(struct evergreen_wm_params
*wm
)
900 /* Calculate the DMIF Request Bandwidth */
901 fixed20_12 disp_clk_request_efficiency
; /* 0.8 */
902 fixed20_12 disp_clk
, bandwidth
;
905 a
.full
= dfixed_const(1000);
906 disp_clk
.full
= dfixed_const(wm
->disp_clk
);
907 disp_clk
.full
= dfixed_div(disp_clk
, a
);
908 a
.full
= dfixed_const(10);
909 disp_clk_request_efficiency
.full
= dfixed_const(8);
910 disp_clk_request_efficiency
.full
= dfixed_div(disp_clk_request_efficiency
, a
);
911 a
.full
= dfixed_const(32);
912 bandwidth
.full
= dfixed_mul(a
, disp_clk
);
913 bandwidth
.full
= dfixed_mul(bandwidth
, disp_clk_request_efficiency
);
915 return dfixed_trunc(bandwidth
);
918 static u32
evergreen_available_bandwidth(struct evergreen_wm_params
*wm
)
920 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
921 u32 dram_bandwidth
= evergreen_dram_bandwidth(wm
);
922 u32 data_return_bandwidth
= evergreen_data_return_bandwidth(wm
);
923 u32 dmif_req_bandwidth
= evergreen_dmif_request_bandwidth(wm
);
925 return min(dram_bandwidth
, min(data_return_bandwidth
, dmif_req_bandwidth
));
928 static u32
evergreen_average_bandwidth(struct evergreen_wm_params
*wm
)
930 /* Calculate the display mode Average Bandwidth
931 * DisplayMode should contain the source and destination dimensions,
935 fixed20_12 line_time
;
936 fixed20_12 src_width
;
937 fixed20_12 bandwidth
;
940 a
.full
= dfixed_const(1000);
941 line_time
.full
= dfixed_const(wm
->active_time
+ wm
->blank_time
);
942 line_time
.full
= dfixed_div(line_time
, a
);
943 bpp
.full
= dfixed_const(wm
->bytes_per_pixel
);
944 src_width
.full
= dfixed_const(wm
->src_width
);
945 bandwidth
.full
= dfixed_mul(src_width
, bpp
);
946 bandwidth
.full
= dfixed_mul(bandwidth
, wm
->vsc
);
947 bandwidth
.full
= dfixed_div(bandwidth
, line_time
);
949 return dfixed_trunc(bandwidth
);
952 static u32
evergreen_latency_watermark(struct evergreen_wm_params
*wm
)
954 /* First calcualte the latency in ns */
955 u32 mc_latency
= 2000; /* 2000 ns. */
956 u32 available_bandwidth
= evergreen_available_bandwidth(wm
);
957 u32 worst_chunk_return_time
= (512 * 8 * 1000) / available_bandwidth
;
958 u32 cursor_line_pair_return_time
= (128 * 4 * 1000) / available_bandwidth
;
959 u32 dc_latency
= 40000000 / wm
->disp_clk
; /* dc pipe latency */
960 u32 other_heads_data_return_time
= ((wm
->num_heads
+ 1) * worst_chunk_return_time
) +
961 (wm
->num_heads
* cursor_line_pair_return_time
);
962 u32 latency
= mc_latency
+ other_heads_data_return_time
+ dc_latency
;
963 u32 max_src_lines_per_dst_line
, lb_fill_bw
, line_fill_time
;
966 if (wm
->num_heads
== 0)
969 a
.full
= dfixed_const(2);
970 b
.full
= dfixed_const(1);
971 if ((wm
->vsc
.full
> a
.full
) ||
972 ((wm
->vsc
.full
> b
.full
) && (wm
->vtaps
>= 3)) ||
974 ((wm
->vsc
.full
>= a
.full
) && wm
->interlaced
))
975 max_src_lines_per_dst_line
= 4;
977 max_src_lines_per_dst_line
= 2;
979 a
.full
= dfixed_const(available_bandwidth
);
980 b
.full
= dfixed_const(wm
->num_heads
);
981 a
.full
= dfixed_div(a
, b
);
983 b
.full
= dfixed_const(1000);
984 c
.full
= dfixed_const(wm
->disp_clk
);
985 b
.full
= dfixed_div(c
, b
);
986 c
.full
= dfixed_const(wm
->bytes_per_pixel
);
987 b
.full
= dfixed_mul(b
, c
);
989 lb_fill_bw
= min(dfixed_trunc(a
), dfixed_trunc(b
));
991 a
.full
= dfixed_const(max_src_lines_per_dst_line
* wm
->src_width
* wm
->bytes_per_pixel
);
992 b
.full
= dfixed_const(1000);
993 c
.full
= dfixed_const(lb_fill_bw
);
994 b
.full
= dfixed_div(c
, b
);
995 a
.full
= dfixed_div(a
, b
);
996 line_fill_time
= dfixed_trunc(a
);
998 if (line_fill_time
< wm
->active_time
)
1001 return latency
+ (line_fill_time
- wm
->active_time
);
1005 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params
*wm
)
1007 if (evergreen_average_bandwidth(wm
) <=
1008 (evergreen_dram_bandwidth_for_display(wm
) / wm
->num_heads
))
1014 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params
*wm
)
1016 if (evergreen_average_bandwidth(wm
) <=
1017 (evergreen_available_bandwidth(wm
) / wm
->num_heads
))
1023 static bool evergreen_check_latency_hiding(struct evergreen_wm_params
*wm
)
1025 u32 lb_partitions
= wm
->lb_size
/ wm
->src_width
;
1026 u32 line_time
= wm
->active_time
+ wm
->blank_time
;
1027 u32 latency_tolerant_lines
;
1031 a
.full
= dfixed_const(1);
1032 if (wm
->vsc
.full
> a
.full
)
1033 latency_tolerant_lines
= 1;
1035 if (lb_partitions
<= (wm
->vtaps
+ 1))
1036 latency_tolerant_lines
= 1;
1038 latency_tolerant_lines
= 2;
1041 latency_hiding
= (latency_tolerant_lines
* line_time
+ wm
->blank_time
);
1043 if (evergreen_latency_watermark(wm
) <= latency_hiding
)
1049 static void evergreen_program_watermarks(struct radeon_device
*rdev
,
1050 struct radeon_crtc
*radeon_crtc
,
1051 u32 lb_size
, u32 num_heads
)
1053 struct drm_display_mode
*mode
= &radeon_crtc
->base
.mode
;
1054 struct evergreen_wm_params wm
;
1057 u32 latency_watermark_a
= 0, latency_watermark_b
= 0;
1058 u32 priority_a_mark
= 0, priority_b_mark
= 0;
1059 u32 priority_a_cnt
= PRIORITY_OFF
;
1060 u32 priority_b_cnt
= PRIORITY_OFF
;
1061 u32 pipe_offset
= radeon_crtc
->crtc_id
* 16;
1062 u32 tmp
, arb_control3
;
1065 if (radeon_crtc
->base
.enabled
&& num_heads
&& mode
) {
1066 pixel_period
= 1000000 / (u32
)mode
->clock
;
1067 line_time
= min((u32
)mode
->crtc_htotal
* pixel_period
, (u32
)65535);
1071 wm
.yclk
= rdev
->pm
.current_mclk
* 10;
1072 wm
.sclk
= rdev
->pm
.current_sclk
* 10;
1073 wm
.disp_clk
= mode
->clock
;
1074 wm
.src_width
= mode
->crtc_hdisplay
;
1075 wm
.active_time
= mode
->crtc_hdisplay
* pixel_period
;
1076 wm
.blank_time
= line_time
- wm
.active_time
;
1077 wm
.interlaced
= false;
1078 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1079 wm
.interlaced
= true;
1080 wm
.vsc
= radeon_crtc
->vsc
;
1082 if (radeon_crtc
->rmx_type
!= RMX_OFF
)
1084 wm
.bytes_per_pixel
= 4; /* XXX: get this from fb config */
1085 wm
.lb_size
= lb_size
;
1086 wm
.dram_channels
= evergreen_get_number_of_dram_channels(rdev
);
1087 wm
.num_heads
= num_heads
;
1089 /* set for high clocks */
1090 latency_watermark_a
= min(evergreen_latency_watermark(&wm
), (u32
)65535);
1091 /* set for low clocks */
1092 /* wm.yclk = low clk; wm.sclk = low clk */
1093 latency_watermark_b
= min(evergreen_latency_watermark(&wm
), (u32
)65535);
1095 /* possibly force display priority to high */
1096 /* should really do this at mode validation time... */
1097 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm
) ||
1098 !evergreen_average_bandwidth_vs_available_bandwidth(&wm
) ||
1099 !evergreen_check_latency_hiding(&wm
) ||
1100 (rdev
->disp_priority
== 2)) {
1101 DRM_DEBUG_KMS("force priority to high\n");
1102 priority_a_cnt
|= PRIORITY_ALWAYS_ON
;
1103 priority_b_cnt
|= PRIORITY_ALWAYS_ON
;
1106 a
.full
= dfixed_const(1000);
1107 b
.full
= dfixed_const(mode
->clock
);
1108 b
.full
= dfixed_div(b
, a
);
1109 c
.full
= dfixed_const(latency_watermark_a
);
1110 c
.full
= dfixed_mul(c
, b
);
1111 c
.full
= dfixed_mul(c
, radeon_crtc
->hsc
);
1112 c
.full
= dfixed_div(c
, a
);
1113 a
.full
= dfixed_const(16);
1114 c
.full
= dfixed_div(c
, a
);
1115 priority_a_mark
= dfixed_trunc(c
);
1116 priority_a_cnt
|= priority_a_mark
& PRIORITY_MARK_MASK
;
1118 a
.full
= dfixed_const(1000);
1119 b
.full
= dfixed_const(mode
->clock
);
1120 b
.full
= dfixed_div(b
, a
);
1121 c
.full
= dfixed_const(latency_watermark_b
);
1122 c
.full
= dfixed_mul(c
, b
);
1123 c
.full
= dfixed_mul(c
, radeon_crtc
->hsc
);
1124 c
.full
= dfixed_div(c
, a
);
1125 a
.full
= dfixed_const(16);
1126 c
.full
= dfixed_div(c
, a
);
1127 priority_b_mark
= dfixed_trunc(c
);
1128 priority_b_cnt
|= priority_b_mark
& PRIORITY_MARK_MASK
;
1132 arb_control3
= RREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
);
1134 tmp
&= ~LATENCY_WATERMARK_MASK(3);
1135 tmp
|= LATENCY_WATERMARK_MASK(1);
1136 WREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
, tmp
);
1137 WREG32(PIPE0_LATENCY_CONTROL
+ pipe_offset
,
1138 (LATENCY_LOW_WATERMARK(latency_watermark_a
) |
1139 LATENCY_HIGH_WATERMARK(line_time
)));
1141 tmp
= RREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
);
1142 tmp
&= ~LATENCY_WATERMARK_MASK(3);
1143 tmp
|= LATENCY_WATERMARK_MASK(2);
1144 WREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
, tmp
);
1145 WREG32(PIPE0_LATENCY_CONTROL
+ pipe_offset
,
1146 (LATENCY_LOW_WATERMARK(latency_watermark_b
) |
1147 LATENCY_HIGH_WATERMARK(line_time
)));
1148 /* restore original selection */
1149 WREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
, arb_control3
);
1151 /* write the priority marks */
1152 WREG32(PRIORITY_A_CNT
+ radeon_crtc
->crtc_offset
, priority_a_cnt
);
1153 WREG32(PRIORITY_B_CNT
+ radeon_crtc
->crtc_offset
, priority_b_cnt
);
1158 * evergreen_bandwidth_update - update display watermarks callback.
1160 * @rdev: radeon_device pointer
1162 * Update the display watermarks based on the requested mode(s)
1165 void evergreen_bandwidth_update(struct radeon_device
*rdev
)
1167 struct drm_display_mode
*mode0
= NULL
;
1168 struct drm_display_mode
*mode1
= NULL
;
1169 u32 num_heads
= 0, lb_size
;
1172 radeon_update_display_priority(rdev
);
1174 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
1175 if (rdev
->mode_info
.crtcs
[i
]->base
.enabled
)
1178 for (i
= 0; i
< rdev
->num_crtc
; i
+= 2) {
1179 mode0
= &rdev
->mode_info
.crtcs
[i
]->base
.mode
;
1180 mode1
= &rdev
->mode_info
.crtcs
[i
+1]->base
.mode
;
1181 lb_size
= evergreen_line_buffer_adjust(rdev
, rdev
->mode_info
.crtcs
[i
], mode0
, mode1
);
1182 evergreen_program_watermarks(rdev
, rdev
->mode_info
.crtcs
[i
], lb_size
, num_heads
);
1183 lb_size
= evergreen_line_buffer_adjust(rdev
, rdev
->mode_info
.crtcs
[i
+1], mode1
, mode0
);
1184 evergreen_program_watermarks(rdev
, rdev
->mode_info
.crtcs
[i
+1], lb_size
, num_heads
);
1189 * evergreen_mc_wait_for_idle - wait for MC idle callback.
1191 * @rdev: radeon_device pointer
1193 * Wait for the MC (memory controller) to be idle.
1195 * Returns 0 if the MC is idle, -1 if not.
1197 int evergreen_mc_wait_for_idle(struct radeon_device
*rdev
)
1202 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1203 /* read MC_STATUS */
1204 tmp
= RREG32(SRBM_STATUS
) & 0x1F00;
1215 void evergreen_pcie_gart_tlb_flush(struct radeon_device
*rdev
)
1220 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL
, 0x1);
1222 WREG32(VM_CONTEXT0_REQUEST_RESPONSE
, REQUEST_TYPE(1));
1223 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1224 /* read MC_STATUS */
1225 tmp
= RREG32(VM_CONTEXT0_REQUEST_RESPONSE
);
1226 tmp
= (tmp
& RESPONSE_TYPE_MASK
) >> RESPONSE_TYPE_SHIFT
;
1228 printk(KERN_WARNING
"[drm] r600 flush TLB failed\n");
1238 static int evergreen_pcie_gart_enable(struct radeon_device
*rdev
)
1243 if (rdev
->gart
.robj
== NULL
) {
1244 dev_err(rdev
->dev
, "No VRAM object for PCIE GART.\n");
1247 r
= radeon_gart_table_vram_pin(rdev
);
1250 radeon_gart_restore(rdev
);
1251 /* Setup L2 cache */
1252 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
1253 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
1254 EFFECTIVE_L2_QUEUE_SIZE(7));
1255 WREG32(VM_L2_CNTL2
, 0);
1256 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1257 /* Setup TLB control */
1258 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
1259 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
1260 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
|
1261 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1262 if (rdev
->flags
& RADEON_IS_IGP
) {
1263 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL
, tmp
);
1264 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL
, tmp
);
1265 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL
, tmp
);
1267 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
1268 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
1269 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
1270 if ((rdev
->family
== CHIP_JUNIPER
) ||
1271 (rdev
->family
== CHIP_CYPRESS
) ||
1272 (rdev
->family
== CHIP_HEMLOCK
) ||
1273 (rdev
->family
== CHIP_BARTS
))
1274 WREG32(MC_VM_MD_L1_TLB3_CNTL
, tmp
);
1276 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
1277 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
1278 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
1279 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
1280 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR
, rdev
->mc
.gtt_start
>> 12);
1281 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR
, rdev
->mc
.gtt_end
>> 12);
1282 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, rdev
->gart
.table_addr
>> 12);
1283 WREG32(VM_CONTEXT0_CNTL
, ENABLE_CONTEXT
| PAGE_TABLE_DEPTH(0) |
1284 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
);
1285 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
,
1286 (u32
)(rdev
->dummy_page
.addr
>> 12));
1287 WREG32(VM_CONTEXT1_CNTL
, 0);
1289 evergreen_pcie_gart_tlb_flush(rdev
);
1290 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1291 (unsigned)(rdev
->mc
.gtt_size
>> 20),
1292 (unsigned long long)rdev
->gart
.table_addr
);
1293 rdev
->gart
.ready
= true;
1297 static void evergreen_pcie_gart_disable(struct radeon_device
*rdev
)
1301 /* Disable all tables */
1302 WREG32(VM_CONTEXT0_CNTL
, 0);
1303 WREG32(VM_CONTEXT1_CNTL
, 0);
1305 /* Setup L2 cache */
1306 WREG32(VM_L2_CNTL
, ENABLE_L2_FRAGMENT_PROCESSING
|
1307 EFFECTIVE_L2_QUEUE_SIZE(7));
1308 WREG32(VM_L2_CNTL2
, 0);
1309 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1310 /* Setup TLB control */
1311 tmp
= EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1312 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
1313 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
1314 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
1315 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
1316 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
1317 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
1318 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
1319 radeon_gart_table_vram_unpin(rdev
);
1322 static void evergreen_pcie_gart_fini(struct radeon_device
*rdev
)
1324 evergreen_pcie_gart_disable(rdev
);
1325 radeon_gart_table_vram_free(rdev
);
1326 radeon_gart_fini(rdev
);
1330 static void evergreen_agp_enable(struct radeon_device
*rdev
)
1334 /* Setup L2 cache */
1335 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
1336 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
1337 EFFECTIVE_L2_QUEUE_SIZE(7));
1338 WREG32(VM_L2_CNTL2
, 0);
1339 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1340 /* Setup TLB control */
1341 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
1342 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
1343 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
|
1344 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1345 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
1346 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
1347 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
1348 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
1349 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
1350 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
1351 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
1352 WREG32(VM_CONTEXT0_CNTL
, 0);
1353 WREG32(VM_CONTEXT1_CNTL
, 0);
1356 void evergreen_mc_stop(struct radeon_device
*rdev
, struct evergreen_mc_save
*save
)
1358 u32 crtc_enabled
, tmp
, frame_count
, blackout
;
1361 save
->vga_render_control
= RREG32(VGA_RENDER_CONTROL
);
1362 save
->vga_hdp_control
= RREG32(VGA_HDP_CONTROL
);
1364 /* disable VGA render */
1365 WREG32(VGA_RENDER_CONTROL
, 0);
1366 /* blank the display controllers */
1367 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
1368 crtc_enabled
= RREG32(EVERGREEN_CRTC_CONTROL
+ crtc_offsets
[i
]) & EVERGREEN_CRTC_MASTER_EN
;
1370 save
->crtc_enabled
[i
] = true;
1371 if (ASIC_IS_DCE6(rdev
)) {
1372 tmp
= RREG32(EVERGREEN_CRTC_BLANK_CONTROL
+ crtc_offsets
[i
]);
1373 if (!(tmp
& EVERGREEN_CRTC_BLANK_DATA_EN
)) {
1374 radeon_wait_for_vblank(rdev
, i
);
1375 tmp
|= EVERGREEN_CRTC_BLANK_DATA_EN
;
1376 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 1);
1377 WREG32(EVERGREEN_CRTC_BLANK_CONTROL
+ crtc_offsets
[i
], tmp
);
1378 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 0);
1381 tmp
= RREG32(EVERGREEN_CRTC_CONTROL
+ crtc_offsets
[i
]);
1382 if (!(tmp
& EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE
)) {
1383 radeon_wait_for_vblank(rdev
, i
);
1384 tmp
|= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE
;
1385 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 1);
1386 WREG32(EVERGREEN_CRTC_CONTROL
+ crtc_offsets
[i
], tmp
);
1387 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 0);
1390 /* wait for the next frame */
1391 frame_count
= radeon_get_vblank_counter(rdev
, i
);
1392 for (j
= 0; j
< rdev
->usec_timeout
; j
++) {
1393 if (radeon_get_vblank_counter(rdev
, i
) != frame_count
)
1398 save
->crtc_enabled
[i
] = false;
1402 radeon_mc_wait_for_idle(rdev
);
1404 blackout
= RREG32(MC_SHARED_BLACKOUT_CNTL
);
1405 if ((blackout
& BLACKOUT_MODE_MASK
) != 1) {
1406 /* Block CPU access */
1407 WREG32(BIF_FB_EN
, 0);
1408 /* blackout the MC */
1409 blackout
&= ~BLACKOUT_MODE_MASK
;
1410 WREG32(MC_SHARED_BLACKOUT_CNTL
, blackout
| 1);
1412 /* wait for the MC to settle */
1416 void evergreen_mc_resume(struct radeon_device
*rdev
, struct evergreen_mc_save
*save
)
1418 u32 tmp
, frame_count
;
1421 /* update crtc base addresses */
1422 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
1423 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ crtc_offsets
[i
],
1424 upper_32_bits(rdev
->mc
.vram_start
));
1425 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ crtc_offsets
[i
],
1426 upper_32_bits(rdev
->mc
.vram_start
));
1427 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ crtc_offsets
[i
],
1428 (u32
)rdev
->mc
.vram_start
);
1429 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ crtc_offsets
[i
],
1430 (u32
)rdev
->mc
.vram_start
);
1432 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH
, upper_32_bits(rdev
->mc
.vram_start
));
1433 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS
, (u32
)rdev
->mc
.vram_start
);
1435 /* unblackout the MC */
1436 tmp
= RREG32(MC_SHARED_BLACKOUT_CNTL
);
1437 tmp
&= ~BLACKOUT_MODE_MASK
;
1438 WREG32(MC_SHARED_BLACKOUT_CNTL
, tmp
);
1439 /* allow CPU access */
1440 WREG32(BIF_FB_EN
, FB_READ_EN
| FB_WRITE_EN
);
1442 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
1443 if (save
->crtc_enabled
[i
]) {
1444 if (ASIC_IS_DCE6(rdev
)) {
1445 tmp
= RREG32(EVERGREEN_CRTC_BLANK_CONTROL
+ crtc_offsets
[i
]);
1446 tmp
|= EVERGREEN_CRTC_BLANK_DATA_EN
;
1447 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 1);
1448 WREG32(EVERGREEN_CRTC_BLANK_CONTROL
+ crtc_offsets
[i
], tmp
);
1449 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 0);
1451 tmp
= RREG32(EVERGREEN_CRTC_CONTROL
+ crtc_offsets
[i
]);
1452 tmp
&= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE
;
1453 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 1);
1454 WREG32(EVERGREEN_CRTC_CONTROL
+ crtc_offsets
[i
], tmp
);
1455 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 0);
1457 /* wait for the next frame */
1458 frame_count
= radeon_get_vblank_counter(rdev
, i
);
1459 for (j
= 0; j
< rdev
->usec_timeout
; j
++) {
1460 if (radeon_get_vblank_counter(rdev
, i
) != frame_count
)
1466 /* Unlock vga access */
1467 WREG32(VGA_HDP_CONTROL
, save
->vga_hdp_control
);
1469 WREG32(VGA_RENDER_CONTROL
, save
->vga_render_control
);
1472 void evergreen_mc_program(struct radeon_device
*rdev
)
1474 struct evergreen_mc_save save
;
1478 /* Initialize HDP */
1479 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
1480 WREG32((0x2c14 + j
), 0x00000000);
1481 WREG32((0x2c18 + j
), 0x00000000);
1482 WREG32((0x2c1c + j
), 0x00000000);
1483 WREG32((0x2c20 + j
), 0x00000000);
1484 WREG32((0x2c24 + j
), 0x00000000);
1486 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL
, 0);
1488 evergreen_mc_stop(rdev
, &save
);
1489 if (evergreen_mc_wait_for_idle(rdev
)) {
1490 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1492 /* Lockout access through VGA aperture*/
1493 WREG32(VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
);
1494 /* Update configuration */
1495 if (rdev
->flags
& RADEON_IS_AGP
) {
1496 if (rdev
->mc
.vram_start
< rdev
->mc
.gtt_start
) {
1497 /* VRAM before AGP */
1498 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
1499 rdev
->mc
.vram_start
>> 12);
1500 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
1501 rdev
->mc
.gtt_end
>> 12);
1503 /* VRAM after AGP */
1504 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
1505 rdev
->mc
.gtt_start
>> 12);
1506 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
1507 rdev
->mc
.vram_end
>> 12);
1510 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
1511 rdev
->mc
.vram_start
>> 12);
1512 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
1513 rdev
->mc
.vram_end
>> 12);
1515 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
, rdev
->vram_scratch
.gpu_addr
>> 12);
1516 /* llano/ontario only */
1517 if ((rdev
->family
== CHIP_PALM
) ||
1518 (rdev
->family
== CHIP_SUMO
) ||
1519 (rdev
->family
== CHIP_SUMO2
)) {
1520 tmp
= RREG32(MC_FUS_VM_FB_OFFSET
) & 0x000FFFFF;
1521 tmp
|= ((rdev
->mc
.vram_end
>> 20) & 0xF) << 24;
1522 tmp
|= ((rdev
->mc
.vram_start
>> 20) & 0xF) << 20;
1523 WREG32(MC_FUS_VM_FB_OFFSET
, tmp
);
1525 tmp
= ((rdev
->mc
.vram_end
>> 24) & 0xFFFF) << 16;
1526 tmp
|= ((rdev
->mc
.vram_start
>> 24) & 0xFFFF);
1527 WREG32(MC_VM_FB_LOCATION
, tmp
);
1528 WREG32(HDP_NONSURFACE_BASE
, (rdev
->mc
.vram_start
>> 8));
1529 WREG32(HDP_NONSURFACE_INFO
, (2 << 7) | (1 << 30));
1530 WREG32(HDP_NONSURFACE_SIZE
, 0x3FFFFFFF);
1531 if (rdev
->flags
& RADEON_IS_AGP
) {
1532 WREG32(MC_VM_AGP_TOP
, rdev
->mc
.gtt_end
>> 16);
1533 WREG32(MC_VM_AGP_BOT
, rdev
->mc
.gtt_start
>> 16);
1534 WREG32(MC_VM_AGP_BASE
, rdev
->mc
.agp_base
>> 22);
1536 WREG32(MC_VM_AGP_BASE
, 0);
1537 WREG32(MC_VM_AGP_TOP
, 0x0FFFFFFF);
1538 WREG32(MC_VM_AGP_BOT
, 0x0FFFFFFF);
1540 if (evergreen_mc_wait_for_idle(rdev
)) {
1541 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1543 evergreen_mc_resume(rdev
, &save
);
1544 /* we need to own VRAM, so turn off the VGA renderer here
1545 * to stop it overwriting our objects */
1546 rv515_vga_render_disable(rdev
);
1552 void evergreen_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
1554 struct radeon_ring
*ring
= &rdev
->ring
[ib
->ring
];
1557 /* set to DX10/11 mode */
1558 radeon_ring_write(ring
, PACKET3(PACKET3_MODE_CONTROL
, 0));
1559 radeon_ring_write(ring
, 1);
1561 if (ring
->rptr_save_reg
) {
1562 next_rptr
= ring
->wptr
+ 3 + 4;
1563 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
1564 radeon_ring_write(ring
, ((ring
->rptr_save_reg
-
1565 PACKET3_SET_CONFIG_REG_START
) >> 2));
1566 radeon_ring_write(ring
, next_rptr
);
1567 } else if (rdev
->wb
.enabled
) {
1568 next_rptr
= ring
->wptr
+ 5 + 4;
1569 radeon_ring_write(ring
, PACKET3(PACKET3_MEM_WRITE
, 3));
1570 radeon_ring_write(ring
, ring
->next_rptr_gpu_addr
& 0xfffffffc);
1571 radeon_ring_write(ring
, (upper_32_bits(ring
->next_rptr_gpu_addr
) & 0xff) | (1 << 18));
1572 radeon_ring_write(ring
, next_rptr
);
1573 radeon_ring_write(ring
, 0);
1576 radeon_ring_write(ring
, PACKET3(PACKET3_INDIRECT_BUFFER
, 2));
1577 radeon_ring_write(ring
,
1581 (ib
->gpu_addr
& 0xFFFFFFFC));
1582 radeon_ring_write(ring
, upper_32_bits(ib
->gpu_addr
) & 0xFF);
1583 radeon_ring_write(ring
, ib
->length_dw
);
1587 static int evergreen_cp_load_microcode(struct radeon_device
*rdev
)
1589 const __be32
*fw_data
;
1592 if (!rdev
->me_fw
|| !rdev
->pfp_fw
)
1600 RB_NO_UPDATE
| RB_BLKSZ(15) | RB_BUFSZ(3));
1602 fw_data
= (const __be32
*)rdev
->pfp_fw
->data
;
1603 WREG32(CP_PFP_UCODE_ADDR
, 0);
1604 for (i
= 0; i
< EVERGREEN_PFP_UCODE_SIZE
; i
++)
1605 WREG32(CP_PFP_UCODE_DATA
, be32_to_cpup(fw_data
++));
1606 WREG32(CP_PFP_UCODE_ADDR
, 0);
1608 fw_data
= (const __be32
*)rdev
->me_fw
->data
;
1609 WREG32(CP_ME_RAM_WADDR
, 0);
1610 for (i
= 0; i
< EVERGREEN_PM4_UCODE_SIZE
; i
++)
1611 WREG32(CP_ME_RAM_DATA
, be32_to_cpup(fw_data
++));
1613 WREG32(CP_PFP_UCODE_ADDR
, 0);
1614 WREG32(CP_ME_RAM_WADDR
, 0);
1615 WREG32(CP_ME_RAM_RADDR
, 0);
1619 static int evergreen_cp_start(struct radeon_device
*rdev
)
1621 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
1625 r
= radeon_ring_lock(rdev
, ring
, 7);
1627 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
1630 radeon_ring_write(ring
, PACKET3(PACKET3_ME_INITIALIZE
, 5));
1631 radeon_ring_write(ring
, 0x1);
1632 radeon_ring_write(ring
, 0x0);
1633 radeon_ring_write(ring
, rdev
->config
.evergreen
.max_hw_contexts
- 1);
1634 radeon_ring_write(ring
, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1635 radeon_ring_write(ring
, 0);
1636 radeon_ring_write(ring
, 0);
1637 radeon_ring_unlock_commit(rdev
, ring
);
1640 WREG32(CP_ME_CNTL
, cp_me
);
1642 r
= radeon_ring_lock(rdev
, ring
, evergreen_default_size
+ 19);
1644 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
1648 /* setup clear context state */
1649 radeon_ring_write(ring
, PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
1650 radeon_ring_write(ring
, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE
);
1652 for (i
= 0; i
< evergreen_default_size
; i
++)
1653 radeon_ring_write(ring
, evergreen_default_state
[i
]);
1655 radeon_ring_write(ring
, PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
1656 radeon_ring_write(ring
, PACKET3_PREAMBLE_END_CLEAR_STATE
);
1658 /* set clear context state */
1659 radeon_ring_write(ring
, PACKET3(PACKET3_CLEAR_STATE
, 0));
1660 radeon_ring_write(ring
, 0);
1662 /* SQ_VTX_BASE_VTX_LOC */
1663 radeon_ring_write(ring
, 0xc0026f00);
1664 radeon_ring_write(ring
, 0x00000000);
1665 radeon_ring_write(ring
, 0x00000000);
1666 radeon_ring_write(ring
, 0x00000000);
1669 radeon_ring_write(ring
, 0xc0036f00);
1670 radeon_ring_write(ring
, 0x00000bc4);
1671 radeon_ring_write(ring
, 0xffffffff);
1672 radeon_ring_write(ring
, 0xffffffff);
1673 radeon_ring_write(ring
, 0xffffffff);
1675 radeon_ring_write(ring
, 0xc0026900);
1676 radeon_ring_write(ring
, 0x00000316);
1677 radeon_ring_write(ring
, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1678 radeon_ring_write(ring
, 0x00000010); /* */
1680 radeon_ring_unlock_commit(rdev
, ring
);
1685 static int evergreen_cp_resume(struct radeon_device
*rdev
)
1687 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
1692 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1693 WREG32(GRBM_SOFT_RESET
, (SOFT_RESET_CP
|
1699 RREG32(GRBM_SOFT_RESET
);
1701 WREG32(GRBM_SOFT_RESET
, 0);
1702 RREG32(GRBM_SOFT_RESET
);
1704 /* Set ring buffer size */
1705 rb_bufsz
= drm_order(ring
->ring_size
/ 8);
1706 tmp
= (drm_order(RADEON_GPU_PAGE_SIZE
/8) << 8) | rb_bufsz
;
1708 tmp
|= BUF_SWAP_32BIT
;
1710 WREG32(CP_RB_CNTL
, tmp
);
1711 WREG32(CP_SEM_WAIT_TIMER
, 0x0);
1712 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL
, 0x0);
1714 /* Set the write pointer delay */
1715 WREG32(CP_RB_WPTR_DELAY
, 0);
1717 /* Initialize the ring buffer's read and write pointers */
1718 WREG32(CP_RB_CNTL
, tmp
| RB_RPTR_WR_ENA
);
1719 WREG32(CP_RB_RPTR_WR
, 0);
1721 WREG32(CP_RB_WPTR
, ring
->wptr
);
1723 /* set the wb address whether it's enabled or not */
1724 WREG32(CP_RB_RPTR_ADDR
,
1725 ((rdev
->wb
.gpu_addr
+ RADEON_WB_CP_RPTR_OFFSET
) & 0xFFFFFFFC));
1726 WREG32(CP_RB_RPTR_ADDR_HI
, upper_32_bits(rdev
->wb
.gpu_addr
+ RADEON_WB_CP_RPTR_OFFSET
) & 0xFF);
1727 WREG32(SCRATCH_ADDR
, ((rdev
->wb
.gpu_addr
+ RADEON_WB_SCRATCH_OFFSET
) >> 8) & 0xFFFFFFFF);
1729 if (rdev
->wb
.enabled
)
1730 WREG32(SCRATCH_UMSK
, 0xff);
1732 tmp
|= RB_NO_UPDATE
;
1733 WREG32(SCRATCH_UMSK
, 0);
1737 WREG32(CP_RB_CNTL
, tmp
);
1739 WREG32(CP_RB_BASE
, ring
->gpu_addr
>> 8);
1740 WREG32(CP_DEBUG
, (1 << 27) | (1 << 28));
1742 ring
->rptr
= RREG32(CP_RB_RPTR
);
1744 evergreen_cp_start(rdev
);
1746 r
= radeon_ring_test(rdev
, RADEON_RING_TYPE_GFX_INDEX
, ring
);
1748 ring
->ready
= false;
1757 static void evergreen_gpu_init(struct radeon_device
*rdev
)
1760 u32 mc_shared_chmap
, mc_arb_ramcfg
;
1764 u32 sq_lds_resource_mgmt
;
1765 u32 sq_gpr_resource_mgmt_1
;
1766 u32 sq_gpr_resource_mgmt_2
;
1767 u32 sq_gpr_resource_mgmt_3
;
1768 u32 sq_thread_resource_mgmt
;
1769 u32 sq_thread_resource_mgmt_2
;
1770 u32 sq_stack_resource_mgmt_1
;
1771 u32 sq_stack_resource_mgmt_2
;
1772 u32 sq_stack_resource_mgmt_3
;
1773 u32 vgt_cache_invalidation
;
1774 u32 hdp_host_path_cntl
, tmp
;
1775 u32 disabled_rb_mask
;
1776 int i
, j
, num_shader_engines
, ps_thread_count
;
1778 switch (rdev
->family
) {
1781 rdev
->config
.evergreen
.num_ses
= 2;
1782 rdev
->config
.evergreen
.max_pipes
= 4;
1783 rdev
->config
.evergreen
.max_tile_pipes
= 8;
1784 rdev
->config
.evergreen
.max_simds
= 10;
1785 rdev
->config
.evergreen
.max_backends
= 4 * rdev
->config
.evergreen
.num_ses
;
1786 rdev
->config
.evergreen
.max_gprs
= 256;
1787 rdev
->config
.evergreen
.max_threads
= 248;
1788 rdev
->config
.evergreen
.max_gs_threads
= 32;
1789 rdev
->config
.evergreen
.max_stack_entries
= 512;
1790 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1791 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1792 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1793 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1794 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1795 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1797 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
1798 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1799 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1800 gb_addr_config
= CYPRESS_GB_ADDR_CONFIG_GOLDEN
;
1803 rdev
->config
.evergreen
.num_ses
= 1;
1804 rdev
->config
.evergreen
.max_pipes
= 4;
1805 rdev
->config
.evergreen
.max_tile_pipes
= 4;
1806 rdev
->config
.evergreen
.max_simds
= 10;
1807 rdev
->config
.evergreen
.max_backends
= 4 * rdev
->config
.evergreen
.num_ses
;
1808 rdev
->config
.evergreen
.max_gprs
= 256;
1809 rdev
->config
.evergreen
.max_threads
= 248;
1810 rdev
->config
.evergreen
.max_gs_threads
= 32;
1811 rdev
->config
.evergreen
.max_stack_entries
= 512;
1812 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1813 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1814 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1815 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1816 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1817 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1819 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
1820 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1821 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1822 gb_addr_config
= JUNIPER_GB_ADDR_CONFIG_GOLDEN
;
1825 rdev
->config
.evergreen
.num_ses
= 1;
1826 rdev
->config
.evergreen
.max_pipes
= 4;
1827 rdev
->config
.evergreen
.max_tile_pipes
= 4;
1828 rdev
->config
.evergreen
.max_simds
= 5;
1829 rdev
->config
.evergreen
.max_backends
= 2 * rdev
->config
.evergreen
.num_ses
;
1830 rdev
->config
.evergreen
.max_gprs
= 256;
1831 rdev
->config
.evergreen
.max_threads
= 248;
1832 rdev
->config
.evergreen
.max_gs_threads
= 32;
1833 rdev
->config
.evergreen
.max_stack_entries
= 256;
1834 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1835 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1836 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1837 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1838 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1839 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1841 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
1842 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1843 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1844 gb_addr_config
= REDWOOD_GB_ADDR_CONFIG_GOLDEN
;
1848 rdev
->config
.evergreen
.num_ses
= 1;
1849 rdev
->config
.evergreen
.max_pipes
= 2;
1850 rdev
->config
.evergreen
.max_tile_pipes
= 2;
1851 rdev
->config
.evergreen
.max_simds
= 2;
1852 rdev
->config
.evergreen
.max_backends
= 1 * rdev
->config
.evergreen
.num_ses
;
1853 rdev
->config
.evergreen
.max_gprs
= 256;
1854 rdev
->config
.evergreen
.max_threads
= 192;
1855 rdev
->config
.evergreen
.max_gs_threads
= 16;
1856 rdev
->config
.evergreen
.max_stack_entries
= 256;
1857 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1858 rdev
->config
.evergreen
.sx_max_export_size
= 128;
1859 rdev
->config
.evergreen
.sx_max_export_pos_size
= 32;
1860 rdev
->config
.evergreen
.sx_max_export_smx_size
= 96;
1861 rdev
->config
.evergreen
.max_hw_contexts
= 4;
1862 rdev
->config
.evergreen
.sq_num_cf_insts
= 1;
1864 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x40;
1865 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1866 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1867 gb_addr_config
= CEDAR_GB_ADDR_CONFIG_GOLDEN
;
1870 rdev
->config
.evergreen
.num_ses
= 1;
1871 rdev
->config
.evergreen
.max_pipes
= 2;
1872 rdev
->config
.evergreen
.max_tile_pipes
= 2;
1873 rdev
->config
.evergreen
.max_simds
= 2;
1874 rdev
->config
.evergreen
.max_backends
= 1 * rdev
->config
.evergreen
.num_ses
;
1875 rdev
->config
.evergreen
.max_gprs
= 256;
1876 rdev
->config
.evergreen
.max_threads
= 192;
1877 rdev
->config
.evergreen
.max_gs_threads
= 16;
1878 rdev
->config
.evergreen
.max_stack_entries
= 256;
1879 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1880 rdev
->config
.evergreen
.sx_max_export_size
= 128;
1881 rdev
->config
.evergreen
.sx_max_export_pos_size
= 32;
1882 rdev
->config
.evergreen
.sx_max_export_smx_size
= 96;
1883 rdev
->config
.evergreen
.max_hw_contexts
= 4;
1884 rdev
->config
.evergreen
.sq_num_cf_insts
= 1;
1886 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x40;
1887 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1888 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1889 gb_addr_config
= CEDAR_GB_ADDR_CONFIG_GOLDEN
;
1892 rdev
->config
.evergreen
.num_ses
= 1;
1893 rdev
->config
.evergreen
.max_pipes
= 4;
1894 rdev
->config
.evergreen
.max_tile_pipes
= 4;
1895 if (rdev
->pdev
->device
== 0x9648)
1896 rdev
->config
.evergreen
.max_simds
= 3;
1897 else if ((rdev
->pdev
->device
== 0x9647) ||
1898 (rdev
->pdev
->device
== 0x964a))
1899 rdev
->config
.evergreen
.max_simds
= 4;
1901 rdev
->config
.evergreen
.max_simds
= 5;
1902 rdev
->config
.evergreen
.max_backends
= 2 * rdev
->config
.evergreen
.num_ses
;
1903 rdev
->config
.evergreen
.max_gprs
= 256;
1904 rdev
->config
.evergreen
.max_threads
= 248;
1905 rdev
->config
.evergreen
.max_gs_threads
= 32;
1906 rdev
->config
.evergreen
.max_stack_entries
= 256;
1907 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1908 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1909 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1910 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1911 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1912 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1914 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x40;
1915 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1916 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1917 gb_addr_config
= SUMO_GB_ADDR_CONFIG_GOLDEN
;
1920 rdev
->config
.evergreen
.num_ses
= 1;
1921 rdev
->config
.evergreen
.max_pipes
= 4;
1922 rdev
->config
.evergreen
.max_tile_pipes
= 4;
1923 rdev
->config
.evergreen
.max_simds
= 2;
1924 rdev
->config
.evergreen
.max_backends
= 1 * rdev
->config
.evergreen
.num_ses
;
1925 rdev
->config
.evergreen
.max_gprs
= 256;
1926 rdev
->config
.evergreen
.max_threads
= 248;
1927 rdev
->config
.evergreen
.max_gs_threads
= 32;
1928 rdev
->config
.evergreen
.max_stack_entries
= 512;
1929 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1930 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1931 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1932 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1933 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1934 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1936 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x40;
1937 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1938 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1939 gb_addr_config
= SUMO2_GB_ADDR_CONFIG_GOLDEN
;
1942 rdev
->config
.evergreen
.num_ses
= 2;
1943 rdev
->config
.evergreen
.max_pipes
= 4;
1944 rdev
->config
.evergreen
.max_tile_pipes
= 8;
1945 rdev
->config
.evergreen
.max_simds
= 7;
1946 rdev
->config
.evergreen
.max_backends
= 4 * rdev
->config
.evergreen
.num_ses
;
1947 rdev
->config
.evergreen
.max_gprs
= 256;
1948 rdev
->config
.evergreen
.max_threads
= 248;
1949 rdev
->config
.evergreen
.max_gs_threads
= 32;
1950 rdev
->config
.evergreen
.max_stack_entries
= 512;
1951 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1952 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1953 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1954 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1955 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1956 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1958 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
1959 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1960 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1961 gb_addr_config
= BARTS_GB_ADDR_CONFIG_GOLDEN
;
1964 rdev
->config
.evergreen
.num_ses
= 1;
1965 rdev
->config
.evergreen
.max_pipes
= 4;
1966 rdev
->config
.evergreen
.max_tile_pipes
= 4;
1967 rdev
->config
.evergreen
.max_simds
= 6;
1968 rdev
->config
.evergreen
.max_backends
= 2 * rdev
->config
.evergreen
.num_ses
;
1969 rdev
->config
.evergreen
.max_gprs
= 256;
1970 rdev
->config
.evergreen
.max_threads
= 248;
1971 rdev
->config
.evergreen
.max_gs_threads
= 32;
1972 rdev
->config
.evergreen
.max_stack_entries
= 256;
1973 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1974 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1975 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1976 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1977 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1978 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1980 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
1981 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1982 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1983 gb_addr_config
= TURKS_GB_ADDR_CONFIG_GOLDEN
;
1986 rdev
->config
.evergreen
.num_ses
= 1;
1987 rdev
->config
.evergreen
.max_pipes
= 2;
1988 rdev
->config
.evergreen
.max_tile_pipes
= 2;
1989 rdev
->config
.evergreen
.max_simds
= 2;
1990 rdev
->config
.evergreen
.max_backends
= 1 * rdev
->config
.evergreen
.num_ses
;
1991 rdev
->config
.evergreen
.max_gprs
= 256;
1992 rdev
->config
.evergreen
.max_threads
= 192;
1993 rdev
->config
.evergreen
.max_gs_threads
= 16;
1994 rdev
->config
.evergreen
.max_stack_entries
= 256;
1995 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1996 rdev
->config
.evergreen
.sx_max_export_size
= 128;
1997 rdev
->config
.evergreen
.sx_max_export_pos_size
= 32;
1998 rdev
->config
.evergreen
.sx_max_export_smx_size
= 96;
1999 rdev
->config
.evergreen
.max_hw_contexts
= 4;
2000 rdev
->config
.evergreen
.sq_num_cf_insts
= 1;
2002 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x40;
2003 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
2004 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
2005 gb_addr_config
= CAICOS_GB_ADDR_CONFIG_GOLDEN
;
2009 /* Initialize HDP */
2010 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
2011 WREG32((0x2c14 + j
), 0x00000000);
2012 WREG32((0x2c18 + j
), 0x00000000);
2013 WREG32((0x2c1c + j
), 0x00000000);
2014 WREG32((0x2c20 + j
), 0x00000000);
2015 WREG32((0x2c24 + j
), 0x00000000);
2018 WREG32(GRBM_CNTL
, GRBM_READ_TIMEOUT(0xff));
2020 evergreen_fix_pci_max_read_req_size(rdev
);
2022 mc_shared_chmap
= RREG32(MC_SHARED_CHMAP
);
2023 if ((rdev
->family
== CHIP_PALM
) ||
2024 (rdev
->family
== CHIP_SUMO
) ||
2025 (rdev
->family
== CHIP_SUMO2
))
2026 mc_arb_ramcfg
= RREG32(FUS_MC_ARB_RAMCFG
);
2028 mc_arb_ramcfg
= RREG32(MC_ARB_RAMCFG
);
2030 /* setup tiling info dword. gb_addr_config is not adequate since it does
2031 * not have bank info, so create a custom tiling dword.
2032 * bits 3:0 num_pipes
2033 * bits 7:4 num_banks
2034 * bits 11:8 group_size
2035 * bits 15:12 row_size
2037 rdev
->config
.evergreen
.tile_config
= 0;
2038 switch (rdev
->config
.evergreen
.max_tile_pipes
) {
2041 rdev
->config
.evergreen
.tile_config
|= (0 << 0);
2044 rdev
->config
.evergreen
.tile_config
|= (1 << 0);
2047 rdev
->config
.evergreen
.tile_config
|= (2 << 0);
2050 rdev
->config
.evergreen
.tile_config
|= (3 << 0);
2053 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
2054 if (rdev
->flags
& RADEON_IS_IGP
)
2055 rdev
->config
.evergreen
.tile_config
|= 1 << 4;
2057 switch ((mc_arb_ramcfg
& NOOFBANK_MASK
) >> NOOFBANK_SHIFT
) {
2058 case 0: /* four banks */
2059 rdev
->config
.evergreen
.tile_config
|= 0 << 4;
2061 case 1: /* eight banks */
2062 rdev
->config
.evergreen
.tile_config
|= 1 << 4;
2064 case 2: /* sixteen banks */
2066 rdev
->config
.evergreen
.tile_config
|= 2 << 4;
2070 rdev
->config
.evergreen
.tile_config
|= 0 << 8;
2071 rdev
->config
.evergreen
.tile_config
|=
2072 ((gb_addr_config
& 0x30000000) >> 28) << 12;
2074 num_shader_engines
= (gb_addr_config
& NUM_SHADER_ENGINES(3) >> 12) + 1;
2076 if ((rdev
->family
>= CHIP_CEDAR
) && (rdev
->family
<= CHIP_HEMLOCK
)) {
2080 WREG32(RCU_IND_INDEX
, 0x204);
2081 efuse_straps_4
= RREG32(RCU_IND_DATA
);
2082 WREG32(RCU_IND_INDEX
, 0x203);
2083 efuse_straps_3
= RREG32(RCU_IND_DATA
);
2084 tmp
= (((efuse_straps_4
& 0xf) << 4) |
2085 ((efuse_straps_3
& 0xf0000000) >> 28));
2088 for (i
= (rdev
->config
.evergreen
.num_ses
- 1); i
>= 0; i
--) {
2089 u32 rb_disable_bitmap
;
2091 WREG32(GRBM_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
| SE_INDEX(i
));
2092 WREG32(RLC_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
| SE_INDEX(i
));
2093 rb_disable_bitmap
= (RREG32(CC_RB_BACKEND_DISABLE
) & 0x00ff0000) >> 16;
2095 tmp
|= rb_disable_bitmap
;
2098 /* enabled rb are just the one not disabled :) */
2099 disabled_rb_mask
= tmp
;
2101 WREG32(GRBM_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
| SE_BROADCAST_WRITES
);
2102 WREG32(RLC_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
| SE_BROADCAST_WRITES
);
2104 WREG32(GB_ADDR_CONFIG
, gb_addr_config
);
2105 WREG32(DMIF_ADDR_CONFIG
, gb_addr_config
);
2106 WREG32(HDP_ADDR_CONFIG
, gb_addr_config
);
2107 WREG32(DMA_TILING_CONFIG
, gb_addr_config
);
2109 if ((rdev
->config
.evergreen
.max_backends
== 1) &&
2110 (rdev
->flags
& RADEON_IS_IGP
)) {
2111 if ((disabled_rb_mask
& 3) == 1) {
2112 /* RB0 disabled, RB1 enabled */
2115 /* RB1 disabled, RB0 enabled */
2119 tmp
= gb_addr_config
& NUM_PIPES_MASK
;
2120 tmp
= r6xx_remap_render_backend(rdev
, tmp
, rdev
->config
.evergreen
.max_backends
,
2121 EVERGREEN_MAX_BACKENDS
, disabled_rb_mask
);
2123 WREG32(GB_BACKEND_MAP
, tmp
);
2125 WREG32(CGTS_SYS_TCC_DISABLE
, 0);
2126 WREG32(CGTS_TCC_DISABLE
, 0);
2127 WREG32(CGTS_USER_SYS_TCC_DISABLE
, 0);
2128 WREG32(CGTS_USER_TCC_DISABLE
, 0);
2130 /* set HW defaults for 3D engine */
2131 WREG32(CP_QUEUE_THRESHOLDS
, (ROQ_IB1_START(0x16) |
2132 ROQ_IB2_START(0x2b)));
2134 WREG32(CP_MEQ_THRESHOLDS
, STQ_SPLIT(0x30));
2136 WREG32(TA_CNTL_AUX
, (DISABLE_CUBE_ANISO
|
2141 sx_debug_1
= RREG32(SX_DEBUG_1
);
2142 sx_debug_1
|= ENABLE_NEW_SMX_ADDRESS
;
2143 WREG32(SX_DEBUG_1
, sx_debug_1
);
2146 smx_dc_ctl0
= RREG32(SMX_DC_CTL0
);
2147 smx_dc_ctl0
&= ~NUMBER_OF_SETS(0x1ff);
2148 smx_dc_ctl0
|= NUMBER_OF_SETS(rdev
->config
.evergreen
.sx_num_of_sets
);
2149 WREG32(SMX_DC_CTL0
, smx_dc_ctl0
);
2151 if (rdev
->family
<= CHIP_SUMO2
)
2152 WREG32(SMX_SAR_CTL0
, 0x00010000);
2154 WREG32(SX_EXPORT_BUFFER_SIZES
, (COLOR_BUFFER_SIZE((rdev
->config
.evergreen
.sx_max_export_size
/ 4) - 1) |
2155 POSITION_BUFFER_SIZE((rdev
->config
.evergreen
.sx_max_export_pos_size
/ 4) - 1) |
2156 SMX_BUFFER_SIZE((rdev
->config
.evergreen
.sx_max_export_smx_size
/ 4) - 1)));
2158 WREG32(PA_SC_FIFO_SIZE
, (SC_PRIM_FIFO_SIZE(rdev
->config
.evergreen
.sc_prim_fifo_size
) |
2159 SC_HIZ_TILE_FIFO_SIZE(rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
) |
2160 SC_EARLYZ_TILE_FIFO_SIZE(rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
)));
2162 WREG32(VGT_NUM_INSTANCES
, 1);
2163 WREG32(SPI_CONFIG_CNTL
, 0);
2164 WREG32(SPI_CONFIG_CNTL_1
, VTX_DONE_DELAY(4));
2165 WREG32(CP_PERFMON_CNTL
, 0);
2167 WREG32(SQ_MS_FIFO_SIZES
, (CACHE_FIFO_SIZE(16 * rdev
->config
.evergreen
.sq_num_cf_insts
) |
2168 FETCH_FIFO_HIWATER(0x4) |
2169 DONE_FIFO_HIWATER(0xe0) |
2170 ALU_UPDATE_FIFO_HIWATER(0x8)));
2172 sq_config
= RREG32(SQ_CONFIG
);
2173 sq_config
&= ~(PS_PRIO(3) |
2177 sq_config
|= (VC_ENABLE
|
2184 switch (rdev
->family
) {
2190 /* no vertex cache */
2191 sq_config
&= ~VC_ENABLE
;
2197 sq_lds_resource_mgmt
= RREG32(SQ_LDS_RESOURCE_MGMT
);
2199 sq_gpr_resource_mgmt_1
= NUM_PS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2))* 12 / 32);
2200 sq_gpr_resource_mgmt_1
|= NUM_VS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 6 / 32);
2201 sq_gpr_resource_mgmt_1
|= NUM_CLAUSE_TEMP_GPRS(4);
2202 sq_gpr_resource_mgmt_2
= NUM_GS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 4 / 32);
2203 sq_gpr_resource_mgmt_2
|= NUM_ES_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 4 / 32);
2204 sq_gpr_resource_mgmt_3
= NUM_HS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 3 / 32);
2205 sq_gpr_resource_mgmt_3
|= NUM_LS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 3 / 32);
2207 switch (rdev
->family
) {
2212 ps_thread_count
= 96;
2215 ps_thread_count
= 128;
2219 sq_thread_resource_mgmt
= NUM_PS_THREADS(ps_thread_count
);
2220 sq_thread_resource_mgmt
|= NUM_VS_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
2221 sq_thread_resource_mgmt
|= NUM_GS_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
2222 sq_thread_resource_mgmt
|= NUM_ES_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
2223 sq_thread_resource_mgmt_2
= NUM_HS_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
2224 sq_thread_resource_mgmt_2
|= NUM_LS_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
2226 sq_stack_resource_mgmt_1
= NUM_PS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2227 sq_stack_resource_mgmt_1
|= NUM_VS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2228 sq_stack_resource_mgmt_2
= NUM_GS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2229 sq_stack_resource_mgmt_2
|= NUM_ES_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2230 sq_stack_resource_mgmt_3
= NUM_HS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2231 sq_stack_resource_mgmt_3
|= NUM_LS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
2233 WREG32(SQ_CONFIG
, sq_config
);
2234 WREG32(SQ_GPR_RESOURCE_MGMT_1
, sq_gpr_resource_mgmt_1
);
2235 WREG32(SQ_GPR_RESOURCE_MGMT_2
, sq_gpr_resource_mgmt_2
);
2236 WREG32(SQ_GPR_RESOURCE_MGMT_3
, sq_gpr_resource_mgmt_3
);
2237 WREG32(SQ_THREAD_RESOURCE_MGMT
, sq_thread_resource_mgmt
);
2238 WREG32(SQ_THREAD_RESOURCE_MGMT_2
, sq_thread_resource_mgmt_2
);
2239 WREG32(SQ_STACK_RESOURCE_MGMT_1
, sq_stack_resource_mgmt_1
);
2240 WREG32(SQ_STACK_RESOURCE_MGMT_2
, sq_stack_resource_mgmt_2
);
2241 WREG32(SQ_STACK_RESOURCE_MGMT_3
, sq_stack_resource_mgmt_3
);
2242 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0);
2243 WREG32(SQ_LDS_RESOURCE_MGMT
, sq_lds_resource_mgmt
);
2245 WREG32(PA_SC_FORCE_EOV_MAX_CNTS
, (FORCE_EOV_MAX_CLK_CNT(4095) |
2246 FORCE_EOV_MAX_REZ_CNT(255)));
2248 switch (rdev
->family
) {
2254 vgt_cache_invalidation
= CACHE_INVALIDATION(TC_ONLY
);
2257 vgt_cache_invalidation
= CACHE_INVALIDATION(VC_AND_TC
);
2260 vgt_cache_invalidation
|= AUTO_INVLD_EN(ES_AND_GS_AUTO
);
2261 WREG32(VGT_CACHE_INVALIDATION
, vgt_cache_invalidation
);
2263 WREG32(VGT_GS_VERTEX_REUSE
, 16);
2264 WREG32(PA_SU_LINE_STIPPLE_VALUE
, 0);
2265 WREG32(PA_SC_LINE_STIPPLE_STATE
, 0);
2267 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
2268 WREG32(VGT_OUT_DEALLOC_CNTL
, 16);
2270 WREG32(CB_PERF_CTR0_SEL_0
, 0);
2271 WREG32(CB_PERF_CTR0_SEL_1
, 0);
2272 WREG32(CB_PERF_CTR1_SEL_0
, 0);
2273 WREG32(CB_PERF_CTR1_SEL_1
, 0);
2274 WREG32(CB_PERF_CTR2_SEL_0
, 0);
2275 WREG32(CB_PERF_CTR2_SEL_1
, 0);
2276 WREG32(CB_PERF_CTR3_SEL_0
, 0);
2277 WREG32(CB_PERF_CTR3_SEL_1
, 0);
2279 /* clear render buffer base addresses */
2280 WREG32(CB_COLOR0_BASE
, 0);
2281 WREG32(CB_COLOR1_BASE
, 0);
2282 WREG32(CB_COLOR2_BASE
, 0);
2283 WREG32(CB_COLOR3_BASE
, 0);
2284 WREG32(CB_COLOR4_BASE
, 0);
2285 WREG32(CB_COLOR5_BASE
, 0);
2286 WREG32(CB_COLOR6_BASE
, 0);
2287 WREG32(CB_COLOR7_BASE
, 0);
2288 WREG32(CB_COLOR8_BASE
, 0);
2289 WREG32(CB_COLOR9_BASE
, 0);
2290 WREG32(CB_COLOR10_BASE
, 0);
2291 WREG32(CB_COLOR11_BASE
, 0);
2293 /* set the shader const cache sizes to 0 */
2294 for (i
= SQ_ALU_CONST_BUFFER_SIZE_PS_0
; i
< 0x28200; i
+= 4)
2296 for (i
= SQ_ALU_CONST_BUFFER_SIZE_HS_0
; i
< 0x29000; i
+= 4)
2299 tmp
= RREG32(HDP_MISC_CNTL
);
2300 tmp
|= HDP_FLUSH_INVALIDATE_CACHE
;
2301 WREG32(HDP_MISC_CNTL
, tmp
);
2303 hdp_host_path_cntl
= RREG32(HDP_HOST_PATH_CNTL
);
2304 WREG32(HDP_HOST_PATH_CNTL
, hdp_host_path_cntl
);
2306 WREG32(PA_CL_ENHANCE
, CLIP_VTX_REORDER_ENA
| NUM_CLIP_SEQ(3));
2312 int evergreen_mc_init(struct radeon_device
*rdev
)
2315 int chansize
, numchan
;
2317 /* Get VRAM informations */
2318 rdev
->mc
.vram_is_ddr
= true;
2319 if ((rdev
->family
== CHIP_PALM
) ||
2320 (rdev
->family
== CHIP_SUMO
) ||
2321 (rdev
->family
== CHIP_SUMO2
))
2322 tmp
= RREG32(FUS_MC_ARB_RAMCFG
);
2324 tmp
= RREG32(MC_ARB_RAMCFG
);
2325 if (tmp
& CHANSIZE_OVERRIDE
) {
2327 } else if (tmp
& CHANSIZE_MASK
) {
2332 tmp
= RREG32(MC_SHARED_CHMAP
);
2333 switch ((tmp
& NOOFCHAN_MASK
) >> NOOFCHAN_SHIFT
) {
2348 rdev
->mc
.vram_width
= numchan
* chansize
;
2349 /* Could aper size report 0 ? */
2350 rdev
->mc
.aper_base
= pci_resource_start(rdev
->pdev
, 0);
2351 rdev
->mc
.aper_size
= pci_resource_len(rdev
->pdev
, 0);
2352 /* Setup GPU memory space */
2353 if ((rdev
->family
== CHIP_PALM
) ||
2354 (rdev
->family
== CHIP_SUMO
) ||
2355 (rdev
->family
== CHIP_SUMO2
)) {
2356 /* size in bytes on fusion */
2357 rdev
->mc
.mc_vram_size
= RREG32(CONFIG_MEMSIZE
);
2358 rdev
->mc
.real_vram_size
= RREG32(CONFIG_MEMSIZE
);
2360 /* size in MB on evergreen/cayman/tn */
2361 rdev
->mc
.mc_vram_size
= RREG32(CONFIG_MEMSIZE
) * 1024 * 1024;
2362 rdev
->mc
.real_vram_size
= RREG32(CONFIG_MEMSIZE
) * 1024 * 1024;
2364 rdev
->mc
.visible_vram_size
= rdev
->mc
.aper_size
;
2365 r700_vram_gtt_location(rdev
, &rdev
->mc
);
2366 radeon_update_bandwidth_info(rdev
);
2371 void evergreen_print_gpu_status_regs(struct radeon_device
*rdev
)
2373 dev_info(rdev
->dev
, " GRBM_STATUS = 0x%08X\n",
2374 RREG32(GRBM_STATUS
));
2375 dev_info(rdev
->dev
, " GRBM_STATUS_SE0 = 0x%08X\n",
2376 RREG32(GRBM_STATUS_SE0
));
2377 dev_info(rdev
->dev
, " GRBM_STATUS_SE1 = 0x%08X\n",
2378 RREG32(GRBM_STATUS_SE1
));
2379 dev_info(rdev
->dev
, " SRBM_STATUS = 0x%08X\n",
2380 RREG32(SRBM_STATUS
));
2381 dev_info(rdev
->dev
, " SRBM_STATUS2 = 0x%08X\n",
2382 RREG32(SRBM_STATUS2
));
2383 dev_info(rdev
->dev
, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2384 RREG32(CP_STALLED_STAT1
));
2385 dev_info(rdev
->dev
, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
2386 RREG32(CP_STALLED_STAT2
));
2387 dev_info(rdev
->dev
, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
2388 RREG32(CP_BUSY_STAT
));
2389 dev_info(rdev
->dev
, " R_008680_CP_STAT = 0x%08X\n",
2391 dev_info(rdev
->dev
, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
2392 RREG32(DMA_STATUS_REG
));
2393 if (rdev
->family
>= CHIP_CAYMAN
) {
2394 dev_info(rdev
->dev
, " R_00D834_DMA_STATUS_REG = 0x%08X\n",
2395 RREG32(DMA_STATUS_REG
+ 0x800));
2399 bool evergreen_is_display_hung(struct radeon_device
*rdev
)
2405 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
2406 if (RREG32(EVERGREEN_CRTC_CONTROL
+ crtc_offsets
[i
]) & EVERGREEN_CRTC_MASTER_EN
) {
2407 crtc_status
[i
] = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT
+ crtc_offsets
[i
]);
2408 crtc_hung
|= (1 << i
);
2412 for (j
= 0; j
< 10; j
++) {
2413 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
2414 if (crtc_hung
& (1 << i
)) {
2415 tmp
= RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT
+ crtc_offsets
[i
]);
2416 if (tmp
!= crtc_status
[i
])
2417 crtc_hung
&= ~(1 << i
);
2428 static u32
evergreen_gpu_check_soft_reset(struct radeon_device
*rdev
)
2434 tmp
= RREG32(GRBM_STATUS
);
2435 if (tmp
& (PA_BUSY
| SC_BUSY
|
2437 TA_BUSY
| VGT_BUSY
|
2439 SPI_BUSY
| VGT_BUSY_NO_DMA
))
2440 reset_mask
|= RADEON_RESET_GFX
;
2442 if (tmp
& (CF_RQ_PENDING
| PF_RQ_PENDING
|
2443 CP_BUSY
| CP_COHERENCY_BUSY
))
2444 reset_mask
|= RADEON_RESET_CP
;
2446 if (tmp
& GRBM_EE_BUSY
)
2447 reset_mask
|= RADEON_RESET_GRBM
| RADEON_RESET_GFX
| RADEON_RESET_CP
;
2449 /* DMA_STATUS_REG */
2450 tmp
= RREG32(DMA_STATUS_REG
);
2451 if (!(tmp
& DMA_IDLE
))
2452 reset_mask
|= RADEON_RESET_DMA
;
2455 tmp
= RREG32(SRBM_STATUS2
);
2457 reset_mask
|= RADEON_RESET_DMA
;
2460 tmp
= RREG32(SRBM_STATUS
);
2461 if (tmp
& (RLC_RQ_PENDING
| RLC_BUSY
))
2462 reset_mask
|= RADEON_RESET_RLC
;
2465 reset_mask
|= RADEON_RESET_IH
;
2468 reset_mask
|= RADEON_RESET_SEM
;
2470 if (tmp
& GRBM_RQ_PENDING
)
2471 reset_mask
|= RADEON_RESET_GRBM
;
2474 reset_mask
|= RADEON_RESET_VMC
;
2476 if (tmp
& (MCB_BUSY
| MCB_NON_DISPLAY_BUSY
|
2477 MCC_BUSY
| MCD_BUSY
))
2478 reset_mask
|= RADEON_RESET_MC
;
2480 if (evergreen_is_display_hung(rdev
))
2481 reset_mask
|= RADEON_RESET_DISPLAY
;
2484 tmp
= RREG32(VM_L2_STATUS
);
2486 reset_mask
|= RADEON_RESET_VMC
;
2488 /* Skip MC reset as it's mostly likely not hung, just busy */
2489 if (reset_mask
& RADEON_RESET_MC
) {
2490 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask
);
2491 reset_mask
&= ~RADEON_RESET_MC
;
2497 static void evergreen_gpu_soft_reset(struct radeon_device
*rdev
, u32 reset_mask
)
2499 struct evergreen_mc_save save
;
2500 u32 grbm_soft_reset
= 0, srbm_soft_reset
= 0;
2503 if (reset_mask
== 0)
2506 dev_info(rdev
->dev
, "GPU softreset: 0x%08X\n", reset_mask
);
2508 evergreen_print_gpu_status_regs(rdev
);
2510 /* Disable CP parsing/prefetching */
2511 WREG32(CP_ME_CNTL
, CP_ME_HALT
| CP_PFP_HALT
);
2513 if (reset_mask
& RADEON_RESET_DMA
) {
2515 tmp
= RREG32(DMA_RB_CNTL
);
2516 tmp
&= ~DMA_RB_ENABLE
;
2517 WREG32(DMA_RB_CNTL
, tmp
);
2522 evergreen_mc_stop(rdev
, &save
);
2523 if (evergreen_mc_wait_for_idle(rdev
)) {
2524 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
2527 if (reset_mask
& (RADEON_RESET_GFX
| RADEON_RESET_COMPUTE
)) {
2528 grbm_soft_reset
|= SOFT_RESET_DB
|
2541 if (reset_mask
& RADEON_RESET_CP
) {
2542 grbm_soft_reset
|= SOFT_RESET_CP
|
2545 srbm_soft_reset
|= SOFT_RESET_GRBM
;
2548 if (reset_mask
& RADEON_RESET_DMA
)
2549 srbm_soft_reset
|= SOFT_RESET_DMA
;
2551 if (reset_mask
& RADEON_RESET_DISPLAY
)
2552 srbm_soft_reset
|= SOFT_RESET_DC
;
2554 if (reset_mask
& RADEON_RESET_RLC
)
2555 srbm_soft_reset
|= SOFT_RESET_RLC
;
2557 if (reset_mask
& RADEON_RESET_SEM
)
2558 srbm_soft_reset
|= SOFT_RESET_SEM
;
2560 if (reset_mask
& RADEON_RESET_IH
)
2561 srbm_soft_reset
|= SOFT_RESET_IH
;
2563 if (reset_mask
& RADEON_RESET_GRBM
)
2564 srbm_soft_reset
|= SOFT_RESET_GRBM
;
2566 if (reset_mask
& RADEON_RESET_VMC
)
2567 srbm_soft_reset
|= SOFT_RESET_VMC
;
2569 if (!(rdev
->flags
& RADEON_IS_IGP
)) {
2570 if (reset_mask
& RADEON_RESET_MC
)
2571 srbm_soft_reset
|= SOFT_RESET_MC
;
2574 if (grbm_soft_reset
) {
2575 tmp
= RREG32(GRBM_SOFT_RESET
);
2576 tmp
|= grbm_soft_reset
;
2577 dev_info(rdev
->dev
, "GRBM_SOFT_RESET=0x%08X\n", tmp
);
2578 WREG32(GRBM_SOFT_RESET
, tmp
);
2579 tmp
= RREG32(GRBM_SOFT_RESET
);
2583 tmp
&= ~grbm_soft_reset
;
2584 WREG32(GRBM_SOFT_RESET
, tmp
);
2585 tmp
= RREG32(GRBM_SOFT_RESET
);
2588 if (srbm_soft_reset
) {
2589 tmp
= RREG32(SRBM_SOFT_RESET
);
2590 tmp
|= srbm_soft_reset
;
2591 dev_info(rdev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
2592 WREG32(SRBM_SOFT_RESET
, tmp
);
2593 tmp
= RREG32(SRBM_SOFT_RESET
);
2597 tmp
&= ~srbm_soft_reset
;
2598 WREG32(SRBM_SOFT_RESET
, tmp
);
2599 tmp
= RREG32(SRBM_SOFT_RESET
);
2602 /* Wait a little for things to settle down */
2605 evergreen_mc_resume(rdev
, &save
);
2608 evergreen_print_gpu_status_regs(rdev
);
2611 int evergreen_asic_reset(struct radeon_device
*rdev
)
2615 reset_mask
= evergreen_gpu_check_soft_reset(rdev
);
2618 r600_set_bios_scratch_engine_hung(rdev
, true);
2620 evergreen_gpu_soft_reset(rdev
, reset_mask
);
2622 reset_mask
= evergreen_gpu_check_soft_reset(rdev
);
2625 r600_set_bios_scratch_engine_hung(rdev
, false);
2631 * evergreen_gfx_is_lockup - Check if the GFX engine is locked up
2633 * @rdev: radeon_device pointer
2634 * @ring: radeon_ring structure holding ring information
2636 * Check if the GFX engine is locked up.
2637 * Returns true if the engine appears to be locked up, false if not.
2639 bool evergreen_gfx_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
2641 u32 reset_mask
= evergreen_gpu_check_soft_reset(rdev
);
2643 if (!(reset_mask
& (RADEON_RESET_GFX
|
2644 RADEON_RESET_COMPUTE
|
2645 RADEON_RESET_CP
))) {
2646 radeon_ring_lockup_update(ring
);
2649 /* force CP activities */
2650 radeon_ring_force_activity(rdev
, ring
);
2651 return radeon_ring_test_lockup(rdev
, ring
);
2655 * evergreen_dma_is_lockup - Check if the DMA engine is locked up
2657 * @rdev: radeon_device pointer
2658 * @ring: radeon_ring structure holding ring information
2660 * Check if the async DMA engine is locked up.
2661 * Returns true if the engine appears to be locked up, false if not.
2663 bool evergreen_dma_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
2665 u32 reset_mask
= evergreen_gpu_check_soft_reset(rdev
);
2667 if (!(reset_mask
& RADEON_RESET_DMA
)) {
2668 radeon_ring_lockup_update(ring
);
2671 /* force ring activities */
2672 radeon_ring_force_activity(rdev
, ring
);
2673 return radeon_ring_test_lockup(rdev
, ring
);
2678 u32
evergreen_get_vblank_counter(struct radeon_device
*rdev
, int crtc
)
2680 if (crtc
>= rdev
->num_crtc
)
2683 return RREG32(CRTC_STATUS_FRAME_COUNT
+ crtc_offsets
[crtc
]);
2686 void evergreen_disable_interrupt_state(struct radeon_device
*rdev
)
2690 if (rdev
->family
>= CHIP_CAYMAN
) {
2691 cayman_cp_int_cntl_setup(rdev
, 0,
2692 CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
);
2693 cayman_cp_int_cntl_setup(rdev
, 1, 0);
2694 cayman_cp_int_cntl_setup(rdev
, 2, 0);
2695 tmp
= RREG32(CAYMAN_DMA1_CNTL
) & ~TRAP_ENABLE
;
2696 WREG32(CAYMAN_DMA1_CNTL
, tmp
);
2698 WREG32(CP_INT_CNTL
, CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
);
2699 tmp
= RREG32(DMA_CNTL
) & ~TRAP_ENABLE
;
2700 WREG32(DMA_CNTL
, tmp
);
2701 WREG32(GRBM_INT_CNTL
, 0);
2702 WREG32(INT_MASK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
2703 WREG32(INT_MASK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
2704 if (rdev
->num_crtc
>= 4) {
2705 WREG32(INT_MASK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
2706 WREG32(INT_MASK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
2708 if (rdev
->num_crtc
>= 6) {
2709 WREG32(INT_MASK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
2710 WREG32(INT_MASK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
2713 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
2714 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
2715 if (rdev
->num_crtc
>= 4) {
2716 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
2717 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
2719 if (rdev
->num_crtc
>= 6) {
2720 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
2721 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
2724 /* only one DAC on DCE6 */
2725 if (!ASIC_IS_DCE6(rdev
))
2726 WREG32(DACA_AUTODETECT_INT_CONTROL
, 0);
2727 WREG32(DACB_AUTODETECT_INT_CONTROL
, 0);
2729 tmp
= RREG32(DC_HPD1_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2730 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
2731 tmp
= RREG32(DC_HPD2_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2732 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
2733 tmp
= RREG32(DC_HPD3_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2734 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
2735 tmp
= RREG32(DC_HPD4_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2736 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
2737 tmp
= RREG32(DC_HPD5_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2738 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
2739 tmp
= RREG32(DC_HPD6_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2740 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
2744 int evergreen_irq_set(struct radeon_device
*rdev
)
2746 u32 cp_int_cntl
= CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
;
2747 u32 cp_int_cntl1
= 0, cp_int_cntl2
= 0;
2748 u32 crtc1
= 0, crtc2
= 0, crtc3
= 0, crtc4
= 0, crtc5
= 0, crtc6
= 0;
2749 u32 hpd1
, hpd2
, hpd3
, hpd4
, hpd5
, hpd6
;
2750 u32 grbm_int_cntl
= 0;
2751 u32 grph1
= 0, grph2
= 0, grph3
= 0, grph4
= 0, grph5
= 0, grph6
= 0;
2752 u32 afmt1
= 0, afmt2
= 0, afmt3
= 0, afmt4
= 0, afmt5
= 0, afmt6
= 0;
2753 u32 dma_cntl
, dma_cntl1
= 0;
2755 if (!rdev
->irq
.installed
) {
2756 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2759 /* don't enable anything if the ih is disabled */
2760 if (!rdev
->ih
.enabled
) {
2761 r600_disable_interrupts(rdev
);
2762 /* force the active interrupt state to all disabled */
2763 evergreen_disable_interrupt_state(rdev
);
2767 hpd1
= RREG32(DC_HPD1_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2768 hpd2
= RREG32(DC_HPD2_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2769 hpd3
= RREG32(DC_HPD3_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2770 hpd4
= RREG32(DC_HPD4_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2771 hpd5
= RREG32(DC_HPD5_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2772 hpd6
= RREG32(DC_HPD6_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2774 afmt1
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
2775 afmt2
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
2776 afmt3
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
2777 afmt4
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
2778 afmt5
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
2779 afmt6
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
2781 dma_cntl
= RREG32(DMA_CNTL
) & ~TRAP_ENABLE
;
2783 if (rdev
->family
>= CHIP_CAYMAN
) {
2784 /* enable CP interrupts on all rings */
2785 if (atomic_read(&rdev
->irq
.ring_int
[RADEON_RING_TYPE_GFX_INDEX
])) {
2786 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2787 cp_int_cntl
|= TIME_STAMP_INT_ENABLE
;
2789 if (atomic_read(&rdev
->irq
.ring_int
[CAYMAN_RING_TYPE_CP1_INDEX
])) {
2790 DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
2791 cp_int_cntl1
|= TIME_STAMP_INT_ENABLE
;
2793 if (atomic_read(&rdev
->irq
.ring_int
[CAYMAN_RING_TYPE_CP2_INDEX
])) {
2794 DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
2795 cp_int_cntl2
|= TIME_STAMP_INT_ENABLE
;
2798 if (atomic_read(&rdev
->irq
.ring_int
[RADEON_RING_TYPE_GFX_INDEX
])) {
2799 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2800 cp_int_cntl
|= RB_INT_ENABLE
;
2801 cp_int_cntl
|= TIME_STAMP_INT_ENABLE
;
2805 if (atomic_read(&rdev
->irq
.ring_int
[R600_RING_TYPE_DMA_INDEX
])) {
2806 DRM_DEBUG("r600_irq_set: sw int dma\n");
2807 dma_cntl
|= TRAP_ENABLE
;
2810 if (rdev
->family
>= CHIP_CAYMAN
) {
2811 dma_cntl1
= RREG32(CAYMAN_DMA1_CNTL
) & ~TRAP_ENABLE
;
2812 if (atomic_read(&rdev
->irq
.ring_int
[CAYMAN_RING_TYPE_DMA1_INDEX
])) {
2813 DRM_DEBUG("r600_irq_set: sw int dma1\n");
2814 dma_cntl1
|= TRAP_ENABLE
;
2818 if (rdev
->irq
.crtc_vblank_int
[0] ||
2819 atomic_read(&rdev
->irq
.pflip
[0])) {
2820 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2821 crtc1
|= VBLANK_INT_MASK
;
2823 if (rdev
->irq
.crtc_vblank_int
[1] ||
2824 atomic_read(&rdev
->irq
.pflip
[1])) {
2825 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2826 crtc2
|= VBLANK_INT_MASK
;
2828 if (rdev
->irq
.crtc_vblank_int
[2] ||
2829 atomic_read(&rdev
->irq
.pflip
[2])) {
2830 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2831 crtc3
|= VBLANK_INT_MASK
;
2833 if (rdev
->irq
.crtc_vblank_int
[3] ||
2834 atomic_read(&rdev
->irq
.pflip
[3])) {
2835 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2836 crtc4
|= VBLANK_INT_MASK
;
2838 if (rdev
->irq
.crtc_vblank_int
[4] ||
2839 atomic_read(&rdev
->irq
.pflip
[4])) {
2840 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2841 crtc5
|= VBLANK_INT_MASK
;
2843 if (rdev
->irq
.crtc_vblank_int
[5] ||
2844 atomic_read(&rdev
->irq
.pflip
[5])) {
2845 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2846 crtc6
|= VBLANK_INT_MASK
;
2848 if (rdev
->irq
.hpd
[0]) {
2849 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2850 hpd1
|= DC_HPDx_INT_EN
;
2852 if (rdev
->irq
.hpd
[1]) {
2853 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2854 hpd2
|= DC_HPDx_INT_EN
;
2856 if (rdev
->irq
.hpd
[2]) {
2857 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2858 hpd3
|= DC_HPDx_INT_EN
;
2860 if (rdev
->irq
.hpd
[3]) {
2861 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2862 hpd4
|= DC_HPDx_INT_EN
;
2864 if (rdev
->irq
.hpd
[4]) {
2865 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2866 hpd5
|= DC_HPDx_INT_EN
;
2868 if (rdev
->irq
.hpd
[5]) {
2869 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2870 hpd6
|= DC_HPDx_INT_EN
;
2872 if (rdev
->irq
.afmt
[0]) {
2873 DRM_DEBUG("evergreen_irq_set: hdmi 0\n");
2874 afmt1
|= AFMT_AZ_FORMAT_WTRIG_MASK
;
2876 if (rdev
->irq
.afmt
[1]) {
2877 DRM_DEBUG("evergreen_irq_set: hdmi 1\n");
2878 afmt2
|= AFMT_AZ_FORMAT_WTRIG_MASK
;
2880 if (rdev
->irq
.afmt
[2]) {
2881 DRM_DEBUG("evergreen_irq_set: hdmi 2\n");
2882 afmt3
|= AFMT_AZ_FORMAT_WTRIG_MASK
;
2884 if (rdev
->irq
.afmt
[3]) {
2885 DRM_DEBUG("evergreen_irq_set: hdmi 3\n");
2886 afmt4
|= AFMT_AZ_FORMAT_WTRIG_MASK
;
2888 if (rdev
->irq
.afmt
[4]) {
2889 DRM_DEBUG("evergreen_irq_set: hdmi 4\n");
2890 afmt5
|= AFMT_AZ_FORMAT_WTRIG_MASK
;
2892 if (rdev
->irq
.afmt
[5]) {
2893 DRM_DEBUG("evergreen_irq_set: hdmi 5\n");
2894 afmt6
|= AFMT_AZ_FORMAT_WTRIG_MASK
;
2897 if (rdev
->family
>= CHIP_CAYMAN
) {
2898 cayman_cp_int_cntl_setup(rdev
, 0, cp_int_cntl
);
2899 cayman_cp_int_cntl_setup(rdev
, 1, cp_int_cntl1
);
2900 cayman_cp_int_cntl_setup(rdev
, 2, cp_int_cntl2
);
2902 WREG32(CP_INT_CNTL
, cp_int_cntl
);
2904 WREG32(DMA_CNTL
, dma_cntl
);
2906 if (rdev
->family
>= CHIP_CAYMAN
)
2907 WREG32(CAYMAN_DMA1_CNTL
, dma_cntl1
);
2909 WREG32(GRBM_INT_CNTL
, grbm_int_cntl
);
2911 WREG32(INT_MASK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, crtc1
);
2912 WREG32(INT_MASK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, crtc2
);
2913 if (rdev
->num_crtc
>= 4) {
2914 WREG32(INT_MASK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, crtc3
);
2915 WREG32(INT_MASK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, crtc4
);
2917 if (rdev
->num_crtc
>= 6) {
2918 WREG32(INT_MASK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, crtc5
);
2919 WREG32(INT_MASK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, crtc6
);
2922 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, grph1
);
2923 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, grph2
);
2924 if (rdev
->num_crtc
>= 4) {
2925 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, grph3
);
2926 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, grph4
);
2928 if (rdev
->num_crtc
>= 6) {
2929 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, grph5
);
2930 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, grph6
);
2933 WREG32(DC_HPD1_INT_CONTROL
, hpd1
);
2934 WREG32(DC_HPD2_INT_CONTROL
, hpd2
);
2935 WREG32(DC_HPD3_INT_CONTROL
, hpd3
);
2936 WREG32(DC_HPD4_INT_CONTROL
, hpd4
);
2937 WREG32(DC_HPD5_INT_CONTROL
, hpd5
);
2938 WREG32(DC_HPD6_INT_CONTROL
, hpd6
);
2940 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, afmt1
);
2941 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, afmt2
);
2942 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, afmt3
);
2943 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, afmt4
);
2944 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, afmt5
);
2945 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, afmt6
);
2950 static void evergreen_irq_ack(struct radeon_device
*rdev
)
2954 rdev
->irq
.stat_regs
.evergreen
.disp_int
= RREG32(DISP_INTERRUPT_STATUS
);
2955 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE
);
2956 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE2
);
2957 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE3
);
2958 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE4
);
2959 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE5
);
2960 rdev
->irq
.stat_regs
.evergreen
.d1grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
);
2961 rdev
->irq
.stat_regs
.evergreen
.d2grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
2962 if (rdev
->num_crtc
>= 4) {
2963 rdev
->irq
.stat_regs
.evergreen
.d3grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
);
2964 rdev
->irq
.stat_regs
.evergreen
.d4grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
2966 if (rdev
->num_crtc
>= 6) {
2967 rdev
->irq
.stat_regs
.evergreen
.d5grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
);
2968 rdev
->irq
.stat_regs
.evergreen
.d6grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
2971 rdev
->irq
.stat_regs
.evergreen
.afmt_status1
= RREG32(AFMT_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
);
2972 rdev
->irq
.stat_regs
.evergreen
.afmt_status2
= RREG32(AFMT_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
2973 rdev
->irq
.stat_regs
.evergreen
.afmt_status3
= RREG32(AFMT_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
);
2974 rdev
->irq
.stat_regs
.evergreen
.afmt_status4
= RREG32(AFMT_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
2975 rdev
->irq
.stat_regs
.evergreen
.afmt_status5
= RREG32(AFMT_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
);
2976 rdev
->irq
.stat_regs
.evergreen
.afmt_status6
= RREG32(AFMT_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
2978 if (rdev
->irq
.stat_regs
.evergreen
.d1grph_int
& GRPH_PFLIP_INT_OCCURRED
)
2979 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
2980 if (rdev
->irq
.stat_regs
.evergreen
.d2grph_int
& GRPH_PFLIP_INT_OCCURRED
)
2981 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
2982 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& LB_D1_VBLANK_INTERRUPT
)
2983 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, VBLANK_ACK
);
2984 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& LB_D1_VLINE_INTERRUPT
)
2985 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, VLINE_ACK
);
2986 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& LB_D2_VBLANK_INTERRUPT
)
2987 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, VBLANK_ACK
);
2988 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& LB_D2_VLINE_INTERRUPT
)
2989 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, VLINE_ACK
);
2991 if (rdev
->num_crtc
>= 4) {
2992 if (rdev
->irq
.stat_regs
.evergreen
.d3grph_int
& GRPH_PFLIP_INT_OCCURRED
)
2993 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
2994 if (rdev
->irq
.stat_regs
.evergreen
.d4grph_int
& GRPH_PFLIP_INT_OCCURRED
)
2995 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
2996 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& LB_D3_VBLANK_INTERRUPT
)
2997 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, VBLANK_ACK
);
2998 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& LB_D3_VLINE_INTERRUPT
)
2999 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, VLINE_ACK
);
3000 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& LB_D4_VBLANK_INTERRUPT
)
3001 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, VBLANK_ACK
);
3002 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& LB_D4_VLINE_INTERRUPT
)
3003 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, VLINE_ACK
);
3006 if (rdev
->num_crtc
>= 6) {
3007 if (rdev
->irq
.stat_regs
.evergreen
.d5grph_int
& GRPH_PFLIP_INT_OCCURRED
)
3008 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
3009 if (rdev
->irq
.stat_regs
.evergreen
.d6grph_int
& GRPH_PFLIP_INT_OCCURRED
)
3010 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
3011 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& LB_D5_VBLANK_INTERRUPT
)
3012 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, VBLANK_ACK
);
3013 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& LB_D5_VLINE_INTERRUPT
)
3014 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, VLINE_ACK
);
3015 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& LB_D6_VBLANK_INTERRUPT
)
3016 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, VBLANK_ACK
);
3017 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& LB_D6_VLINE_INTERRUPT
)
3018 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, VLINE_ACK
);
3021 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& DC_HPD1_INTERRUPT
) {
3022 tmp
= RREG32(DC_HPD1_INT_CONTROL
);
3023 tmp
|= DC_HPDx_INT_ACK
;
3024 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
3026 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& DC_HPD2_INTERRUPT
) {
3027 tmp
= RREG32(DC_HPD2_INT_CONTROL
);
3028 tmp
|= DC_HPDx_INT_ACK
;
3029 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
3031 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& DC_HPD3_INTERRUPT
) {
3032 tmp
= RREG32(DC_HPD3_INT_CONTROL
);
3033 tmp
|= DC_HPDx_INT_ACK
;
3034 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
3036 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& DC_HPD4_INTERRUPT
) {
3037 tmp
= RREG32(DC_HPD4_INT_CONTROL
);
3038 tmp
|= DC_HPDx_INT_ACK
;
3039 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
3041 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& DC_HPD5_INTERRUPT
) {
3042 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
3043 tmp
|= DC_HPDx_INT_ACK
;
3044 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
3046 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& DC_HPD6_INTERRUPT
) {
3047 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
3048 tmp
|= DC_HPDx_INT_ACK
;
3049 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
3051 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status1
& AFMT_AZ_FORMAT_WTRIG
) {
3052 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
);
3053 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
3054 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, tmp
);
3056 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status2
& AFMT_AZ_FORMAT_WTRIG
) {
3057 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
3058 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
3059 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, tmp
);
3061 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status3
& AFMT_AZ_FORMAT_WTRIG
) {
3062 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
);
3063 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
3064 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, tmp
);
3066 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status4
& AFMT_AZ_FORMAT_WTRIG
) {
3067 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
3068 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
3069 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, tmp
);
3071 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status5
& AFMT_AZ_FORMAT_WTRIG
) {
3072 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
);
3073 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
3074 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, tmp
);
3076 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status6
& AFMT_AZ_FORMAT_WTRIG
) {
3077 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
3078 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
3079 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, tmp
);
3083 static void evergreen_irq_disable(struct radeon_device
*rdev
)
3085 r600_disable_interrupts(rdev
);
3086 /* Wait and acknowledge irq */
3088 evergreen_irq_ack(rdev
);
3089 evergreen_disable_interrupt_state(rdev
);
3092 void evergreen_irq_suspend(struct radeon_device
*rdev
)
3094 evergreen_irq_disable(rdev
);
3095 r600_rlc_stop(rdev
);
3098 static u32
evergreen_get_ih_wptr(struct radeon_device
*rdev
)
3102 if (rdev
->wb
.enabled
)
3103 wptr
= le32_to_cpu(rdev
->wb
.wb
[R600_WB_IH_WPTR_OFFSET
/4]);
3105 wptr
= RREG32(IH_RB_WPTR
);
3107 if (wptr
& RB_OVERFLOW
) {
3108 /* When a ring buffer overflow happen start parsing interrupt
3109 * from the last not overwritten vector (wptr + 16). Hopefully
3110 * this should allow us to catchup.
3112 dev_warn(rdev
->dev
, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3113 wptr
, rdev
->ih
.rptr
, (wptr
+ 16) + rdev
->ih
.ptr_mask
);
3114 rdev
->ih
.rptr
= (wptr
+ 16) & rdev
->ih
.ptr_mask
;
3115 tmp
= RREG32(IH_RB_CNTL
);
3116 tmp
|= IH_WPTR_OVERFLOW_CLEAR
;
3117 WREG32(IH_RB_CNTL
, tmp
);
3119 return (wptr
& rdev
->ih
.ptr_mask
);
3122 int evergreen_irq_process(struct radeon_device
*rdev
)
3126 u32 src_id
, src_data
;
3128 bool queue_hotplug
= false;
3129 bool queue_hdmi
= false;
3131 if (!rdev
->ih
.enabled
|| rdev
->shutdown
)
3134 wptr
= evergreen_get_ih_wptr(rdev
);
3137 /* is somebody else already processing irqs? */
3138 if (atomic_xchg(&rdev
->ih
.lock
, 1))
3141 rptr
= rdev
->ih
.rptr
;
3142 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr
, wptr
);
3144 /* Order reading of wptr vs. reading of IH ring data */
3147 /* display interrupts */
3148 evergreen_irq_ack(rdev
);
3150 while (rptr
!= wptr
) {
3151 /* wptr/rptr are in bytes! */
3152 ring_index
= rptr
/ 4;
3153 src_id
= le32_to_cpu(rdev
->ih
.ring
[ring_index
]) & 0xff;
3154 src_data
= le32_to_cpu(rdev
->ih
.ring
[ring_index
+ 1]) & 0xfffffff;
3157 case 1: /* D1 vblank/vline */
3159 case 0: /* D1 vblank */
3160 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& LB_D1_VBLANK_INTERRUPT
) {
3161 if (rdev
->irq
.crtc_vblank_int
[0]) {
3162 drm_handle_vblank(rdev
->ddev
, 0);
3163 rdev
->pm
.vblank_sync
= true;
3164 wake_up(&rdev
->irq
.vblank_queue
);
3166 if (atomic_read(&rdev
->irq
.pflip
[0]))
3167 radeon_crtc_handle_flip(rdev
, 0);
3168 rdev
->irq
.stat_regs
.evergreen
.disp_int
&= ~LB_D1_VBLANK_INTERRUPT
;
3169 DRM_DEBUG("IH: D1 vblank\n");
3172 case 1: /* D1 vline */
3173 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& LB_D1_VLINE_INTERRUPT
) {
3174 rdev
->irq
.stat_regs
.evergreen
.disp_int
&= ~LB_D1_VLINE_INTERRUPT
;
3175 DRM_DEBUG("IH: D1 vline\n");
3179 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3183 case 2: /* D2 vblank/vline */
3185 case 0: /* D2 vblank */
3186 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& LB_D2_VBLANK_INTERRUPT
) {
3187 if (rdev
->irq
.crtc_vblank_int
[1]) {
3188 drm_handle_vblank(rdev
->ddev
, 1);
3189 rdev
->pm
.vblank_sync
= true;
3190 wake_up(&rdev
->irq
.vblank_queue
);
3192 if (atomic_read(&rdev
->irq
.pflip
[1]))
3193 radeon_crtc_handle_flip(rdev
, 1);
3194 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
&= ~LB_D2_VBLANK_INTERRUPT
;
3195 DRM_DEBUG("IH: D2 vblank\n");
3198 case 1: /* D2 vline */
3199 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& LB_D2_VLINE_INTERRUPT
) {
3200 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
&= ~LB_D2_VLINE_INTERRUPT
;
3201 DRM_DEBUG("IH: D2 vline\n");
3205 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3209 case 3: /* D3 vblank/vline */
3211 case 0: /* D3 vblank */
3212 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& LB_D3_VBLANK_INTERRUPT
) {
3213 if (rdev
->irq
.crtc_vblank_int
[2]) {
3214 drm_handle_vblank(rdev
->ddev
, 2);
3215 rdev
->pm
.vblank_sync
= true;
3216 wake_up(&rdev
->irq
.vblank_queue
);
3218 if (atomic_read(&rdev
->irq
.pflip
[2]))
3219 radeon_crtc_handle_flip(rdev
, 2);
3220 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
&= ~LB_D3_VBLANK_INTERRUPT
;
3221 DRM_DEBUG("IH: D3 vblank\n");
3224 case 1: /* D3 vline */
3225 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& LB_D3_VLINE_INTERRUPT
) {
3226 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
&= ~LB_D3_VLINE_INTERRUPT
;
3227 DRM_DEBUG("IH: D3 vline\n");
3231 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3235 case 4: /* D4 vblank/vline */
3237 case 0: /* D4 vblank */
3238 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& LB_D4_VBLANK_INTERRUPT
) {
3239 if (rdev
->irq
.crtc_vblank_int
[3]) {
3240 drm_handle_vblank(rdev
->ddev
, 3);
3241 rdev
->pm
.vblank_sync
= true;
3242 wake_up(&rdev
->irq
.vblank_queue
);
3244 if (atomic_read(&rdev
->irq
.pflip
[3]))
3245 radeon_crtc_handle_flip(rdev
, 3);
3246 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
&= ~LB_D4_VBLANK_INTERRUPT
;
3247 DRM_DEBUG("IH: D4 vblank\n");
3250 case 1: /* D4 vline */
3251 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& LB_D4_VLINE_INTERRUPT
) {
3252 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
&= ~LB_D4_VLINE_INTERRUPT
;
3253 DRM_DEBUG("IH: D4 vline\n");
3257 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3261 case 5: /* D5 vblank/vline */
3263 case 0: /* D5 vblank */
3264 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& LB_D5_VBLANK_INTERRUPT
) {
3265 if (rdev
->irq
.crtc_vblank_int
[4]) {
3266 drm_handle_vblank(rdev
->ddev
, 4);
3267 rdev
->pm
.vblank_sync
= true;
3268 wake_up(&rdev
->irq
.vblank_queue
);
3270 if (atomic_read(&rdev
->irq
.pflip
[4]))
3271 radeon_crtc_handle_flip(rdev
, 4);
3272 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
&= ~LB_D5_VBLANK_INTERRUPT
;
3273 DRM_DEBUG("IH: D5 vblank\n");
3276 case 1: /* D5 vline */
3277 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& LB_D5_VLINE_INTERRUPT
) {
3278 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
&= ~LB_D5_VLINE_INTERRUPT
;
3279 DRM_DEBUG("IH: D5 vline\n");
3283 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3287 case 6: /* D6 vblank/vline */
3289 case 0: /* D6 vblank */
3290 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& LB_D6_VBLANK_INTERRUPT
) {
3291 if (rdev
->irq
.crtc_vblank_int
[5]) {
3292 drm_handle_vblank(rdev
->ddev
, 5);
3293 rdev
->pm
.vblank_sync
= true;
3294 wake_up(&rdev
->irq
.vblank_queue
);
3296 if (atomic_read(&rdev
->irq
.pflip
[5]))
3297 radeon_crtc_handle_flip(rdev
, 5);
3298 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
&= ~LB_D6_VBLANK_INTERRUPT
;
3299 DRM_DEBUG("IH: D6 vblank\n");
3302 case 1: /* D6 vline */
3303 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& LB_D6_VLINE_INTERRUPT
) {
3304 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
&= ~LB_D6_VLINE_INTERRUPT
;
3305 DRM_DEBUG("IH: D6 vline\n");
3309 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3313 case 42: /* HPD hotplug */
3316 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& DC_HPD1_INTERRUPT
) {
3317 rdev
->irq
.stat_regs
.evergreen
.disp_int
&= ~DC_HPD1_INTERRUPT
;
3318 queue_hotplug
= true;
3319 DRM_DEBUG("IH: HPD1\n");
3323 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& DC_HPD2_INTERRUPT
) {
3324 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
&= ~DC_HPD2_INTERRUPT
;
3325 queue_hotplug
= true;
3326 DRM_DEBUG("IH: HPD2\n");
3330 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& DC_HPD3_INTERRUPT
) {
3331 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
&= ~DC_HPD3_INTERRUPT
;
3332 queue_hotplug
= true;
3333 DRM_DEBUG("IH: HPD3\n");
3337 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& DC_HPD4_INTERRUPT
) {
3338 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
&= ~DC_HPD4_INTERRUPT
;
3339 queue_hotplug
= true;
3340 DRM_DEBUG("IH: HPD4\n");
3344 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& DC_HPD5_INTERRUPT
) {
3345 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
&= ~DC_HPD5_INTERRUPT
;
3346 queue_hotplug
= true;
3347 DRM_DEBUG("IH: HPD5\n");
3351 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& DC_HPD6_INTERRUPT
) {
3352 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
&= ~DC_HPD6_INTERRUPT
;
3353 queue_hotplug
= true;
3354 DRM_DEBUG("IH: HPD6\n");
3358 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3365 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status1
& AFMT_AZ_FORMAT_WTRIG
) {
3366 rdev
->irq
.stat_regs
.evergreen
.afmt_status1
&= ~AFMT_AZ_FORMAT_WTRIG
;
3368 DRM_DEBUG("IH: HDMI0\n");
3372 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status2
& AFMT_AZ_FORMAT_WTRIG
) {
3373 rdev
->irq
.stat_regs
.evergreen
.afmt_status2
&= ~AFMT_AZ_FORMAT_WTRIG
;
3375 DRM_DEBUG("IH: HDMI1\n");
3379 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status3
& AFMT_AZ_FORMAT_WTRIG
) {
3380 rdev
->irq
.stat_regs
.evergreen
.afmt_status3
&= ~AFMT_AZ_FORMAT_WTRIG
;
3382 DRM_DEBUG("IH: HDMI2\n");
3386 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status4
& AFMT_AZ_FORMAT_WTRIG
) {
3387 rdev
->irq
.stat_regs
.evergreen
.afmt_status4
&= ~AFMT_AZ_FORMAT_WTRIG
;
3389 DRM_DEBUG("IH: HDMI3\n");
3393 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status5
& AFMT_AZ_FORMAT_WTRIG
) {
3394 rdev
->irq
.stat_regs
.evergreen
.afmt_status5
&= ~AFMT_AZ_FORMAT_WTRIG
;
3396 DRM_DEBUG("IH: HDMI4\n");
3400 if (rdev
->irq
.stat_regs
.evergreen
.afmt_status6
& AFMT_AZ_FORMAT_WTRIG
) {
3401 rdev
->irq
.stat_regs
.evergreen
.afmt_status6
&= ~AFMT_AZ_FORMAT_WTRIG
;
3403 DRM_DEBUG("IH: HDMI5\n");
3407 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3411 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data
);
3412 radeon_fence_process(rdev
, R600_RING_TYPE_UVD_INDEX
);
3416 dev_err(rdev
->dev
, "GPU fault detected: %d 0x%08x\n", src_id
, src_data
);
3417 dev_err(rdev
->dev
, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
3418 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR
));
3419 dev_err(rdev
->dev
, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
3420 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS
));
3421 /* reset addr and status */
3422 WREG32_P(VM_CONTEXT1_CNTL2
, 1, ~1);
3424 case 176: /* CP_INT in ring buffer */
3425 case 177: /* CP_INT in IB1 */
3426 case 178: /* CP_INT in IB2 */
3427 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data
);
3428 radeon_fence_process(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
3430 case 181: /* CP EOP event */
3431 DRM_DEBUG("IH: CP EOP\n");
3432 if (rdev
->family
>= CHIP_CAYMAN
) {
3435 radeon_fence_process(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
3438 radeon_fence_process(rdev
, CAYMAN_RING_TYPE_CP1_INDEX
);
3441 radeon_fence_process(rdev
, CAYMAN_RING_TYPE_CP2_INDEX
);
3445 radeon_fence_process(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
3447 case 224: /* DMA trap event */
3448 DRM_DEBUG("IH: DMA trap\n");
3449 radeon_fence_process(rdev
, R600_RING_TYPE_DMA_INDEX
);
3451 case 233: /* GUI IDLE */
3452 DRM_DEBUG("IH: GUI idle\n");
3454 case 244: /* DMA trap event */
3455 if (rdev
->family
>= CHIP_CAYMAN
) {
3456 DRM_DEBUG("IH: DMA1 trap\n");
3457 radeon_fence_process(rdev
, CAYMAN_RING_TYPE_DMA1_INDEX
);
3461 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3465 /* wptr/rptr are in bytes! */
3467 rptr
&= rdev
->ih
.ptr_mask
;
3470 schedule_work(&rdev
->hotplug_work
);
3472 schedule_work(&rdev
->audio_work
);
3473 rdev
->ih
.rptr
= rptr
;
3474 WREG32(IH_RB_RPTR
, rdev
->ih
.rptr
);
3475 atomic_set(&rdev
->ih
.lock
, 0);
3477 /* make sure wptr hasn't changed while processing */
3478 wptr
= evergreen_get_ih_wptr(rdev
);
3486 * evergreen_dma_fence_ring_emit - emit a fence on the DMA ring
3488 * @rdev: radeon_device pointer
3489 * @fence: radeon fence object
3491 * Add a DMA fence packet to the ring to write
3492 * the fence seq number and DMA trap packet to generate
3493 * an interrupt if needed (evergreen-SI).
3495 void evergreen_dma_fence_ring_emit(struct radeon_device
*rdev
,
3496 struct radeon_fence
*fence
)
3498 struct radeon_ring
*ring
= &rdev
->ring
[fence
->ring
];
3499 u64 addr
= rdev
->fence_drv
[fence
->ring
].gpu_addr
;
3500 /* write the fence */
3501 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_FENCE
, 0, 0));
3502 radeon_ring_write(ring
, addr
& 0xfffffffc);
3503 radeon_ring_write(ring
, (upper_32_bits(addr
) & 0xff));
3504 radeon_ring_write(ring
, fence
->seq
);
3505 /* generate an interrupt */
3506 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_TRAP
, 0, 0));
3508 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_SRBM_WRITE
, 0, 0));
3509 radeon_ring_write(ring
, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL
>> 2));
3510 radeon_ring_write(ring
, 1);
3514 * evergreen_dma_ring_ib_execute - schedule an IB on the DMA engine
3516 * @rdev: radeon_device pointer
3517 * @ib: IB object to schedule
3519 * Schedule an IB in the DMA ring (evergreen).
3521 void evergreen_dma_ring_ib_execute(struct radeon_device
*rdev
,
3522 struct radeon_ib
*ib
)
3524 struct radeon_ring
*ring
= &rdev
->ring
[ib
->ring
];
3526 if (rdev
->wb
.enabled
) {
3527 u32 next_rptr
= ring
->wptr
+ 4;
3528 while ((next_rptr
& 7) != 5)
3531 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_WRITE
, 0, 1));
3532 radeon_ring_write(ring
, ring
->next_rptr_gpu_addr
& 0xfffffffc);
3533 radeon_ring_write(ring
, upper_32_bits(ring
->next_rptr_gpu_addr
) & 0xff);
3534 radeon_ring_write(ring
, next_rptr
);
3537 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
3538 * Pad as necessary with NOPs.
3540 while ((ring
->wptr
& 7) != 5)
3541 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_NOP
, 0, 0));
3542 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER
, 0, 0));
3543 radeon_ring_write(ring
, (ib
->gpu_addr
& 0xFFFFFFE0));
3544 radeon_ring_write(ring
, (ib
->length_dw
<< 12) | (upper_32_bits(ib
->gpu_addr
) & 0xFF));
3549 * evergreen_copy_dma - copy pages using the DMA engine
3551 * @rdev: radeon_device pointer
3552 * @src_offset: src GPU address
3553 * @dst_offset: dst GPU address
3554 * @num_gpu_pages: number of GPU pages to xfer
3555 * @fence: radeon fence object
3557 * Copy GPU paging using the DMA engine (evergreen-cayman).
3558 * Used by the radeon ttm implementation to move pages if
3559 * registered as the asic copy callback.
3561 int evergreen_copy_dma(struct radeon_device
*rdev
,
3562 uint64_t src_offset
, uint64_t dst_offset
,
3563 unsigned num_gpu_pages
,
3564 struct radeon_fence
**fence
)
3566 struct radeon_semaphore
*sem
= NULL
;
3567 int ring_index
= rdev
->asic
->copy
.dma_ring_index
;
3568 struct radeon_ring
*ring
= &rdev
->ring
[ring_index
];
3569 u32 size_in_dw
, cur_size_in_dw
;
3573 r
= radeon_semaphore_create(rdev
, &sem
);
3575 DRM_ERROR("radeon: moving bo (%d).\n", r
);
3579 size_in_dw
= (num_gpu_pages
<< RADEON_GPU_PAGE_SHIFT
) / 4;
3580 num_loops
= DIV_ROUND_UP(size_in_dw
, 0xfffff);
3581 r
= radeon_ring_lock(rdev
, ring
, num_loops
* 5 + 11);
3583 DRM_ERROR("radeon: moving bo (%d).\n", r
);
3584 radeon_semaphore_free(rdev
, &sem
, NULL
);
3588 if (radeon_fence_need_sync(*fence
, ring
->idx
)) {
3589 radeon_semaphore_sync_rings(rdev
, sem
, (*fence
)->ring
,
3591 radeon_fence_note_sync(*fence
, ring
->idx
);
3593 radeon_semaphore_free(rdev
, &sem
, NULL
);
3596 for (i
= 0; i
< num_loops
; i
++) {
3597 cur_size_in_dw
= size_in_dw
;
3598 if (cur_size_in_dw
> 0xFFFFF)
3599 cur_size_in_dw
= 0xFFFFF;
3600 size_in_dw
-= cur_size_in_dw
;
3601 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_COPY
, 0, cur_size_in_dw
));
3602 radeon_ring_write(ring
, dst_offset
& 0xfffffffc);
3603 radeon_ring_write(ring
, src_offset
& 0xfffffffc);
3604 radeon_ring_write(ring
, upper_32_bits(dst_offset
) & 0xff);
3605 radeon_ring_write(ring
, upper_32_bits(src_offset
) & 0xff);
3606 src_offset
+= cur_size_in_dw
* 4;
3607 dst_offset
+= cur_size_in_dw
* 4;
3610 r
= radeon_fence_emit(rdev
, fence
, ring
->idx
);
3612 radeon_ring_unlock_undo(rdev
, ring
);
3616 radeon_ring_unlock_commit(rdev
, ring
);
3617 radeon_semaphore_free(rdev
, &sem
, *fence
);
3622 static int evergreen_startup(struct radeon_device
*rdev
)
3624 struct radeon_ring
*ring
;
3627 /* enable pcie gen2 link */
3628 evergreen_pcie_gen2_enable(rdev
);
3630 if (ASIC_IS_DCE5(rdev
)) {
3631 if (!rdev
->me_fw
|| !rdev
->pfp_fw
|| !rdev
->rlc_fw
|| !rdev
->mc_fw
) {
3632 r
= ni_init_microcode(rdev
);
3634 DRM_ERROR("Failed to load firmware!\n");
3638 r
= ni_mc_load_microcode(rdev
);
3640 DRM_ERROR("Failed to load MC firmware!\n");
3644 if (!rdev
->me_fw
|| !rdev
->pfp_fw
|| !rdev
->rlc_fw
) {
3645 r
= r600_init_microcode(rdev
);
3647 DRM_ERROR("Failed to load firmware!\n");
3653 r
= r600_vram_scratch_init(rdev
);
3657 evergreen_mc_program(rdev
);
3658 if (rdev
->flags
& RADEON_IS_AGP
) {
3659 evergreen_agp_enable(rdev
);
3661 r
= evergreen_pcie_gart_enable(rdev
);
3665 evergreen_gpu_init(rdev
);
3667 r
= evergreen_blit_init(rdev
);
3669 r600_blit_fini(rdev
);
3670 rdev
->asic
->copy
.copy
= NULL
;
3671 dev_warn(rdev
->dev
, "failed blitter (%d) falling back to memcpy\n", r
);
3674 /* allocate wb buffer */
3675 r
= radeon_wb_init(rdev
);
3679 r
= radeon_fence_driver_start_ring(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
3681 dev_err(rdev
->dev
, "failed initializing CP fences (%d).\n", r
);
3685 r
= radeon_fence_driver_start_ring(rdev
, R600_RING_TYPE_DMA_INDEX
);
3687 dev_err(rdev
->dev
, "failed initializing DMA fences (%d).\n", r
);
3691 r
= rv770_uvd_resume(rdev
);
3693 r
= radeon_fence_driver_start_ring(rdev
,
3694 R600_RING_TYPE_UVD_INDEX
);
3696 dev_err(rdev
->dev
, "UVD fences init error (%d).\n", r
);
3700 rdev
->ring
[R600_RING_TYPE_UVD_INDEX
].ring_size
= 0;
3703 r
= r600_irq_init(rdev
);
3705 DRM_ERROR("radeon: IH init failed (%d).\n", r
);
3706 radeon_irq_kms_fini(rdev
);
3709 evergreen_irq_set(rdev
);
3711 ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
3712 r
= radeon_ring_init(rdev
, ring
, ring
->ring_size
, RADEON_WB_CP_RPTR_OFFSET
,
3713 R600_CP_RB_RPTR
, R600_CP_RB_WPTR
,
3714 0, 0xfffff, RADEON_CP_PACKET2
);
3718 ring
= &rdev
->ring
[R600_RING_TYPE_DMA_INDEX
];
3719 r
= radeon_ring_init(rdev
, ring
, ring
->ring_size
, R600_WB_DMA_RPTR_OFFSET
,
3720 DMA_RB_RPTR
, DMA_RB_WPTR
,
3721 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP
, 0, 0));
3725 r
= evergreen_cp_load_microcode(rdev
);
3728 r
= evergreen_cp_resume(rdev
);
3731 r
= r600_dma_resume(rdev
);
3735 ring
= &rdev
->ring
[R600_RING_TYPE_UVD_INDEX
];
3736 if (ring
->ring_size
) {
3737 r
= radeon_ring_init(rdev
, ring
, ring
->ring_size
,
3738 R600_WB_UVD_RPTR_OFFSET
,
3739 UVD_RBC_RB_RPTR
, UVD_RBC_RB_WPTR
,
3740 0, 0xfffff, RADEON_CP_PACKET2
);
3742 r
= r600_uvd_init(rdev
);
3745 DRM_ERROR("radeon: error initializing UVD (%d).\n", r
);
3748 r
= radeon_ib_pool_init(rdev
);
3750 dev_err(rdev
->dev
, "IB initialization failed (%d).\n", r
);
3754 r
= r600_audio_init(rdev
);
3756 DRM_ERROR("radeon: audio init failed\n");
3763 int evergreen_resume(struct radeon_device
*rdev
)
3767 /* reset the asic, the gfx blocks are often in a bad state
3768 * after the driver is unloaded or after a resume
3770 if (radeon_asic_reset(rdev
))
3771 dev_warn(rdev
->dev
, "GPU reset failed !\n");
3772 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3773 * posting will perform necessary task to bring back GPU into good
3777 atom_asic_init(rdev
->mode_info
.atom_context
);
3779 rdev
->accel_working
= true;
3780 r
= evergreen_startup(rdev
);
3782 DRM_ERROR("evergreen startup failed on resume\n");
3783 rdev
->accel_working
= false;
3791 int evergreen_suspend(struct radeon_device
*rdev
)
3793 r600_audio_fini(rdev
);
3794 radeon_uvd_suspend(rdev
);
3796 r600_dma_stop(rdev
);
3797 r600_uvd_rbc_stop(rdev
);
3798 evergreen_irq_suspend(rdev
);
3799 radeon_wb_disable(rdev
);
3800 evergreen_pcie_gart_disable(rdev
);
3805 /* Plan is to move initialization in that function and use
3806 * helper function so that radeon_device_init pretty much
3807 * do nothing more than calling asic specific function. This
3808 * should also allow to remove a bunch of callback function
3811 int evergreen_init(struct radeon_device
*rdev
)
3816 if (!radeon_get_bios(rdev
)) {
3817 if (ASIC_IS_AVIVO(rdev
))
3820 /* Must be an ATOMBIOS */
3821 if (!rdev
->is_atom_bios
) {
3822 dev_err(rdev
->dev
, "Expecting atombios for evergreen GPU\n");
3825 r
= radeon_atombios_init(rdev
);
3828 /* reset the asic, the gfx blocks are often in a bad state
3829 * after the driver is unloaded or after a resume
3831 if (radeon_asic_reset(rdev
))
3832 dev_warn(rdev
->dev
, "GPU reset failed !\n");
3833 /* Post card if necessary */
3834 if (!radeon_card_posted(rdev
)) {
3836 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
3839 DRM_INFO("GPU not posted. posting now...\n");
3840 atom_asic_init(rdev
->mode_info
.atom_context
);
3842 /* Initialize scratch registers */
3843 r600_scratch_init(rdev
);
3844 /* Initialize surface registers */
3845 radeon_surface_init(rdev
);
3846 /* Initialize clocks */
3847 radeon_get_clock_info(rdev
->ddev
);
3849 r
= radeon_fence_driver_init(rdev
);
3852 /* initialize AGP */
3853 if (rdev
->flags
& RADEON_IS_AGP
) {
3854 r
= radeon_agp_init(rdev
);
3856 radeon_agp_disable(rdev
);
3858 /* initialize memory controller */
3859 r
= evergreen_mc_init(rdev
);
3862 /* Memory manager */
3863 r
= radeon_bo_init(rdev
);
3867 r
= radeon_irq_kms_init(rdev
);
3871 rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
].ring_obj
= NULL
;
3872 r600_ring_init(rdev
, &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
], 1024 * 1024);
3874 rdev
->ring
[R600_RING_TYPE_DMA_INDEX
].ring_obj
= NULL
;
3875 r600_ring_init(rdev
, &rdev
->ring
[R600_RING_TYPE_DMA_INDEX
], 64 * 1024);
3877 r
= radeon_uvd_init(rdev
);
3879 rdev
->ring
[R600_RING_TYPE_UVD_INDEX
].ring_obj
= NULL
;
3880 r600_ring_init(rdev
, &rdev
->ring
[R600_RING_TYPE_UVD_INDEX
],
3884 rdev
->ih
.ring_obj
= NULL
;
3885 r600_ih_ring_init(rdev
, 64 * 1024);
3887 r
= r600_pcie_gart_init(rdev
);
3891 rdev
->accel_working
= true;
3892 r
= evergreen_startup(rdev
);
3894 dev_err(rdev
->dev
, "disabling GPU acceleration\n");
3896 r600_dma_fini(rdev
);
3897 r600_irq_fini(rdev
);
3898 radeon_wb_fini(rdev
);
3899 radeon_ib_pool_fini(rdev
);
3900 radeon_irq_kms_fini(rdev
);
3901 evergreen_pcie_gart_fini(rdev
);
3902 rdev
->accel_working
= false;
3905 /* Don't start up if the MC ucode is missing on BTC parts.
3906 * The default clocks and voltages before the MC ucode
3907 * is loaded are not suffient for advanced operations.
3909 if (ASIC_IS_DCE5(rdev
)) {
3910 if (!rdev
->mc_fw
&& !(rdev
->flags
& RADEON_IS_IGP
)) {
3911 DRM_ERROR("radeon: MC ucode required for NI+.\n");
3919 void evergreen_fini(struct radeon_device
*rdev
)
3921 r600_audio_fini(rdev
);
3922 r600_blit_fini(rdev
);
3924 r600_dma_fini(rdev
);
3925 r600_irq_fini(rdev
);
3926 radeon_wb_fini(rdev
);
3927 radeon_ib_pool_fini(rdev
);
3928 radeon_irq_kms_fini(rdev
);
3929 evergreen_pcie_gart_fini(rdev
);
3930 radeon_uvd_fini(rdev
);
3931 r600_vram_scratch_fini(rdev
);
3932 radeon_gem_fini(rdev
);
3933 radeon_fence_driver_fini(rdev
);
3934 radeon_agp_fini(rdev
);
3935 radeon_bo_fini(rdev
);
3936 radeon_atombios_fini(rdev
);
3941 void evergreen_pcie_gen2_enable(struct radeon_device
*rdev
)
3943 u32 link_width_cntl
, speed_cntl
, mask
;
3946 if (radeon_pcie_gen2
== 0)
3949 if (rdev
->flags
& RADEON_IS_IGP
)
3952 if (!(rdev
->flags
& RADEON_IS_PCIE
))
3955 /* x2 cards have a special sequence */
3956 if (ASIC_IS_X2(rdev
))
3959 ret
= drm_pcie_get_speed_cap_mask(rdev
->ddev
, &mask
);
3963 if (!(mask
& DRM_PCIE_SPEED_50
))
3966 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3967 if (speed_cntl
& LC_CURRENT_DATA_RATE
) {
3968 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
3972 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
3974 if ((speed_cntl
& LC_OTHER_SIDE_EVER_SENT_GEN2
) ||
3975 (speed_cntl
& LC_OTHER_SIDE_SUPPORTS_GEN2
)) {
3977 link_width_cntl
= RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
);
3978 link_width_cntl
&= ~LC_UPCONFIGURE_DIS
;
3979 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
3981 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3982 speed_cntl
&= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN
;
3983 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3985 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3986 speed_cntl
|= LC_CLR_FAILED_SPD_CHANGE_CNT
;
3987 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3989 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3990 speed_cntl
&= ~LC_CLR_FAILED_SPD_CHANGE_CNT
;
3991 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3993 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3994 speed_cntl
|= LC_GEN2_EN_STRAP
;
3995 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3998 link_width_cntl
= RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
);
3999 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4001 link_width_cntl
|= LC_UPCONFIGURE_DIS
;
4003 link_width_cntl
&= ~LC_UPCONFIGURE_DIS
;
4004 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);