2 * Copyright 2010 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
29 #include "radeon_asic.h"
30 #include "radeon_drm.h"
31 #include "evergreend.h"
34 #include "evergreen_reg.h"
36 #define EVERGREEN_PFP_UCODE_SIZE 1120
37 #define EVERGREEN_PM4_UCODE_SIZE 1376
39 static void evergreen_gpu_init(struct radeon_device
*rdev
);
40 void evergreen_fini(struct radeon_device
*rdev
);
42 /* get temperature in millidegrees */
43 u32
evergreen_get_temp(struct radeon_device
*rdev
)
45 u32 temp
= (RREG32(CG_MULT_THERMAL_STATUS
) & ASIC_T_MASK
) >>
51 else if ((temp
>> 9) & 1)
54 actual_temp
= (temp
>> 1) & 0xff;
56 return actual_temp
* 1000;
59 void evergreen_pm_misc(struct radeon_device
*rdev
)
61 int req_ps_idx
= rdev
->pm
.requested_power_state_index
;
62 int req_cm_idx
= rdev
->pm
.requested_clock_mode_index
;
63 struct radeon_power_state
*ps
= &rdev
->pm
.power_state
[req_ps_idx
];
64 struct radeon_voltage
*voltage
= &ps
->clock_info
[req_cm_idx
].voltage
;
66 if ((voltage
->type
== VOLTAGE_SW
) && voltage
->voltage
) {
67 if (voltage
->voltage
!= rdev
->pm
.current_vddc
) {
68 radeon_atom_set_voltage(rdev
, voltage
->voltage
);
69 rdev
->pm
.current_vddc
= voltage
->voltage
;
70 DRM_DEBUG("Setting: v: %d\n", voltage
->voltage
);
75 void evergreen_pm_prepare(struct radeon_device
*rdev
)
77 struct drm_device
*ddev
= rdev
->ddev
;
78 struct drm_crtc
*crtc
;
79 struct radeon_crtc
*radeon_crtc
;
82 /* disable any active CRTCs */
83 list_for_each_entry(crtc
, &ddev
->mode_config
.crtc_list
, head
) {
84 radeon_crtc
= to_radeon_crtc(crtc
);
85 if (radeon_crtc
->enabled
) {
86 tmp
= RREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
);
87 tmp
|= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE
;
88 WREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
, tmp
);
93 void evergreen_pm_finish(struct radeon_device
*rdev
)
95 struct drm_device
*ddev
= rdev
->ddev
;
96 struct drm_crtc
*crtc
;
97 struct radeon_crtc
*radeon_crtc
;
100 /* enable any active CRTCs */
101 list_for_each_entry(crtc
, &ddev
->mode_config
.crtc_list
, head
) {
102 radeon_crtc
= to_radeon_crtc(crtc
);
103 if (radeon_crtc
->enabled
) {
104 tmp
= RREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
);
105 tmp
&= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE
;
106 WREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
, tmp
);
111 bool evergreen_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
)
113 bool connected
= false;
117 if (RREG32(DC_HPD1_INT_STATUS
) & DC_HPDx_SENSE
)
121 if (RREG32(DC_HPD2_INT_STATUS
) & DC_HPDx_SENSE
)
125 if (RREG32(DC_HPD3_INT_STATUS
) & DC_HPDx_SENSE
)
129 if (RREG32(DC_HPD4_INT_STATUS
) & DC_HPDx_SENSE
)
133 if (RREG32(DC_HPD5_INT_STATUS
) & DC_HPDx_SENSE
)
137 if (RREG32(DC_HPD6_INT_STATUS
) & DC_HPDx_SENSE
)
147 void evergreen_hpd_set_polarity(struct radeon_device
*rdev
,
148 enum radeon_hpd_id hpd
)
151 bool connected
= evergreen_hpd_sense(rdev
, hpd
);
155 tmp
= RREG32(DC_HPD1_INT_CONTROL
);
157 tmp
&= ~DC_HPDx_INT_POLARITY
;
159 tmp
|= DC_HPDx_INT_POLARITY
;
160 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
163 tmp
= RREG32(DC_HPD2_INT_CONTROL
);
165 tmp
&= ~DC_HPDx_INT_POLARITY
;
167 tmp
|= DC_HPDx_INT_POLARITY
;
168 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
171 tmp
= RREG32(DC_HPD3_INT_CONTROL
);
173 tmp
&= ~DC_HPDx_INT_POLARITY
;
175 tmp
|= DC_HPDx_INT_POLARITY
;
176 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
179 tmp
= RREG32(DC_HPD4_INT_CONTROL
);
181 tmp
&= ~DC_HPDx_INT_POLARITY
;
183 tmp
|= DC_HPDx_INT_POLARITY
;
184 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
187 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
189 tmp
&= ~DC_HPDx_INT_POLARITY
;
191 tmp
|= DC_HPDx_INT_POLARITY
;
192 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
195 tmp
= RREG32(DC_HPD6_INT_CONTROL
);
197 tmp
&= ~DC_HPDx_INT_POLARITY
;
199 tmp
|= DC_HPDx_INT_POLARITY
;
200 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
207 void evergreen_hpd_init(struct radeon_device
*rdev
)
209 struct drm_device
*dev
= rdev
->ddev
;
210 struct drm_connector
*connector
;
211 u32 tmp
= DC_HPDx_CONNECTION_TIMER(0x9c4) |
212 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN
;
214 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
215 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
216 switch (radeon_connector
->hpd
.hpd
) {
218 WREG32(DC_HPD1_CONTROL
, tmp
);
219 rdev
->irq
.hpd
[0] = true;
222 WREG32(DC_HPD2_CONTROL
, tmp
);
223 rdev
->irq
.hpd
[1] = true;
226 WREG32(DC_HPD3_CONTROL
, tmp
);
227 rdev
->irq
.hpd
[2] = true;
230 WREG32(DC_HPD4_CONTROL
, tmp
);
231 rdev
->irq
.hpd
[3] = true;
234 WREG32(DC_HPD5_CONTROL
, tmp
);
235 rdev
->irq
.hpd
[4] = true;
238 WREG32(DC_HPD6_CONTROL
, tmp
);
239 rdev
->irq
.hpd
[5] = true;
245 if (rdev
->irq
.installed
)
246 evergreen_irq_set(rdev
);
249 void evergreen_hpd_fini(struct radeon_device
*rdev
)
251 struct drm_device
*dev
= rdev
->ddev
;
252 struct drm_connector
*connector
;
254 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
255 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
256 switch (radeon_connector
->hpd
.hpd
) {
258 WREG32(DC_HPD1_CONTROL
, 0);
259 rdev
->irq
.hpd
[0] = false;
262 WREG32(DC_HPD2_CONTROL
, 0);
263 rdev
->irq
.hpd
[1] = false;
266 WREG32(DC_HPD3_CONTROL
, 0);
267 rdev
->irq
.hpd
[2] = false;
270 WREG32(DC_HPD4_CONTROL
, 0);
271 rdev
->irq
.hpd
[3] = false;
274 WREG32(DC_HPD5_CONTROL
, 0);
275 rdev
->irq
.hpd
[4] = false;
278 WREG32(DC_HPD6_CONTROL
, 0);
279 rdev
->irq
.hpd
[5] = false;
287 void evergreen_bandwidth_update(struct radeon_device
*rdev
)
292 static int evergreen_mc_wait_for_idle(struct radeon_device
*rdev
)
297 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
299 tmp
= RREG32(SRBM_STATUS
) & 0x1F00;
310 void evergreen_pcie_gart_tlb_flush(struct radeon_device
*rdev
)
315 WREG32(VM_CONTEXT0_REQUEST_RESPONSE
, REQUEST_TYPE(1));
316 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
318 tmp
= RREG32(VM_CONTEXT0_REQUEST_RESPONSE
);
319 tmp
= (tmp
& RESPONSE_TYPE_MASK
) >> RESPONSE_TYPE_SHIFT
;
321 printk(KERN_WARNING
"[drm] r600 flush TLB failed\n");
331 int evergreen_pcie_gart_enable(struct radeon_device
*rdev
)
336 if (rdev
->gart
.table
.vram
.robj
== NULL
) {
337 dev_err(rdev
->dev
, "No VRAM object for PCIE GART.\n");
340 r
= radeon_gart_table_vram_pin(rdev
);
343 radeon_gart_restore(rdev
);
345 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
346 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
347 EFFECTIVE_L2_QUEUE_SIZE(7));
348 WREG32(VM_L2_CNTL2
, 0);
349 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
350 /* Setup TLB control */
351 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
352 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
353 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
|
354 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
355 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
356 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
357 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
358 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
359 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
360 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
361 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
362 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR
, rdev
->mc
.gtt_start
>> 12);
363 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR
, rdev
->mc
.gtt_end
>> 12);
364 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, rdev
->gart
.table_addr
>> 12);
365 WREG32(VM_CONTEXT0_CNTL
, ENABLE_CONTEXT
| PAGE_TABLE_DEPTH(0) |
366 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
);
367 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
,
368 (u32
)(rdev
->dummy_page
.addr
>> 12));
369 WREG32(VM_CONTEXT1_CNTL
, 0);
371 evergreen_pcie_gart_tlb_flush(rdev
);
372 rdev
->gart
.ready
= true;
376 void evergreen_pcie_gart_disable(struct radeon_device
*rdev
)
381 /* Disable all tables */
382 WREG32(VM_CONTEXT0_CNTL
, 0);
383 WREG32(VM_CONTEXT1_CNTL
, 0);
386 WREG32(VM_L2_CNTL
, ENABLE_L2_FRAGMENT_PROCESSING
|
387 EFFECTIVE_L2_QUEUE_SIZE(7));
388 WREG32(VM_L2_CNTL2
, 0);
389 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
390 /* Setup TLB control */
391 tmp
= EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
392 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
393 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
394 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
395 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
396 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
397 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
398 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
399 if (rdev
->gart
.table
.vram
.robj
) {
400 r
= radeon_bo_reserve(rdev
->gart
.table
.vram
.robj
, false);
401 if (likely(r
== 0)) {
402 radeon_bo_kunmap(rdev
->gart
.table
.vram
.robj
);
403 radeon_bo_unpin(rdev
->gart
.table
.vram
.robj
);
404 radeon_bo_unreserve(rdev
->gart
.table
.vram
.robj
);
409 void evergreen_pcie_gart_fini(struct radeon_device
*rdev
)
411 evergreen_pcie_gart_disable(rdev
);
412 radeon_gart_table_vram_free(rdev
);
413 radeon_gart_fini(rdev
);
417 void evergreen_agp_enable(struct radeon_device
*rdev
)
422 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
423 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
424 EFFECTIVE_L2_QUEUE_SIZE(7));
425 WREG32(VM_L2_CNTL2
, 0);
426 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
427 /* Setup TLB control */
428 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
429 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
430 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
|
431 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
432 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
433 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
434 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
435 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
436 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
437 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
438 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
439 WREG32(VM_CONTEXT0_CNTL
, 0);
440 WREG32(VM_CONTEXT1_CNTL
, 0);
443 static void evergreen_mc_stop(struct radeon_device
*rdev
, struct evergreen_mc_save
*save
)
445 save
->vga_control
[0] = RREG32(D1VGA_CONTROL
);
446 save
->vga_control
[1] = RREG32(D2VGA_CONTROL
);
447 save
->vga_control
[2] = RREG32(EVERGREEN_D3VGA_CONTROL
);
448 save
->vga_control
[3] = RREG32(EVERGREEN_D4VGA_CONTROL
);
449 save
->vga_control
[4] = RREG32(EVERGREEN_D5VGA_CONTROL
);
450 save
->vga_control
[5] = RREG32(EVERGREEN_D6VGA_CONTROL
);
451 save
->vga_render_control
= RREG32(VGA_RENDER_CONTROL
);
452 save
->vga_hdp_control
= RREG32(VGA_HDP_CONTROL
);
453 save
->crtc_control
[0] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
);
454 save
->crtc_control
[1] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
455 save
->crtc_control
[2] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
);
456 save
->crtc_control
[3] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
457 save
->crtc_control
[4] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
);
458 save
->crtc_control
[5] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
461 WREG32(VGA_RENDER_CONTROL
, 0);
462 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 1);
463 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 1);
464 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 1);
465 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 1);
466 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 1);
467 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 1);
468 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
469 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
470 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
471 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
472 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
473 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
474 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
475 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
476 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
477 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
478 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
479 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
481 WREG32(D1VGA_CONTROL
, 0);
482 WREG32(D2VGA_CONTROL
, 0);
483 WREG32(EVERGREEN_D3VGA_CONTROL
, 0);
484 WREG32(EVERGREEN_D4VGA_CONTROL
, 0);
485 WREG32(EVERGREEN_D5VGA_CONTROL
, 0);
486 WREG32(EVERGREEN_D6VGA_CONTROL
, 0);
489 static void evergreen_mc_resume(struct radeon_device
*rdev
, struct evergreen_mc_save
*save
)
491 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC0_REGISTER_OFFSET
,
492 upper_32_bits(rdev
->mc
.vram_start
));
493 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC0_REGISTER_OFFSET
,
494 upper_32_bits(rdev
->mc
.vram_start
));
495 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
,
496 (u32
)rdev
->mc
.vram_start
);
497 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
,
498 (u32
)rdev
->mc
.vram_start
);
500 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC1_REGISTER_OFFSET
,
501 upper_32_bits(rdev
->mc
.vram_start
));
502 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC1_REGISTER_OFFSET
,
503 upper_32_bits(rdev
->mc
.vram_start
));
504 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
,
505 (u32
)rdev
->mc
.vram_start
);
506 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
,
507 (u32
)rdev
->mc
.vram_start
);
509 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC2_REGISTER_OFFSET
,
510 upper_32_bits(rdev
->mc
.vram_start
));
511 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC2_REGISTER_OFFSET
,
512 upper_32_bits(rdev
->mc
.vram_start
));
513 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
,
514 (u32
)rdev
->mc
.vram_start
);
515 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
,
516 (u32
)rdev
->mc
.vram_start
);
518 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC3_REGISTER_OFFSET
,
519 upper_32_bits(rdev
->mc
.vram_start
));
520 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC3_REGISTER_OFFSET
,
521 upper_32_bits(rdev
->mc
.vram_start
));
522 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
,
523 (u32
)rdev
->mc
.vram_start
);
524 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
,
525 (u32
)rdev
->mc
.vram_start
);
527 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC4_REGISTER_OFFSET
,
528 upper_32_bits(rdev
->mc
.vram_start
));
529 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC4_REGISTER_OFFSET
,
530 upper_32_bits(rdev
->mc
.vram_start
));
531 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
,
532 (u32
)rdev
->mc
.vram_start
);
533 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
,
534 (u32
)rdev
->mc
.vram_start
);
536 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC5_REGISTER_OFFSET
,
537 upper_32_bits(rdev
->mc
.vram_start
));
538 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC5_REGISTER_OFFSET
,
539 upper_32_bits(rdev
->mc
.vram_start
));
540 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
,
541 (u32
)rdev
->mc
.vram_start
);
542 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
,
543 (u32
)rdev
->mc
.vram_start
);
545 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH
, upper_32_bits(rdev
->mc
.vram_start
));
546 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS
, (u32
)rdev
->mc
.vram_start
);
547 /* Unlock host access */
548 WREG32(VGA_HDP_CONTROL
, save
->vga_hdp_control
);
550 /* Restore video state */
551 WREG32(D1VGA_CONTROL
, save
->vga_control
[0]);
552 WREG32(D2VGA_CONTROL
, save
->vga_control
[1]);
553 WREG32(EVERGREEN_D3VGA_CONTROL
, save
->vga_control
[2]);
554 WREG32(EVERGREEN_D4VGA_CONTROL
, save
->vga_control
[3]);
555 WREG32(EVERGREEN_D5VGA_CONTROL
, save
->vga_control
[4]);
556 WREG32(EVERGREEN_D6VGA_CONTROL
, save
->vga_control
[5]);
557 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 1);
558 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 1);
559 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 1);
560 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 1);
561 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 1);
562 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 1);
563 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, save
->crtc_control
[0]);
564 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, save
->crtc_control
[1]);
565 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, save
->crtc_control
[2]);
566 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, save
->crtc_control
[3]);
567 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, save
->crtc_control
[4]);
568 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, save
->crtc_control
[5]);
569 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
570 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
571 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
572 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
573 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
574 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
575 WREG32(VGA_RENDER_CONTROL
, save
->vga_render_control
);
578 static void evergreen_mc_program(struct radeon_device
*rdev
)
580 struct evergreen_mc_save save
;
585 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
586 WREG32((0x2c14 + j
), 0x00000000);
587 WREG32((0x2c18 + j
), 0x00000000);
588 WREG32((0x2c1c + j
), 0x00000000);
589 WREG32((0x2c20 + j
), 0x00000000);
590 WREG32((0x2c24 + j
), 0x00000000);
592 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL
, 0);
594 evergreen_mc_stop(rdev
, &save
);
595 if (evergreen_mc_wait_for_idle(rdev
)) {
596 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
598 /* Lockout access through VGA aperture*/
599 WREG32(VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
);
600 /* Update configuration */
601 if (rdev
->flags
& RADEON_IS_AGP
) {
602 if (rdev
->mc
.vram_start
< rdev
->mc
.gtt_start
) {
603 /* VRAM before AGP */
604 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
605 rdev
->mc
.vram_start
>> 12);
606 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
607 rdev
->mc
.gtt_end
>> 12);
610 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
611 rdev
->mc
.gtt_start
>> 12);
612 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
613 rdev
->mc
.vram_end
>> 12);
616 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
617 rdev
->mc
.vram_start
>> 12);
618 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
619 rdev
->mc
.vram_end
>> 12);
621 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
, 0);
622 tmp
= ((rdev
->mc
.vram_end
>> 24) & 0xFFFF) << 16;
623 tmp
|= ((rdev
->mc
.vram_start
>> 24) & 0xFFFF);
624 WREG32(MC_VM_FB_LOCATION
, tmp
);
625 WREG32(HDP_NONSURFACE_BASE
, (rdev
->mc
.vram_start
>> 8));
626 WREG32(HDP_NONSURFACE_INFO
, (2 << 7));
627 WREG32(HDP_NONSURFACE_SIZE
, 0x3FFFFFFF);
628 if (rdev
->flags
& RADEON_IS_AGP
) {
629 WREG32(MC_VM_AGP_TOP
, rdev
->mc
.gtt_end
>> 16);
630 WREG32(MC_VM_AGP_BOT
, rdev
->mc
.gtt_start
>> 16);
631 WREG32(MC_VM_AGP_BASE
, rdev
->mc
.agp_base
>> 22);
633 WREG32(MC_VM_AGP_BASE
, 0);
634 WREG32(MC_VM_AGP_TOP
, 0x0FFFFFFF);
635 WREG32(MC_VM_AGP_BOT
, 0x0FFFFFFF);
637 if (evergreen_mc_wait_for_idle(rdev
)) {
638 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
640 evergreen_mc_resume(rdev
, &save
);
641 /* we need to own VRAM, so turn off the VGA renderer here
642 * to stop it overwriting our objects */
643 rv515_vga_render_disable(rdev
);
650 static int evergreen_cp_load_microcode(struct radeon_device
*rdev
)
652 const __be32
*fw_data
;
655 if (!rdev
->me_fw
|| !rdev
->pfp_fw
)
659 WREG32(CP_RB_CNTL
, RB_NO_UPDATE
| (15 << 8) | (3 << 0));
661 fw_data
= (const __be32
*)rdev
->pfp_fw
->data
;
662 WREG32(CP_PFP_UCODE_ADDR
, 0);
663 for (i
= 0; i
< EVERGREEN_PFP_UCODE_SIZE
; i
++)
664 WREG32(CP_PFP_UCODE_DATA
, be32_to_cpup(fw_data
++));
665 WREG32(CP_PFP_UCODE_ADDR
, 0);
667 fw_data
= (const __be32
*)rdev
->me_fw
->data
;
668 WREG32(CP_ME_RAM_WADDR
, 0);
669 for (i
= 0; i
< EVERGREEN_PM4_UCODE_SIZE
; i
++)
670 WREG32(CP_ME_RAM_DATA
, be32_to_cpup(fw_data
++));
672 WREG32(CP_PFP_UCODE_ADDR
, 0);
673 WREG32(CP_ME_RAM_WADDR
, 0);
674 WREG32(CP_ME_RAM_RADDR
, 0);
678 int evergreen_cp_resume(struct radeon_device
*rdev
)
684 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
685 WREG32(GRBM_SOFT_RESET
, (SOFT_RESET_CP
|
690 RREG32(GRBM_SOFT_RESET
);
692 WREG32(GRBM_SOFT_RESET
, 0);
693 RREG32(GRBM_SOFT_RESET
);
695 /* Set ring buffer size */
696 rb_bufsz
= drm_order(rdev
->cp
.ring_size
/ 8);
697 tmp
= RB_NO_UPDATE
| (drm_order(RADEON_GPU_PAGE_SIZE
/8) << 8) | rb_bufsz
;
699 tmp
|= BUF_SWAP_32BIT
;
701 WREG32(CP_RB_CNTL
, tmp
);
702 WREG32(CP_SEM_WAIT_TIMER
, 0x4);
704 /* Set the write pointer delay */
705 WREG32(CP_RB_WPTR_DELAY
, 0);
707 /* Initialize the ring buffer's read and write pointers */
708 WREG32(CP_RB_CNTL
, tmp
| RB_RPTR_WR_ENA
);
709 WREG32(CP_RB_RPTR_WR
, 0);
710 WREG32(CP_RB_WPTR
, 0);
711 WREG32(CP_RB_RPTR_ADDR
, rdev
->cp
.gpu_addr
& 0xFFFFFFFF);
712 WREG32(CP_RB_RPTR_ADDR_HI
, upper_32_bits(rdev
->cp
.gpu_addr
));
714 WREG32(CP_RB_CNTL
, tmp
);
716 WREG32(CP_RB_BASE
, rdev
->cp
.gpu_addr
>> 8);
717 WREG32(CP_DEBUG
, (1 << 27) | (1 << 28));
719 rdev
->cp
.rptr
= RREG32(CP_RB_RPTR
);
720 rdev
->cp
.wptr
= RREG32(CP_RB_WPTR
);
723 rdev
->cp
.ready
= true;
724 r
= radeon_ring_test(rdev
);
726 rdev
->cp
.ready
= false;
735 static u32
evergreen_get_tile_pipe_to_backend_map(struct radeon_device
*rdev
,
738 u32 backend_disable_mask
)
741 u32 enabled_backends_mask
= 0;
742 u32 enabled_backends_count
= 0;
744 u32 swizzle_pipe
[EVERGREEN_MAX_PIPES
];
747 bool force_no_swizzle
;
749 if (num_tile_pipes
> EVERGREEN_MAX_PIPES
)
750 num_tile_pipes
= EVERGREEN_MAX_PIPES
;
751 if (num_tile_pipes
< 1)
753 if (num_backends
> EVERGREEN_MAX_BACKENDS
)
754 num_backends
= EVERGREEN_MAX_BACKENDS
;
755 if (num_backends
< 1)
758 for (i
= 0; i
< EVERGREEN_MAX_BACKENDS
; ++i
) {
759 if (((backend_disable_mask
>> i
) & 1) == 0) {
760 enabled_backends_mask
|= (1 << i
);
761 ++enabled_backends_count
;
763 if (enabled_backends_count
== num_backends
)
767 if (enabled_backends_count
== 0) {
768 enabled_backends_mask
= 1;
769 enabled_backends_count
= 1;
772 if (enabled_backends_count
!= num_backends
)
773 num_backends
= enabled_backends_count
;
775 memset((uint8_t *)&swizzle_pipe
[0], 0, sizeof(u32
) * EVERGREEN_MAX_PIPES
);
776 switch (rdev
->family
) {
779 force_no_swizzle
= false;
785 force_no_swizzle
= true;
788 if (force_no_swizzle
) {
789 bool last_backend_enabled
= false;
791 force_no_swizzle
= false;
792 for (i
= 0; i
< EVERGREEN_MAX_BACKENDS
; ++i
) {
793 if (((enabled_backends_mask
>> i
) & 1) == 1) {
794 if (last_backend_enabled
)
795 force_no_swizzle
= true;
796 last_backend_enabled
= true;
798 last_backend_enabled
= false;
802 switch (num_tile_pipes
) {
807 DRM_ERROR("odd number of pipes!\n");
814 if (force_no_swizzle
) {
827 if (force_no_swizzle
) {
844 if (force_no_swizzle
) {
866 for (cur_pipe
= 0; cur_pipe
< num_tile_pipes
; ++cur_pipe
) {
867 while (((1 << cur_backend
) & enabled_backends_mask
) == 0)
868 cur_backend
= (cur_backend
+ 1) % EVERGREEN_MAX_BACKENDS
;
870 backend_map
|= (((cur_backend
& 0xf) << (swizzle_pipe
[cur_pipe
] * 4)));
872 cur_backend
= (cur_backend
+ 1) % EVERGREEN_MAX_BACKENDS
;
878 static void evergreen_gpu_init(struct radeon_device
*rdev
)
880 u32 cc_rb_backend_disable
= 0;
881 u32 cc_gc_shader_pipe_config
;
882 u32 gb_addr_config
= 0;
883 u32 mc_shared_chmap
, mc_arb_ramcfg
;
889 u32 sq_lds_resource_mgmt
;
890 u32 sq_gpr_resource_mgmt_1
;
891 u32 sq_gpr_resource_mgmt_2
;
892 u32 sq_gpr_resource_mgmt_3
;
893 u32 sq_thread_resource_mgmt
;
894 u32 sq_thread_resource_mgmt_2
;
895 u32 sq_stack_resource_mgmt_1
;
896 u32 sq_stack_resource_mgmt_2
;
897 u32 sq_stack_resource_mgmt_3
;
898 u32 vgt_cache_invalidation
;
899 u32 hdp_host_path_cntl
;
900 int i
, j
, num_shader_engines
, ps_thread_count
;
902 switch (rdev
->family
) {
905 rdev
->config
.evergreen
.num_ses
= 2;
906 rdev
->config
.evergreen
.max_pipes
= 4;
907 rdev
->config
.evergreen
.max_tile_pipes
= 8;
908 rdev
->config
.evergreen
.max_simds
= 10;
909 rdev
->config
.evergreen
.max_backends
= 4 * rdev
->config
.evergreen
.num_ses
;
910 rdev
->config
.evergreen
.max_gprs
= 256;
911 rdev
->config
.evergreen
.max_threads
= 248;
912 rdev
->config
.evergreen
.max_gs_threads
= 32;
913 rdev
->config
.evergreen
.max_stack_entries
= 512;
914 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
915 rdev
->config
.evergreen
.sx_max_export_size
= 256;
916 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
917 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
918 rdev
->config
.evergreen
.max_hw_contexts
= 8;
919 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
921 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
922 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
923 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
926 rdev
->config
.evergreen
.num_ses
= 1;
927 rdev
->config
.evergreen
.max_pipes
= 4;
928 rdev
->config
.evergreen
.max_tile_pipes
= 4;
929 rdev
->config
.evergreen
.max_simds
= 10;
930 rdev
->config
.evergreen
.max_backends
= 4 * rdev
->config
.evergreen
.num_ses
;
931 rdev
->config
.evergreen
.max_gprs
= 256;
932 rdev
->config
.evergreen
.max_threads
= 248;
933 rdev
->config
.evergreen
.max_gs_threads
= 32;
934 rdev
->config
.evergreen
.max_stack_entries
= 512;
935 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
936 rdev
->config
.evergreen
.sx_max_export_size
= 256;
937 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
938 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
939 rdev
->config
.evergreen
.max_hw_contexts
= 8;
940 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
942 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
943 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
944 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
947 rdev
->config
.evergreen
.num_ses
= 1;
948 rdev
->config
.evergreen
.max_pipes
= 4;
949 rdev
->config
.evergreen
.max_tile_pipes
= 4;
950 rdev
->config
.evergreen
.max_simds
= 5;
951 rdev
->config
.evergreen
.max_backends
= 2 * rdev
->config
.evergreen
.num_ses
;
952 rdev
->config
.evergreen
.max_gprs
= 256;
953 rdev
->config
.evergreen
.max_threads
= 248;
954 rdev
->config
.evergreen
.max_gs_threads
= 32;
955 rdev
->config
.evergreen
.max_stack_entries
= 256;
956 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
957 rdev
->config
.evergreen
.sx_max_export_size
= 256;
958 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
959 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
960 rdev
->config
.evergreen
.max_hw_contexts
= 8;
961 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
963 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
964 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
965 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
969 rdev
->config
.evergreen
.num_ses
= 1;
970 rdev
->config
.evergreen
.max_pipes
= 2;
971 rdev
->config
.evergreen
.max_tile_pipes
= 2;
972 rdev
->config
.evergreen
.max_simds
= 2;
973 rdev
->config
.evergreen
.max_backends
= 1 * rdev
->config
.evergreen
.num_ses
;
974 rdev
->config
.evergreen
.max_gprs
= 256;
975 rdev
->config
.evergreen
.max_threads
= 192;
976 rdev
->config
.evergreen
.max_gs_threads
= 16;
977 rdev
->config
.evergreen
.max_stack_entries
= 256;
978 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
979 rdev
->config
.evergreen
.sx_max_export_size
= 128;
980 rdev
->config
.evergreen
.sx_max_export_pos_size
= 32;
981 rdev
->config
.evergreen
.sx_max_export_smx_size
= 96;
982 rdev
->config
.evergreen
.max_hw_contexts
= 4;
983 rdev
->config
.evergreen
.sq_num_cf_insts
= 1;
985 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x40;
986 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
987 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
992 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
993 WREG32((0x2c14 + j
), 0x00000000);
994 WREG32((0x2c18 + j
), 0x00000000);
995 WREG32((0x2c1c + j
), 0x00000000);
996 WREG32((0x2c20 + j
), 0x00000000);
997 WREG32((0x2c24 + j
), 0x00000000);
1000 WREG32(GRBM_CNTL
, GRBM_READ_TIMEOUT(0xff));
1002 cc_gc_shader_pipe_config
= RREG32(CC_GC_SHADER_PIPE_CONFIG
) & ~2;
1004 cc_gc_shader_pipe_config
|=
1005 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK
<< rdev
->config
.evergreen
.max_pipes
)
1006 & EVERGREEN_MAX_PIPES_MASK
);
1007 cc_gc_shader_pipe_config
|=
1008 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK
<< rdev
->config
.evergreen
.max_simds
)
1009 & EVERGREEN_MAX_SIMDS_MASK
);
1011 cc_rb_backend_disable
=
1012 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK
<< rdev
->config
.evergreen
.max_backends
)
1013 & EVERGREEN_MAX_BACKENDS_MASK
);
1016 mc_shared_chmap
= RREG32(MC_SHARED_CHMAP
);
1017 mc_arb_ramcfg
= RREG32(MC_ARB_RAMCFG
);
1019 switch (rdev
->config
.evergreen
.max_tile_pipes
) {
1022 gb_addr_config
|= NUM_PIPES(0);
1025 gb_addr_config
|= NUM_PIPES(1);
1028 gb_addr_config
|= NUM_PIPES(2);
1031 gb_addr_config
|= NUM_PIPES(3);
1035 gb_addr_config
|= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg
& BURSTLENGTH_MASK
) >> BURSTLENGTH_SHIFT
);
1036 gb_addr_config
|= BANK_INTERLEAVE_SIZE(0);
1037 gb_addr_config
|= NUM_SHADER_ENGINES(rdev
->config
.evergreen
.num_ses
- 1);
1038 gb_addr_config
|= SHADER_ENGINE_TILE_SIZE(1);
1039 gb_addr_config
|= NUM_GPUS(0); /* Hemlock? */
1040 gb_addr_config
|= MULTI_GPU_TILE_SIZE(2);
1042 if (((mc_arb_ramcfg
& NOOFCOLS_MASK
) >> NOOFCOLS_SHIFT
) > 2)
1043 gb_addr_config
|= ROW_SIZE(2);
1045 gb_addr_config
|= ROW_SIZE((mc_arb_ramcfg
& NOOFCOLS_MASK
) >> NOOFCOLS_SHIFT
);
1047 if (rdev
->ddev
->pdev
->device
== 0x689e) {
1050 u8 efuse_box_bit_131_124
;
1052 WREG32(RCU_IND_INDEX
, 0x204);
1053 efuse_straps_4
= RREG32(RCU_IND_DATA
);
1054 WREG32(RCU_IND_INDEX
, 0x203);
1055 efuse_straps_3
= RREG32(RCU_IND_DATA
);
1056 efuse_box_bit_131_124
= (u8
)(((efuse_straps_4
& 0xf) << 4) | ((efuse_straps_3
& 0xf0000000) >> 28));
1058 switch(efuse_box_bit_131_124
) {
1060 gb_backend_map
= 0x76543210;
1063 gb_backend_map
= 0x77553311;
1066 gb_backend_map
= 0x77553300;
1069 gb_backend_map
= 0x77552211;
1072 gb_backend_map
= 0x77443300;
1075 gb_backend_map
= 0x66552211;
1078 gb_backend_map
= 0x77552200;
1081 gb_backend_map
= 0x66442200;
1084 gb_backend_map
= 0x66553311;
1087 DRM_ERROR("bad backend map, using default\n");
1089 evergreen_get_tile_pipe_to_backend_map(rdev
,
1090 rdev
->config
.evergreen
.max_tile_pipes
,
1091 rdev
->config
.evergreen
.max_backends
,
1092 ((EVERGREEN_MAX_BACKENDS_MASK
<<
1093 rdev
->config
.evergreen
.max_backends
) &
1094 EVERGREEN_MAX_BACKENDS_MASK
));
1097 } else if (rdev
->ddev
->pdev
->device
== 0x68b9) {
1099 u8 efuse_box_bit_127_124
;
1101 WREG32(RCU_IND_INDEX
, 0x203);
1102 efuse_straps_3
= RREG32(RCU_IND_DATA
);
1103 efuse_box_bit_127_124
= (u8
)(efuse_straps_3
& 0xF0000000) >> 28;
1105 switch(efuse_box_bit_127_124
) {
1107 gb_backend_map
= 0x00003210;
1113 gb_backend_map
= 0x00003311;
1116 DRM_ERROR("bad backend map, using default\n");
1118 evergreen_get_tile_pipe_to_backend_map(rdev
,
1119 rdev
->config
.evergreen
.max_tile_pipes
,
1120 rdev
->config
.evergreen
.max_backends
,
1121 ((EVERGREEN_MAX_BACKENDS_MASK
<<
1122 rdev
->config
.evergreen
.max_backends
) &
1123 EVERGREEN_MAX_BACKENDS_MASK
));
1128 evergreen_get_tile_pipe_to_backend_map(rdev
,
1129 rdev
->config
.evergreen
.max_tile_pipes
,
1130 rdev
->config
.evergreen
.max_backends
,
1131 ((EVERGREEN_MAX_BACKENDS_MASK
<<
1132 rdev
->config
.evergreen
.max_backends
) &
1133 EVERGREEN_MAX_BACKENDS_MASK
));
1135 rdev
->config
.evergreen
.tile_config
= gb_addr_config
;
1136 WREG32(GB_BACKEND_MAP
, gb_backend_map
);
1137 WREG32(GB_ADDR_CONFIG
, gb_addr_config
);
1138 WREG32(DMIF_ADDR_CONFIG
, gb_addr_config
);
1139 WREG32(HDP_ADDR_CONFIG
, gb_addr_config
);
1141 num_shader_engines
= ((RREG32(GB_ADDR_CONFIG
) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
1142 grbm_gfx_index
= INSTANCE_BROADCAST_WRITES
;
1144 for (i
= 0; i
< rdev
->config
.evergreen
.num_ses
; i
++) {
1145 u32 rb
= cc_rb_backend_disable
| (0xf0 << 16);
1146 u32 sp
= cc_gc_shader_pipe_config
;
1147 u32 gfx
= grbm_gfx_index
| SE_INDEX(i
);
1149 if (i
== num_shader_engines
) {
1150 rb
|= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK
);
1151 sp
|= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK
);
1154 WREG32(GRBM_GFX_INDEX
, gfx
);
1155 WREG32(RLC_GFX_INDEX
, gfx
);
1157 WREG32(CC_RB_BACKEND_DISABLE
, rb
);
1158 WREG32(CC_SYS_RB_BACKEND_DISABLE
, rb
);
1159 WREG32(GC_USER_RB_BACKEND_DISABLE
, rb
);
1160 WREG32(CC_GC_SHADER_PIPE_CONFIG
, sp
);
1163 grbm_gfx_index
|= SE_BROADCAST_WRITES
;
1164 WREG32(GRBM_GFX_INDEX
, grbm_gfx_index
);
1165 WREG32(RLC_GFX_INDEX
, grbm_gfx_index
);
1167 WREG32(CGTS_SYS_TCC_DISABLE
, 0);
1168 WREG32(CGTS_TCC_DISABLE
, 0);
1169 WREG32(CGTS_USER_SYS_TCC_DISABLE
, 0);
1170 WREG32(CGTS_USER_TCC_DISABLE
, 0);
1172 /* set HW defaults for 3D engine */
1173 WREG32(CP_QUEUE_THRESHOLDS
, (ROQ_IB1_START(0x16) |
1174 ROQ_IB2_START(0x2b)));
1176 WREG32(CP_MEQ_THRESHOLDS
, STQ_SPLIT(0x30));
1178 WREG32(TA_CNTL_AUX
, (DISABLE_CUBE_ANISO
|
1183 sx_debug_1
= RREG32(SX_DEBUG_1
);
1184 sx_debug_1
|= ENABLE_NEW_SMX_ADDRESS
;
1185 WREG32(SX_DEBUG_1
, sx_debug_1
);
1188 smx_dc_ctl0
= RREG32(SMX_DC_CTL0
);
1189 smx_dc_ctl0
&= ~NUMBER_OF_SETS(0x1ff);
1190 smx_dc_ctl0
|= NUMBER_OF_SETS(rdev
->config
.evergreen
.sx_num_of_sets
);
1191 WREG32(SMX_DC_CTL0
, smx_dc_ctl0
);
1193 WREG32(SX_EXPORT_BUFFER_SIZES
, (COLOR_BUFFER_SIZE((rdev
->config
.evergreen
.sx_max_export_size
/ 4) - 1) |
1194 POSITION_BUFFER_SIZE((rdev
->config
.evergreen
.sx_max_export_pos_size
/ 4) - 1) |
1195 SMX_BUFFER_SIZE((rdev
->config
.evergreen
.sx_max_export_smx_size
/ 4) - 1)));
1197 WREG32(PA_SC_FIFO_SIZE
, (SC_PRIM_FIFO_SIZE(rdev
->config
.evergreen
.sc_prim_fifo_size
) |
1198 SC_HIZ_TILE_FIFO_SIZE(rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
) |
1199 SC_EARLYZ_TILE_FIFO_SIZE(rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
)));
1201 WREG32(VGT_NUM_INSTANCES
, 1);
1202 WREG32(SPI_CONFIG_CNTL
, 0);
1203 WREG32(SPI_CONFIG_CNTL_1
, VTX_DONE_DELAY(4));
1204 WREG32(CP_PERFMON_CNTL
, 0);
1206 WREG32(SQ_MS_FIFO_SIZES
, (CACHE_FIFO_SIZE(16 * rdev
->config
.evergreen
.sq_num_cf_insts
) |
1207 FETCH_FIFO_HIWATER(0x4) |
1208 DONE_FIFO_HIWATER(0xe0) |
1209 ALU_UPDATE_FIFO_HIWATER(0x8)));
1211 sq_config
= RREG32(SQ_CONFIG
);
1212 sq_config
&= ~(PS_PRIO(3) |
1216 sq_config
|= (VC_ENABLE
|
1223 if (rdev
->family
== CHIP_CEDAR
)
1224 /* no vertex cache */
1225 sq_config
&= ~VC_ENABLE
;
1227 sq_lds_resource_mgmt
= RREG32(SQ_LDS_RESOURCE_MGMT
);
1229 sq_gpr_resource_mgmt_1
= NUM_PS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2))* 12 / 32);
1230 sq_gpr_resource_mgmt_1
|= NUM_VS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 6 / 32);
1231 sq_gpr_resource_mgmt_1
|= NUM_CLAUSE_TEMP_GPRS(4);
1232 sq_gpr_resource_mgmt_2
= NUM_GS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 4 / 32);
1233 sq_gpr_resource_mgmt_2
|= NUM_ES_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 4 / 32);
1234 sq_gpr_resource_mgmt_3
= NUM_HS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 3 / 32);
1235 sq_gpr_resource_mgmt_3
|= NUM_LS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 3 / 32);
1237 if (rdev
->family
== CHIP_CEDAR
)
1238 ps_thread_count
= 96;
1240 ps_thread_count
= 128;
1242 sq_thread_resource_mgmt
= NUM_PS_THREADS(ps_thread_count
);
1243 sq_thread_resource_mgmt
|= NUM_VS_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
1244 sq_thread_resource_mgmt
|= NUM_GS_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
1245 sq_thread_resource_mgmt
|= NUM_ES_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
1246 sq_thread_resource_mgmt_2
= NUM_HS_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
1247 sq_thread_resource_mgmt_2
|= NUM_LS_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
1249 sq_stack_resource_mgmt_1
= NUM_PS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
1250 sq_stack_resource_mgmt_1
|= NUM_VS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
1251 sq_stack_resource_mgmt_2
= NUM_GS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
1252 sq_stack_resource_mgmt_2
|= NUM_ES_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
1253 sq_stack_resource_mgmt_3
= NUM_HS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
1254 sq_stack_resource_mgmt_3
|= NUM_LS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
1256 WREG32(SQ_CONFIG
, sq_config
);
1257 WREG32(SQ_GPR_RESOURCE_MGMT_1
, sq_gpr_resource_mgmt_1
);
1258 WREG32(SQ_GPR_RESOURCE_MGMT_2
, sq_gpr_resource_mgmt_2
);
1259 WREG32(SQ_GPR_RESOURCE_MGMT_3
, sq_gpr_resource_mgmt_3
);
1260 WREG32(SQ_THREAD_RESOURCE_MGMT
, sq_thread_resource_mgmt
);
1261 WREG32(SQ_THREAD_RESOURCE_MGMT_2
, sq_thread_resource_mgmt_2
);
1262 WREG32(SQ_STACK_RESOURCE_MGMT_1
, sq_stack_resource_mgmt_1
);
1263 WREG32(SQ_STACK_RESOURCE_MGMT_2
, sq_stack_resource_mgmt_2
);
1264 WREG32(SQ_STACK_RESOURCE_MGMT_3
, sq_stack_resource_mgmt_3
);
1265 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0);
1266 WREG32(SQ_LDS_RESOURCE_MGMT
, sq_lds_resource_mgmt
);
1268 WREG32(PA_SC_FORCE_EOV_MAX_CNTS
, (FORCE_EOV_MAX_CLK_CNT(4095) |
1269 FORCE_EOV_MAX_REZ_CNT(255)));
1271 if (rdev
->family
== CHIP_CEDAR
)
1272 vgt_cache_invalidation
= CACHE_INVALIDATION(TC_ONLY
);
1274 vgt_cache_invalidation
= CACHE_INVALIDATION(VC_AND_TC
);
1275 vgt_cache_invalidation
|= AUTO_INVLD_EN(ES_AND_GS_AUTO
);
1276 WREG32(VGT_CACHE_INVALIDATION
, vgt_cache_invalidation
);
1278 WREG32(VGT_GS_VERTEX_REUSE
, 16);
1279 WREG32(PA_SC_LINE_STIPPLE_STATE
, 0);
1281 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
1282 WREG32(VGT_OUT_DEALLOC_CNTL
, 16);
1284 WREG32(CB_PERF_CTR0_SEL_0
, 0);
1285 WREG32(CB_PERF_CTR0_SEL_1
, 0);
1286 WREG32(CB_PERF_CTR1_SEL_0
, 0);
1287 WREG32(CB_PERF_CTR1_SEL_1
, 0);
1288 WREG32(CB_PERF_CTR2_SEL_0
, 0);
1289 WREG32(CB_PERF_CTR2_SEL_1
, 0);
1290 WREG32(CB_PERF_CTR3_SEL_0
, 0);
1291 WREG32(CB_PERF_CTR3_SEL_1
, 0);
1293 /* clear render buffer base addresses */
1294 WREG32(CB_COLOR0_BASE
, 0);
1295 WREG32(CB_COLOR1_BASE
, 0);
1296 WREG32(CB_COLOR2_BASE
, 0);
1297 WREG32(CB_COLOR3_BASE
, 0);
1298 WREG32(CB_COLOR4_BASE
, 0);
1299 WREG32(CB_COLOR5_BASE
, 0);
1300 WREG32(CB_COLOR6_BASE
, 0);
1301 WREG32(CB_COLOR7_BASE
, 0);
1302 WREG32(CB_COLOR8_BASE
, 0);
1303 WREG32(CB_COLOR9_BASE
, 0);
1304 WREG32(CB_COLOR10_BASE
, 0);
1305 WREG32(CB_COLOR11_BASE
, 0);
1307 /* set the shader const cache sizes to 0 */
1308 for (i
= SQ_ALU_CONST_BUFFER_SIZE_PS_0
; i
< 0x28200; i
+= 4)
1310 for (i
= SQ_ALU_CONST_BUFFER_SIZE_HS_0
; i
< 0x29000; i
+= 4)
1313 hdp_host_path_cntl
= RREG32(HDP_HOST_PATH_CNTL
);
1314 WREG32(HDP_HOST_PATH_CNTL
, hdp_host_path_cntl
);
1316 WREG32(PA_CL_ENHANCE
, CLIP_VTX_REORDER_ENA
| NUM_CLIP_SEQ(3));
1322 int evergreen_mc_init(struct radeon_device
*rdev
)
1325 int chansize
, numchan
;
1327 /* Get VRAM informations */
1328 rdev
->mc
.vram_is_ddr
= true;
1329 tmp
= RREG32(MC_ARB_RAMCFG
);
1330 if (tmp
& CHANSIZE_OVERRIDE
) {
1332 } else if (tmp
& CHANSIZE_MASK
) {
1337 tmp
= RREG32(MC_SHARED_CHMAP
);
1338 switch ((tmp
& NOOFCHAN_MASK
) >> NOOFCHAN_SHIFT
) {
1353 rdev
->mc
.vram_width
= numchan
* chansize
;
1354 /* Could aper size report 0 ? */
1355 rdev
->mc
.aper_base
= pci_resource_start(rdev
->pdev
, 0);
1356 rdev
->mc
.aper_size
= pci_resource_len(rdev
->pdev
, 0);
1357 /* Setup GPU memory space */
1358 /* size in MB on evergreen */
1359 rdev
->mc
.mc_vram_size
= RREG32(CONFIG_MEMSIZE
) * 1024 * 1024;
1360 rdev
->mc
.real_vram_size
= RREG32(CONFIG_MEMSIZE
) * 1024 * 1024;
1361 rdev
->mc
.visible_vram_size
= rdev
->mc
.aper_size
;
1362 r600_vram_gtt_location(rdev
, &rdev
->mc
);
1363 radeon_update_bandwidth_info(rdev
);
1368 bool evergreen_gpu_is_lockup(struct radeon_device
*rdev
)
1370 /* FIXME: implement for evergreen */
1374 static int evergreen_gpu_soft_reset(struct radeon_device
*rdev
)
1376 struct evergreen_mc_save save
;
1380 dev_info(rdev
->dev
, "GPU softreset \n");
1381 dev_info(rdev
->dev
, " GRBM_STATUS=0x%08X\n",
1382 RREG32(GRBM_STATUS
));
1383 dev_info(rdev
->dev
, " GRBM_STATUS_SE0=0x%08X\n",
1384 RREG32(GRBM_STATUS_SE0
));
1385 dev_info(rdev
->dev
, " GRBM_STATUS_SE1=0x%08X\n",
1386 RREG32(GRBM_STATUS_SE1
));
1387 dev_info(rdev
->dev
, " SRBM_STATUS=0x%08X\n",
1388 RREG32(SRBM_STATUS
));
1389 evergreen_mc_stop(rdev
, &save
);
1390 if (evergreen_mc_wait_for_idle(rdev
)) {
1391 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1393 /* Disable CP parsing/prefetching */
1394 WREG32(CP_ME_CNTL
, CP_ME_HALT
| CP_PFP_HALT
);
1396 /* reset all the gfx blocks */
1397 grbm_reset
= (SOFT_RESET_CP
|
1410 dev_info(rdev
->dev
, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset
);
1411 WREG32(GRBM_SOFT_RESET
, grbm_reset
);
1412 (void)RREG32(GRBM_SOFT_RESET
);
1414 WREG32(GRBM_SOFT_RESET
, 0);
1415 (void)RREG32(GRBM_SOFT_RESET
);
1417 /* reset all the system blocks */
1418 srbm_reset
= SRBM_SOFT_RESET_ALL_MASK
;
1420 dev_info(rdev
->dev
, " SRBM_SOFT_RESET=0x%08X\n", srbm_reset
);
1421 WREG32(SRBM_SOFT_RESET
, srbm_reset
);
1422 (void)RREG32(SRBM_SOFT_RESET
);
1424 WREG32(SRBM_SOFT_RESET
, 0);
1425 (void)RREG32(SRBM_SOFT_RESET
);
1426 /* Wait a little for things to settle down */
1428 dev_info(rdev
->dev
, " GRBM_STATUS=0x%08X\n",
1429 RREG32(GRBM_STATUS
));
1430 dev_info(rdev
->dev
, " GRBM_STATUS_SE0=0x%08X\n",
1431 RREG32(GRBM_STATUS_SE0
));
1432 dev_info(rdev
->dev
, " GRBM_STATUS_SE1=0x%08X\n",
1433 RREG32(GRBM_STATUS_SE1
));
1434 dev_info(rdev
->dev
, " SRBM_STATUS=0x%08X\n",
1435 RREG32(SRBM_STATUS
));
1436 /* After reset we need to reinit the asic as GPU often endup in an
1439 atom_asic_init(rdev
->mode_info
.atom_context
);
1440 evergreen_mc_resume(rdev
, &save
);
1444 int evergreen_asic_reset(struct radeon_device
*rdev
)
1446 return evergreen_gpu_soft_reset(rdev
);
1451 u32
evergreen_get_vblank_counter(struct radeon_device
*rdev
, int crtc
)
1455 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC0_REGISTER_OFFSET
);
1457 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
1459 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC2_REGISTER_OFFSET
);
1461 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
1463 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC4_REGISTER_OFFSET
);
1465 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
1471 void evergreen_disable_interrupt_state(struct radeon_device
*rdev
)
1475 WREG32(CP_INT_CNTL
, 0);
1476 WREG32(GRBM_INT_CNTL
, 0);
1477 WREG32(INT_MASK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
1478 WREG32(INT_MASK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
1479 WREG32(INT_MASK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
1480 WREG32(INT_MASK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
1481 WREG32(INT_MASK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
1482 WREG32(INT_MASK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
1484 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
1485 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
1486 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
1487 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
1488 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
1489 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
1491 WREG32(DACA_AUTODETECT_INT_CONTROL
, 0);
1492 WREG32(DACB_AUTODETECT_INT_CONTROL
, 0);
1494 tmp
= RREG32(DC_HPD1_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
1495 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
1496 tmp
= RREG32(DC_HPD2_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
1497 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
1498 tmp
= RREG32(DC_HPD3_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
1499 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
1500 tmp
= RREG32(DC_HPD4_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
1501 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
1502 tmp
= RREG32(DC_HPD5_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
1503 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
1504 tmp
= RREG32(DC_HPD6_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
1505 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
1509 int evergreen_irq_set(struct radeon_device
*rdev
)
1511 u32 cp_int_cntl
= CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
;
1512 u32 crtc1
= 0, crtc2
= 0, crtc3
= 0, crtc4
= 0, crtc5
= 0, crtc6
= 0;
1513 u32 hpd1
, hpd2
, hpd3
, hpd4
, hpd5
, hpd6
;
1514 u32 grbm_int_cntl
= 0;
1516 if (!rdev
->irq
.installed
) {
1517 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
1520 /* don't enable anything if the ih is disabled */
1521 if (!rdev
->ih
.enabled
) {
1522 r600_disable_interrupts(rdev
);
1523 /* force the active interrupt state to all disabled */
1524 evergreen_disable_interrupt_state(rdev
);
1528 hpd1
= RREG32(DC_HPD1_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
1529 hpd2
= RREG32(DC_HPD2_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
1530 hpd3
= RREG32(DC_HPD3_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
1531 hpd4
= RREG32(DC_HPD4_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
1532 hpd5
= RREG32(DC_HPD5_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
1533 hpd6
= RREG32(DC_HPD6_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
1535 if (rdev
->irq
.sw_int
) {
1536 DRM_DEBUG("evergreen_irq_set: sw int\n");
1537 cp_int_cntl
|= RB_INT_ENABLE
;
1539 if (rdev
->irq
.crtc_vblank_int
[0]) {
1540 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
1541 crtc1
|= VBLANK_INT_MASK
;
1543 if (rdev
->irq
.crtc_vblank_int
[1]) {
1544 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
1545 crtc2
|= VBLANK_INT_MASK
;
1547 if (rdev
->irq
.crtc_vblank_int
[2]) {
1548 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
1549 crtc3
|= VBLANK_INT_MASK
;
1551 if (rdev
->irq
.crtc_vblank_int
[3]) {
1552 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
1553 crtc4
|= VBLANK_INT_MASK
;
1555 if (rdev
->irq
.crtc_vblank_int
[4]) {
1556 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
1557 crtc5
|= VBLANK_INT_MASK
;
1559 if (rdev
->irq
.crtc_vblank_int
[5]) {
1560 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
1561 crtc6
|= VBLANK_INT_MASK
;
1563 if (rdev
->irq
.hpd
[0]) {
1564 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
1565 hpd1
|= DC_HPDx_INT_EN
;
1567 if (rdev
->irq
.hpd
[1]) {
1568 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
1569 hpd2
|= DC_HPDx_INT_EN
;
1571 if (rdev
->irq
.hpd
[2]) {
1572 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
1573 hpd3
|= DC_HPDx_INT_EN
;
1575 if (rdev
->irq
.hpd
[3]) {
1576 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
1577 hpd4
|= DC_HPDx_INT_EN
;
1579 if (rdev
->irq
.hpd
[4]) {
1580 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
1581 hpd5
|= DC_HPDx_INT_EN
;
1583 if (rdev
->irq
.hpd
[5]) {
1584 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
1585 hpd6
|= DC_HPDx_INT_EN
;
1587 if (rdev
->irq
.gui_idle
) {
1588 DRM_DEBUG("gui idle\n");
1589 grbm_int_cntl
|= GUI_IDLE_INT_ENABLE
;
1592 WREG32(CP_INT_CNTL
, cp_int_cntl
);
1593 WREG32(GRBM_INT_CNTL
, grbm_int_cntl
);
1595 WREG32(INT_MASK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, crtc1
);
1596 WREG32(INT_MASK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, crtc2
);
1597 WREG32(INT_MASK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, crtc3
);
1598 WREG32(INT_MASK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, crtc4
);
1599 WREG32(INT_MASK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, crtc5
);
1600 WREG32(INT_MASK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, crtc6
);
1602 WREG32(DC_HPD1_INT_CONTROL
, hpd1
);
1603 WREG32(DC_HPD2_INT_CONTROL
, hpd2
);
1604 WREG32(DC_HPD3_INT_CONTROL
, hpd3
);
1605 WREG32(DC_HPD4_INT_CONTROL
, hpd4
);
1606 WREG32(DC_HPD5_INT_CONTROL
, hpd5
);
1607 WREG32(DC_HPD6_INT_CONTROL
, hpd6
);
1612 static inline void evergreen_irq_ack(struct radeon_device
*rdev
,
1615 u32
*disp_int_cont2
,
1616 u32
*disp_int_cont3
,
1617 u32
*disp_int_cont4
,
1618 u32
*disp_int_cont5
)
1622 *disp_int
= RREG32(DISP_INTERRUPT_STATUS
);
1623 *disp_int_cont
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE
);
1624 *disp_int_cont2
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE2
);
1625 *disp_int_cont3
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE3
);
1626 *disp_int_cont4
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE4
);
1627 *disp_int_cont5
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE5
);
1629 if (*disp_int
& LB_D1_VBLANK_INTERRUPT
)
1630 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, VBLANK_ACK
);
1631 if (*disp_int
& LB_D1_VLINE_INTERRUPT
)
1632 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, VLINE_ACK
);
1634 if (*disp_int_cont
& LB_D2_VBLANK_INTERRUPT
)
1635 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, VBLANK_ACK
);
1636 if (*disp_int_cont
& LB_D2_VLINE_INTERRUPT
)
1637 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, VLINE_ACK
);
1639 if (*disp_int_cont2
& LB_D3_VBLANK_INTERRUPT
)
1640 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, VBLANK_ACK
);
1641 if (*disp_int_cont2
& LB_D3_VLINE_INTERRUPT
)
1642 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, VLINE_ACK
);
1644 if (*disp_int_cont3
& LB_D4_VBLANK_INTERRUPT
)
1645 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, VBLANK_ACK
);
1646 if (*disp_int_cont3
& LB_D4_VLINE_INTERRUPT
)
1647 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, VLINE_ACK
);
1649 if (*disp_int_cont4
& LB_D5_VBLANK_INTERRUPT
)
1650 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, VBLANK_ACK
);
1651 if (*disp_int_cont4
& LB_D5_VLINE_INTERRUPT
)
1652 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, VLINE_ACK
);
1654 if (*disp_int_cont5
& LB_D6_VBLANK_INTERRUPT
)
1655 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, VBLANK_ACK
);
1656 if (*disp_int_cont5
& LB_D6_VLINE_INTERRUPT
)
1657 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, VLINE_ACK
);
1659 if (*disp_int
& DC_HPD1_INTERRUPT
) {
1660 tmp
= RREG32(DC_HPD1_INT_CONTROL
);
1661 tmp
|= DC_HPDx_INT_ACK
;
1662 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
1664 if (*disp_int_cont
& DC_HPD2_INTERRUPT
) {
1665 tmp
= RREG32(DC_HPD2_INT_CONTROL
);
1666 tmp
|= DC_HPDx_INT_ACK
;
1667 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
1669 if (*disp_int_cont2
& DC_HPD3_INTERRUPT
) {
1670 tmp
= RREG32(DC_HPD3_INT_CONTROL
);
1671 tmp
|= DC_HPDx_INT_ACK
;
1672 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
1674 if (*disp_int_cont3
& DC_HPD4_INTERRUPT
) {
1675 tmp
= RREG32(DC_HPD4_INT_CONTROL
);
1676 tmp
|= DC_HPDx_INT_ACK
;
1677 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
1679 if (*disp_int_cont4
& DC_HPD5_INTERRUPT
) {
1680 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
1681 tmp
|= DC_HPDx_INT_ACK
;
1682 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
1684 if (*disp_int_cont5
& DC_HPD6_INTERRUPT
) {
1685 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
1686 tmp
|= DC_HPDx_INT_ACK
;
1687 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
1691 void evergreen_irq_disable(struct radeon_device
*rdev
)
1693 u32 disp_int
, disp_int_cont
, disp_int_cont2
;
1694 u32 disp_int_cont3
, disp_int_cont4
, disp_int_cont5
;
1696 r600_disable_interrupts(rdev
);
1697 /* Wait and acknowledge irq */
1699 evergreen_irq_ack(rdev
, &disp_int
, &disp_int_cont
, &disp_int_cont2
,
1700 &disp_int_cont3
, &disp_int_cont4
, &disp_int_cont5
);
1701 evergreen_disable_interrupt_state(rdev
);
1704 static void evergreen_irq_suspend(struct radeon_device
*rdev
)
1706 evergreen_irq_disable(rdev
);
1707 r600_rlc_stop(rdev
);
1710 static inline u32
evergreen_get_ih_wptr(struct radeon_device
*rdev
)
1714 /* XXX use writeback */
1715 wptr
= RREG32(IH_RB_WPTR
);
1717 if (wptr
& RB_OVERFLOW
) {
1718 /* When a ring buffer overflow happen start parsing interrupt
1719 * from the last not overwritten vector (wptr + 16). Hopefully
1720 * this should allow us to catchup.
1722 dev_warn(rdev
->dev
, "IH ring buffer overflow (0x%08X, %d, %d)\n",
1723 wptr
, rdev
->ih
.rptr
, (wptr
+ 16) + rdev
->ih
.ptr_mask
);
1724 rdev
->ih
.rptr
= (wptr
+ 16) & rdev
->ih
.ptr_mask
;
1725 tmp
= RREG32(IH_RB_CNTL
);
1726 tmp
|= IH_WPTR_OVERFLOW_CLEAR
;
1727 WREG32(IH_RB_CNTL
, tmp
);
1729 return (wptr
& rdev
->ih
.ptr_mask
);
1732 int evergreen_irq_process(struct radeon_device
*rdev
)
1734 u32 wptr
= evergreen_get_ih_wptr(rdev
);
1735 u32 rptr
= rdev
->ih
.rptr
;
1736 u32 src_id
, src_data
;
1738 u32 disp_int
, disp_int_cont
, disp_int_cont2
;
1739 u32 disp_int_cont3
, disp_int_cont4
, disp_int_cont5
;
1740 unsigned long flags
;
1741 bool queue_hotplug
= false;
1743 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr
, wptr
);
1744 if (!rdev
->ih
.enabled
)
1747 spin_lock_irqsave(&rdev
->ih
.lock
, flags
);
1750 spin_unlock_irqrestore(&rdev
->ih
.lock
, flags
);
1753 if (rdev
->shutdown
) {
1754 spin_unlock_irqrestore(&rdev
->ih
.lock
, flags
);
1759 /* display interrupts */
1760 evergreen_irq_ack(rdev
, &disp_int
, &disp_int_cont
, &disp_int_cont2
,
1761 &disp_int_cont3
, &disp_int_cont4
, &disp_int_cont5
);
1763 rdev
->ih
.wptr
= wptr
;
1764 while (rptr
!= wptr
) {
1765 /* wptr/rptr are in bytes! */
1766 ring_index
= rptr
/ 4;
1767 src_id
= rdev
->ih
.ring
[ring_index
] & 0xff;
1768 src_data
= rdev
->ih
.ring
[ring_index
+ 1] & 0xfffffff;
1771 case 1: /* D1 vblank/vline */
1773 case 0: /* D1 vblank */
1774 if (disp_int
& LB_D1_VBLANK_INTERRUPT
) {
1775 drm_handle_vblank(rdev
->ddev
, 0);
1776 wake_up(&rdev
->irq
.vblank_queue
);
1777 disp_int
&= ~LB_D1_VBLANK_INTERRUPT
;
1778 DRM_DEBUG("IH: D1 vblank\n");
1781 case 1: /* D1 vline */
1782 if (disp_int
& LB_D1_VLINE_INTERRUPT
) {
1783 disp_int
&= ~LB_D1_VLINE_INTERRUPT
;
1784 DRM_DEBUG("IH: D1 vline\n");
1788 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
1792 case 2: /* D2 vblank/vline */
1794 case 0: /* D2 vblank */
1795 if (disp_int_cont
& LB_D2_VBLANK_INTERRUPT
) {
1796 drm_handle_vblank(rdev
->ddev
, 1);
1797 wake_up(&rdev
->irq
.vblank_queue
);
1798 disp_int_cont
&= ~LB_D2_VBLANK_INTERRUPT
;
1799 DRM_DEBUG("IH: D2 vblank\n");
1802 case 1: /* D2 vline */
1803 if (disp_int_cont
& LB_D2_VLINE_INTERRUPT
) {
1804 disp_int_cont
&= ~LB_D2_VLINE_INTERRUPT
;
1805 DRM_DEBUG("IH: D2 vline\n");
1809 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
1813 case 3: /* D3 vblank/vline */
1815 case 0: /* D3 vblank */
1816 if (disp_int_cont2
& LB_D3_VBLANK_INTERRUPT
) {
1817 drm_handle_vblank(rdev
->ddev
, 2);
1818 wake_up(&rdev
->irq
.vblank_queue
);
1819 disp_int_cont2
&= ~LB_D3_VBLANK_INTERRUPT
;
1820 DRM_DEBUG("IH: D3 vblank\n");
1823 case 1: /* D3 vline */
1824 if (disp_int_cont2
& LB_D3_VLINE_INTERRUPT
) {
1825 disp_int_cont2
&= ~LB_D3_VLINE_INTERRUPT
;
1826 DRM_DEBUG("IH: D3 vline\n");
1830 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
1834 case 4: /* D4 vblank/vline */
1836 case 0: /* D4 vblank */
1837 if (disp_int_cont3
& LB_D4_VBLANK_INTERRUPT
) {
1838 drm_handle_vblank(rdev
->ddev
, 3);
1839 wake_up(&rdev
->irq
.vblank_queue
);
1840 disp_int_cont3
&= ~LB_D4_VBLANK_INTERRUPT
;
1841 DRM_DEBUG("IH: D4 vblank\n");
1844 case 1: /* D4 vline */
1845 if (disp_int_cont3
& LB_D4_VLINE_INTERRUPT
) {
1846 disp_int_cont3
&= ~LB_D4_VLINE_INTERRUPT
;
1847 DRM_DEBUG("IH: D4 vline\n");
1851 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
1855 case 5: /* D5 vblank/vline */
1857 case 0: /* D5 vblank */
1858 if (disp_int_cont4
& LB_D5_VBLANK_INTERRUPT
) {
1859 drm_handle_vblank(rdev
->ddev
, 4);
1860 wake_up(&rdev
->irq
.vblank_queue
);
1861 disp_int_cont4
&= ~LB_D5_VBLANK_INTERRUPT
;
1862 DRM_DEBUG("IH: D5 vblank\n");
1865 case 1: /* D5 vline */
1866 if (disp_int_cont4
& LB_D5_VLINE_INTERRUPT
) {
1867 disp_int_cont4
&= ~LB_D5_VLINE_INTERRUPT
;
1868 DRM_DEBUG("IH: D5 vline\n");
1872 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
1876 case 6: /* D6 vblank/vline */
1878 case 0: /* D6 vblank */
1879 if (disp_int_cont5
& LB_D6_VBLANK_INTERRUPT
) {
1880 drm_handle_vblank(rdev
->ddev
, 5);
1881 wake_up(&rdev
->irq
.vblank_queue
);
1882 disp_int_cont5
&= ~LB_D6_VBLANK_INTERRUPT
;
1883 DRM_DEBUG("IH: D6 vblank\n");
1886 case 1: /* D6 vline */
1887 if (disp_int_cont5
& LB_D6_VLINE_INTERRUPT
) {
1888 disp_int_cont5
&= ~LB_D6_VLINE_INTERRUPT
;
1889 DRM_DEBUG("IH: D6 vline\n");
1893 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
1897 case 42: /* HPD hotplug */
1900 if (disp_int
& DC_HPD1_INTERRUPT
) {
1901 disp_int
&= ~DC_HPD1_INTERRUPT
;
1902 queue_hotplug
= true;
1903 DRM_DEBUG("IH: HPD1\n");
1907 if (disp_int_cont
& DC_HPD2_INTERRUPT
) {
1908 disp_int_cont
&= ~DC_HPD2_INTERRUPT
;
1909 queue_hotplug
= true;
1910 DRM_DEBUG("IH: HPD2\n");
1914 if (disp_int_cont2
& DC_HPD3_INTERRUPT
) {
1915 disp_int_cont2
&= ~DC_HPD3_INTERRUPT
;
1916 queue_hotplug
= true;
1917 DRM_DEBUG("IH: HPD3\n");
1921 if (disp_int_cont3
& DC_HPD4_INTERRUPT
) {
1922 disp_int_cont3
&= ~DC_HPD4_INTERRUPT
;
1923 queue_hotplug
= true;
1924 DRM_DEBUG("IH: HPD4\n");
1928 if (disp_int_cont4
& DC_HPD5_INTERRUPT
) {
1929 disp_int_cont4
&= ~DC_HPD5_INTERRUPT
;
1930 queue_hotplug
= true;
1931 DRM_DEBUG("IH: HPD5\n");
1935 if (disp_int_cont5
& DC_HPD6_INTERRUPT
) {
1936 disp_int_cont5
&= ~DC_HPD6_INTERRUPT
;
1937 queue_hotplug
= true;
1938 DRM_DEBUG("IH: HPD6\n");
1942 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
1946 case 176: /* CP_INT in ring buffer */
1947 case 177: /* CP_INT in IB1 */
1948 case 178: /* CP_INT in IB2 */
1949 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data
);
1950 radeon_fence_process(rdev
);
1952 case 181: /* CP EOP event */
1953 DRM_DEBUG("IH: CP EOP\n");
1955 case 233: /* GUI IDLE */
1956 DRM_DEBUG("IH: CP EOP\n");
1957 rdev
->pm
.gui_idle
= true;
1958 wake_up(&rdev
->irq
.idle_queue
);
1961 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
1965 /* wptr/rptr are in bytes! */
1967 rptr
&= rdev
->ih
.ptr_mask
;
1969 /* make sure wptr hasn't changed while processing */
1970 wptr
= evergreen_get_ih_wptr(rdev
);
1971 if (wptr
!= rdev
->ih
.wptr
)
1974 queue_work(rdev
->wq
, &rdev
->hotplug_work
);
1975 rdev
->ih
.rptr
= rptr
;
1976 WREG32(IH_RB_RPTR
, rdev
->ih
.rptr
);
1977 spin_unlock_irqrestore(&rdev
->ih
.lock
, flags
);
1981 static int evergreen_startup(struct radeon_device
*rdev
)
1985 if (!rdev
->me_fw
|| !rdev
->pfp_fw
|| !rdev
->rlc_fw
) {
1986 r
= r600_init_microcode(rdev
);
1988 DRM_ERROR("Failed to load firmware!\n");
1993 evergreen_mc_program(rdev
);
1994 if (rdev
->flags
& RADEON_IS_AGP
) {
1995 evergreen_agp_enable(rdev
);
1997 r
= evergreen_pcie_gart_enable(rdev
);
2001 evergreen_gpu_init(rdev
);
2003 if (!rdev
->r600_blit
.shader_obj
) {
2004 r
= r600_blit_init(rdev
);
2006 DRM_ERROR("radeon: failed blitter (%d).\n", r
);
2011 r
= radeon_bo_reserve(rdev
->r600_blit
.shader_obj
, false);
2012 if (unlikely(r
!= 0))
2014 r
= radeon_bo_pin(rdev
->r600_blit
.shader_obj
, RADEON_GEM_DOMAIN_VRAM
,
2015 &rdev
->r600_blit
.shader_gpu_addr
);
2016 radeon_bo_unreserve(rdev
->r600_blit
.shader_obj
);
2018 DRM_ERROR("failed to pin blit object %d\n", r
);
2024 r
= r600_irq_init(rdev
);
2026 DRM_ERROR("radeon: IH init failed (%d).\n", r
);
2027 radeon_irq_kms_fini(rdev
);
2030 evergreen_irq_set(rdev
);
2032 r
= radeon_ring_init(rdev
, rdev
->cp
.ring_size
);
2035 r
= evergreen_cp_load_microcode(rdev
);
2038 r
= evergreen_cp_resume(rdev
);
2041 /* write back buffer are not vital so don't worry about failure */
2042 r600_wb_enable(rdev
);
2047 int evergreen_resume(struct radeon_device
*rdev
)
2051 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2052 * posting will perform necessary task to bring back GPU into good
2056 atom_asic_init(rdev
->mode_info
.atom_context
);
2057 /* Initialize clocks */
2058 r
= radeon_clocks_init(rdev
);
2063 r
= evergreen_startup(rdev
);
2065 DRM_ERROR("r600 startup failed on resume\n");
2069 r
= r600_ib_test(rdev
);
2071 DRM_ERROR("radeon: failled testing IB (%d).\n", r
);
2079 int evergreen_suspend(struct radeon_device
*rdev
)
2084 /* FIXME: we should wait for ring to be empty */
2086 rdev
->cp
.ready
= false;
2087 evergreen_irq_suspend(rdev
);
2088 r600_wb_disable(rdev
);
2089 evergreen_pcie_gart_disable(rdev
);
2091 /* unpin shaders bo */
2092 r
= radeon_bo_reserve(rdev
->r600_blit
.shader_obj
, false);
2093 if (likely(r
== 0)) {
2094 radeon_bo_unpin(rdev
->r600_blit
.shader_obj
);
2095 radeon_bo_unreserve(rdev
->r600_blit
.shader_obj
);
2101 static bool evergreen_card_posted(struct radeon_device
*rdev
)
2105 /* first check CRTCs */
2106 reg
= RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
) |
2107 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
) |
2108 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
) |
2109 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
) |
2110 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
) |
2111 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
2112 if (reg
& EVERGREEN_CRTC_MASTER_EN
)
2115 /* then check MEM_SIZE, in case the crtcs are off */
2116 if (RREG32(CONFIG_MEMSIZE
))
2122 /* Plan is to move initialization in that function and use
2123 * helper function so that radeon_device_init pretty much
2124 * do nothing more than calling asic specific function. This
2125 * should also allow to remove a bunch of callback function
2128 int evergreen_init(struct radeon_device
*rdev
)
2132 r
= radeon_dummy_page_init(rdev
);
2135 /* This don't do much */
2136 r
= radeon_gem_init(rdev
);
2140 if (!radeon_get_bios(rdev
)) {
2141 if (ASIC_IS_AVIVO(rdev
))
2144 /* Must be an ATOMBIOS */
2145 if (!rdev
->is_atom_bios
) {
2146 dev_err(rdev
->dev
, "Expecting atombios for R600 GPU\n");
2149 r
= radeon_atombios_init(rdev
);
2152 /* Post card if necessary */
2153 if (!evergreen_card_posted(rdev
)) {
2155 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
2158 DRM_INFO("GPU not posted. posting now...\n");
2159 atom_asic_init(rdev
->mode_info
.atom_context
);
2161 /* Initialize scratch registers */
2162 r600_scratch_init(rdev
);
2163 /* Initialize surface registers */
2164 radeon_surface_init(rdev
);
2165 /* Initialize clocks */
2166 radeon_get_clock_info(rdev
->ddev
);
2167 r
= radeon_clocks_init(rdev
);
2171 r
= radeon_fence_driver_init(rdev
);
2174 /* initialize AGP */
2175 if (rdev
->flags
& RADEON_IS_AGP
) {
2176 r
= radeon_agp_init(rdev
);
2178 radeon_agp_disable(rdev
);
2180 /* initialize memory controller */
2181 r
= evergreen_mc_init(rdev
);
2184 /* Memory manager */
2185 r
= radeon_bo_init(rdev
);
2189 r
= radeon_irq_kms_init(rdev
);
2193 rdev
->cp
.ring_obj
= NULL
;
2194 r600_ring_init(rdev
, 1024 * 1024);
2196 rdev
->ih
.ring_obj
= NULL
;
2197 r600_ih_ring_init(rdev
, 64 * 1024);
2199 r
= r600_pcie_gart_init(rdev
);
2203 rdev
->accel_working
= true;
2204 r
= evergreen_startup(rdev
);
2206 dev_err(rdev
->dev
, "disabling GPU acceleration\n");
2209 r600_irq_fini(rdev
);
2210 radeon_irq_kms_fini(rdev
);
2211 evergreen_pcie_gart_fini(rdev
);
2212 rdev
->accel_working
= false;
2214 if (rdev
->accel_working
) {
2215 r
= radeon_ib_pool_init(rdev
);
2217 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r
);
2218 rdev
->accel_working
= false;
2220 r
= r600_ib_test(rdev
);
2222 DRM_ERROR("radeon: failed testing IB (%d).\n", r
);
2223 rdev
->accel_working
= false;
2229 void evergreen_fini(struct radeon_device
*rdev
)
2231 /*r600_blit_fini(rdev);*/
2234 r600_irq_fini(rdev
);
2235 radeon_irq_kms_fini(rdev
);
2236 evergreen_pcie_gart_fini(rdev
);
2237 radeon_gem_fini(rdev
);
2238 radeon_fence_driver_fini(rdev
);
2239 radeon_clocks_fini(rdev
);
2240 radeon_agp_fini(rdev
);
2241 radeon_bo_fini(rdev
);
2242 radeon_atombios_fini(rdev
);
2245 radeon_dummy_page_fini(rdev
);