2 * Copyright 2010 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Alex Deucher <alexander.deucher@amd.com>
28 #include <drm/radeon_drm.h>
31 #include "evergreend.h"
32 #include "evergreen_blit_shaders.h"
33 #include "cayman_blit_shaders.h"
34 #include "radeon_blit_common.h"
38 set_render_target(struct radeon_device
*rdev
, int format
,
39 int w
, int h
, u64 gpu_addr
)
41 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
49 cb_color_info
= CB_FORMAT(format
) |
50 CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM
) |
51 CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1
);
53 slice
= ((w
* h
) / 64) - 1;
55 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONTEXT_REG
, 15));
56 radeon_ring_write(ring
, (CB_COLOR0_BASE
- PACKET3_SET_CONTEXT_REG_START
) >> 2);
57 radeon_ring_write(ring
, gpu_addr
>> 8);
58 radeon_ring_write(ring
, pitch
);
59 radeon_ring_write(ring
, slice
);
60 radeon_ring_write(ring
, 0);
61 radeon_ring_write(ring
, cb_color_info
);
62 radeon_ring_write(ring
, 0);
63 radeon_ring_write(ring
, (w
- 1) | ((h
- 1) << 16));
64 radeon_ring_write(ring
, 0);
65 radeon_ring_write(ring
, 0);
66 radeon_ring_write(ring
, 0);
67 radeon_ring_write(ring
, 0);
68 radeon_ring_write(ring
, 0);
69 radeon_ring_write(ring
, 0);
70 radeon_ring_write(ring
, 0);
71 radeon_ring_write(ring
, 0);
76 cp_set_surface_sync(struct radeon_device
*rdev
,
77 u32 sync_type
, u32 size
,
80 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
83 if (size
== 0xffffffff)
84 cp_coher_size
= 0xffffffff;
86 cp_coher_size
= ((size
+ 255) >> 8);
88 if (rdev
->family
>= CHIP_CAYMAN
) {
89 /* CP_COHER_CNTL2 has to be set manually when submitting a surface_sync
90 * to the RB directly. For IBs, the CP programs this as part of the
91 * surface_sync packet.
93 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
94 radeon_ring_write(ring
, (0x85e8 - PACKET3_SET_CONFIG_REG_START
) >> 2);
95 radeon_ring_write(ring
, 0); /* CP_COHER_CNTL2 */
97 radeon_ring_write(ring
, PACKET3(PACKET3_SURFACE_SYNC
, 3));
98 radeon_ring_write(ring
, sync_type
);
99 radeon_ring_write(ring
, cp_coher_size
);
100 radeon_ring_write(ring
, mc_addr
>> 8);
101 radeon_ring_write(ring
, 10); /* poll interval */
104 /* emits 11dw + 1 surface sync = 16dw */
106 set_shaders(struct radeon_device
*rdev
)
108 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
112 gpu_addr
= rdev
->r600_blit
.shader_gpu_addr
+ rdev
->r600_blit
.vs_offset
;
113 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONTEXT_REG
, 3));
114 radeon_ring_write(ring
, (SQ_PGM_START_VS
- PACKET3_SET_CONTEXT_REG_START
) >> 2);
115 radeon_ring_write(ring
, gpu_addr
>> 8);
116 radeon_ring_write(ring
, 2);
117 radeon_ring_write(ring
, 0);
120 gpu_addr
= rdev
->r600_blit
.shader_gpu_addr
+ rdev
->r600_blit
.ps_offset
;
121 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONTEXT_REG
, 4));
122 radeon_ring_write(ring
, (SQ_PGM_START_PS
- PACKET3_SET_CONTEXT_REG_START
) >> 2);
123 radeon_ring_write(ring
, gpu_addr
>> 8);
124 radeon_ring_write(ring
, 1);
125 radeon_ring_write(ring
, 0);
126 radeon_ring_write(ring
, 2);
128 gpu_addr
= rdev
->r600_blit
.shader_gpu_addr
+ rdev
->r600_blit
.vs_offset
;
129 cp_set_surface_sync(rdev
, PACKET3_SH_ACTION_ENA
, 512, gpu_addr
);
132 /* emits 10 + 1 sync (5) = 15 */
134 set_vtx_resource(struct radeon_device
*rdev
, u64 gpu_addr
)
136 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
137 u32 sq_vtx_constant_word2
, sq_vtx_constant_word3
;
139 /* high addr, stride */
140 sq_vtx_constant_word2
= SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr
) & 0xff) |
143 sq_vtx_constant_word2
|= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32
);
146 sq_vtx_constant_word3
= SQ_VTCX_SEL_X(SQ_SEL_X
) |
147 SQ_VTCX_SEL_Y(SQ_SEL_Y
) |
148 SQ_VTCX_SEL_Z(SQ_SEL_Z
) |
149 SQ_VTCX_SEL_W(SQ_SEL_W
);
151 radeon_ring_write(ring
, PACKET3(PACKET3_SET_RESOURCE
, 8));
152 radeon_ring_write(ring
, 0x580);
153 radeon_ring_write(ring
, gpu_addr
& 0xffffffff);
154 radeon_ring_write(ring
, 48 - 1); /* size */
155 radeon_ring_write(ring
, sq_vtx_constant_word2
);
156 radeon_ring_write(ring
, sq_vtx_constant_word3
);
157 radeon_ring_write(ring
, 0);
158 radeon_ring_write(ring
, 0);
159 radeon_ring_write(ring
, 0);
160 radeon_ring_write(ring
, S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_BUFFER
));
162 if ((rdev
->family
== CHIP_CEDAR
) ||
163 (rdev
->family
== CHIP_PALM
) ||
164 (rdev
->family
== CHIP_SUMO
) ||
165 (rdev
->family
== CHIP_SUMO2
) ||
166 (rdev
->family
== CHIP_CAICOS
))
167 cp_set_surface_sync(rdev
,
168 PACKET3_TC_ACTION_ENA
, 48, gpu_addr
);
170 cp_set_surface_sync(rdev
,
171 PACKET3_VC_ACTION_ENA
, 48, gpu_addr
);
177 set_tex_resource(struct radeon_device
*rdev
,
178 int format
, int w
, int h
, int pitch
,
179 u64 gpu_addr
, u32 size
)
181 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
182 u32 sq_tex_resource_word0
, sq_tex_resource_word1
;
183 u32 sq_tex_resource_word4
, sq_tex_resource_word7
;
188 sq_tex_resource_word0
= TEX_DIM(SQ_TEX_DIM_2D
);
189 sq_tex_resource_word0
|= ((((pitch
>> 3) - 1) << 6) |
191 sq_tex_resource_word1
= ((h
- 1) << 0) |
192 TEX_ARRAY_MODE(ARRAY_1D_TILED_THIN1
);
194 sq_tex_resource_word4
= TEX_DST_SEL_X(SQ_SEL_X
) |
195 TEX_DST_SEL_Y(SQ_SEL_Y
) |
196 TEX_DST_SEL_Z(SQ_SEL_Z
) |
197 TEX_DST_SEL_W(SQ_SEL_W
);
199 sq_tex_resource_word7
= format
|
200 S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_TEXTURE
);
202 cp_set_surface_sync(rdev
,
203 PACKET3_TC_ACTION_ENA
, size
, gpu_addr
);
205 radeon_ring_write(ring
, PACKET3(PACKET3_SET_RESOURCE
, 8));
206 radeon_ring_write(ring
, 0);
207 radeon_ring_write(ring
, sq_tex_resource_word0
);
208 radeon_ring_write(ring
, sq_tex_resource_word1
);
209 radeon_ring_write(ring
, gpu_addr
>> 8);
210 radeon_ring_write(ring
, gpu_addr
>> 8);
211 radeon_ring_write(ring
, sq_tex_resource_word4
);
212 radeon_ring_write(ring
, 0);
213 radeon_ring_write(ring
, 0);
214 radeon_ring_write(ring
, sq_tex_resource_word7
);
219 set_scissors(struct radeon_device
*rdev
, int x1
, int y1
,
222 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
223 /* workaround some hw bugs */
228 if (rdev
->family
>= CHIP_CAYMAN
) {
229 if ((x2
== 1) && (y2
== 1))
233 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONTEXT_REG
, 2));
234 radeon_ring_write(ring
, (PA_SC_SCREEN_SCISSOR_TL
- PACKET3_SET_CONTEXT_REG_START
) >> 2);
235 radeon_ring_write(ring
, (x1
<< 0) | (y1
<< 16));
236 radeon_ring_write(ring
, (x2
<< 0) | (y2
<< 16));
238 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONTEXT_REG
, 2));
239 radeon_ring_write(ring
, (PA_SC_GENERIC_SCISSOR_TL
- PACKET3_SET_CONTEXT_REG_START
) >> 2);
240 radeon_ring_write(ring
, (x1
<< 0) | (y1
<< 16) | (1 << 31));
241 radeon_ring_write(ring
, (x2
<< 0) | (y2
<< 16));
243 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONTEXT_REG
, 2));
244 radeon_ring_write(ring
, (PA_SC_WINDOW_SCISSOR_TL
- PACKET3_SET_CONTEXT_REG_START
) >> 2);
245 radeon_ring_write(ring
, (x1
<< 0) | (y1
<< 16) | (1 << 31));
246 radeon_ring_write(ring
, (x2
<< 0) | (y2
<< 16));
251 draw_auto(struct radeon_device
*rdev
)
253 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
254 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
255 radeon_ring_write(ring
, (VGT_PRIMITIVE_TYPE
- PACKET3_SET_CONFIG_REG_START
) >> 2);
256 radeon_ring_write(ring
, DI_PT_RECTLIST
);
258 radeon_ring_write(ring
, PACKET3(PACKET3_INDEX_TYPE
, 0));
259 radeon_ring_write(ring
,
263 DI_INDEX_SIZE_16_BIT
);
265 radeon_ring_write(ring
, PACKET3(PACKET3_NUM_INSTANCES
, 0));
266 radeon_ring_write(ring
, 1);
268 radeon_ring_write(ring
, PACKET3(PACKET3_DRAW_INDEX_AUTO
, 1));
269 radeon_ring_write(ring
, 3);
270 radeon_ring_write(ring
, DI_SRC_SEL_AUTO_INDEX
);
276 set_default_state(struct radeon_device
*rdev
)
278 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
279 u32 sq_config
, sq_gpr_resource_mgmt_1
, sq_gpr_resource_mgmt_2
, sq_gpr_resource_mgmt_3
;
280 u32 sq_thread_resource_mgmt
, sq_thread_resource_mgmt_2
;
281 u32 sq_stack_resource_mgmt_1
, sq_stack_resource_mgmt_2
, sq_stack_resource_mgmt_3
;
282 int num_ps_gprs
, num_vs_gprs
, num_temp_gprs
;
283 int num_gs_gprs
, num_es_gprs
, num_hs_gprs
, num_ls_gprs
;
284 int num_ps_threads
, num_vs_threads
, num_gs_threads
, num_es_threads
;
285 int num_hs_threads
, num_ls_threads
;
286 int num_ps_stack_entries
, num_vs_stack_entries
, num_gs_stack_entries
, num_es_stack_entries
;
287 int num_hs_stack_entries
, num_ls_stack_entries
;
291 /* set clear context state */
292 radeon_ring_write(ring
, PACKET3(PACKET3_CLEAR_STATE
, 0));
293 radeon_ring_write(ring
, 0);
295 if (rdev
->family
< CHIP_CAYMAN
) {
296 switch (rdev
->family
) {
312 num_ps_stack_entries
= 42;
313 num_vs_stack_entries
= 42;
314 num_gs_stack_entries
= 42;
315 num_es_stack_entries
= 42;
316 num_hs_stack_entries
= 42;
317 num_ls_stack_entries
= 42;
327 num_ps_threads
= 128;
333 num_ps_stack_entries
= 42;
334 num_vs_stack_entries
= 42;
335 num_gs_stack_entries
= 42;
336 num_es_stack_entries
= 42;
337 num_hs_stack_entries
= 42;
338 num_ls_stack_entries
= 42;
348 num_ps_threads
= 128;
354 num_ps_stack_entries
= 85;
355 num_vs_stack_entries
= 85;
356 num_gs_stack_entries
= 85;
357 num_es_stack_entries
= 85;
358 num_hs_stack_entries
= 85;
359 num_ls_stack_entries
= 85;
370 num_ps_threads
= 128;
376 num_ps_stack_entries
= 85;
377 num_vs_stack_entries
= 85;
378 num_gs_stack_entries
= 85;
379 num_es_stack_entries
= 85;
380 num_hs_stack_entries
= 85;
381 num_ls_stack_entries
= 85;
397 num_ps_stack_entries
= 42;
398 num_vs_stack_entries
= 42;
399 num_gs_stack_entries
= 42;
400 num_es_stack_entries
= 42;
401 num_hs_stack_entries
= 42;
402 num_ls_stack_entries
= 42;
418 num_ps_stack_entries
= 42;
419 num_vs_stack_entries
= 42;
420 num_gs_stack_entries
= 42;
421 num_es_stack_entries
= 42;
422 num_hs_stack_entries
= 42;
423 num_ls_stack_entries
= 42;
439 num_ps_stack_entries
= 85;
440 num_vs_stack_entries
= 85;
441 num_gs_stack_entries
= 85;
442 num_es_stack_entries
= 85;
443 num_hs_stack_entries
= 85;
444 num_ls_stack_entries
= 85;
454 num_ps_threads
= 128;
460 num_ps_stack_entries
= 85;
461 num_vs_stack_entries
= 85;
462 num_gs_stack_entries
= 85;
463 num_es_stack_entries
= 85;
464 num_hs_stack_entries
= 85;
465 num_ls_stack_entries
= 85;
475 num_ps_threads
= 128;
481 num_ps_stack_entries
= 42;
482 num_vs_stack_entries
= 42;
483 num_gs_stack_entries
= 42;
484 num_es_stack_entries
= 42;
485 num_hs_stack_entries
= 42;
486 num_ls_stack_entries
= 42;
496 num_ps_threads
= 128;
502 num_ps_stack_entries
= 42;
503 num_vs_stack_entries
= 42;
504 num_gs_stack_entries
= 42;
505 num_es_stack_entries
= 42;
506 num_hs_stack_entries
= 42;
507 num_ls_stack_entries
= 42;
511 if ((rdev
->family
== CHIP_CEDAR
) ||
512 (rdev
->family
== CHIP_PALM
) ||
513 (rdev
->family
== CHIP_SUMO
) ||
514 (rdev
->family
== CHIP_SUMO2
) ||
515 (rdev
->family
== CHIP_CAICOS
))
518 sq_config
= VC_ENABLE
;
520 sq_config
|= (EXPORT_SRC_C
|
529 sq_gpr_resource_mgmt_1
= (NUM_PS_GPRS(num_ps_gprs
) |
530 NUM_VS_GPRS(num_vs_gprs
) |
531 NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
));
532 sq_gpr_resource_mgmt_2
= (NUM_GS_GPRS(num_gs_gprs
) |
533 NUM_ES_GPRS(num_es_gprs
));
534 sq_gpr_resource_mgmt_3
= (NUM_HS_GPRS(num_hs_gprs
) |
535 NUM_LS_GPRS(num_ls_gprs
));
536 sq_thread_resource_mgmt
= (NUM_PS_THREADS(num_ps_threads
) |
537 NUM_VS_THREADS(num_vs_threads
) |
538 NUM_GS_THREADS(num_gs_threads
) |
539 NUM_ES_THREADS(num_es_threads
));
540 sq_thread_resource_mgmt_2
= (NUM_HS_THREADS(num_hs_threads
) |
541 NUM_LS_THREADS(num_ls_threads
));
542 sq_stack_resource_mgmt_1
= (NUM_PS_STACK_ENTRIES(num_ps_stack_entries
) |
543 NUM_VS_STACK_ENTRIES(num_vs_stack_entries
));
544 sq_stack_resource_mgmt_2
= (NUM_GS_STACK_ENTRIES(num_gs_stack_entries
) |
545 NUM_ES_STACK_ENTRIES(num_es_stack_entries
));
546 sq_stack_resource_mgmt_3
= (NUM_HS_STACK_ENTRIES(num_hs_stack_entries
) |
547 NUM_LS_STACK_ENTRIES(num_ls_stack_entries
));
549 /* disable dyn gprs */
550 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
551 radeon_ring_write(ring
, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
- PACKET3_SET_CONFIG_REG_START
) >> 2);
552 radeon_ring_write(ring
, 0);
555 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
556 radeon_ring_write(ring
, (SQ_LDS_RESOURCE_MGMT
- PACKET3_SET_CONFIG_REG_START
) >> 2);
557 radeon_ring_write(ring
, 0x10001000);
560 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 11));
561 radeon_ring_write(ring
, (SQ_CONFIG
- PACKET3_SET_CONFIG_REG_START
) >> 2);
562 radeon_ring_write(ring
, sq_config
);
563 radeon_ring_write(ring
, sq_gpr_resource_mgmt_1
);
564 radeon_ring_write(ring
, sq_gpr_resource_mgmt_2
);
565 radeon_ring_write(ring
, sq_gpr_resource_mgmt_3
);
566 radeon_ring_write(ring
, 0);
567 radeon_ring_write(ring
, 0);
568 radeon_ring_write(ring
, sq_thread_resource_mgmt
);
569 radeon_ring_write(ring
, sq_thread_resource_mgmt_2
);
570 radeon_ring_write(ring
, sq_stack_resource_mgmt_1
);
571 radeon_ring_write(ring
, sq_stack_resource_mgmt_2
);
572 radeon_ring_write(ring
, sq_stack_resource_mgmt_3
);
575 /* CONTEXT_CONTROL */
576 radeon_ring_write(ring
, 0xc0012800);
577 radeon_ring_write(ring
, 0x80000000);
578 radeon_ring_write(ring
, 0x80000000);
580 /* SQ_VTX_BASE_VTX_LOC */
581 radeon_ring_write(ring
, 0xc0026f00);
582 radeon_ring_write(ring
, 0x00000000);
583 radeon_ring_write(ring
, 0x00000000);
584 radeon_ring_write(ring
, 0x00000000);
587 radeon_ring_write(ring
, 0xc0036e00);
588 radeon_ring_write(ring
, 0x00000000);
589 radeon_ring_write(ring
, 0x00000012);
590 radeon_ring_write(ring
, 0x00000000);
591 radeon_ring_write(ring
, 0x00000000);
593 /* set to DX10/11 mode */
594 radeon_ring_write(ring
, PACKET3(PACKET3_MODE_CONTROL
, 0));
595 radeon_ring_write(ring
, 1);
597 /* emit an IB pointing at default state */
598 dwords
= ALIGN(rdev
->r600_blit
.state_len
, 0x10);
599 gpu_addr
= rdev
->r600_blit
.shader_gpu_addr
+ rdev
->r600_blit
.state_offset
;
600 radeon_ring_write(ring
, PACKET3(PACKET3_INDIRECT_BUFFER
, 2));
601 radeon_ring_write(ring
, gpu_addr
& 0xFFFFFFFC);
602 radeon_ring_write(ring
, upper_32_bits(gpu_addr
) & 0xFF);
603 radeon_ring_write(ring
, dwords
);
607 int evergreen_blit_init(struct radeon_device
*rdev
)
613 int num_packet2s
= 0;
615 rdev
->r600_blit
.primitives
.set_render_target
= set_render_target
;
616 rdev
->r600_blit
.primitives
.cp_set_surface_sync
= cp_set_surface_sync
;
617 rdev
->r600_blit
.primitives
.set_shaders
= set_shaders
;
618 rdev
->r600_blit
.primitives
.set_vtx_resource
= set_vtx_resource
;
619 rdev
->r600_blit
.primitives
.set_tex_resource
= set_tex_resource
;
620 rdev
->r600_blit
.primitives
.set_scissors
= set_scissors
;
621 rdev
->r600_blit
.primitives
.draw_auto
= draw_auto
;
622 rdev
->r600_blit
.primitives
.set_default_state
= set_default_state
;
624 rdev
->r600_blit
.ring_size_common
= 8; /* sync semaphore */
625 rdev
->r600_blit
.ring_size_common
+= 55; /* shaders + def state */
626 rdev
->r600_blit
.ring_size_common
+= 16; /* fence emit for VB IB */
627 rdev
->r600_blit
.ring_size_common
+= 5; /* done copy */
628 rdev
->r600_blit
.ring_size_common
+= 16; /* fence emit for done copy */
630 rdev
->r600_blit
.ring_size_per_loop
= 74;
631 if (rdev
->family
>= CHIP_CAYMAN
)
632 rdev
->r600_blit
.ring_size_per_loop
+= 9; /* additional DWs for surface sync */
634 rdev
->r600_blit
.max_dim
= 16384;
636 rdev
->r600_blit
.state_offset
= 0;
638 if (rdev
->family
< CHIP_CAYMAN
)
639 rdev
->r600_blit
.state_len
= evergreen_default_size
;
641 rdev
->r600_blit
.state_len
= cayman_default_size
;
643 dwords
= rdev
->r600_blit
.state_len
;
644 while (dwords
& 0xf) {
645 packet2s
[num_packet2s
++] = cpu_to_le32(PACKET2(0));
649 obj_size
= dwords
* 4;
650 obj_size
= ALIGN(obj_size
, 256);
652 rdev
->r600_blit
.vs_offset
= obj_size
;
653 if (rdev
->family
< CHIP_CAYMAN
)
654 obj_size
+= evergreen_vs_size
* 4;
656 obj_size
+= cayman_vs_size
* 4;
657 obj_size
= ALIGN(obj_size
, 256);
659 rdev
->r600_blit
.ps_offset
= obj_size
;
660 if (rdev
->family
< CHIP_CAYMAN
)
661 obj_size
+= evergreen_ps_size
* 4;
663 obj_size
+= cayman_ps_size
* 4;
664 obj_size
= ALIGN(obj_size
, 256);
666 /* pin copy shader into vram if not already initialized */
667 if (!rdev
->r600_blit
.shader_obj
) {
668 r
= radeon_bo_create(rdev
, obj_size
, PAGE_SIZE
, true,
669 RADEON_GEM_DOMAIN_VRAM
,
670 NULL
, &rdev
->r600_blit
.shader_obj
);
672 DRM_ERROR("evergreen failed to allocate shader\n");
676 r
= radeon_bo_reserve(rdev
->r600_blit
.shader_obj
, false);
677 if (unlikely(r
!= 0))
679 r
= radeon_bo_pin(rdev
->r600_blit
.shader_obj
, RADEON_GEM_DOMAIN_VRAM
,
680 &rdev
->r600_blit
.shader_gpu_addr
);
681 radeon_bo_unreserve(rdev
->r600_blit
.shader_obj
);
683 dev_err(rdev
->dev
, "(%d) pin blit object failed\n", r
);
688 DRM_DEBUG("evergreen blit allocated bo %08x vs %08x ps %08x\n",
690 rdev
->r600_blit
.vs_offset
, rdev
->r600_blit
.ps_offset
);
692 r
= radeon_bo_reserve(rdev
->r600_blit
.shader_obj
, false);
693 if (unlikely(r
!= 0))
695 r
= radeon_bo_kmap(rdev
->r600_blit
.shader_obj
, &ptr
);
697 DRM_ERROR("failed to map blit object %d\n", r
);
701 if (rdev
->family
< CHIP_CAYMAN
) {
702 memcpy_toio(ptr
+ rdev
->r600_blit
.state_offset
,
703 evergreen_default_state
, rdev
->r600_blit
.state_len
* 4);
706 memcpy_toio(ptr
+ rdev
->r600_blit
.state_offset
+ (rdev
->r600_blit
.state_len
* 4),
707 packet2s
, num_packet2s
* 4);
708 for (i
= 0; i
< evergreen_vs_size
; i
++)
709 *(u32
*)((unsigned long)ptr
+ rdev
->r600_blit
.vs_offset
+ i
* 4) = cpu_to_le32(evergreen_vs
[i
]);
710 for (i
= 0; i
< evergreen_ps_size
; i
++)
711 *(u32
*)((unsigned long)ptr
+ rdev
->r600_blit
.ps_offset
+ i
* 4) = cpu_to_le32(evergreen_ps
[i
]);
713 memcpy_toio(ptr
+ rdev
->r600_blit
.state_offset
,
714 cayman_default_state
, rdev
->r600_blit
.state_len
* 4);
717 memcpy_toio(ptr
+ rdev
->r600_blit
.state_offset
+ (rdev
->r600_blit
.state_len
* 4),
718 packet2s
, num_packet2s
* 4);
719 for (i
= 0; i
< cayman_vs_size
; i
++)
720 *(u32
*)((unsigned long)ptr
+ rdev
->r600_blit
.vs_offset
+ i
* 4) = cpu_to_le32(cayman_vs
[i
]);
721 for (i
= 0; i
< cayman_ps_size
; i
++)
722 *(u32
*)((unsigned long)ptr
+ rdev
->r600_blit
.ps_offset
+ i
* 4) = cpu_to_le32(cayman_ps
[i
]);
724 radeon_bo_kunmap(rdev
->r600_blit
.shader_obj
);
725 radeon_bo_unreserve(rdev
->r600_blit
.shader_obj
);
727 radeon_ttm_set_active_vram_size(rdev
, rdev
->mc
.real_vram_size
);