drivers/gpu/drm/radeon/evergreen_hdmi.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Christian König.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Christian König
  25  *          Rafał Miłecki
  26  */
  27 #include <linux/hdmi.h>
  28 #include <drm/drmP.h>
  29 #include <drm/radeon_drm.h>
  30 #include "radeon.h"
  31 #include "radeon_asic.h"
  32 #include "evergreend.h"
  33 #include "atom.h"
  34
  35 extern void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder);
  36 extern void dce6_afmt_write_sad_regs(struct drm_encoder *encoder);
  37 extern void dce6_afmt_select_pin(struct drm_encoder *encoder);
  38
  39 /*
  40  * update the N and CTS parameters for a given pixel clock rate
  41  */
  42 static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
  43 {
  44         struct drm_device *dev = encoder->dev;
  45         struct radeon_device *rdev = dev->dev_private;
  46         struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
  47         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  48         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  49         uint32_t offset = dig->afmt->offset;
  50
  51         WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz));
  52         WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz);
  53
  54         WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz));
  55         WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz);
  56
  57         WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz));
  58         WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
  59 }
  60
  61 static void dce4_afmt_write_speaker_allocation(struct drm_encoder *encoder)
  62 {
  63         struct radeon_device *rdev = encoder->dev->dev_private;
  64         struct drm_connector *connector;
  65         struct radeon_connector *radeon_connector = NULL;
  66         u32 tmp;
  67         u8 *sadb;
  68         int sad_count;
  69
  70         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
  71                 if (connector->encoder == encoder) {
  72                         radeon_connector = to_radeon_connector(connector);
  73                         break;
  74                 }
  75         }
  76
  77         if (!radeon_connector) {
  78                 DRM_ERROR("Couldn't find encoder's connector\n");
  79                 return;
  80         }
  81
  82         sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb);
  83         if (sad_count < 0) {
  84                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
  85                 return;
  86         }
  87
  88         /* program the speaker allocation */
  89         tmp = RREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
  90         tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
  91         /* set HDMI mode */
  92         tmp |= HDMI_CONNECTION;
  93         if (sad_count)
  94                 tmp |= SPEAKER_ALLOCATION(sadb[0]);
  95         else
  96                 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
  97         WREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
  98
  99         kfree(sadb);
 100 }
 101
 102 static void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder)
 103 {
 104         struct radeon_device *rdev = encoder->dev->dev_private;
 105         struct drm_connector *connector;
 106         struct radeon_connector *radeon_connector = NULL;
 107         struct cea_sad *sads;
 108         int i, sad_count;
 109
 110         static const u16 eld_reg_to_type[][2] = {
 111                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
 112                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
 113                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
 114                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
 115                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
 116                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
 117                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
 118                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
 119                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
 120                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
 121                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
 122                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
 123         };
 124
 125         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
 126                 if (connector->encoder == encoder) {
 127                         radeon_connector = to_radeon_connector(connector);
 128                         break;
 129                 }
 130         }
 131
 132         if (!radeon_connector) {
 133                 DRM_ERROR("Couldn't find encoder's connector\n");
 134                 return;
 135         }
 136
 137         sad_count = drm_edid_to_sad(radeon_connector->edid, &sads);
 138         if (sad_count < 0) {
 139                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
 140                 return;
 141         }
 142         BUG_ON(!sads);
 143
 144         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
 145                 u32 value = 0;
 146                 int j;
 147
 148                 for (j = 0; j < sad_count; j++) {
 149                         struct cea_sad *sad = &sads[j];
 150
 151                         if (sad->format == eld_reg_to_type[i][1]) {
 152                                 value = MAX_CHANNELS(sad->channels) |
 153                                         DESCRIPTOR_BYTE_2(sad->byte2) |
 154                                         SUPPORTED_FREQUENCIES(sad->freq);
 155                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
 156                                         value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq);
 157                                 break;
 158                         }
 159                 }
 160                 WREG32(eld_reg_to_type[i][0], value);
 161         }
 162
 163         kfree(sads);
 164 }
 165
 166 /*
 167  * build a HDMI Video Info Frame
 168  */
 169 static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder,
 170                                                 void *buffer, size_t size)
 171 {
 172         struct drm_device *dev = encoder->dev;
 173         struct radeon_device *rdev = dev->dev_private;
 174         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 175         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 176         uint32_t offset = dig->afmt->offset;
 177         uint8_t *frame = buffer + 3;
 178         uint8_t *header = buffer;
 179
 180         WREG32(AFMT_AVI_INFO0 + offset,
 181                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
 182         WREG32(AFMT_AVI_INFO1 + offset,
 183                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
 184         WREG32(AFMT_AVI_INFO2 + offset,
 185                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
 186         WREG32(AFMT_AVI_INFO3 + offset,
 187                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
 188 }
 189
 190 static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock)
 191 {
 192         struct drm_device *dev = encoder->dev;
 193         struct radeon_device *rdev = dev->dev_private;
 194         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 195         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 196         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 197         u32 base_rate = 24000;
 198         u32 max_ratio = clock / base_rate;
 199         u32 dto_phase;
 200         u32 dto_modulo = clock;
 201         u32 wallclock_ratio;
 202         u32 dto_cntl;
 203
 204         if (!dig || !dig->afmt)
 205                 return;
 206
 207         if (ASIC_IS_DCE6(rdev)) {
 208                 dto_phase = 24 * 1000;
 209         } else {
 210                 if (max_ratio >= 8) {
 211                         dto_phase = 192 * 1000;
 212                         wallclock_ratio = 3;
 213                 } else if (max_ratio >= 4) {
 214                         dto_phase = 96 * 1000;
 215                         wallclock_ratio = 2;
 216                 } else if (max_ratio >= 2) {
 217                         dto_phase = 48 * 1000;
 218                         wallclock_ratio = 1;
 219                 } else {
 220                         dto_phase = 24 * 1000;
 221                         wallclock_ratio = 0;
 222                 }
 223                 dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
 224                 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
 225                 WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);
 226         }
 227
 228         /* XXX two dtos; generally use dto0 for hdmi */
 229         /* Express [24MHz / target pixel clock] as an exact rational
 230          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
 231          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
 232          */
 233         WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id));
 234         WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
 235         WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo);
 236 }
 237
 238
 239 /*
 240  * update the info frames with the data from the current display mode
 241  */
 242 void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
 243 {
 244         struct drm_device *dev = encoder->dev;
 245         struct radeon_device *rdev = dev->dev_private;
 246         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 247         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 248         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
 249         struct hdmi_avi_infoframe frame;
 250         uint32_t offset;
 251         ssize_t err;
 252
 253         if (!dig || !dig->afmt)
 254                 return;
 255
 256         /* Silent, r600_hdmi_enable will raise WARN for us */
 257         if (!dig->afmt->enabled)
 258                 return;
 259         offset = dig->afmt->offset;
 260
 261         evergreen_audio_set_dto(encoder, mode->clock);
 262
 263         WREG32(HDMI_VBI_PACKET_CONTROL + offset,
 264                HDMI_NULL_SEND); /* send null packets when required */
 265
 266         WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
 267
 268         WREG32(HDMI_VBI_PACKET_CONTROL + offset,
 269                HDMI_NULL_SEND | /* send null packets when required */
 270                HDMI_GC_SEND | /* send general control packets */
 271                HDMI_GC_CONT); /* send general control packets every frame */
 272
 273         WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
 274                HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
 275                HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
 276
 277         WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
 278                AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
 279
 280         WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
 281                HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
 282
 283         WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
 284
 285         WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
 286                HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
 287                HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
 288
 289         WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
 290                AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
 291
 292         /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
 293
 294         WREG32(HDMI_ACR_PACKET_CONTROL + offset,
 295                HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
 296                HDMI_ACR_SOURCE); /* select SW CTS value */
 297
 298         evergreen_hdmi_update_ACR(encoder, mode->clock);
 299
 300         WREG32(AFMT_60958_0 + offset,
 301                AFMT_60958_CS_CHANNEL_NUMBER_L(1));
 302
 303         WREG32(AFMT_60958_1 + offset,
 304                AFMT_60958_CS_CHANNEL_NUMBER_R(2));
 305
 306         WREG32(AFMT_60958_2 + offset,
 307                AFMT_60958_CS_CHANNEL_NUMBER_2(3) |
 308                AFMT_60958_CS_CHANNEL_NUMBER_3(4) |
 309                AFMT_60958_CS_CHANNEL_NUMBER_4(5) |
 310                AFMT_60958_CS_CHANNEL_NUMBER_5(6) |
 311                AFMT_60958_CS_CHANNEL_NUMBER_6(7) |
 312                AFMT_60958_CS_CHANNEL_NUMBER_7(8));
 313
 314         if (ASIC_IS_DCE6(rdev)) {
 315                 dce6_afmt_write_speaker_allocation(encoder);
 316         } else {
 317                 dce4_afmt_write_speaker_allocation(encoder);
 318         }
 319
 320         WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
 321                AFMT_AUDIO_CHANNEL_ENABLE(0xff));
 322
 323         /* fglrx sets 0x40 in 0x5f80 here */
 324
 325         if (ASIC_IS_DCE6(rdev)) {
 326                 dce6_afmt_select_pin(encoder);
 327                 dce6_afmt_write_sad_regs(encoder);
 328         } else {
 329                 evergreen_hdmi_write_sad_regs(encoder);
 330         }
 331
 332         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
 333         if (err < 0) {
 334                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
 335                 return;
 336         }
 337
 338         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
 339         if (err < 0) {
 340                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
 341                 return;
 342         }
 343
 344         evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
 345
 346         WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset,
 347                   HDMI_AVI_INFO_SEND | /* enable AVI info frames */
 348                   HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */
 349
 350         WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
 351                  HDMI_AVI_INFO_LINE(2), /* anything other than 0 */
 352                  ~HDMI_AVI_INFO_LINE_MASK);
 353
 354         WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
 355                   AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */
 356
 357         /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
 358         WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
 359         WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
 360         WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
 361         WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);
 362 }
 363
 364 void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
 365 {
 366         struct drm_device *dev = encoder->dev;
 367         struct radeon_device *rdev = dev->dev_private;
 368         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 369         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 370
 371         if (!dig || !dig->afmt)
 372                 return;
 373
 374         /* Silent, r600_hdmi_enable will raise WARN for us */
 375         if (enable && dig->afmt->enabled)
 376                 return;
 377         if (!enable && !dig->afmt->enabled)
 378                 return;
 379
 380         if (enable) {
 381                 if (ASIC_IS_DCE6(rdev))
 382                         dig->afmt->pin = dce6_audio_get_pin(rdev);
 383                 else
 384                         dig->afmt->pin = r600_audio_get_pin(rdev);
 385         } else {
 386                 dig->afmt->pin = NULL;
 387         }
 388
 389         dig->afmt->enabled = enable;
 390
 391         DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
 392                   enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
 393 }