2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Christian König.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Christian König
27 #include <linux/hdmi.h>
29 #include <drm/radeon_drm.h>
31 #include "radeon_asic.h"
32 #include "radeon_audio.h"
33 #include "evergreend.h"
36 /* enable the audio stream */
37 void dce4_audio_enable(struct radeon_device
*rdev
,
38 struct r600_audio_pin
*pin
,
41 u32 tmp
= RREG32(AZ_HOT_PLUG_CONTROL
);
49 tmp
|= PIN0_AUDIO_ENABLED
;
51 tmp
|= PIN1_AUDIO_ENABLED
;
53 tmp
|= PIN2_AUDIO_ENABLED
;
55 tmp
|= PIN3_AUDIO_ENABLED
;
57 tmp
&= ~(AUDIO_ENABLED
|
64 WREG32(AZ_HOT_PLUG_CONTROL
, tmp
);
67 void evergreen_hdmi_update_acr(struct drm_encoder
*encoder
, long offset
,
68 const struct radeon_hdmi_acr
*acr
)
70 struct drm_device
*dev
= encoder
->dev
;
71 struct radeon_device
*rdev
= dev
->dev_private
;
75 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
76 bpc
= radeon_crtc
->bpc
;
80 WREG32(HDMI_ACR_PACKET_CONTROL
+ offset
,
81 HDMI_ACR_AUTO_SEND
); /* allow hw to sent ACR packets when required */
83 WREG32(HDMI_ACR_PACKET_CONTROL
+ offset
,
84 HDMI_ACR_SOURCE
| /* select SW CTS value */
85 HDMI_ACR_AUTO_SEND
); /* allow hw to sent ACR packets when required */
87 WREG32(HDMI_ACR_32_0
+ offset
, HDMI_ACR_CTS_32(acr
->cts_32khz
));
88 WREG32(HDMI_ACR_32_1
+ offset
, acr
->n_32khz
);
90 WREG32(HDMI_ACR_44_0
+ offset
, HDMI_ACR_CTS_44(acr
->cts_44_1khz
));
91 WREG32(HDMI_ACR_44_1
+ offset
, acr
->n_44_1khz
);
93 WREG32(HDMI_ACR_48_0
+ offset
, HDMI_ACR_CTS_48(acr
->cts_48khz
));
94 WREG32(HDMI_ACR_48_1
+ offset
, acr
->n_48khz
);
97 void dce4_afmt_write_latency_fields(struct drm_encoder
*encoder
,
98 struct drm_connector
*connector
, struct drm_display_mode
*mode
)
100 struct radeon_device
*rdev
= encoder
->dev
->dev_private
;
103 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
104 if (connector
->latency_present
[1])
105 tmp
= VIDEO_LIPSYNC(connector
->video_latency
[1]) |
106 AUDIO_LIPSYNC(connector
->audio_latency
[1]);
108 tmp
= VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
110 if (connector
->latency_present
[0])
111 tmp
= VIDEO_LIPSYNC(connector
->video_latency
[0]) |
112 AUDIO_LIPSYNC(connector
->audio_latency
[0]);
114 tmp
= VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
116 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC
, tmp
);
119 void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder
*encoder
,
120 u8
*sadb
, int sad_count
)
122 struct radeon_device
*rdev
= encoder
->dev
->dev_private
;
125 /* program the speaker allocation */
126 tmp
= RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER
);
127 tmp
&= ~(DP_CONNECTION
| SPEAKER_ALLOCATION_MASK
);
129 tmp
|= HDMI_CONNECTION
;
131 tmp
|= SPEAKER_ALLOCATION(sadb
[0]);
133 tmp
|= SPEAKER_ALLOCATION(5); /* stereo */
134 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER
, tmp
);
137 void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder
*encoder
,
138 u8
*sadb
, int sad_count
)
140 struct radeon_device
*rdev
= encoder
->dev
->dev_private
;
143 /* program the speaker allocation */
144 tmp
= RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER
);
145 tmp
&= ~(HDMI_CONNECTION
| SPEAKER_ALLOCATION_MASK
);
147 tmp
|= DP_CONNECTION
;
149 tmp
|= SPEAKER_ALLOCATION(sadb
[0]);
151 tmp
|= SPEAKER_ALLOCATION(5); /* stereo */
152 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER
, tmp
);
155 void evergreen_hdmi_write_sad_regs(struct drm_encoder
*encoder
,
156 struct cea_sad
*sads
, int sad_count
)
159 struct radeon_device
*rdev
= encoder
->dev
->dev_private
;
160 static const u16 eld_reg_to_type
[][2] = {
161 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0
, HDMI_AUDIO_CODING_TYPE_PCM
},
162 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1
, HDMI_AUDIO_CODING_TYPE_AC3
},
163 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2
, HDMI_AUDIO_CODING_TYPE_MPEG1
},
164 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3
, HDMI_AUDIO_CODING_TYPE_MP3
},
165 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4
, HDMI_AUDIO_CODING_TYPE_MPEG2
},
166 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5
, HDMI_AUDIO_CODING_TYPE_AAC_LC
},
167 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6
, HDMI_AUDIO_CODING_TYPE_DTS
},
168 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7
, HDMI_AUDIO_CODING_TYPE_ATRAC
},
169 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9
, HDMI_AUDIO_CODING_TYPE_EAC3
},
170 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10
, HDMI_AUDIO_CODING_TYPE_DTS_HD
},
171 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11
, HDMI_AUDIO_CODING_TYPE_MLP
},
172 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13
, HDMI_AUDIO_CODING_TYPE_WMA_PRO
},
175 for (i
= 0; i
< ARRAY_SIZE(eld_reg_to_type
); i
++) {
178 int max_channels
= -1;
181 for (j
= 0; j
< sad_count
; j
++) {
182 struct cea_sad
*sad
= &sads
[j
];
184 if (sad
->format
== eld_reg_to_type
[i
][1]) {
185 if (sad
->channels
> max_channels
) {
186 value
= MAX_CHANNELS(sad
->channels
) |
187 DESCRIPTOR_BYTE_2(sad
->byte2
) |
188 SUPPORTED_FREQUENCIES(sad
->freq
);
189 max_channels
= sad
->channels
;
192 if (sad
->format
== HDMI_AUDIO_CODING_TYPE_PCM
)
193 stereo_freqs
|= sad
->freq
;
199 value
|= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs
);
201 WREG32_ENDPOINT(0, eld_reg_to_type
[i
][0], value
);
206 * build a AVI Info Frame
208 void evergreen_set_avi_packet(struct radeon_device
*rdev
, u32 offset
,
209 unsigned char *buffer
, size_t size
)
211 uint8_t *frame
= buffer
+ 3;
213 WREG32(AFMT_AVI_INFO0
+ offset
,
214 frame
[0x0] | (frame
[0x1] << 8) | (frame
[0x2] << 16) | (frame
[0x3] << 24));
215 WREG32(AFMT_AVI_INFO1
+ offset
,
216 frame
[0x4] | (frame
[0x5] << 8) | (frame
[0x6] << 16) | (frame
[0x7] << 24));
217 WREG32(AFMT_AVI_INFO2
+ offset
,
218 frame
[0x8] | (frame
[0x9] << 8) | (frame
[0xA] << 16) | (frame
[0xB] << 24));
219 WREG32(AFMT_AVI_INFO3
+ offset
,
220 frame
[0xC] | (frame
[0xD] << 8) | (buffer
[1] << 24));
222 WREG32_OR(HDMI_INFOFRAME_CONTROL0
+ offset
,
223 HDMI_AVI_INFO_SEND
| /* enable AVI info frames */
224 HDMI_AVI_INFO_CONT
); /* required for audio info values to be updated */
226 WREG32_P(HDMI_INFOFRAME_CONTROL1
+ offset
,
227 HDMI_AVI_INFO_LINE(2), /* anything other than 0 */
228 ~HDMI_AVI_INFO_LINE_MASK
);
231 void dce4_hdmi_audio_set_dto(struct radeon_device
*rdev
,
232 struct radeon_crtc
*crtc
, unsigned int clock
)
234 unsigned int max_ratio
= clock
/ 24000;
239 if (max_ratio
>= 8) {
240 dto_phase
= 192 * 1000;
242 } else if (max_ratio
>= 4) {
243 dto_phase
= 96 * 1000;
245 } else if (max_ratio
>= 2) {
246 dto_phase
= 48 * 1000;
249 dto_phase
= 24 * 1000;
253 value
= RREG32(DCCG_AUDIO_DTO0_CNTL
) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK
;
254 value
|= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio
);
255 value
&= ~DCCG_AUDIO_DTO1_USE_512FBR_DTO
;
256 WREG32(DCCG_AUDIO_DTO0_CNTL
, value
);
258 /* Two dtos; generally use dto0 for HDMI */
262 value
|= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc
->crtc_id
);
264 WREG32(DCCG_AUDIO_DTO_SOURCE
, value
);
266 /* Express [24MHz / target pixel clock] as an exact rational
267 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
268 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
270 WREG32(DCCG_AUDIO_DTO0_PHASE
, dto_phase
);
271 WREG32(DCCG_AUDIO_DTO0_MODULE
, clock
);
274 void dce4_dp_audio_set_dto(struct radeon_device
*rdev
,
275 struct radeon_crtc
*crtc
, unsigned int clock
)
279 value
= RREG32(DCCG_AUDIO_DTO1_CNTL
) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK
;
280 value
|= DCCG_AUDIO_DTO1_USE_512FBR_DTO
;
281 WREG32(DCCG_AUDIO_DTO1_CNTL
, value
);
283 /* Two dtos; generally use dto1 for DP */
285 value
|= DCCG_AUDIO_DTO_SEL
;
288 value
|= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc
->crtc_id
);
290 WREG32(DCCG_AUDIO_DTO_SOURCE
, value
);
292 /* Express [24MHz / target pixel clock] as an exact rational
293 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
294 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
296 WREG32(DCCG_AUDIO_DTO1_PHASE
, 24000);
297 WREG32(DCCG_AUDIO_DTO1_MODULE
, clock
);
300 void dce4_set_vbi_packet(struct drm_encoder
*encoder
, u32 offset
)
302 struct drm_device
*dev
= encoder
->dev
;
303 struct radeon_device
*rdev
= dev
->dev_private
;
305 WREG32(HDMI_VBI_PACKET_CONTROL
+ offset
,
306 HDMI_NULL_SEND
| /* send null packets when required */
307 HDMI_GC_SEND
| /* send general control packets */
308 HDMI_GC_CONT
); /* send general control packets every frame */
311 void dce4_hdmi_set_color_depth(struct drm_encoder
*encoder
, u32 offset
, int bpc
)
313 struct drm_device
*dev
= encoder
->dev
;
314 struct radeon_device
*rdev
= dev
->dev_private
;
315 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
318 val
= RREG32(HDMI_CONTROL
+ offset
);
319 val
&= ~HDMI_DEEP_COLOR_ENABLE
;
320 val
&= ~HDMI_DEEP_COLOR_DEPTH_MASK
;
328 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
329 connector
->name
, bpc
);
332 val
|= HDMI_DEEP_COLOR_ENABLE
;
333 val
|= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR
);
334 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
338 val
|= HDMI_DEEP_COLOR_ENABLE
;
339 val
|= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR
);
340 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
345 WREG32(HDMI_CONTROL
+ offset
, val
);
348 void dce4_set_audio_packet(struct drm_encoder
*encoder
, u32 offset
)
350 struct drm_device
*dev
= encoder
->dev
;
351 struct radeon_device
*rdev
= dev
->dev_private
;
353 WREG32(AFMT_INFOFRAME_CONTROL0
+ offset
,
354 AFMT_AUDIO_INFO_UPDATE
); /* required for audio info values to be updated */
356 WREG32(AFMT_60958_0
+ offset
,
357 AFMT_60958_CS_CHANNEL_NUMBER_L(1));
359 WREG32(AFMT_60958_1
+ offset
,
360 AFMT_60958_CS_CHANNEL_NUMBER_R(2));
362 WREG32(AFMT_60958_2
+ offset
,
363 AFMT_60958_CS_CHANNEL_NUMBER_2(3) |
364 AFMT_60958_CS_CHANNEL_NUMBER_3(4) |
365 AFMT_60958_CS_CHANNEL_NUMBER_4(5) |
366 AFMT_60958_CS_CHANNEL_NUMBER_5(6) |
367 AFMT_60958_CS_CHANNEL_NUMBER_6(7) |
368 AFMT_60958_CS_CHANNEL_NUMBER_7(8));
370 WREG32(AFMT_AUDIO_PACKET_CONTROL2
+ offset
,
371 AFMT_AUDIO_CHANNEL_ENABLE(0xff));
373 /* allow 60958 channel status and send audio packets fields to be updated */
374 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ offset
,
375 AFMT_AUDIO_SAMPLE_SEND
| AFMT_RESET_FIFO_WHEN_AUDIO_DIS
| AFMT_60958_CS_UPDATE
);
379 void dce4_set_mute(struct drm_encoder
*encoder
, u32 offset
, bool mute
)
381 struct drm_device
*dev
= encoder
->dev
;
382 struct radeon_device
*rdev
= dev
->dev_private
;
385 WREG32_OR(HDMI_GC
+ offset
, HDMI_GC_AVMUTE
);
387 WREG32_AND(HDMI_GC
+ offset
, ~HDMI_GC_AVMUTE
);
390 void evergreen_hdmi_enable(struct drm_encoder
*encoder
, bool enable
)
392 struct drm_device
*dev
= encoder
->dev
;
393 struct radeon_device
*rdev
= dev
->dev_private
;
394 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
395 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
397 if (!dig
|| !dig
->afmt
)
401 WREG32(HDMI_INFOFRAME_CONTROL1
+ dig
->afmt
->offset
,
402 HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
404 WREG32(HDMI_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
,
405 HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
406 HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
408 WREG32(HDMI_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
,
409 HDMI_AUDIO_INFO_SEND
| /* enable audio info frames (frames won't be set until audio is enabled) */
410 HDMI_AUDIO_INFO_CONT
); /* required for audio info values to be updated */
412 WREG32(HDMI_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
, 0);
415 dig
->afmt
->enabled
= enable
;
417 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
418 enable
? "En" : "Dis", dig
->afmt
->offset
, radeon_encoder
->encoder_id
);
421 void evergreen_dp_enable(struct drm_encoder
*encoder
, bool enable
)
423 struct drm_device
*dev
= encoder
->dev
;
424 struct radeon_device
*rdev
= dev
->dev_private
;
425 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
426 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
428 if (!dig
|| !dig
->afmt
)
432 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
433 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
434 struct radeon_connector_atom_dig
*dig_connector
;
437 WREG32(EVERGREEN_DP_SEC_TIMESTAMP
+ dig
->afmt
->offset
,
438 EVERGREEN_DP_SEC_TIMESTAMP_MODE(1));
440 if (radeon_connector
->con_priv
) {
441 dig_connector
= radeon_connector
->con_priv
;
442 val
= RREG32(EVERGREEN_DP_SEC_AUD_N
+ dig
->afmt
->offset
);
443 val
&= ~EVERGREEN_DP_SEC_N_BASE_MULTIPLE(0xf);
445 if (dig_connector
->dp_clock
== 162000)
446 val
|= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(3);
448 val
|= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(5);
450 WREG32(EVERGREEN_DP_SEC_AUD_N
+ dig
->afmt
->offset
, val
);
453 WREG32(EVERGREEN_DP_SEC_CNTL
+ dig
->afmt
->offset
,
454 EVERGREEN_DP_SEC_ASP_ENABLE
| /* Audio packet transmission */
455 EVERGREEN_DP_SEC_ATP_ENABLE
| /* Audio timestamp packet transmission */
456 EVERGREEN_DP_SEC_AIP_ENABLE
| /* Audio infoframe packet transmission */
457 EVERGREEN_DP_SEC_STREAM_ENABLE
); /* Master enable for secondary stream engine */
459 WREG32(EVERGREEN_DP_SEC_CNTL
+ dig
->afmt
->offset
, 0);
462 dig
->afmt
->enabled
= enable
;