drivers/gpu/drm/radeon/evergreen_hdmi.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Christian König.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Christian König
  25  *          Rafał Miłecki
  26  */
  27 #include <linux/hdmi.h>
  28 #include <drm/drmP.h>
  29 #include <drm/radeon_drm.h>
  30 #include "radeon.h"
  31 #include "radeon_asic.h"
  32 #include "evergreend.h"
  33 #include "atom.h"
  34
  35 extern void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder);
  36 extern void dce6_afmt_write_sad_regs(struct drm_encoder *encoder);
  37 extern void dce6_afmt_select_pin(struct drm_encoder *encoder);
  38
  39 /*
  40  * update the N and CTS parameters for a given pixel clock rate
  41  */
  42 static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
  43 {
  44         struct drm_device *dev = encoder->dev;
  45         struct radeon_device *rdev = dev->dev_private;
  46         struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
  47         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  48         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  49         uint32_t offset = dig->afmt->offset;
  50
  51         WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz));
  52         WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz);
  53
  54         WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz));
  55         WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz);
  56
  57         WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz));
  58         WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
  59 }
  60
  61 static void dce4_afmt_write_speaker_allocation(struct drm_encoder *encoder)
  62 {
  63         struct radeon_device *rdev = encoder->dev->dev_private;
  64         struct drm_connector *connector;
  65         struct radeon_connector *radeon_connector = NULL;
  66         u32 tmp;
  67         u8 *sadb;
  68         int sad_count;
  69
  70         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
  71                 if (connector->encoder == encoder)
  72                         radeon_connector = to_radeon_connector(connector);
  73         }
  74
  75         if (!radeon_connector) {
  76                 DRM_ERROR("Couldn't find encoder's connector\n");
  77                 return;
  78         }
  79
  80         sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb);
  81         if (sad_count < 0) {
  82                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
  83                 return;
  84         }
  85
  86         /* program the speaker allocation */
  87         tmp = RREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
  88         tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
  89         /* set HDMI mode */
  90         tmp |= HDMI_CONNECTION;
  91         if (sad_count)
  92                 tmp |= SPEAKER_ALLOCATION(sadb[0]);
  93         else
  94                 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
  95         WREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
  96
  97         kfree(sadb);
  98 }
  99
 100 static void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder)
 101 {
 102         struct radeon_device *rdev = encoder->dev->dev_private;
 103         struct drm_connector *connector;
 104         struct radeon_connector *radeon_connector = NULL;
 105         struct cea_sad *sads;
 106         int i, sad_count;
 107
 108         static const u16 eld_reg_to_type[][2] = {
 109                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
 110                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
 111                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
 112                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
 113                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
 114                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
 115                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
 116                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
 117                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
 118                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
 119                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
 120                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
 121         };
 122
 123         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
 124                 if (connector->encoder == encoder)
 125                         radeon_connector = to_radeon_connector(connector);
 126         }
 127
 128         if (!radeon_connector) {
 129                 DRM_ERROR("Couldn't find encoder's connector\n");
 130                 return;
 131         }
 132
 133         sad_count = drm_edid_to_sad(radeon_connector->edid, &sads);
 134         if (sad_count < 0) {
 135                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
 136                 return;
 137         }
 138         BUG_ON(!sads);
 139
 140         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
 141                 u32 value = 0;
 142                 int j;
 143
 144                 for (j = 0; j < sad_count; j++) {
 145                         struct cea_sad *sad = &sads[j];
 146
 147                         if (sad->format == eld_reg_to_type[i][1]) {
 148                                 value = MAX_CHANNELS(sad->channels) |
 149                                         DESCRIPTOR_BYTE_2(sad->byte2) |
 150                                         SUPPORTED_FREQUENCIES(sad->freq);
 151                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
 152                                         value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq);
 153                                 break;
 154                         }
 155                 }
 156                 WREG32(eld_reg_to_type[i][0], value);
 157         }
 158
 159         kfree(sads);
 160 }
 161
 162 /*
 163  * build a HDMI Video Info Frame
 164  */
 165 static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder,
 166                                                 void *buffer, size_t size)
 167 {
 168         struct drm_device *dev = encoder->dev;
 169         struct radeon_device *rdev = dev->dev_private;
 170         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 171         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 172         uint32_t offset = dig->afmt->offset;
 173         uint8_t *frame = buffer + 3;
 174         uint8_t *header = buffer;
 175
 176         WREG32(AFMT_AVI_INFO0 + offset,
 177                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
 178         WREG32(AFMT_AVI_INFO1 + offset,
 179                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
 180         WREG32(AFMT_AVI_INFO2 + offset,
 181                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
 182         WREG32(AFMT_AVI_INFO3 + offset,
 183                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
 184 }
 185
 186 static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock)
 187 {
 188         struct drm_device *dev = encoder->dev;
 189         struct radeon_device *rdev = dev->dev_private;
 190         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 191         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 192         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 193         u32 base_rate = 24000;
 194         u32 max_ratio = clock / base_rate;
 195         u32 dto_phase;
 196         u32 dto_modulo = clock;
 197         u32 wallclock_ratio;
 198         u32 dto_cntl;
 199
 200         if (!dig || !dig->afmt)
 201                 return;
 202
 203         if (ASIC_IS_DCE6(rdev)) {
 204                 dto_phase = 24 * 1000;
 205         } else {
 206                 if (max_ratio >= 8) {
 207                         dto_phase = 192 * 1000;
 208                         wallclock_ratio = 3;
 209                 } else if (max_ratio >= 4) {
 210                         dto_phase = 96 * 1000;
 211                         wallclock_ratio = 2;
 212                 } else if (max_ratio >= 2) {
 213                         dto_phase = 48 * 1000;
 214                         wallclock_ratio = 1;
 215                 } else {
 216                         dto_phase = 24 * 1000;
 217                         wallclock_ratio = 0;
 218                 }
 219                 dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
 220                 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
 221                 WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);
 222         }
 223
 224         /* XXX two dtos; generally use dto0 for hdmi */
 225         /* Express [24MHz / target pixel clock] as an exact rational
 226          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
 227          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
 228          */
 229         WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id));
 230         WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
 231         WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo);
 232 }
 233
 234
 235 /*
 236  * update the info frames with the data from the current display mode
 237  */
 238 void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
 239 {
 240         struct drm_device *dev = encoder->dev;
 241         struct radeon_device *rdev = dev->dev_private;
 242         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 243         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 244         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
 245         struct hdmi_avi_infoframe frame;
 246         uint32_t offset;
 247         ssize_t err;
 248
 249         if (!dig || !dig->afmt)
 250                 return;
 251
 252         /* Silent, r600_hdmi_enable will raise WARN for us */
 253         if (!dig->afmt->enabled)
 254                 return;
 255         offset = dig->afmt->offset;
 256
 257         evergreen_audio_set_dto(encoder, mode->clock);
 258
 259         WREG32(HDMI_VBI_PACKET_CONTROL + offset,
 260                HDMI_NULL_SEND); /* send null packets when required */
 261
 262         WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
 263
 264         WREG32(HDMI_VBI_PACKET_CONTROL + offset,
 265                HDMI_NULL_SEND | /* send null packets when required */
 266                HDMI_GC_SEND | /* send general control packets */
 267                HDMI_GC_CONT); /* send general control packets every frame */
 268
 269         WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
 270                HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
 271                HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
 272
 273         WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
 274                AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
 275
 276         WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
 277                HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
 278
 279         WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
 280
 281         WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
 282                HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
 283                HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
 284
 285         WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
 286                AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
 287
 288         /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
 289
 290         WREG32(HDMI_ACR_PACKET_CONTROL + offset,
 291                HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
 292                HDMI_ACR_SOURCE); /* select SW CTS value */
 293
 294         evergreen_hdmi_update_ACR(encoder, mode->clock);
 295
 296         WREG32(AFMT_60958_0 + offset,
 297                AFMT_60958_CS_CHANNEL_NUMBER_L(1));
 298
 299         WREG32(AFMT_60958_1 + offset,
 300                AFMT_60958_CS_CHANNEL_NUMBER_R(2));
 301
 302         WREG32(AFMT_60958_2 + offset,
 303                AFMT_60958_CS_CHANNEL_NUMBER_2(3) |
 304                AFMT_60958_CS_CHANNEL_NUMBER_3(4) |
 305                AFMT_60958_CS_CHANNEL_NUMBER_4(5) |
 306                AFMT_60958_CS_CHANNEL_NUMBER_5(6) |
 307                AFMT_60958_CS_CHANNEL_NUMBER_6(7) |
 308                AFMT_60958_CS_CHANNEL_NUMBER_7(8));
 309
 310         if (ASIC_IS_DCE6(rdev)) {
 311                 dce6_afmt_write_speaker_allocation(encoder);
 312         } else {
 313                 dce4_afmt_write_speaker_allocation(encoder);
 314         }
 315
 316         WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
 317                AFMT_AUDIO_CHANNEL_ENABLE(0xff));
 318
 319         /* fglrx sets 0x40 in 0x5f80 here */
 320
 321         if (ASIC_IS_DCE6(rdev)) {
 322                 dce6_afmt_select_pin(encoder);
 323                 dce6_afmt_write_sad_regs(encoder);
 324         } else {
 325                 evergreen_hdmi_write_sad_regs(encoder);
 326         }
 327
 328         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
 329         if (err < 0) {
 330                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
 331                 return;
 332         }
 333
 334         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
 335         if (err < 0) {
 336                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
 337                 return;
 338         }
 339
 340         evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
 341
 342         WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset,
 343                   HDMI_AVI_INFO_SEND | /* enable AVI info frames */
 344                   HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */
 345
 346         WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
 347                  HDMI_AVI_INFO_LINE(2), /* anything other than 0 */
 348                  ~HDMI_AVI_INFO_LINE_MASK);
 349
 350         WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
 351                   AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */
 352
 353         /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
 354         WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
 355         WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
 356         WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
 357         WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);
 358 }
 359
 360 void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
 361 {
 362         struct drm_device *dev = encoder->dev;
 363         struct radeon_device *rdev = dev->dev_private;
 364         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 365         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 366
 367         if (!dig || !dig->afmt)
 368                 return;
 369
 370         /* Silent, r600_hdmi_enable will raise WARN for us */
 371         if (enable && dig->afmt->enabled)
 372                 return;
 373         if (!enable && !dig->afmt->enabled)
 374                 return;
 375
 376         if (enable) {
 377                 if (ASIC_IS_DCE6(rdev))
 378                         dig->afmt->pin = dce6_audio_get_pin(rdev);
 379                 else
 380                         dig->afmt->pin = r600_audio_get_pin(rdev);
 381         } else {
 382                 dig->afmt->pin = NULL;
 383         }
 384
 385         dig->afmt->enabled = enable;
 386
 387         DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
 388                   enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
 389 }